MM54C175 NSC | Alldatasheet

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Y Wide supply voltage range 3V to 15V Y Guaranteed noise margin 1.0V Y High noise immunity 0.45 V CC (typ.) Y Low power TTL compatibility Fan out of 2 driving 74L Connection Diagram & Truth Table Dual-In-Line Package TL/F/5900–1 Top View Order Number MM54C175 or MM74C175 Each Flip-Flop Inputs Outputs Clear Clock D Q Q LX X L H H u HH L H u LL H HH X N C N C HL X N C N C H e High level L e Low level X e Irrelevant u e Transition from low to high level NC e No change C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin b0.3V to V CC a0.3V Operating Temperature Range MM54C175 b55§Ct o a125§C MM74C175 b40§Ct o a85§C Storage Temperature Range b65§Ct o a150§C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3V to 15V Absolute Maximum V CC 18V Lead Temperature (Soldering, 10 seconds) 260 §C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage V CC e 5V 3.5 V VCC e 10V 8.0 V VIN(0) Logical ‘‘0’’ Input Voltage V CC e 5V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage V CC e 5V, I O eb 10 mA 4.5 V VCC e 10V, I O eb 10 mA 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage V CC e 5V, I O e 10 mA 0.5 V VCC e 10V, I O e 10 mA 1.0 V IIN(1) Logical ‘‘1’’ Input Current V CC e 15V, V IN e 15V 0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V CC e 15V, V IN e 0V b1.0 b0.005 mA ICC Supply Current V CC e 15V 0.05 300 mA CMOS/LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, V CC e 4.5V V CC b 1.5 V 74C, V CC e 4.75V V CC b 1.5 V VIN(0) Logical ‘‘0’’ Input Voltage 54C, V CC e 4.5V 0.8 V 74C, V CC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, V CC e 4.5V, I O eb 360 mA 2.4 V 74C, V CC e 4.75V, I O eb 360 mA 2.4 V VOUT(0) Logical ‘‘0’’ Output Voltage 54C, V CC e 4.5V, I O e 360 mA 0.4 V 74C, V CC e 4.75V, I O e 360 mA 0.4 V OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC e 5V, T A e 25§C, b1.75 b3.3 mA(P-Channel) V OUT e 0V ISOURCE Output Source Current V CC e 10V, T A e 25§C, b8.0 b15 mA(P-Channel) V OUT e 0V ISINK Output Sink Current V CC e 5V, T A e 25§C, 1.75 3.6 mA(N-Channel) V OUT e VCC ISINK Output Sink Current V CC e 10V, T A e 25§C, 8.0 16 mA(N-Channel) V OUT e VCC Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay Time to V CC e 5V 190 300 ns a Logical ‘‘0’’ or Logical ‘‘1’’ from V CC e 10V 75 110 ns Clock to Q or Q tpd Propagation Delay Time to a V CC e 5V 180 300 ns Logical ‘‘0’’ from Clear to Q V CC e 10V 70 110 ns tpd Propagation Delay Time to a V CC e 5V 230 400 ns Logical ‘‘1’’ from Clear to Q V CC e 10V 90 150 ns tS Time Prior to Clock Pulse that V CC e 5V 100 45 ns Data Must be Present V CC e 10V 40 16 ns tH Time After Clock Pulse that V CC e 5V 0 b11 ns Data Must be Held V CC e 10V 0 b4n s tW Minimum Clock Pulse Width V CC e 5.0V 130 250 ns VCC e 10V 45 100 ns tW Minimum Clear Pulse Width V CC e 5.0V 120 250 ns VCC e 10V 45 100 ns tr Maximum Clock Rise Time V CC e 5V 15 450 ms VCC e 10V 5.0 125 ms tf Maximum Clock Fall Time V CC e 5V 15 50 ms VCC e 10V 5.0 50 ms fMAX Maximum Clock Frequency V CC e 5V 2.0 3.5 MHz VCC e 10V 5.0 10 MHz CIN Input Capacitance Clear Input (Note 2) 10 pF Any Other Input 5.0 pF CPD Power Dissipation Capacitance Per Package (Note 3) 130 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics Application Note AN-90. Switching Time Waveforms CMOS to CMOS TL/F/5900–6

TL/F/5900–2 TL/F/5900–3 TL/F/5900–4 TL/F/5900–5

Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C175J or MM74C175J

MM54C175/MM74C175 Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C175N or MM74C175N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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