MM74C175

MM74C175 FAIRCHILD | Alldatasheet

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Technical content

Features

■ Wide supply voltage range: 3V to 15V ■ Guaranteed noise margin: 1.0V ■ High noise immunity: 0.45 VCC (typ.) ■ Low power TTL compatibility: Fan out of 2 driving 74L Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View Truth Table Each Flip-Flop H = HIGH Level L = LOW Level X = Irrelevant ↑ = Transition from LOW-to-HIGH level NC = No Change Order Number Package Number Package Description MM74C175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Inputs Outputs Clear Clock D Q Q LXXLH H ↑ HHL H ↑ LLH HHX N C N C HLX N C N C

www.fairchildsemi.com 2 MM74C175 Block Diagrams Typical One of Four

3 www.fairchildsemi.com MM74C175 Absolute Maximum Ratings(Note 1) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The Electrical Characteristics table provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise specified Voltage at Any Pin −0.3V to VCC +0.3V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3V to 15V Absolute Maximum VCC 18V Lead Temperature (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5V 3.5 V VCC = 10V 8.0 V VIN(0) Logical “0” Input Voltage V CC = 5V 1.5 V VCC = 10V 2.0 V VOUT(1) Logical “1” Output Voltage V CC = 5V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 V VOUT(0) Logical “0” Output Voltage V CC = 5V, IO = 10 µA0 . 5 V VCC = 10V, IO = 10 µA1 . 0 V IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.05 300 µA CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage 74C, V CC = 4.75V V CC − 1.5 V VIN(0) Logical “0” Input Voltage 74C, V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage 74C, V CC = 4.75V, IO = −360 µA2 . 4 V VOUT(0) Logical “0” Output Voltage 74C, V CC = 4.75V, IO = 360 µA0 . 4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current V CC = 5V, TA = 25°C, −1.75 −3.3 mA (P-Channel) V OUT = 0V ISOURCE Output Source Current V CC = 10V, TA = 25°C, −8.0 −15 mA (P-Channel) V OUT = 0V ISINK Output Sink Current V CC = 5V, TA = 25°C, 1.75 3.6 mA (N-Channel) V OUT = VCC ISINK Output Sink Current V CC = 10V, TA = 25°C, 8.0 16 mA (N-Channel) V OUT = VCC

www.fairchildsemi.com 4 MM74C175 TA = 25°C, CL = 50 pF , unless otherwise noted Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. Switching Time Waveforms CMOS to CMOS Symbol Parameter Conditions Min Typ Max Units tpd Propagation Delay Time to V CC = 5V 190 300 ns a Logical “0” or Logical “1” from VCC = 10V 75 110 ns Clock to Q or Q tpd Propagation Delay Time to a V CC = 5V 180 300 ns Logical “0” from Clear to Q V CC = 10V 70 110 ns tpd Propagation Delay Time to a V CC = 5V 230 400 ns Logical “1” from Clear to Q V CC = 10V 90 150 ns tS Time Prior to Clock Pulse that V CC = 5V 100 45 ns Data Must be Present V CC = 10V 40 16 ns tH Time After Clock Pulse that V CC = 5V 0 −11 ns Data Must be Held V CC = 10V 0 −4n s tW Minimum Clock Pulse Width V CC = 5.0V 130 250 ns VCC = 10V 45 100 ns tW Minimum Clear Pulse Width V CC = 5.0V 120 250 ns VCC = 10V 45 100 ns tr Maximum Clock Rise Time V CC = 5V 15 450 µs VCC = 10V 5.0 125 µs tf Maximum Clock Fall Time V CC = 5V 15 50 µs VCC = 10V 5.0 50 µs fMAX Maximum Clock Frequency V CC = 5V 2.0 3.5 MHz VCC = 10V 5.0 10 MHz C IN Input Capacitance Clear Input (Note 3) 10 pF Any Other Input 5.0 pF C PD Power Dissipation Capacitance Per Package (Note 4) 130 pF

5 www.fairchildsemi.com MM74C175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C175 Quad D-Type Flip-Flop LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E