MM54C173 NSC | Alldatasheet

Document overview

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Technical content

Features

Y Tenth power TTL compatible Drive 2 LPTTL loads Y High noise immunity 0.45 VCC (typ.) Y Low power Y Medium speed operation Y High impedance TRI-STATE Y Input disable without gating the clock

Applications

TL/F/5898–2 Top View Order Number MM54C173 or MM74C173 Truth Table (Both Output Disables Low) tn tna1 Data Input Disable Data Output Input Logic ‘‘1’’ on One or Both Inputs X Qn Logic ‘‘0’’ on Both Inputs Logic ‘‘0’’ on Both Inputs TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Pin b0.3V to VCC a0.3V Operating Temperature Range MM54C173 b55§C to a125§C MM74C173 b40§C to a85§C Storage Temperature Range b65§C to a150§C Maximum VCC Voltage 18V Power Dissipation (PD) Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range 3V to 15V Lead Temperature (Soldering, 10 seconds) 260§C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5V 3.5 V VCC e 10V 8.0 V VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5V 1.5 V VCC e 10V 2.0 V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5V 4.5 V VCC e 10V 9.0 V VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5V 0.5 V VCC e 10V 1.0 V IIN(1) Logical ‘‘1’’ Input Current VCC e 15V 0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current b1.0 0.005 mA IOZ Output Current in High VCC e 15V, VO e 15V 0.001 1.0 mA Impedance State VCC e 15V, VO e 0V b1.0 0.001 mA ICC Supply Current VCC e 15V 0.05 300 mA LOW POWER TTL/CMOS INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C, VCC e 4.5V VCCb1.5 V 74C, VCC e 4.5V VCCb1.5 V VIN(0) Logical ‘‘0’’ Input Voltage 54C, VCC e 4.5V 0.8 V 74C, VCC e 4.75V 0.8 V VOUT(1) Logical ‘‘1’’ Output Voltage 54C, VCC e 4.5V, IO e b360 mA 2.4 V 74C, VCC e 4.75V, IO e b360 mA 2.4 V VOUT(1) Logical ‘‘0’’ Output Voltage 54C, VCC e 4.5V, IO e 360 mA 0.4 V 74C, VCC e 4.75V, IO e 360 mA 0.4 V tpd0, tpd1 Propagation Delay Time to a Logical ‘‘0’’ or Logical VCC e 5V, CL e 50 pF, 500 ns ‘‘1’’ from Clock TA e 25§C OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current VCC e 5V, VIN(0) e 0V b1.75 mA TA e 25§C, VOUT e 0V ISOURCE Output Source Current VCC e 10V, VIN(0) e 0V b8.0 mA TA e 25§C, VOUT e 0V ISINK Output Sink Current VCC e 5V, VIN(1) e 5V 1.75 mA TA e 25§C, VOUT e VCC ISINK Output Sink Current VCC e 10V, VIN(1) e 10V 8.0 mA TA e 25§C, VOUT e VCC Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.

tpd0, tpd1 Propagation Delay Time to a Logical ‘‘0’’ VCC e 5V 220 400 ns or Logical ‘‘1’’ from Clock to Output VCC e 10V 200 ns tS Input Data Set-up Time VCC e 5V ns VCC e 10V ns tH Input Data Hold Time VCC e 5V ns VCC e 10V ns tS Input Disable Set-up Time, tS DISS VCC e 5V 100 200 ns VCC e 10V ns tH Input Disable Hold Time, tH DISS VCC e 5V ns VCC e 10V ns t1H, t0H Delay from Output Disable to High Impedance VCC e 5V, RL e 10k 170 340 ns State (from Logical ‘‘1’’ or Logical ‘‘0’’ Level) VCC e 10V, RL e 10k 140 ns tH1 Delay from Output Disable to Logical ‘‘1’’ VCC e 5V 170 340 ns Level (from High Impedance State) VCC e 10V 140 ns tH0 Delay from Output Disable to Logical ‘‘0’’ VCC e 5V 170 340 ns Level (from High Impedance State) VCC e 10V 140 ns tpd0, tpd1 Propagation Delay from Clear to Output VCC e 5V 240 490 ns VCC e 10V 180 ns fMAX Maximum Clock Frequency VCC e 5V MHz VCC e 10V 7.0 MHz tW Minimum Clear Pulse Width VCC e 5V 150 ns VCC e 10V ns tr, tf Maximum Clock Rise and Fall Time VCC e 5V ms VCC e 10V ms CIN Input Capacitance (Note 2) pF CPD Power Dissipation Capacitance (Note 3) *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guarantee.d Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note AN-90. Switching Time Waveforms TL/F/5898–3

TL/F/5898–1

Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C173J or MM74C173J

MM54C173/MM74C173 TRI-STATE Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C173N or MM74C173N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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