MM74C165

MM74C165 FAIRCHILD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 6

Technical content

Features

■ Wide supply voltage range: 3V to 15V ■ Guaranteed noise margin: 1V ■ High noise immunity: 0.45 VCC (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L ■ Parallel loading independent of clock ■ Dual clock inputs ■ Fully static operation Ordering Code: Connection Diagram Pin Assignments for DIP Top View Order Number Package Number Package Description MM74165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

www.fairchildsemi.com 2 MM74C165 Block Diagrams *Please look into Section 8, Appendix D for availability of various package types. Truth Table X = Don't Care H = VIN(1) L = VIN(0) ↑ = Clock transition from VIN(0) to VIN(1) P0 thru P7 = Data present (and loaded into) parallel inputs Q0 thru Q6 = Internal flip-flop outputs State Inputs Internal Outputs PL Clock1 Clock2 Ds P0 thru P7 Q0 Q1 Q7 Q7 (as enable) Parallel Load L X X X P 0 … P 7P 0P 1P 7P 7 E n a b l e H L L X X P 0P 1P 7P 7 Shift (with Ds) H ↑ L H X H P0 P6 P6 Shift (with Ds) H ↑ LL X L H P 5 P 5 Hold (Disable) H ↑ HXXL H P 5 P 5

3 www.fairchildsemi.com MM74C165 Absolute Maximum Ratings(Note 1) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Tempera- ture Range” they are not meant to imply that the devices should be oper- ated at these limits. The Electrical Characteristics table provides conditions for actual device operation. Min/Max limits apply across temperature range unless otherwise noted Voltage at Any Pin −0.3V to VCC + 0.3V Operating T emperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Absolute Maximum VCC 18V Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range 3V to 15V Lead Temperature (Soldering, 10 seconds) 260 °C Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage V CC = 5V 3.5 V VCC = 10V 8.0 V VIN(0) Logical “0” Input Voltage V CC = 5V 1.5 V VCC = 10V 2.0 V VOUT(1) Logical “1” Output Voltage V CC = 5V, IO = −10 µA4 . 5 V VCC = 10V, IO = −10 µA9 . 0 V VOUT(0) Logical “0” Output Voltage V CC = 5V, IO = +10 µA0 . 5 V VCC = 10V, IO = +10 µA1 . 0 V IIN(1) Logical “1” Input Current V CC = 15V, VIN = 15V 0.005 1.0 µA IIN(0) Logical “0” Input Current V CC = 15V, VIN = 0V −1.0 −0.005 µA ICC Supply Current V CC = 15V 0.05 300 µA CMOS TO LPTTL INTERFACE VIN(1) Logical “1” Input Voltage V CC = 4.75V V CC − 1.5 V VIN(0) Logical “0” Input Voltage V CC = 4.75V 0.8 V VOUT(1) Logical “1” Output Voltage V CC = 4.75V, IO = −360 µA2 . 4 V VOUT(0) Logical “0” Output Voltage V CC = 4.75V, IO = 360 µA0 . 4 V OUTPUT DRIVE (See Family Characteristics Data Sheet) (short circuit current) ISOURCE Output Source Current V CC = 5V −1.75 −3.3 mA (P-Channel) T A = 25°C, VOUT = 0V ISOURCE Output Source Current V CC = 10V −8.0 −15 mA (P-Channel) T A = 25°C, VOUT = 0V ISINK Output Sink Current V CC = 5V 1.75 3.6 mA (N-Channel) T A = 25°C, VOUT = VCC ISINK Output Sink Current V CC = 10V 8.0 16 mA (N-Channel) T A = 25°C, VOUT = VCC

www.fairchildsemi.com 4 MM74C165 TA = 25°C, CL = 50 pF , unless otherwise noted Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: C PD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note AN-90. Switching Time Waveform Note A: The remaining six data and the serial input are LOW. Note B: Prior to test, HIGH level data is loaded into the P7 input. Symbol Parameter Conditions Min Typ Max Units tpd0, tpd1 Propagation Delay Time to a Logical “0” or VCC = 5V 200 400 ns Logical “1” from Clock or Load to Q or QVCC = 10V 80 200 ns tpd0, tpd1 Propagation Delay Time to a Logical “0” or VCC = 5V 200 400 ns Logical “1” from H to Q or Q VCC = 10V 80 200 ns tS Clock Inhibit Set-up Time V CC = 5V 150 75 ns VCC = 10V 60 30 ns tS Serial Input Set-up Time V CC = 5V 50 25 ns VCC = 10V 30 15 ns tH Serial Input Hold Time V CC = 5V 50 0 ns VCC = 10V 30 0 ns tS Parallel Input Set-Up Time V CC = 5V 150 75 ns VCC = 10V 60 30 ns tH Parallel Input Hold Time V CC = 5V 50 0 ns VCC = 10V 30 0 ns tW Minimum Clock Pulse Width V CC = 5V 70 200 ns VCC = 10V 30 100 ns tW Minimum Load Pulse Width V CC = 5V 85 180 ns VCC = 10V 30 90 ns fMAX Maximum Clock Frequency V CC = 5V 2.5 6 MHz VCC = 10V 5 12 MHz tr, tf Maximum Clock Rise and Fall Time V CC = 5V 10 µs VCC = 10V 5 µs C IN Input Capacitance (Note 3) 5 pF C PD Power Dissipation Capacitance (Note 4) 65 pF

5 www.fairchildsemi.com MM74C165 Logic Waveform

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74C165 Parallel-Load 8-Bit Shift Register LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E