MM58274C-12 NSC | Alldatasheet
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x 3} . £ A National Semiconductor Fd MM58274C-12 Microprocessor Compatible Real Time Clock General Description Features ‘The MM58274C-12 is fabricated using low threshold metal ™ Same pin-out as MM58174A, MM58274B, MM58274C, gate CMOS technology and is designed to operate in bus ‘and MM58274 oriented microprocessor systems where a real time clock ™ Timekeeping from tenths of seconds to tens of years in and calendar function are required. The on-chip 32.768 kHz independently accessible registers. crystal controlled oscillator will maintain timekeeping down = Leap year register to 2.2V to allow low power standby battery operation. This @ 42 hour operation ‘only device is pin compatible with the MMS8174A but continues» Buffered crystal frequency output in test mode for easy timekeeping up to tens of years. oscillator setting . allows Ne for tit Applications weir nnaed Nag akows simple teeing for tne & Point of sale terminals '§ Independent interrupting time with open drain output © Toller terminals Fully TTL compatible ™ Word processors | Low power standby operation (10 #A at 2.2V) @ Data logging '@ Low cost 16-pin DIP and 20-pin PCC '§ Industrial process control Block Diagram coven. wut soonest arom won wt mew A i sm TuF/Se02-1 FIGURE 1 1-84
Absolute Maximum Ratings (note 1) Operating Conditions z If Military/Aerospace specified devices are required, Min Max Units | 9 please contact the National Semiconductor Sales ‘Operating Supply Voltage 45 55 v ~ Office/Distributors for availability and specifications. ‘Standby Mode Supply Voltage 22 55 v 6 DC input or Output Voltage ~0.3V to Vpp + 0.3V DC Input or Output Voltage © Vp Vv x DC Input or Output Diode Current £5.0mA Operating Temperature Range = —40 85 “ce ‘Storage Temperature, TsTg —65°C to + 150°C ‘Supply Voltage, Voo 65V Power Dissipation, Pp 500 mW Lead Temperature (Soldering, 10 seconds) 260" Electrical Characteristics voo = sv + 10%, T = —40°C to +85°C unless otherwise stated. Symbol | Parameter [| Gonaitons [win Tye [Max [Unita Vin High Level Input v Voltage (except XTALIN) Vit Low Level Input v Voltage (except XTAL IN) Vou High Level Output lon = —20 pA Vpp - 0.1 v Voltage (080-083) fon = -1.6mA 37 v Vou High Level Output lon = —20 pA Vpp - 0.1 v Voltage (INT) (in Test Mode) Vou Low Level Output lo. = 20 pA v Voltage (080-DB3, jou = 1.6mA v INT) i Low Level input Current | Vin = Vgg (Note 2) BA (AD0-AD3, DBO-DB3) —[imapee [eres Te (WR, RD) (e3) lozH Ouput High Level Vout = Voo pA Leakage Current (INT) loo ‘Average Supply Current | All Vin = Voc or Open Circuit Vpp = 2.2V (Standby Mode) 10 BA Vo = 5.0V (Active Mode) 1 mA Cm | tnputcapactence [Ts Tt Cour (Oui Disable) ee ce ee ‘Note 1: Absolute Maximum Ratings ae those values beyond which damage to the device may occur. All voltages referenced lo ground unless otherwise noted. ‘Note 2: The DB0-D83 and ADO-ADS lines ail have active P-channel pul-up transistors which will source current. The CS, FID, and WF lines have intemal pull-up resistors 10 Voo 1-85
a
3 AC Switching Characteristics
8 READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR Vpp = 5V +0.5V, C, = 100 pF z =| symbol Specification Units Ta = —40°C to +85°C tao Address Bus Vali to Data Vaid re ee ee to Cp Slot nto Dla Val ee ‘ew Read Strobe With (Note 3, Note 7) re ee tra ‘Address Bus Hold Time from Trailing Edge ns of Read Strobe tes Chip Select Hold Time from Trailing Edge ns of Read Strobe tRH Data Hold Time from Trailing Edge 70 ns of Read Strobe tuz Time from Trailing Edge of Read Strobe ns Until O/P Drivers are TRI-STATE® WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL Voo = 5V +0.5V == Speciation Symbol n Unite Ta = —40°C to +85°C taw Address Bus Valid to Write Strobe ~ ns (Note 4, Note 6) tosw Chip SelectOniowite Strobe | __ aso | 10s tow DataBusVaidtownteswobe | aon | a0 || ww Wite Strobe With (Note 6) | aso | os ts twes Chip Select Hold Time Following ns Write Strobe twa Address Bus Hold Time Foliowing ns Write Strobe _~ two Data Bus Hoid Time Following 100 ns Write Strobe _~ taws Address Bus Valid Before 70 ns Start of Write Strobe Note 3: Excop or special case restcion: with inlerple programed, max read subs wih Of contol rqieter (ADDR 0) fs 80 ma Seo bacon on itera Programming. ‘Note 4: Ail timings measured to the trailing edge of write strobe (data latched by the trating edge of WR). Note 6 Input test wavelorm peak voltages are 2.4V and 0.4V. Output signal ae measured to thee 2.4V and 04V level Note 6: Write strobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low, ie., WS, = TS + WR. Hence write strobe commences when bot signals are low, and terminates when the fst signal returns High. Note 7: Read siobo as usod inthe lad Timing Taba is dined as he paiod when both chp select and rad inputs are low, WS = TS + FD Note &: Typical numbers ao at Voc = 5.0V and Ta ~ 25°C 1-86
Switching Time Waveforms z Read Cycle Timing (Notes 5 and 7) Fy aw ce, Sn. ae ) uv ‘ex + twa toe tea: on aS Few aw wm ony rE an" ee ur/s002-2 Write Cycle Timing (Notes 5 and 6) Py ne” ww ese ‘w aay a tees | F___oav ° _— “ (== 1) ew TUr/s002-4 Connection Diagrams Dual-in-Line Package z wy, az B Yoo IF l2ig Pe wB TALI 32 °1«-20 19 w ‘xTaL out N/omfa 18} XTAL OUT Nos: 17 Nt baad mr Des—6 16 N/C one 00 e247 159 AD0 oer aot wes 14f—ant me 02 910 11 12:13
1 AELE 1 |
Top View ‘TUF /5602-2 Top View FIGURE 2 Order Number MM58274CJ-12, MM58274CN-12 or MM58274CV-12 ‘See NS Package J16A, N16A, or V20A 1-87
offering extended timekeeping up to units and tens of years. of the chip. The 16-pin package outline is shown in Figure 2. when the device is in test mode. This allows for easy oscilla- the 32.768 kHz timekeeping oscillator circuit. only 3 bits) will return a logic 0 on any unused bits. When output. Nearest second, The time then updates every 100 ms with tion see the section on Test Mode. FIGURE 3. Typical System Connection Diagram
Functional Description (continued) Fe device which are synchronously clocked by this signal. All Both counters may be accessed for read or write operations | 3 time data and data-changed flag change on the falling edge as desired. rm Of the clock setting pulse. ‘The tens of hours register has only one active bit and the $ Data-Changed Flag {2p nro safe wat fo logic 0. Data bit 7 of the clock |S ‘The data. fag le set by the clock setting pulse to sating regia is te ‘AM/PM indicator; logic 0 indicating indicate that the time data has been altered since the clock M, - was last read. This flag occupies bit 3 of the control register Bit 0 of the clock setting register must be written to 0 for where it can be tested by the processor to sense data- ‘correct 12 hour operation. Soo to sector, "Methods of Device Operation’, fr aug, Dav8 Counters mn, “I ration”, for - . gested clock reading techniques using the lag ‘There are two days : 2) units of days Seconds Counters b) tons of days. There are three counters for seconds: ‘The days counters will count up to 28, 29, 30 or 31 depend- a) tenths of seconds ing on the state of the months counters and the leap year 1b) unis of seconde counter. The microprocessor has fl read/write access to ¢) tens of seconds. The registers are accessed at the addresses shown in Ta- Months Counters ble |. The tenths of seconds register is reset to 0 when the There are two months counters: clock start/stop bit (bit 2 of the control register) is set to a) units of months logic 1. Tho units and tens of seconde are eet up by the b) tens of months. roCcessor, ing time setting to nearest second. three registers cen be read by the provossor for ime cutpat Both these counters have full read/write access. Minutes Counters ‘Years Counters There are two minutes counters: There are two years counters: 4) units of minutes 8) unite of years b) tens of minutes. b) tons of years. . Both registers may be read to or written from as required. et ent ante oo ena aleve access. The years Hours Counters There are two hours counters: ) units of hours b) tens of hours. TABLE I. Address Decoding of ReakTime Clock internal Registers ReglsterSelected | ___———Addrona (Binary) | Aocess a ae ee
0 Control Register ° ° ° 0 0 Split Read and Write
1 Tenths of Seconds ° ° ° 1 1 Read Only
- Units Seconds 0 ° 1 ° 2 RW 3. Tens Seconds ° ° 1 1 3 RW
4 Units Minutes: o 1 0 i) 4 R/W
- Tens Minutes 0 1 ° 1 5 RW
6 Unit Hours ° 1 1 ° 6 RW
7 Tens Hours 0 1 1 1 7 RW
8 Units Days 1 ° ° ° 8 RW
9 Tens Days 1 o 0 1 9 R/W
10 Units Months 1 0 1 ° A RW
11 Tens Months 1 0 1 1 8 RW
- Units Years 1 1 ° 0 c RW 13° ‘Tens Years 1 1 ° 1 D R/W 1 |
14 Day of Wook 1 1 1 ° E RW
15 Clock Setting/ 1 1 1 1 F RW
a eS) Functional Description (continues) & | Day of Week Counter $8 | The day of week counter increments as the time rolts from ‘The AM/PM indicator returns a logic 0 for AM and a logic 1 SS | (14:59 PM to 12:00 AM). It counts from 1 to 7 and rolls back for PM. Itis clocked when the hours counter rolls from 11:59 =| to 1. Any day of the week may be specified as day 1. to 12:00. Clock Setting Register/interrupt Register The 12-hour mode bit is set to logic 0 for 12-hour mode, The interrupt select bit in the control register determines logic 1 is illegal. which of these two registers is accessible to the processor IMPORTANT NOTE: Hours mode and AM/PM bits cannot at address 15, Normal clock and interrupt timing operations be set in the same write operation. See the section on \\ni- will always continue regardless of which register is selected tialization (Methods of Device Operation) for a suggested onto the bus. The layout of these registers is shown in setting routine. Table Il. All bits in the clock setting register may be read by the proc- The clock setting register is comprised of three separate essor. functions: The interrupt register controls the operation of the timer for a) leap year counter: bits 2 and 3 interrupt output. The processor programs this register for of this register ime delay ©) 12-hour mode set: bit 0 (see Table IIA). that will occur between interrupts. The time delays that can The leap year counter is a 2-stage binary counter which be programmed and the data words that select these are is clocked by the months counter. it changes state as the outlined in Table IIB. Saeueny 1 fom 1189 on December 31 to 00:00 on Data bit 3 of the i pt register sets for either single or . repeated interrupts; logic 0 gives single mode, logic 1 sets The counter should be loaded with the ‘number of years (erropeated meade eee since last leap year’ 0.9, if 1980 was the last leap year, a i , , ‘i clock programmed in 1983 should have 3 stored in the leap {sing the Interrupts described in the Device Operation 2ec- year counter. If the clock is programmed during a leap year, then the leap year counter should be set to 0. The contents of the leap year counter can be read by the pP. TABLE IIA. Clock Setting Register Layout Function Data Bits Used Access Leap Year Counter x O Indicates a Leap Year RW ‘AM/PM Indicator O0=AM 1=PM RW 12-Hour Bit x 0 = 12-Hour Mode RW 1 = Illegal TABLE IIB. Interrupt Control Register Control Word ‘nets [es [ose | par | eo No Interrupt Interrupt output cleared, x 0 o o start/stop bit set to 1.
0.1 Second on 0 0 1
0.5 Second ont 0 1 0
fSecond DBS = Ofori . on : 1 $ Seconds DB3 = 1 for repeated interrupt °
10 Seconds ont 1 o 1
30 Seconds ot 1 1 °
60 Seconds ot 1 1 1
Timing Accuracy: single interrupt mode (all time delays): + 1 ms Repeated Mode: + 1 ms on intial timeout, thereafter synchronous with first interrupt (.., timing errors do not accumulate). 1-90
Functional Description (continue z Control Register A logic 0 in the interrupt select bit makes the clock setting | RR There are three registers which control different operations register available to the processor. A logic 1 selects the of the : interrupt register. en sting roak The interrupt start/stop bit controls the running of the inter- | 5S a) the clock setting register rupt timer. It is programmed in the same way as the clock | ™ 'b) the interrupt register start/stop bit; logic 1 to halt the interrupt and reset the tim- ¢) the control register. er, logic 0 to start interrupt timing. The clock setting and interrupt registers both reside at ad- When no interrupt is programmed (interrupt control register dress 15, access to one or the other being controlled by the set to 0), the interrupt start/stop bit is automatically set to a interrupt select bit; data bit 1 of the controt register. logic 1. When any new interrupt is subsequently pro- The clock setting register programs the timekeeping of the grammed, timing will not commence until the start/stop bit clock. The 12-hour mode and the AM/PM indicator occupy is loaded with 0. bits 0 and 1, respectively. Data bits 2 and 3 set the leap year In the single interrupt mode, interrupt timing stops when a counter. timeout ocours. The processor restarts timing by writing log- The interrupt register controls the operation of the interrupt ic 0 into the start/stop bit. timer, selecting the required delay period and either single In repeated interrupt mode the interrupt timer continues to oF repeated interrupt. count with no intervention by the processor necessary. The control register is responsible for controlling the opera- Interrupt timing may be stopped in either mode by writing a tions of the clock and supplying status information to the logic 1 into the interrupt start/stop bit. The timer is reset and Processor. It appears as two different registers; one with can be restarted in the normal way, giving a full time delay write only access and one with read only access. Period before the next interrupt. The write only register consists of a bank of four latches {In general, the control register is set up such that writing 0's which control the internal processes of the clock. into it will start anything that is stopped, pull the clock out of The read only register contains two output data latches test mode and select the clock setting register onto the bus. which will supply status information for the processor. Table In other words, writing 0 will maintain normal clock operation I shows the mapping of the various contro! latches and and restart interrupt timing, etc. status flags in the control register. The control register is The read only portion of the control register has two status located at address 0. outputs: The write only portion of the control register contains four Since the MM58274C-12 keeps real time, the time data latches: changes asynchronously with the processor and this may A logic 1 written into the test bit puts the device into test ‘occur while the processor is reading time data out of the mode. This allows setting of the oscillator frequency as well clock. as rapid testing of the device registers, if required. A more ‘Some method of waming the processor when the time data complete description is given in the Test Mode section. For has changed must thus be included. This is provided for by normal operation the test bit is loaded with logic 0. the data-changed flag located in bit 3 of the control register. The clock start/stop bit stops the timekeeping of the clock This flag is set by the clock setting pulse which also clocks and resets to 0 the tenths of seconds counter. The time of the time registers. Testing this bit can tell the processor day may then be written into the various clock registers and whether or not the time has changed. The flag is cleared by the clock restarted synchronously with an external time read of the control register but not by any write operations. source. Timekeeping is maintained thereafter. No other register read has any effect on the state of the A logic 1 written to the start/stop bit halts clock timing. Tim- data-changed flag. - ing is restarted when the start/stop bit is written with a logic Data bit 0 is the interrupt flag. This flag is set whenever the 0. interrupt timer times out, pulling the interrupt output low. In a A 5 polled interrupt routine the processor can test this flag to ine aves Soret determines wiih Of ine THO Togs determine if the MMS8274C-12 was the interrupting device. address b selected This interrupt flag and the interrupt output are both cleared 7 by a read of the control register. TABLE Ill. The Control Register Layout Access(eadroy) [ops [se Toms Bo Rad From: DataCrangodFiag | of ttt Fag Write To: Test Clock Start/Stop Interrupt Select Interrupt Start/Stop 0 = Normal 0 = Clock Run 0 = Clock Setting Register 0 = Interrupt Run 1 = Test Mode 1. = Glock Stop 1 = Interrupt Register 1 = Interrupt Stop 1-91
then go low only after the read has been completed. onto the interrupt output. will not affect the data-changed flag since time data read the oscillator is buttered out onto the interrupt line. National rT uses test for functic .
4 Leap Years and AM/PM bit) may now be loaded in any
gated onto the interrupt output to provide a buffered output not be altered from the value programmed in step 5. If an interrupt is programmed, the 32.768 kHz output is Sours. are recommended when the device is set up (all numbers (Gata-changed flag set). FIGURE 4. Test Mode Organization
Functional Description (continues) a Reading the Time Registers 8 Using the data-changed flag technique supports microproc- ‘Single interrupt Mode: tJ ‘essors with block move facilities, as all the necessary time When appropriate, write 0 or 2 to the control register to | data may be read sequentially and then tested for validity as restart the interrupt timer. »® 1) Rend te trol register, address 0: This is a dummy Repesiod Intorupt Mode: control register, address 0: This is a dummy Te m ° ming continues, synchronized with the control register Fra, weet the date-changed fag (OCF) prior to reading write which originally started interrupt timing. No further in- registers. tervention is necessary from the processor to maintain tim- 2) Read time registers: All desired time registers are reed ing. . In either mode interrupt timing can be stopped by writing 1 3) Read the control register and test DCF: /f DCF is cleared into the control register (interrupt start/stop set to 1). Timing (logic 0), then no clock setting pulses have after occurred for the full delay period recommences when the interrupt ‘Since step 1. All time data is guaranteed good and time start/stop bit is again loaded with 0 as normal. reading is complete. IMPORTANT NOTE: Using the interrupt timer places a con- \\t DCF is set (logic 1), then a time change has occurred straint on the maximum Read Strobe width which may be since step 1 and time data may not be consistent. Repeat ‘applied to the clock. Normally all registers may be read from steps 2 and 3 until DCF is clear. The control read of step 3 with a taw down to DC (.e., CS and RID held continuously will have reset DCF, automatically repeating the step 1 ac- Jow). When the interrupt timer is active however, the maxi- tion. mum read strobe width that can be applied to the control m "a This rect Mo aom the interrupt timer to property re- The interrupt timer generates interrupts at time intervals ‘s which are programmed into the interrupt register. A single ‘set when it times out. Note thet It only affects reading of the interrupt after delay or repeated interrupts may be pro- control register—all other addresses in the clock may be grammed. Table IIB lists the different time delays and the accessed with DC read strobes, regardiass of the state of data words that select them in the interrupt register. the interrupt timer. Writes to any address are unaffected. Onoe the interrupt register has been used to set up the NOTES ON AC TIMING REQUIREMENTS delay time and to select for single or repeat, it takes no Although the Switching Time Waveforms show Microbus further part in the workings of the interrupt system. All activi- control signals used for clock access, this does not pre- ty by the processor then takes place in the control register. clude the use of the MM56274C-12 in other non-Microbus Initializing: systems. Figure 5's a simplified logic diagram showing how 1) Write 3 to the control register (ADO): Clock timing contin- the control Sires a gate ema We cont piaharen cS ues, interrupt register selected and interrupt timing stopped. the clock registers. From diagram it is 4 . i could be used to generate the internal data transfer strobes, 2) Write interrupt control word to address 15: The interrupt ‘with FD and WR inputs sot up fst. This situation is Muster: register is loaded with the correct word (chosen from Table ed in Figure 6. . The stunt time delay required and for single or repeat ‘igure 6. inonoote ” ann © repeated ‘The interna! data busses of the MM58274C-12 are fully 3) Write 0 oF 2 to the control ré Int t timing com- ‘CMOS, contributing to the flexibility of the control inputs. Viting ? eclent tho coat notte ‘When determining the suitability of any given control signal Wiehe ing pape ia aten aid Oo ae pattern for the MM58274C-12 the timing specifications in Normal pack ves Wind regis! Z ‘AC Switching Characteristics should be examined. As long feeping remains unal Z ‘as these timings are mat (or exceeded) the MMS6274C-12 On Interrupt: will function correctly. Read the control register and test for Interrupt Flag (bit 0). ‘When the MM58274C-12 is connected to the system via a If the flag is cleared (logic 0), then the device is not the peripheral port, the freedom from timing constraints allows source of the interrupt. for very simple control signal tion, as in Figure 7. For San if the flag is set (logic 1), then the clock did generate an reading (Figure 7a), Address, CS and RD may be activated interrupt. The flag is reset and the interrupt output is cleared ‘simultaneously and the data will be available at the port by the control register read that was used to test for inter- after tap-max (650 ns). For writing (Figure 76), the address rupt. and data may be applied simultaneously; 70 ns later CS and WR may be strobed together. 1-93
8 Functional Description (continues)
FIGURE 5. MM58274C-12 Microprocessor Interface Diagram FIGURE 6. Valid MM58274C-12 Control Signals Using Chip Select Generated Access Strobes
FIGURE 7. Simple Port Generated Control Signals
a
3 Functional Description (continues)
5 APPLICATION HINTS the dats charged tag: ADO Thi is a dummy read to reset
8 rm oe nah et nontet nal terminals and deta 3) Read control register ADO unti data-changed flag is set. in systems as inals. ita loggers, " | time reading is usually only required on a random demand 4) ie 0 or 2 to control register. Interrupt ting, co basis. Using the data-changed flag as outlined in the section ‘ on methods of operation is ideal for this type of system. Time Reading with Very Siow Read Cycles Some systems, however, need to sense a change in real Ifa system takes longer than 100 ms to complete reading of time; e.g., industrial timers/process controllers, TV/VCR all the necessary time registers (e.g., when CMOS proces- clocks, any system where real time is displayed. ‘sors are used) or where high level interpreted language rou- ‘The interrupt timer on the MM58274C-12 can generate in- tines are used, then the data-changed flag will always be set terupts synchronously with the time registers changing, us- when tested and is of no value. In this case, the time regis- ing software to provide the initial synchronization. ters themselves must be tested to ensure data accuracy. In single interrupt mode the processor is responsible for ini- The technique below will detect both time changing be- tiating each timing cycle and the timed period is accurate to tween read strobes (.6., between reading tons of minutes £1 ms, and units of hours) and also time changing during read, In repeated interrupt mode the period from the initial proces- which can produce invalid data. Sor start to the first timeout is also only accurate to +1 ms. 1) Read and store the value of the /owest order time register The following interrupts maintain accurate delay periods rel- required. ative to the first timeout. Thus, to utilize interrupt to control 2) Read out all the time registers required. The registers time reading, we will use repeated interrupt mode. may be read out in any order, simplifying software require- In repeated mode the time period between interrupts is ex- ments. act, which means that timeouts will always occur at the 9) Read the lowest order register and compare it with the ‘same point relative to the internal clock setting pulses. The value stored previously in step 1. If it is still the same, then case for 0.18 interrupts is shown in Figure A-1. The same is all time data is good. If it has changed, then store the new true for other delay periods, only there will be more clock value and go back to step 2. setting pulses between each interrupt timeout. If we set up In general, the rule is that the first and last reads must both the interupt timer so that interupt always times out just of tho lowest order time register. These two values can after the clock setting pulse ocours (Figure A-2), then there then be compared to ensure that no change has occurred. is no need to test the data-changed fiag as we know that This technique works because for any higher order time reg. the time data has just changed and will not alter again for istor to change, all the lower order registers must also another 100 ms. change. If the lowest order register does not change, then This can be achieved as outlined below: no higher order register has changed either. 1) Follow steps 1 and 2 of the section on interrupt program- ming. In step 2 set up for repeated interrupt. 10m Plies INTERNAL CLOCK SETTING PULSES ‘oeay—+ tory (WTERRUPT oP | tenure =) ennurr SERVICED SERVICED TUF/se02-11 FIGURE A-1. Time Delay from Clock Setting Pulses to Interrupt is Constant [100 m ay INTERNAL cLocK. ‘SETTING ‘PULSES INTERRUPT or TUF 8602-12 FIGURE A-2. Interrupt Timer Synchronized with Clock Setting Pulses 1-96