MM58274CN

MM58274C NSC | Alldatasheet

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Y Same pin-out as MM58174A, MM58274B, and MM58274 Y Timekeeping from tenths of seconds to tens of years in independently accessible registers Y Leap year register Y Hours counter programmable for 12 or 24-hour operation Y Buffered crystal frequency output in test mode for easy oscillator setting Y Data-changed flag allows simple testing for time rollover Y Independent interrupting time with open drain output Y Fully TTL compatible Y Low power standby operation (10 mA at 2.2V) Y Low cost 16-pin DIP and 20-pin PCC Block Diagram TL/F/11219–1 FIGURE 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corp. MicrobusTM is a trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. DC Input or Output Voltage b0.3V to V DD a 0.3V DC Input or Output Diode Current g5.0 mA Storage Temperature, T STG b65§Ct o a150§C Supply Voltage, V DD 6.5V Power Dissipation, P D 500 mW Lead Temperature (Soldering, 10 seconds) 260 § Operating Conditions Min Max Units Operating Supply Voltage 4.5 5.5 V Standby Mode Supply Voltage 2.2 5.5 V DC Input or Output Voltage 0 V DD V Operating Temperature Range b40 85 §C Electrical Characteristics VDD e 5V g10%, T eb 40§Ct o a85§C unless otherwise stated. Symbol Parameter Conditions Min Typ Max Units VIH High Level Input 2.0 V Voltage (except XTAL IN) VIL Low Level Input 0.8 V Voltage (except XTAL IN) VOH High Level Output I OH eb 20 mAV DD b 0.1 V Voltage (DB0–DB3) I OH eb 1.6 mA 3.7 V VOH High Level Output I OH eb 20 mAV DD b 0.1 V Voltage (INT) (In Test Mode) VOL Low Level Output I OL e 20 mA 0.1 V Voltage (DB0–DB3, i OL e 1.6 mA 0.4 V INT) IIL Low Level Input Current V IN e VSS (Note 2) b5 b80 mA (AD0–AD3, DB0–DB3) IIL Low Level Input Current V IN e VSS (Note 2) b5 b190 mA (WR,R D ) IIL Low Level Input Current V IN e VSS (Note 2) b5 b550 mA (CS) IOZH Ouput High Level V OUT e VDD 2.0 mA Leakage Current (INT ) IDD Average Supply Current All V IN e VCC or Open Circuit VDD e 2.2V (Standby Mode) 4 10 mA VDD e 5.0V (Active Mode) 1 mA CIN Input Capacitance 5 10 pF COUT Output Capacitance (Outputs Disabled) 10 pF Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. All voltages referenced to ground unless otherwise noted. Note 2: The DB0–DB3 and AD0–AD3 lines all have active P-channel pull-up transistors which will source current. The CS ,R D , and WR lines have internal pull-up resistors to V DD.

AC Switching Characteristics READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR VDD e 5V g0.5V, C L e 100 pF Commercial Symbol Parameter Specification Units TA eb 40§Ct o a85§C Min Typ Max tAD Address Bus Valid to Data Valid 390 650 ns tCSD Chip Select On to Data Valid 140 300 ns tRD Read Strobe On to Data Valid 140 300 ns tRW Read Strobe Width (Note 3, Note 7) DC tRA Address Bus Hold Time from Trailing Edge 0 ns of Read Strobe tCSH Chip Select Hold Time from Trailing Edge 0 ns of Read Strobe tRH Data Hold Time from Trailing Edge 70 160 ns of Read Strobe tHZ Time from Trailing Edge of Read Strobe 250 ns Until O/P Drivers are TRI-STATE É WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL VDD e 5V g0.5V Commercial Symbol Parameter Specification Units TA eb 40§Ct o a85§C Min Typ Max tAW Address Bus Valid to Write Strobe O 400 125 ns (Note 4, Note 6) tCSW Chip Select On to Write Strobe O 250 100 ns tDW Data Bus Valid to Write Strobe O 400 220 ns tWW Write Strobe Width (Note 6) 250 95 ns tWCS Chip Select Hold Time Following 0 ns Write Strobe O tWA Address Bus Hold Time Following 0 ns Write Strobe O tWD Data Bus Hold Time Following 100 35 ns Write Strobe O tAWS Address Bus Valid Before 70 20 ns Start of Write Strobe Note 3: Except for special case restriction: with interrupts programmed, max read strobe width of control register (ADDR 0) is 30 ms. See section on Interrupt Programming. Note 4: All timings measured to the trailing edge of write strobe (data latched by the trailing edge of WR ). Note 6: Write strobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low, ie., WS , e CS a WR. Hence write strobe commences when both signals are low, and terminates when the first signal returns high. Note 7: Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low, ie., RS e CS a RD. Note 8: Typical numbers are at V CC e 5.0V and T A e 25§C.

Read Cycle Timing (Notes 5 and 7) TL/F/11219–2 Write Cycle Timing (Notes 5 and 6) TL/F/11219–3 Connection Diagrams Dual-In-Line Package TL/F/11219–4 Top View TL/F/11219–5 Top View FIGURE 2 Order Number MM58274CJ, MM58274CN or MM58274CV See NS Package J16A, N16A, or V20A

Functional Description (Continued) device which are synchronously clocked by this signal. All time data and data-changed flag change on the falling edge of the clock setting pulse. Data-Changed Flag The data-changed flag is set by the clock setting pulse to indicate that the time data has been altered since the clock was last read. This flag occupies bit 3 of the control register where it can be tested by the processor to sense data- changed. It will be reset by a read of the control register. See the section, ‘‘Methods of Device Operation’’, for sug- gested clock reading techniques using this flag. Seconds Counters There are three counters for seconds: a) tenths of seconds b) units of seconds c) tens of seconds. The registers are accessed at the addresses shown in Ta- ble I. The tenths of seconds register is reset to 0 when the clock start/stop bit (bit 2 of the control register) is set to logic 1. The units and tens of seconds are set up by the processor, giving time setting to the nearest second. All three registers can be read by the processor for time output. Minutes Counters There are two minutes counters: a) units of minutes b) tens of minutes. Both registers may be read to or written from as required. Hours Counters There are two hours counters: a) units of hours b) tens of hours. Both counters may be accessed for read or write operations as desired. In 12-hour mode, the tens of hours register has only one active bit and the top three bits are set to logic 0. Data bit 1 of the clock setting register is the AM/PM indicator; logic 0 indicating AM, logic 1 for PM. When 24-hour mode is programmed, the tens of hours reg- ister reads out two bits of data and the two most significant bits are set to logic 0. There is no AM/PM indication and bit 1 of the clock setting register will read out a logic 0. In both 12/24-hour modes, the units of hours will read out four active data bits. 12 or 24-hour mode is selected by bit 0 of the clock setting register, logic 0 for 12-hour mode, logic 1 for the 24-hour mode. Days Counters There are two days counters: a) units of days b) tens of days. The days counters will count up to 28, 29, 30 or 31 depend- ing on the state of the months counters and the leap year counter. The microprocessor has full read/write access to these registers. Months Counters There are two months counters: a) units of months b) tens of months. Both these counters have full read/write access. Years Counters There are two years counters: a) units of years b) tens of years. Both these counters have full read/write access. The years will count up to 99 and roll over to 00. TABLE I. Address Decoding of Real-Time Clock Internal Registers Register Selected Address (Binary) (Hex) Access AD3 AD2 AD1 AD0

0 Control Register 0 0 0 0 0 Split Read and Write

1 Tenths of Seconds 0 0 0 1 1 Read Only

2 Units Seconds 0 0 1 0 2 R/W

3 Tens Seconds 0 0 1 1 3 R/W

4 Units Minutes 0 1 0 0 4 R/W

5 Tens Minutes 0 1 0 1 5 R/W

6 Unit Hours 0 1 1 0 6 R/W

7 Tens Hours 0 1 1 1 7 R/W

8 Units Days 1 0 0 0 8 R/W

9 Tens Days 1 0 0 1 9 R/W

10 Units Months 1 0 1 0 A R/W

11 Tens Months 1 0 1 1 B R/W

12 Units Years 1 1 0 0 C R/W

13 Tens Years 1 1 0 1 D R/W

14 Day of Week 1 1 1 0 E R/W

15 Clock Setting/ 1 1 1 1 F R/W

Functional Description (Continued) Day of Week Counter The day of week counter increments as the time rolls from 23:59 to 00:00 (11:59 PM to 12:00 AM in 12-hour mode). It counts from 1 to 7 and rolls back to 1. Any day of the week may be specified as day 1. Clock Setting Register/Interrupt Register The interrupt select bit in the control register determines which of these two registers is accessible to the processor at address 15. Normal clock and interrupt timing operations will always continue regardless of which register is selected onto the bus. The layout of these registers is shown in Table II. The clock setting register is comprised of three separate functions: a) leap year counter: bits 2 and 3 b) AM/PM indicator: bit 1 c) 12-hour mode set: bit 0 (see Table IIA). The leap year counter is a 2-stage binary counter which is clocked by the months counter. It changes state as the time rolls over from 11:59 on December 31 to 00:00 on January 1. The counter should be loaded with the ‘number of years since last leap year’ e.g., if 1980 was the last leap year, a clock programmed in 1983 should have 3 stored in the leap year counter. If the clock is programmed during a leap year, then the leap year counter should be set to 0. The contents of the leap year counter can be read by the mP. The AM/PM indicator returns a logic 0 for AM and a logic 1 for PM. It is clocked when the hours counter rolls from 11:59 to 12:00 in 12-hour mode. In 24-hour mode this bit is set to logic 0. The 12/24-hour mode set determines whether the hours counter counts from 1 to 12 or from 0 to 23. It also controls the AM/PM indicator, enabling it for 12-hour mode and forc- ing it to logic 0 for the 24-hour mode. The 12/24-hour mode bit is set to logic 0 for 12-hour mode and it is set to logic 1 for 24-hour mode. IMPORTANT NOTE: Hours mode and AM/PM bits cannot be set in the same write operation. See the section on Ini- tialization (Methods of Device Operation) for a suggested setting routine. All bits in the clock setting register may be read by the proc- essor. The interrupt register controls the operation of the timer for interrupt output. The processor programs this register for single or repeated interrupts at the selected time intervals. The lower three bits of this register set the time delay period that will occur between interrupts. The time delays that can be programmed and the data words that select these are outlined in Table IIB. Data bit 3 of the interrupt register sets for either single or repeated interrupts; logic 0 gives single mode, logic 1 sets for repeated mode. Using the interrupt is described in the Device Operation sec- tion. TABLE IIA. Clock Setting Register Layout Function Data Bits Used Comments Access DB3 DB2 DB1 DB0 Leap Year Counter X X 0 Indicates a Leap Year R/W AM/PM Indicator (12-Hour Mode) X 0 e AM 1 e PM R/W 0 in 24-Hour Mode 12/24-Hour Select Bit X 0 e 12-Hour Mode R/W 1 e 24-Hour Mode TABLE IIB. Interrupt Control Register Function Comments Control Word DB3 DB2 DB1 DB0 No Interrupt Interrupt output cleared, X 0 0 0 start/stop bit set to 1.

0.1 Second 0/1 0 0 1

0.5 Second 0/1 0 1 0

1 Second DB3 e 0 for single interrupt 0/1 0 1 1

5 Seconds DB3 e 1 for repeated interrupt 0/1 1 0 0

10 Seconds 0/1 1 0 1

30 Seconds 0/1 1 1 0

60 Seconds 0/1 1 1 1

Timing Accuracy: single interrupt mode (all time delays): g1m s Repeated Mode: g1 ms on initial timeout, thereafter synchronous with first interrupt (i.e., timing errors do not accumulate).

Functional Description (Continued) Control Register There are three registers which control different operations of the clock: a) the clock setting register b) the interrupt register c) the control register. The clock setting and interrupt registers both reside at ad- dress 15, access to one or the other being controlled by the interrupt select bit; data bit 1 of the control register. The clock setting register programs the timekeeping of the clock. The 12/24-hour mode select and the AM/PM indica- tor for 12-hour mode occupy bits 0 and 1, respectively. Data bits 2 and 3 set the leap year counter. The interrupt register controls the operation of the interrupt timer, selecting the required delay period and either single or repeated interrupt. The control register is responsible for controlling the opera- tions of the clock and supplying status information to the processor. It appears as two different registers; one with write only access and one with read only access. The write only register consists of a bank of four latches which control the internal processes of the clock. The read only register contains two output data latches which will supply status information for the processor. Table III shows the mapping of the various control latches and status flags in the control register. The control register is located at address 0. The write only portion of the control register contains four latches: A logic 1 written into the test bit puts the device into test mode. This allows setting of the oscillator frequency as well as rapid testing of the device registers, if required. A more complete description is given in the Test Mode section. For normal operation the test bit is loaded with logic 0. The clock start/stop bit stops the timekeeping of the clock and resets to 0 the tenths of seconds counter. The time of day may then be written into the various clock registers and the clock restarted synchronously with an external time source. Timekeeping is maintained thereafter. A logic 1 written to the start/stop bit halts clock timing. Tim- ing is restarted when the start/stop bit is written with a logic The interrupt select bit determines which of the two regis- ters mapped onto address 15 will be accessed when this address is selected. A logic 0 in the interrupt select bit makes the clock setting register available to the processor. A logic 1 selects the interrupt register. The interrupt start/stop bit controls the running of the inter- rupt timer. It is programmed in the same way as the clock start/stop bit; logic 1 to halt the interrupt and reset the tim- er, logic 0 to start interrupt timing. When no interrupt is programmed (interrupt control register set to 0), the interrupt start/stop bit is automatically set to a logic 1. When any new interrupt is subsequently pro- grammed, timing will not commence until the start/stop bit is loaded with 0. In the single interrupt mode, interrupt timing stops when a timeout occurs. The processor restarts timing by writing log- ic 0 into the start/stop bit. In repeated interrupt mode the interrupt timer continues to count with no intervention by the processor necessary. Interrupt timing may be stopped in either mode by writing a logic 1 into the interrupt start/stop bit. The timer is reset and can be restarted in the normal way, giving a full time delay period before the next interrupt. In general, the control register is set up such that writing 0’s into it will start anything that is stopped, pull the clock out of test mode and select the clock setting register onto the bus. In other words, writing 0 will maintain normal clock operation and restart interrupt timing, etc. The read only portion of the control register has two status outputs: Since the MM58274C keeps real time, the time data changes asynchronously with the processor and this may occur while the processor is reading time data out of the clock. Some method of warning the processor when the time data has changed must thus be included. This is provided for by the data-changed flag located in bit 3 of the control register. This flag is set by the clock setting pulse which also clocks the time registers. Testing this bit can tell the processor whether or not the time has changed. The flag is cleared by a read of the control register but not by any write operations. No other register read has any effect on the state of the data-changed flag. Data bit 0 is the interrupt flag. This flag is set whenever the interrupt timer times out, pulling the interrupt output low. In a polled interrupt routine the processor can test this flag to determine if the MM58274C was the interrupting device. This interrupt flag and the interrupt output are both cleared by a read of the control register. TABLE III. The Control Register Layout Access (addr0) DB3 DB2 DB1 DB0 Read From: Data-Changed Flag 0 0 Interrupt Flag Write To: Test Clock Start/Stop Interrupt Select Interrupt Start/Stop 0 e Normal 0 e Clock Run 0 e Clock Setting Register 0 e Interrupt Run 1 e Test Mode 1 e Clock Stop 1 e Interrupt Register 1 e Interrupt Stop

FIGURE 7. Simple Port Generated Control Signals

Functional Description (Continued) APPLICATION HINTS Time Reading Using Interrupt In systems such as point of sale terminals and data loggers, time reading is usually only required on a random demand basis. Using the data-changed flag as outlined in the section on methods of operation is ideal for this type of system. Some systems, however, need to sense a change in real time; e.g., industrial timers/process controllers, TV/VCR clocks, any system where real time is displayed. The interrupt timer on the MM58274C can generate inter- rupts synchronously with the time registers changing, using software to provide the initial synchronization. In single interrupt mode the processor is responsible for ini- tiating each timing cycle and the timed period is accurate to g1 ms. In repeated interrupt mode the period from the initial proces- sor start to the first timeout is also only accurate to g1 ms. The following interrupts maintain accurate delay periods rel- ative to the first timeout. Thus, to utilize interrupt to control time reading, we will use repeated interrupt mode. In repeated mode the time period between interrupts is ex- act, which means that timeouts will always occur at the same point relative to the internal clock setting pulses. The case for 0.1s interrupts is shown in Figure A-1 . The same is true for other delay periods, only there will be more clock setting pulses between each interrupt timeout. If we set up the interrupt timer so that interrupt always times out just after the clock setting pulse occurs ( Figure A-2 ), then there is no need to test the data-changed flag as we know that the time data has just changed and will not alter again for another 100 ms. This can be achieved as outlined below: 1) Follow steps 1 and 2 of the section on interrupt program- ming. In step 2 set up for repeated interrupt. 2) Read control register AD0: This is a dummy read to reset the data-changed flag. 3) Read control register AD0 until data-changed flag is set. 4) Write 0 or 2 to control register. Interrupt timing com- mences. Time Reading with Very Slow Read Cycles If a system takes longer than 100 ms to complete reading of all the necessary time registers (e.g., when CMOS proces- sors are used) or where high level interpreted language rou- tines are used, then the data-changed flag will always be set when tested and is of no value. In this case, the time regis- ters themselves must be tested to ensure data accuracy. The technique below will detect both time changing be- tween read strobes (i.e., between reading tens of minutes and units of hours) and also time changing during read, which can produce invalid data. 1) Read and store the value of the lowest order time register required. 2) Read out all the time registers required. The registers may be read out in any order, simplifying software require- ments. 3) Read the lowest order register and compare it with the value stored previously in step 1. If it is still the same, then all time data is good. If it has changed, then store the new value and go back to step 2. In general, the rule is that the first and last reads must both be of the lowest order time register. These two values can then be compared to ensure that no change has occurred. This technique works because for any higher order time reg- ister to change, all the lower order registers must also change. If the lowest order register does not change, then no higher order register has changed either. TL/F/11219–12 FIGURE A-1. Time Delay from Clock Setting Pulses to Interrupt is Constant TL/F/11219–13 FIGURE A-2. Interrupt Timer Synchronized with Clock Setting Pulses

Physical Dimensions inches (millimeters) Cavity Dual-In-Line Package (J) Order Number MM58274CJ Molded Dual-In-Line Package (N) Order Number MM58274CN

MM58274C Microprocessor Compatible Real Time Clock Physical Dimensions inches (millimeters) (Continued) Plastic Chip Carrier (V) Order Number MM58274CV LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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