MM58167

MM58167B NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

Features

Y Microprocessor compatible (8-bit data bus) Y Milliseconds through month counters Y 56 bits of RAM with comparator to compare the real time counter to the RAM data Y 2 INTERRUPT OUTPUTS with 8 possible interrupt signals Y POWER DOWN input that disables all inputs and out- puts except for one of the interrupts Y Status bit to indicate rollover during a read Y 32.768 kHz crystal oscillator Y Four-year calendar (no leap year) Y 24-hour clock Connection Diagrams Dual-In-Line Package TL/F/11070–1 Top View Order Number MM58167BN See NS Package Number N24A TL/F/11070–2 Top View Order Number MM58167BV See NS Package Number V28A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at All Pins V SS b 0.3V to V DD a 0.3V Operating Temperature 0 §Ct o7 0 §C Storage Temperature b65§Ct o a150§C VDDbVSS 6.0V Lead Temperature (Soldering, 10 sec.) 300 §C Electrical Characteristics VSS e 0V, 0 §C s TA s 70§C Parameter Conditions Min Max Units Supply Voltage VDD Outputs Enabled 4.5 5.5 V VDD POWER DOWN Mode 2.2 5.5 V Supply Current IDD, Dynamic Outputs TRI-STATE É fIN e 32.768 kHz, V DD e 5.5V 20 mAVIH t VDD b 0.3V VIL s VSS a 0.3V IDD, Dynamic Outputs TRI-STATE fIN e 32.768 kHz, V DD e 5.5V 5 mA VIH e 2.0V, V IL e 0.8V Input Voltage Logical Low 0.0 0.8 V Logical high 2.0 V DD V Input Leakage Current V SS s VIN s VDD b11 mA Output Impedance I/O and INTERRUPT OUT Logical Low V DD e 4.5V, I OL e 1.6 mA 0.4 V Logical High V DD e 4.5V, I OH eb 400 mA 2.4 V IOH eb 10 mA 0.8 V DD V TRI-STATE V SS s VOUT s VDD b11 mA Output Impedance RDY and STANDBY INTERRUPT (Open Drain Devices) Logical Low, Sink V DD e 4.5V, I OL e 1.6 mA 0.4 V Logical High, Leakage V OUT s VDD 10 mA

The real time counter is divided into 4-bit digits with 2 digits being accessed during any read or write cycle. Each digit represents a BCD number and is defined in Table I. Any unused bits are held at a logical zero during a read and ignored during a write. An unused bit is any bit not neces- sary to provide a full BCD number. For example tens of hours cannot legally exceed the number 2, thus only 2 bits are necessary to define the tens of hours. The other 2 bits in the tens of hours digit are unused. The unused bits are des- ignated in Table I as dashes. The addressable portion of the counter is from milliseconds to months. The counter itself is a ripple counter. The ripple delay is less than 60 ms above 4.5V and 300 ms at 2.2V. RAM 56 bits of RAM are contained on-chip. These can be used for any necessary power down storage or as an alarm latch for comparison to the real time counter. The data in the RAM can be compared to the real time counter on a digit basis. The only digits that are not compared are the unit ten thousandths of seconds and tens of days of the week (these are unused in the real time counter). If the two most significant bits of any RAM digit are ones, then this RAM location will always compare. The rule of thumb for an ‘‘alarm’’ interrupt is: All nibbles of higher order than speci- fied are set to C hex (always compare). All nibbles lower than specified are set to ‘‘zero’’. As an example, if an alarm is to occur everyday at 10:15 a.m., configure the bits in RAM as shown in Table II. The RAM is formatted the same as the real time counter, 4 bits per digit, 14 digits, however there are no unused bits. The unused bits in the real time counter will compare only to zeros in the RAM. An address map is shown in Table III. Interrupts and Comparator There are two interrupt outputs. The first is the INTERRUPT OUTPUT (a true high signal). This output can be pro- grammed to provide 8 different output signals. They are:

10 Hz, once per second, once per minute, once per hour,

once a day, once a week, once a month, and when a RAM/ real time counter comparison occurs. To enable the output a one is written into the interrupt control register at the bit location corresponding to the desired output frequency ( Fig- ure 1 ). Once one or more bits have been set in the interrupt control register, the corresponding counter’s rollover to its reset state will clock the interrupt status register and cause the interrupt output to go high. To reset the interrupt and to identify which frequency caused the interrupt, the interrupt status register is read. Reading this register places the con- tents of the status register on the data bus. The interrupting frequency will be identified by a one in the respective bit position. Removing the read will reset the interrupt. The second interrupt is the STANDBY INTERRUPT (open drain output, active low). This interrupt occurs when enabled and when a RAM/real time counter comparison occurs. The STANDBY INTERRUPT is enabled by writing a one on the D0 line at address 16 H or disabled by writing a zero on the D0 line. This interrupt is not triggered by the edge of the compare signal, but rather by the level. Thus if the compare is enabled when the STANDBY INTERRUPT is enabled, the interrupt will turn on immediately. TABLE I. Real Time Counter Format Units Max Tens Max Counter Addressed D0 D1 D2 D3 BCD D4 D5 D6 D7 BCD Code Code Milliseconds (00 H) Ð Ð Ð Ð 0 D4 D5 D6 D7 9 Hundredths and Tenths Sec (01 H) D0 D1 D2 D3 9 D4 D5 D6 D7 9 Seconds (02 H) D0 D1 D2 D3 9 D4 D5 D6 Ð 5 Minutes (03 H) D0 D1 D2 D3 9 D4 D5 D6 Ð 5 Hours (04 H) D0 D1 D2 D3 9 D4 D5 Ð Ð 2 Day of the Week (05 H) D 0 D 1 D 2 Ð7Ð Ð Ð Ð0 Day of the Month (06 H) D0 D1 D2 D3 9 D4 D5 Ð Ð 3 Month (07 H)D 0D 1D 2D 3 9 D 4 Ð Ð Ð 1 (Ð) indicates unused bits

Functional Description (Continued) TABLE II. Clock RAM Bit Map for Alarm Interrupt Everyday at 10:15 a.m. Address Data Function Hi Nibble Lo Nibble 4321076543210 Milliseconds 0 1 0 0 0 0 0 0 0 No RAM Exists Hundredths and 0100100000000Tenths of Seconds Seconds 0 1 0 1 0 0 0 0 0 0 0 0 0 Minutes 0 1 0 1 1 0 0 0 1 0 1 0 1 Hours 0 1 1 0 0 0 0 0 1 0 0 0 0 Day of Week 0 1 1 0 1 No RAM Exists 1 1 X X Day of Month 0 1 1 1 0 1 1 X X 1 1 X X Months 0 1 1 1 1 1 1 X X 1 1 X X TABLE III. Address Codes and Function A4 A3 A2 A1 A0 Function 0 0 0 0 0 CounterÐMilliseconds 0 0 0 0 1 CounterÐHundredths and Tenths of Seconds 0 0 0 1 0 CounterÐSeconds 0 0 0 1 1 CounterÐMinutes 0 0 1 0 0 CounterÐHours 0 0 1 0 1 CounterÐDay of Week 0 0 1 1 0 CounterÐDay of Month 0 0 1 1 1 CounterÐMonth 0 1 0 0 0 RAMÐMilliseconds 0 1 0 0 1 RAMÐHundredths and Tenths of Seconds 0 1 0 1 0 RAMÐSeconds 0 1 0 1 1 RAMÐMinutes 0 1 1 0 0 RAMÐHours 0 1 1 0 1 RAMÐDay of Week 0 1 1 1 0 RAMÐDay of Month 0 1 1 1 1 RAMÐMonths 1 0 0 0 0 Interrupt Status Register 1 0 0 0 1 Interrupt Control Register 1 0 0 1 0 Counters Reset 1 0 0 1 1 RAM Reset 1 0 1 0 0 Status Bit 1 0 1 0 1 GO Comand 1 0 1 1 0 STANDBY INTERRUPT 1 1 1 1 1 Test Mode All others unused The comparator is a cascaded exclusive NOR. Its output is latched 61 ms after the rising edge of the 1 kHz clock signal (input to the milliseconds counter). This allows the counter to ripple through before looking at the comparator. For oper- ation at less than 4.5V, the thousandths of seconds counter should not be included in a compare because of the possi- bility of having a ripple delay greater than 61 ms. (For output timing see Interrupt Timing.) Power Down Mode The POWER DOWN input is essentially a second chip se- lect. It disables all inputs and outputs except for the STANDBY INTERRUPT. When this input is at a logical zero, the device will not respond to any external signals. It will, however, maintain timekeeping and turn on the STANDBY INTERRUPT if programmed to do so. (The programming must be done before the POWER DOWN input goes to a

hundredths, tenths, units, and tens of seconds counters. This GO command is used for precise starting of the clock. precisely at a given minute. set following a counter read, the counter should be reread. H will reset the status bit. followed by reading the rollover status bit. Example: Read months, then read rollover status. 20 pF–25 pF. The crystal frequency is 32,768 Hz. oscillator input levels should be within 0.3V of the supplies. chip select and control strobes are low. FIGURE 1. Interrupt Register Format

Functional Description (Continued) Typical Supply Current vs Supply VoltageStandby Interrupt during Power DownTypical Characteristics TL/F/11070–4 TL/F/11070–5 FIGURE 2 Interrupt Timing 0§C s TA s 70§C, 4.5V s VDD s 5.5V, V SS e 0V Symbol Parameter Min Max Units tINTON Status Register Clock to INTERRUPT OUTPUT 5 ms(Pin 13) High (Note 1) tSBYON Compare Valid to STANDBY INTERRUPT 5 ms(Pin 14) Low (Note 1) tINTOFF Trailing Edge of Status Register 5 msRead to INTERRUPT OUTPUT Low tSBYOFF Trailing Edge of Write Cycle (D0 e 0; Address e 16H) to STANDBY 5 ms INTERRUPT Off (High Impedance State) Note 1: The status register clocks are: the corresponding counter’s rollover to its reset state or the compare becoming valid. The compare becomes valid 61 ms after the 1/10,000 of a second counter is clocked, if the real time counter data matches the RAM data. Read Cycle Timing 0§C s TA s 70§C, 4.5V s VDD s 5.5V, V SS e 0V Symbol Parameter Min Max Units tAR Address Bus Valid to Read Strobe (Note 3) 100 ns tCSR Chip Select to Read Strobe (Note 2) 0 ns tRRY Read Strobe to Ready Strobe 150 ns tRYD Ready Strobe to Data Valid 800 ns tAD Address Bus Valid to Data Valid 1050 ns tRH Data Hold Time from Trailing Edge of Read Strobe 0 ns tHZ Trailing Edge of Read Strobe to TRI-STATE Mode 250 ns tRYH Read Hold Time after Ready Strobe 0 ns tRA Address Bus Hold Time from Trailing Edge of Read Strobe 50 ns tRYDV Rising Edge of Ready to Data Valid 100 ns Note 2: When reading, a deselect time of 500 ns minimum must occur between counter reads. Deselect is: CS e 1o r( W R ) # (RD) e 1. Note 3: If t AR e 0 and Chip Select, Address Valid or Read are coincident then they must exist for 1050 ns.

TL/F/11070–10 FIGURE 7 Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number MM58167BN

MM58167B Microprocessor Real Time Clock Physical Dimensions inches (millimeters) (Continued) Order Number MM58167BV LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: (

a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.