MM57409 NSC | Alldatasheet
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5 National PRELIMINARY
= Semiconductor = Corporation MM57409 Super Number Cruncher General Description Features The Super Number Cruncher (SNC) is an MOS/LSI arithme- _ ™ Scientific calculator instructions (RPN) tic processor (actually, a pre-programmed member of Na- ‘* Up to 12-digit mantissa, 2-digit exponent tional's single-chip microcontroller COPS™ family) intended © 4-ragister stack, one memory register for use in number processing applications. Scientific calcu- © Trigonometric functions, logarithmic functions, lator functions, conditional output capability, internal number YX, @%, ar ‘storage, and input/output instructions have been combined * Error flag generation and recovery in this single chip device. Programming is done in calculator ™ Flexible input/output keyboard level language which simplifies software develop- © Multidigit OUT instruction with foating-point or scientit- ment. Data or instructions can be synchronous or asynchro- ic notations nous, |/O digit count, t/O notation mode, and error control * Programmable mantissa digit count for OUT are user programmable; a sense input and flag outputs are instruction available for single bit control; and instructions and lines are * Sense input and flag outputs: available for I/O expansion. © Eight high-impedance I/O lines (TRI-STATE®), six I/O . . lines, and four output lines for |/O expansion. Applications 1 Interface simplicity @ Instruments * On-chip clock OSC . § Microprocessor/minicomputer peripheral * Generates all /0 control signals = Test Equipment * MICROBUS™ interface Process controllers Block Diagram ww Lez 1 nas f ee aon ie el i Hes — HE = vor % or & = He= % = CT «= Lo ss % . % I= wm COTS merous { 1 2-4 <> te By A w if a aod T srw INTR/ROY = i — bres — fue —o [ood Tu/o0rs179-1 FIGURE 1 3-242
Absolute Maximum Ratings = Specifications for Military/Aerospace products are not Power Dissipation 0.75W at 25°C FS contained In this datasheet. Refer to the associated oawatzrc |Z reliability electrical test specifications document. Total Source Current 80mA anaes amen Roatve GND —0.5V to +7V Total Sink Current 75 mA mbient Operating Temperature oo to +70°C Note: Absolute maximum ratings inalcate limits beyond Ambient Storage Temperature 65°C to + 50°C Which damage to the device may occur. DC and AC electri- Lead Temperature (Soldering, 10 sec.) 300°C cal specifications are not insured when operating the device at absolute maximum ratings. Parameter [| Conditions | Min [Max [Units Operaing Vtiage (Vo (Rote [4s | sa |v Power Supply Ripple (Peak to Peak) re er ee ee? Operating Supply Current All inputs and outputs open Tr=0°C 4 mA Ta = 25°C 35 Ta = 70°C 27 Input Voltage Levels. CKI Logic High (Vix) Voc = 5V +5% 2.0 Logic Low (Vi) Voc = 5V 25% —0.3 0.4 Logic High (Vix) Voc = Max 25 RESET Logic High 0.7 Voc v Logic Low -0.3 06 All Other Inputs Logic High Voc = Max 25 Logic High Voc = 5V +5% 2.0 Logic Low —0.3 08 irgtontape OOS WAY Ln 0 Output Voltage Levels TTL Operation Logic High (Vor) lon = —100 pA 24 Logic Low (VoL) loy = 1.6 mA Vv CMOS Operation Logic High (Vou) lon = 10 pA Voc — 0.4 Logic Low (Vou) lo = 10 pA Output Current Levels, Output Source Current Voc = 4.5V Vou = 2.4V —100 650 pA K} TRI-STATE Output Leakage Current (R, D Lines) —25 25 pA CKO Output Output Source Current (lox) Vou = 2.0V -0.2 mA Output Sink Current (lou), VoL = 0.4V 0.4 mA Input Current Levels Input Load Source Current Vin = 2.0V 14 230 BA (Cl, RESET) Voc 4.5V Total Sink Current Allowed All /O Combined 75 mA Each D, R Port 20 mA Each, O, 1/0, F1, F2 10 mA SYNC Line 25 mA Total Source Current Allowed All 1/0 Combined 80 Each D Pin 5.0 mA All Other Output Pins 1.6 3-243
= Parameter [| ___Gonaitions [Min [Max [Unite Microcycte Time (tm) a CKI Frequency (f)) 1.6 4.0 MHz Duty Cycle (Note 2) 30 60 % Rise Time 60 ns Fall Time 40 ns Inputs (Figure 3) tseTuP 17 Hs tHoLD 300 ns Output Propagation Delay C, = 50 PF (Figure 3) Vour = 1.8V CKO tpp1. tepo 0.17 Bs SYNC tei, tepo AL = 2.4k0 1.0 BS All Other Outputs [= soKe Paes MICROBUS Timing Cy = 100 pF Voc = 5V +5% Read Operation (Figure 4) CS Stabie Before RD—icgp 65 CS Hold Time for RD—tacs 20 RD Pulse Width—tan 400 Data Delay from RD—tap 375 RD to Data Floating—tpr 250 ns Write Operation (Figure 5) GS Stable Before WR—tcsw 65 TS Hold Time for WR—-twes 20 WR Pulse Width—tww 400 Data Setup Time—tpw 320 Data Hold Time—twp, 100 INTD/RDY Transition Time from WR—twi 700 Note 1: Voc voltage change must be less than 0.5V in a 1 ms period to maintain proper operation. Note 2 Duty Cycle = twi/itwi + two). 3.244
level is shown in Figure 6. The structure of the M (memory) | & Connection Diagram level is similar, lacking only the guard/link digit. The mantis- | 9} Dual-in-Line ‘sa and the exponent each have a sign, which may be read 3 or changed by SNC instructions, The guard/link digitineach | ® ro 40 vec of the x, y, z, and t levels of the stack is used for the execu- nn) 2 39 -— bp tion of the arithmetic instructions. Regardless of any operat- onc md 3 38 [— 03 ing mode, all data internal to the SNC is stored in scientific nc 4 st;ecs notation format with the mantissa rounded to 12 digits. ‘SYNC 5 6 Li The arithmetic unit performs all mathematic operations of ae 35 Oe the MM57409, storing its results in the data register file, Wi—7 34 05 The R port can be used as an 8-bit high-impedance I/O INTR/ROY 5 3 06 Port. If the R port is to be used, the first instruction the SNC As 32 07 must receive after a power up or reset is the RIO instruction. F2— 10 31 Ro The state of the R port will be 03 hex. A host processor can ERROR ——] 11 30 Ar then instruct the SNC to output an 8-bit value to the R port 09 —J 12 29 fe or read the state of the R lines. Before reading the input Or 3 28 — Fs State of the R lines, the lines must be put into a high-imped- "2 — 14 a7 Re ance mode. The R lines are then high-impedance inputs 103 5 6 RS and must be externally driven high or low. pa fod ‘An external processor may also cause a 4-bit value to be aoe od a output to either the O or I/O ports. The input state of the 1/0 wots bod port or the present state of the output lines of the O port awd a men may be read from the SNC. If the I/O lines are to be used as inputs, the value F must first be written to the port using the Top View rop/si79-2 VO Instruction. ‘NC means no extemal con Two flags are provided on the SNC—F1 and F2. These nection allowed on these pins. flags may be set high or pulsed high through the use of FIGURE 2 appropriate SNC instructions. When pulsed, the pulse width Molded Dualsin-Line Package (N) of F1 is four microcycles and the pulse width of F2 is three ‘Order Number MM57409N microcycles. (A microcycle is the external clock input divid- See NS Package Number N40A ed by 16—see Oscillator section for further information.) These flags may also be tested by test/conditional output [_PinName | Description —_—i| instructions if they are first set high. An external test input (Ci) is also provided tor conditional output control and is Do-07 8-Bit Data Bus (bidirectional) tested by the TC! instruction. 109-103 4-Bit I/O Lines (bidirectional) There are four general purpose internal flags (IF1-IF4) in o-Og 4-Bit Output Lines the SNC that can be reset, of tested using the appropriate Ro-Ry 8-Bit Bidirectional I/O Lines with instructions. TRISTATE ERROR Eror igre Tho SNC hes soar ser conotale operating moses us oo. BNP row eal riage Any combination ofthese moges may be soacid, These : modes are: x _ WA | MicROBUS Handshake Signals 1. Angular mode—The SNC can be instructed to accept and RESET System Reset return data in either degrees or radians. Res ic Mero vycle Clock 2, Input/Output mode—The SNC will accept and output nu- merical data in either scientific notation (signed exponent K} CKI, CKO ‘System Oscillator and mantissa) or floating-point (decimal point position, cl Test/Conditional Input signed mantissa). Note that only the input or output data can be in floating-point or scientific notation—the data Functional Description internal to the SNC is always in scientific notation. ‘The MM57409 Super Number Gruncher (SNC) is intended 3. Rounding—The SNC can be instructed to round the out: for microprocessor number processing applications as a mi- Put to the Mantissa Digit Count (MDC). This rounding may ctocomputer peripheral device. The block diagram of ie also be disabled. The rounding mode causes rounding on SNC is shown in Figure 1. Data paths are illustrated in sim- the output data only—the data internal to the SNC is still plied form to depict how the various logic elements com- in scientific notation format with the mantissa rounded to municate with each other, Positive logic is used, ie., when a 12 digits. , ; bit is set, itis a logic “1” (greater than 2V) and when a bit is aaah ent inelinemaraali ar rab Mibeanehirart ae reset, it is a logic “0” (less than 0.8V). floating-point mode. This means that fractional numbers (ix|<1) may INTERNAL LOGIC ‘not appesr to be rounded. The data register file, consisting of a 4-level stack and one 4. Mantissa Digit Counter (MDC)—The number of digits the mamory location, is the source and dastination ragistar for SNC expects in the mantissa during the multiple digit all mathematic operations. The organization of anx, y, z, or t OUT operation may be set anywhere between 1 and 12. 3-245
5 Functional Description (continued)
(MSB) = 1 indicates floating-point 1/0 cle) for the SNC. This signal is available at the SYNC output. = 0 indicates rounding to MDC is performed CKI frequency. = 1 indicates the absolute value of x is a non-zero. must be used. = O indicates x > Oorx = 0 output will be rounded to the MDG. BitO: Error of the SNC after an error condition is also shown in Table |.
- an ECLR (error clear) instruction
- an MCLR (master clear) instruction
FIGURE 3. Basic Timing
FIGURE 4. MICROBUS Read Operation Timing FIGURE 6. Stack Level x, y, z or t Structure
1 Peat Point I/O Mod etal Ovelitor
9 | O= No Error Has Occurred v. FIGURE 7. SNC Status Register FIGURE 9. Power-Up Reset Circult
(write strobe) transfers the information on the bus into the two entered will be accepted . write. Pulsing the FD line (read strobe) will cause an internal x exponent. idle loop until the device is selected and the WR is pulsed out interference.
- RO, WR, CS—High-impedance (Figure 10a) writes the address N and the data for that address back to
- Cl, RESET—Internal load device (Figure 10b) the SNC.
- Rr-Ro—Push-pull with TRI-STATE (Figure 11b) READ: O0hex (SNC says write data to
FIGURE 10. SNC Input Characteristics
a. TRI-STATE Output b. Push-Pull Outputs with TRISTATE. FIGURE 11. SNC Output Characteristics
a S| The next example illustrates when AIN1 is entered immedi- of the data and the data in the form nD where n is the §5 | _ ately after the previous example: address and D is the data. The host should then write the = 4 same information back to the SNC to indicate that it re- See rhe (eNC ape arte datato ceived the data. This procedure continues unti all data has : 4 been read by the host. The data addresses are shown in mantissa address 1) Table Il for scientif i " A fic notation mode and in Table II for float- WRITE: 15hex (5 —> mantissa digit 1) ing-point mode, One exception to the number entry initiation is that the stack ii , . ie mot pushed if the instruction pror to an entered digit was Table V contains data formats for other output instructions. EN (enter)—EN pushed the stack. However, the x register is Sil cleared and the entered data put in x ae eeete eet notes OUTPUT ii nl mode is termi instruction ex- wo of the instructions — ae ey DL aINT NOPK wr acy manban IMNZ and DMNZ—deserve special comment. These in- =_—e . " ‘structions increment or decrement the memory mantissa 5 and if the new value of the mantissa is = 0, then R will have Data Input Description the value contained in the operand field. The increment/ ‘The AIN2 instruction is a 2-byte, single digit asynchronous decrement portion affects the entire 12-digit mantissa, start- input instruction. This instruction does not initiate number ing at digit 12 (LSD), regardless of the MDC and the decimal ‘entry mode and the x level of the stack is not cleared. The point. So, if the host wished to decrement the memory twice first byte is the instruction’s opcode: 91 hex. The second and then change R, the x register would be cleared, AIN2 byte is of the form nD where n is the digit address and D is would be used to write a 2 to digit 12, and the memory and x the BCD digit. Since n is specified by the host, AIN2 can be would be exchanged. The host could then expect the SNC used to write to any digit in the x register. Digits may only be to load R upon the second execution of the DMNZ instruc- entered in scientific notation format. This example will write tion. 87 to the MSD of the x mantissa. Refer to Table IV. If the host wished to observe the true results of the LSH (left WRITE: 91hex —_(AIN2 opcode) shift x mantissa) and RSH (right shift x mantissa), rounding WRITE: 47hex (4 is the address of the the output to the MDC should be disabled. Otherwise the MSD mantissa digit, 7 shift might be obscured due to rounding. is data) Execution times for all SNC instructions are contained in Table VI. Typical instruction times are given for math and Data Output Description memory operation instructions, and worst case times given The OUT instruction is a multidigit output instruction that will for all else. These times were found with the CKI input fre- output all digits of the x register. The host writes the OUT quency equal to 4 MHz (4 us microcycie time) and are mea- opcode (8F hex) and the SNC will respond with the address sured from the rising edge of the WR signal to the rising edge of the INTR/RDY line. TABLE |. SNC Error Conditions 1. Inxorlog x when xis < 0 % y, Z, t, M unchanged 2. xty,x-y, x'y, ory/xwhen result Previous x —> y; xis invalid data is < 10100 or < 10-99 3. M+x,M—x,M*x,orM/xwhich —_y, 2, t, Munchanged; x is invalid data result is 2 10100 of < 10-99 4, Tan 90°, 270°, 450°, etc. y. 2, t, M unchanged; x is invalid data 5. Sinx,Cosx,orTanxwhenthe —_y, 2, t, Munchanged; x is invalid data absolute value of xis < 9000" (157.08 radians) 6. _arcsin x or across x when the ¥,2, t, M unchanged; x is invalid data absolute value of xis > 1 or < 10-50 7. square root of x when x < 0 X,Y, Zt, M unchanged 8. y/xwhenx = 0 x.y swapped; z, t, M unchanged 9. 1/xwhenx = 0 1—> x,y,z, 1, Munchanged 10. M/xwhenx = 0 Mtox< y, 2, t, M unchanged 44. yXwheny <0 x, y swapped; z, t, M unchanged 12. Floating-point OUT instruction x, y, 2, t, M unchanged when the number of mantissa digits to the lett of the decimal point is >12 13, Attempt to enter a number Error occurs on termination of = 10100 or < 10-99 number entry mode. The stack push at initiation of number entry will occur normally. x contains invalid data. 3-250
TABLE II. OUT Instruction—Floating-Point = D7-D, DPX D3 Dz Dy _~—iDp B 2 sm 0 ty) Se 3 Decimal Point Position (OP POS). 4 11 Most significant mantissa digit. On the Out instruction, this digit will be nonzero unless |x| <1, in which case it will be zero and decimal point position will be 11. 5 10 Second most significant mantissa digit, MOC+3 _2-MDC_Least significant mantissa digit. TABLE III. OUT instruction—Scientific Notation D7-Da Os Da Ds Do ° Most significant exponent digit. 1 Least significant exponent digit. 2 sm 0 ° Se 3 Not used. 4 Most significant mantissa digit. Decimal point follows this digit. 5 Second most significant mantissa digit. MDC+3 Least significant mantissa digit. TABLE IV. AIN2 Instruction D7-Ds Ds Dz Ds ° Most significant exponent digit. 1 Least significant exponent digit.
2 Sm 0 t) Se
3 Not used. 4 Most significant mantissa digit. 5 Second most significant mantissa digit. 14 Second least significant mantissa digit. 15 Least significant mantissa digit. ‘Sm = Sign of mantissa, 0 = positive, 1 = negative. Se = Sign of exponent, 0 = postive, 1 = negative. MDC = Mantissa digit count. DP POS = Decimal point position indicator is a value in the range from 11 down to 12—MDC, which indicates a digit, as given by the OPX column in the table, after which the decimal point is located. 9-251
= TABLE V. Output Instruction Data Formats 8 | TTT S| Output S| instruction Dy Ds Ds De Ds De Dy Do See eS ouTt (LSD+ 1) Digit 4 (LSD) Digit o eer Sight outa (LSD +3) Digit 3 (LSD-+2) Digit 2 rs igtg SDH 2) IQS OUuT3 (LSD +5) Digit $ (LSD+4) Digit 4 <r ESHA Digits outa (LSD +7) Digit 7 (LSD +6) Digit 6 er SESE) DIQNG OUTS (LSD+9) Digit 9 (LSD+8) Digit 8 —S eS 8) Digit OUTS (MSD) Digit 11 (MSD —1) Digit 10 Sign of Sign of OUTSGN Mantisca ° 0 Exponent Link/Guard Digit — a SE rrr OUTEXP MSD EXPONENT LSD Exponent TS Oe Emporio outer ve Round. Not Angles xAs Signof xComp. — Error Mode Mode Used Mode Fraction x too Status —.— So avanv—Xn— OO Fraction xt Status OUTIO 103 102 10; 100 1 0 ° 1 a ouTO Og Oz O71 Oo 1 1 t) 1 a OUTR Ry Re Rs Ry Rg Re Ri Ro A RR OUTFL ° Fp Fy ° IF 4 Fy Fp Fy a LS s OuTMDC MDCwss___ MDCysp-1 _MDCysp-2 __ MDCisa 1 1 ty) 0 i t _pne es TABLE VI. Instruction Execution Times Alll times are measured with 4 MHz at CKI and are measured from the rising edge of WR to the rising edge of INTR/RDY. Worst Case Worst Case Execution Time (ms) Execution Time (ms) 0-8 1.6 TJC | Ist Byte 3.0 op 15 a 2nd Byte 1.4 EE 1.5 TX2 | 1st Byte 3.0 cs a 2nd Byte 14 PI 18 TXN | 1st Byte 3.0 AIN1 1st Byte 0.3 a 2nd Byte 14 2nd Byte 09 TXF | 1st Byte 3.0 NoP1 16 a 2nd Byte 14 NoP2 31 TERR | 1st Byte 3.0 SMDC n a4 a 2nd Byte 14 : lon 34 TMNZ | ist Byte 4.0 i On 34 a 2nd Byte 1.4 LOR 1st Byte 3.4 TMZ | ist Byte 40 2nd Byte 15 a 2nd Byte 14 AIN2 1st Byte 34 TF 1st Byte 1 2nd Byte 16 a 2nd Byte Os OUT1-OUT6 3.0 TFL | 1stByte 1 OUTSGN 3.0 a 2nd Byte 0s OUTEXP. 3.0 IMNZ_ | st Byte 3.0 OUTST 3.0 a 2nd Byte 0.5 OUTIO 3.0 DMNZ | 1st Byte 44 OuTO 3.0 a 2nd Byte Os OUTR 3.0 TIF1~4 | 1st Byte 3.0 OUTFL 3.0 a 2nd Byte 15 OUTMDC 3.0 OUT 1st Byte 3.0 3-252
TABLE VI. Instruction Execution Times (Continued) = Worst Case Worst Case ~ Executlon Time (ms) Execution Time (ms) 3 RAD 27 MCLR 5.1 DEG 27 EN 55 NRND 27 ROLL 84 RND 27 POP 86 FLP 27 SIN 820 SCI 27 cos 830 ECLR 27 TAN 540 SIF1-4 27 ARCSIN 840 RIFI-4 27 ARCCOS: 700 ROFF 27 ARCTAN 410 RON 27 RTD 162 RIO 27 OTR 162 ‘SFI 27 XXY 29 PFA 27 Ex 440 SF2 27 10x 100 PF2 27 sQ 18 Instruction Execution Time (ms) LN 210 XXM 42 LOG 140 ws 57 Ux 66 MR 7.0 YX 400 M+ 13.2 + 20 M- 13.2 - 20 Mt 11.8 . 28 M/ 60 / 66 CLAM 6.0 LSH 5.2 CLAX 3.0 RSH 25 Note 1: Add 0.3 ms to the execution time of any instruction which initiates number entry and is preceded by an enter instruction. Note 2: Add 2.5 ms to the execution time of any instruction which initiates number entry and is not preceded by an enter instruction. Note 3: Add 2.0 ms to the execution time of any instruction which terminates number entry mode. MM57409 Number Cruncher Instruction Set 0 00 —_ | Mantissa or exponent digits. If the previous code was EN (enter), 1 01 then the digit is placed in x. If the previous code was not EN, the 2 02 stack is pushed as follows: 3 03 digit > x 4 04 xy 5 05 yz 3 6 06 zt 7 07 8 08 9 09 —_| See Number Entry Mode Description oP OA Decimai point. Digits that follow will be mantissa fraction. Ee 08 _| Enter exponent. Digits that follow will be exponent digits. If this is the first data entry, a “1” will be loaded into the mantissa. cs OC —_| Change sign. The mantissa's sign is changed unless EE was the last number entry initiation, in which case the exponents sign is changed. PI 0D 3.14159265359 — x. AINA OE _| Single digit asynchronous input. See Number Entry Mode Description. NOP1 OF No operation. NOP2 22 | Terminate number entry, no other operation. 3-263
4 MMS57409 Number Cruncher Instruction Set (Continued)
a MANTISSA DIGIT COUNT (MDC) CONTROL INSTRUCTIONS. [ smoc [ n | 7(n-1) [SettheMDC = nn = 1,2,3,4,5,6,7,8,9, A,B, Chex 1/0, 0, AND PC PORT WRITE INSTRUCTIONS Le} n A(n) Write n to the 4-bit general I/O port. n = 0 through F hex. ° n B(n) | Write nto the 4-bit general O port. n — 0 through F hex. LOR a 92 | Load the R port with “a”, where “a”, is 8-bit value from 00 hex a__| through FF hex. DATA INPUT INSTRUCTIONS. ain2[__|__91__ [Asynchronous input 2. See Data Input Description. DATA OUTPUT INSTRUCTIONS ouTt 80 Output x mantissa LSD and LSD+1. ouT2 81 | Output x mantissa LSD +2 and LSD+3. OUuT3 82 Output x mantissa LSD + 4 and LSD+ 5. outs 83 | Outputx mantissa LSD +6 and LSD +7. OUTS 84 | Output x mantissa LSD+8 and LSD+9. ouTe 85 | Qutput x mantissa MSD ~1 and MSD. OUTSGN 86 | Output link/guard digit and mantissa/exponent sign digit. OUTEXP 87 Output x exponent digit. OUTST 88 | Output 8.bit status register. oUTIO 89 | Output the state of the 4-bit general I/O port. OUTO 8D —_| Output the state of the 4-bit general outut port. OUTR 8A _| Output the state of the 8-bit R port. OUTFI 88 —_| Output F1, F2, and the four internal flags, IF1 through IF4. ouTMDC 8C —_| Output the Mantissa Digit Count. OUT 8F _ | Multiple digit output instruction. See Data Output Description. TEST/CONDITIONAL OUTPUT INSTRUCTIONS TCl a 10 If external test input Cl = logic “1”, load R with “a”, where “a” a __|isan8-bit value from 00 hex through FF hex. TXZ a VW Ifx = 0, load R with “a”. TXN a 12 —_|Ifxis negative, load R with “a”, a TXF a 13 {If the absolute value of x is a fraction, load R with “a”. a TERR a 14 | Ifthe error flag is set, load R with “a”. TMNZ a 16 | If memory is not equal to 0, load R with “a”. a TMZ a 17 | lf memory equals 0, load R with “a”. a ' TFt a 18 [If the external flag input 1 = togic “1”, load R with “a”. a TF2 a 1B If the external flag input 2 = logic “1", load R with "a". a IMNZ a 19 | Increment the mantissa contained in memory, and if the new @ __| value of the memory is not = 0, load R with “a”. DMNZ a 1A _ | Decrement the mantissa contained in memory, and if the new a _| value of the memory is not ~ 0, load R with “a”. TIF na 4(8+n)_| ifthe internal flag n = logic “1”, load R with “a”. = 1,2,3,4. a 3-254
MM57409 Number Cruncher Instruction Set (Continued) = poweloreme] S| oom | oe CLRX 20 o—x. MCLR oF Master clear: clear all internal registers and outputs; 10 —> MDC. Scientific notation mode; round to MDC on output; R port ‘set to 03 hex and is enabled; |/O port unaffected. EN 21 Enter and push stack. The same digit will be in x and y. ROLL 23 Roll stack: A x, ad “eA NS ya ¥ TLIDD/5173=17 POP 2E Pop the stack: y > x ane tmz o-t SIN 24 sin(x) > x cos 25 cos(x) > x TAN 26 tan(x) > x ARCSIN 27 arcsin(x) —> x ARCCOS 28 arccos(x) —> x ARCTAN 29 arctan(x) —> x RTD 2c Convert the value in x from radians to degrees. DTR 2D Convert the value in x from degrees to radians. XXY 30 Exchange x and y. Ex 31 xx 10X 32 10% —> x sQ 33 xe x SQRT 34 Square root(x) —> x LN 35 Inx > x LOG 36 Logx > x Wx 37 Wx > x YX 38 > KOOL tozzoy + 39 YX KOE tazzoy =_ SA yx x 0ttoz4z>y . 3B YX>xX OL taz4zy / 3c yx x0 tt azz sy LSH 3E Left shift x mantissa, DP unchanged, MSD in guard/link digit. ASH oF Right shift x mantissa, DP unchanged, link/guard digit —> MSD. XXM 40 Exchange x and memory. MS: a4 Store x in memory. MR 42 Memory + x > y—>z—t. M+ 43 Memory +x —> memory. M- 44 Memory -x —> memory. M* 45 Memory*x —> memory. M/ 46 Memory divided by x —> memory. CLRM 47 Clear memory; 0 —> memory. 3-255
= MM57409 Number Cruncher Instruction Set (Continued) wo Baloo] Soe RAD 50 | Set radian angular mode. DEG 51 ‘Set degrees angular mode. NAND 54 Round to MDC on output disabled. RND 65 Round to MOC on output enabled. FLP 56 _| Set floating-point 1/0 mode. Sci 57 Set scientific notation I/O mode. ECLR 2B Clear error flag. SIFt 58 | Setinternal flag 1. SIF2 5A | Setinternal flag 2. SIF3 5C | Set internal flag 3. ‘SIF4 5E Set internal flag 4. RIF1 59 Reset internal flag 1. RIF2 5B Reset internal! flag 2. RIF 5D _| Reset internal flag 3. RIF4 SF Reset internal flag 4. ROFF 60 TRI-STATE the R port. RON 61 Enable the R port. RIO 62 R port is enabled as high-impedance I/O. SFI 67 ‘Set external flag 1 high. PFI 68 Pulse external flag 1 high. If F1 is already high, then itis reset. SF2 69 Set external flag 2 high. PF2 6A Pulse external flag 2 high. It F2 is already high, then it is reset. 3-256