MM54C910 TI1 | Alldatasheet
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MM54C910,MM74C910 MM54C910 MM74C910 256-Bit TRI-STATE Random Access Read/Write Memory Literature Number: SNOS343A
MM54C910/MM74C910 256 Bit TRI-STATE Random Access Read/Write Memory September 1989 MM54C910/MM74C910 256 Bit TRI-STATE É Random Access Read/Write Memory General Description The MM54C910/MM74C910 is a 64 word by 4-bit random access memory. Inputs consist of six address lines, four data input lines, a WE ,a n daM E line. The six address lines are internally decoded to select one of the 64 word loca- tions. An internal address register latches the address infor- mation on the positive to negative transition of ME . The TRI-STATE outputs allow for easy memory expansion. Address Operation: Address inputs must be stable (t SA) prior to the positive to negative transition of ME , and (t HA) after the positive to negative transition of ME . The address register holds the information and stable address inputs are not needed at any other time. Write Operation: Data is written into memory at the select- ed address if WE goes low while ME is low. WE must be held low for t WE and data must remain stable t HD after WE returns high. Read Operation: Data is nondestructively read from a memory location by an address operation with WE held high. Outputs are in the TRI-STATE (Hi-Z) condition when the device is writing or disabled.
Features
Y Supply voltage range 3.0V to 5.5V Y High noise immunity 0.45VCC (typ.) Y TTL compatible fan out 1 TTL load Y Input address register Y Low power consumption 250 nW/package (typ.) (chip enabled or disabled) Y Fast access time 250 ns (typ.) at 5.0V Y TRI-STATE outputs Y High voltage inputs Logic Diagrams TL/F/5914–1 Input Protection TL/F/5914–2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Obsolete
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at Any Output Pin b0.3V to V CC a0.3V Voltage at Any Input Pin b0.3V to a15V Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Operating V CC Range 3.0V to 5.5V Standby V CC Range 1.5V to 5.5V Absolute Maximum (V CC) 6.0V Lead Temperature (T L) (Soldering, 10 sec.) 260 §C Operating Conditions Min Max Units Supply Voltage (V CC) MM54C910 4.5 5.5 V MM74C910 4.75 5.25 V Temperature (T MM54C910 b55 a125 §C MM74C910 b40 a85 §C Min/Max limits apply accross the temperature and power supply range indicated Symbol Parameter Conditions Min Typ Max Units VIN(1) Logical ‘‘1’’ Input Voltage Full Range VCC b 1.5 V VIN(0) Logical ‘‘0’’ Input Voltage Full Range 0.8 V IIN(1) Logical ‘‘1’’ Input Current V IN e 15V 0.005 2.0 mA VIN e 5V 0.005 1.0 mA IIN(0) Logical ‘‘0’’ Input Current V IN e 0V b1.0 b0.005 mA VOUT(1) Logical ‘‘1’’ Output Voltage I O eb 150 mAV CC b 0.5 V IO eb 400 mA 2.4 V VOUT(0) Logical ‘‘0’’ Output Voltage I O e 1.6 mA 0.4 V IOZ Output Current in High VO e 5V 0.005 1.0 mA Impedance State V O e 0V b1.0 b0.005 mA ICC Supply Current VCC e 5V 5.0 300 mA Symbol Parameter Min Typ Max Units tACC Access Time from Address 250 500 ns tpd Propagation Delay from ME 180 360 ns tSA Address Input Set-Up Time 140 70 ns tHA Address Input Hold Time 20 10 ns tME Memory Enable Pulse Width 200 100 ns tME Memory Enable Pulse Width 400 200 ns tSD Data Input Set-Up Time 0 ns tHD Data Input Hold Time 30 15 ns tWE Write Enable Pulse Width 140 70 ns t1H,t 0H Delay to TRI-STATE (Note 4) 100 200 ns CAPACITANCE CIN Input Capacity 5.0 pFAny Input (Note 2) COUT Output Capacity 9.0 pFAny Output (Note 2) CPD Power Dissipation Capacity 350 pF(Note 3) Obsolete
TA eb 55§Ct o a125§CT A eb 40§Ct o a85§C Symbol Parameter VCC e 4.5V to 5.5V VCC e 4.75V to 5.25V Units Min Max Min Max tACC Access Time from Address 860 700 ns tpd1,t pd0 Propagation Delay from ME 660 540 ns tSA Address Input Set-Up Time 200 160 ns tHA Address Input Hold Time 20 20 ns tME Memory Enable Pulse Width 280 260 ns tME Memory Enable Pulse Width 750 600 ns tSD Data Input Set-Up Time 0 0 ns tHD Data Input Hold Time 50 50 ns tWE Write Enable Pulse Width 200 180 ns t1H,t 0H Delay to TRI-STATE (Note 4) 200 200 ns *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Capacitance is guaranteed by periodic testing. Note 3: CPD determines the no load AC power consumption for any CMOS device. For complete explanation see 54C/74C Family Characteristics application note AN-90. Note 4: See AC test circuits for t 1H,t 0H. Typical Performance Characteristics Typical Access Time vs Ambient Temperature TL/F/5914–4 Truth Table ME WE Operation Outputs L L Write TRI-STATE L H Read Data H L Inhibit, Store TRI-STATE H H Inhibit, Store TRI-STATE AC Test Circuits t0H TL/F/5914–5 t1H TL/F/5914–6 Obsolete
AC Test Circuits (Continued) All Other AC Tests TL/F/5914–7 Switching Time Waveforms Read Cycle (See Note 1) TL/F/5914–8 Write Cycle (See Note 1) TL/F/5914–9 Obsolete
Switching Time Waveforms (Continued) Read Modify Write Cycle (See Note 1) TL/F/5914–10 t0H TL/F/5914–11 t1H TL/F/5914–12 Note 1: MEMORY ENABLE must be brought high for t ME nanoseconds between every address change. Note 2: tr e tf e 20 ns for all inputs. Connection Diagram Dual-In-Line Package TL/F/5914–3 Top View Order Number MM54C910 or MM74C910 Obsolete
Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C910J or MM74C910J Obsolete
MM54C910/MM74C910 256 Bit TRI-STATE Random Access Read/Write Memory Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C910N or MM74C910N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
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Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Obsolete
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