MM54240

MM54240 NSC | Alldatasheet

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Technical content

Features

Y Supply voltage rangeÐ4.75V to 11.5V single supply Y Low quiescent currentÐ5.0 mA maximum Y On-chip oscillator based on inexpensive R-C components Y Pulse width modulation techniques minimize error and maximize frequency tolerance Y Mode input for either master or slave operations Y Chip select (CS ) input in the master mode Y Selectable output port options in the slave mode Y Transmit/receive control output (CS ) in the slave mode Functional Block Diagram TL/F/10819–1 Order Number MM54240N See NS Package Number N24C Pin Configuration 1V SS

2 D7 (MSB)

9 D0 (LSB)

10 Serial

11 Mode

13 V DD

14 R /C1

15 W /C2

17 OSC

18 A6 (MSB)

24 A0 (LSB)

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

(exceeding these ratings could result in permanent damage to the device) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage on Any Pin with Respect to V SS b0.5V to a12.0V Operating Temperature b40§Ct o a85§C Storage Temperature b65§Ct o a150§C Lead Temperature (Soldering, 10 seconds) 300 §C Electrical Characteristics TA within operating range, V SS e 0V Symbol Parameter Conditions Min Typ Max Units VDD Supply Voltage 4.75 11.5 V IDD Supply Current, Quiescent V DD e 4.75V to 11.5V 5.0 mA Input Voltage VIL Logic ‘‘0’’ V DD e 4.75V to 11.5V 0 0.8 V VIH Logic ‘‘1’’ V DD e 4.75V to 5.25V 2.4 V DD V VIH Logic ‘‘1’’ V DD e 5.25V to 11.5V V DD b 2.85 V DD V Output Current (D0–D7) IOL VOL e 0.4V V DD e 4.75V to 11.5V 2.0 mA IOH VOH e 2.4V V DD e 4.75V to 5.25V 200 mA IOH VOH e 0.5 V DD VDD e 5.25V to 11.5V 200 mA IOH VOH e 0.6 V DD (Weak V OH)V DD e 4.75V to 11.5V 0.5 30 mA IOS Short Circuit Output Current V DD e 4.75V to 5.25V 5 mA Output (CS Slave) IOL VOL e 0.5V V DD e 4.75V to 11.5V 0.4 mA Frequency RC Input F For a Fixed (RC) 1 (Note 1) V DD e 4.75V to 7.0V 200 400 600 kHz F For a Fixed (RC) 2 (Note 1) V DD e 7.0V to 11.5V 200 400 600 kHz Output Current (Serial) IOL VOL e 0.4V V DD e 4.75V to 11.5V 2.0 mA ILEAK Open-Drain Leakage V DD e 4.75V to 11.5V 10 mA Internal Input Pull-Up Resistors, CS , Mode IIL VIN e VSS VDD e 4.75V to 11.5V 15 100 mA Note 1: (RC)1 or (RC) 2: suggeste dR1k X–10 k X, suggested C 50 pFd–500 pFd. Typical Application TL/F/10819–2

The MM54240 consists of four major logic blocks: Sequen- tial Control, Shift Register, PWM Encoder and PWM Decod- er. Data Ports (D0–D7): The data ports are bidirectional and have three output levels (high, low and weak pull-up). The weak pull-up mode is only available when the MM54240 is a slave device. For the master circuit, the outputs are config- ured with standard high and low states coincident with prop- erly enabled CS and R . This permits direct interface or buff- ered interface with the standard bus structure of a proces- sor system. The first three data ports (D0, D1, D2) also serve as status pins coincident with enabled CS and S .* For the slave circuit, specialized input and output options are available by selecting the C1 and C2 inputs. The data port can still be read even if it is configured as an output port. Address Ports (A0–A6): The address ports are for the in- put of address information into the MM54240. For the mas- ter circuit, the input must be valid during the R and W com- mand strobes. For the slave circuit, a unique hard-wired code must be on the address ports. This code is the ad- dress of the slave circuit for addressing purposes. No inter- nal pull-ups are provided. Mode: This input is low for slave and high (or open) for master selections. An internal pull-up resistor is provided. Chip Select (CS ): This pin has an internal pull-up resistor to VDD. In the master mode, CS is an input and has to be pulled low before the R ,W ,o rS strobes can be acknowl- edged. When CS is a logic high, the data port pins are high impedance. In the slave mode, CS is an output. It is a logic ‘‘0’’ when the circuit is expecting to receive a transmission. CS is intended only for controlling a transceiver buffer de- vice. During the receive mode, CS will produce a high-going pulse when the dummy bit is received, but prior to the inter- nal address compare. Thus, all slaves (addressed or not * The other data ports will output logic ‘‘0’’. addressed) will produce this pulse when receiving a trans- mission. The slave that is addressed will keep CS high until it completes the transmission to the master. Read/Control 1 (R /C1): In the master mode, while CS is active low, this input can be used to initiate either of the following three operations depending upon the present status of the circuit. 1. To initiate a read command 2. To enable output ports if transmission received is valid 3. To terminate read command if transmission received is incorrect (if master is in state 4 awaiting data from slave, a dummy read will set master to initialize) In the slave mode, this input, together with W /C2, selects the specialized output port configuration. Write/Control 2 (W /C2): In the master mode, while CS is active low, this input can be used to initiate a write com- mand. In the slave mode, this input, together with R /C1, selects the specialized output port configuration. Status (S ): In the master mode, while CS is active low, this input enables circuit status information to be output at the first three data ports. The other five data ports will be at logic ‘‘0’’. In the slave mode, this input sets all the output (D0–D7) latches to the logic ‘‘1’’ state. In the slave mode, status cannot be interrogated. OSC: This input is for connection to a resistor-capacitor cir- cuit for the on-chip oscillator. Frequency tolerance is speci- fied for two voltage ranges. In a master-slave system, if no one circuit has a frequency more than a factor of 2 different from any other circuit, then, valid transmission is guaran- teed. Nominal setting is 400 kHz. Serial: Input and output pin for serial transmission. Output has open-drain configuration. Data Format 1. Serially transmitted data TL/F/10819–3 2. Pulse width modulation coding TL/F/10819–4 A bit is equivalent to 96 clocks of the R-C oscillator frequency i.e.; when R-C frequency e 400 kHz, 1 bit e 240 ms, 1 word e 4.32 ms.

Circuit Description (Continued) Slave Circuit Logic Flow Diagram TL/F/10819–5 Specialized Output Options for Slave Circuits C1 C2 Description 1 1 All 8 Pins are High Impedance Input Ports 0 1 All 8 Pins are Standard Low Impedance Output Ports 0 0 D1–D4 are Standard Low Impedance Output Ports D5–D8 are High Impedance Input Ports 1 0 Logic ‘‘0’’ Outputs are Low Impedance Output Ports Logic ‘‘1’’ Outputs are Weak Pull-Ups to V DD * In this option, the slave data ports can be connected in a wired-OR configuration with open-col- lector or open-drain outputs on the peripheral. Master Circuit Logic Flow Diagram TL/F/10819–6 Master Configuration State Chart Status Register Description D2 D1 D0 0 0 0 Not Used 0 0 1 In Process of Transmitting to Slave during Write Slave Mode 0 1 0 Valid Data Received from Slave 0 1 1 Not Used 1 0 0 Awaiting Data from Slave during Read Slave Mode 1 0 1 In Process of Transmitting to Slave during Read Slave Mode 1 1 0 Invalid Data Received from Slave * 1 1 1 Initialization/Idle Condition * This state is entered if address or parity do not match.

Timing Diagram Description TL/F/10819–7 Symbol Parameter Min Max Units tDS Data and Address Set-Up Time Ð 2 t OSC tDH Data and Address Hold Time 5 Ð t OSC tPV Serial Port Valid Ð 5 t OSC tPF Serial Port Float Ð 1733 t OSC tDV Output Data Valid Ð 1.0 ms tDF Output Data Float 0 ns t1 Overlap Requirement none Ð t2 Delay Between Master-Slave Transmission 0.2 1.4 ms t3 CS # Function 3 Ð t OSC tPD Rise and Fall Time Ð 100 ns Oscillator Calculations Conditions: V e 5V g5% F & 400 kHz b40§C s T s 85§C F e K RC where 0.8 s K s 1.4 Master Write Operation TL/F/10819–8

Timing Diagram Description (Continued) Master Read Operation TL/F/10819–9 t1ÐThere is no overlap requirement for CHIP SELECT t2ÐDelay between master-slave transmission 0.2 ms to 1.4 ms t3ÐMinimum duration is 3 cycles of oscillator clock * During ‘‘waiting to receive’’ state, CS coupled with R /C1 will force device into the device ready state. ** If address or parity do not match, the data invalid state is entered. CS coupled with R /C1 will force device into the device ready state.

Microprocessor Interface to Master Note: The timeout of the one-shot should be t 6 clock periods of the MM54240 oscillator. TL/F/10819–10 Microprocessor Interface to Master TL/F/10819–11 Note: The INS8255 is specified by the microprocessor to operate in mode 0. Port A is configured as input or output. Ports B and C are configured as output only. Load ports A and B prior to loading port C.

Typical Applications (Continued) Master to Slave (Short Distance) TL/F/10819–12 Master to Slave (Long Haul) TL/F/10819–13

MM54240 Asynchronous Receiver/Transmitter Remote Controller Physical Dimensions inches (millimeters) 24-Lead (SD) Molded Dual-In-Line Package (N) Order Number MM54240N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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