MM5309 NSC | Alldatasheet
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ica, (ek, SO eR | eae I ace Rs el ae ie he ie aaa * aa ees Beat el ee St Se National . Digital Clocks | 2 / Z yj J g MMS309, MM5311, MM5312, MM5313, = MM5314, /MM5315 Digital Clocks FA | General Description Ly 8 / -_> These digital clocks are monolithic MOS integrated Leading zero blanking (12our format) = circuits utilizing P-channel Jow-threshold, hancement “ ‘mode and ion implanted. depletion mode devices. The" 7-Segment outputs = devices provide all the logic required to build several fw Single su types of clocks. Two display modes (4 or 6-digits) inal pely = facilitate end-product designs of varied sophistication. Fast and slow set controls 8 The circuits interface to LED and gas discharge displays . ; with minimal additional components, and require only = Internal multiplex oscillator Pp 2 ‘single power supply. The timekeeping function w= For features of individual clocks, see Table | operates from either a 50 or 60 Hz input, and the dis- z play format may be either 12 hours (with leading-zero blanking) or 24 hours. Outputs consist of multiplexed display drives (BCD and 7-segment) and digit enables. The devices operate over a power supply range of 11V , to 19V and do not require a regulated supply. These Applications = clocks are packaged in dual-inline packages. = Desk clocks Rd Features = Automobile clocks = = 50 or 60 Hz operation © Industrial clocks FA "12 or 24-hour display format = Interval Timers 8 TABLE! > [Features T[wmssoe [ wwssin [ wwssra [ mmesrs | weave | wasars_| z B05 Outputs x x ‘Hold Count Control x _
1 Hz Output a
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ar . % | Absolute Maximum Ratings : . Voltage at Any Pin * Vgs + 0.3 to Vgg -,20V Operating Temperature -28°C to +70°C Storage Temperature 65°C to +150°C Lead Temperature (Soldering, 10 seconds) 300°C x | Electrical Characteristics 1 within operating range, Veg = 11V to 19V, Vp = OV, unless otherwise specified. SS | Power supply voltage Vss (Vpp = OV) n 19 v oo | Pomer Supely Curent Vsg = 14V, (No Output Loads) 10 mA TH | 50/60 Hz Input Frequency de 50 or 60 60k Hz 8 50/60 Hz Input Voltage b= Logical High Levet Vss-1 Vss Vss v = Logical Low Level Yop Vop Vss—-10 v Of | Multintex Frequency Determined by External R&C 0.100 1.0 60 kHz All Logic Inputs Driven by External Timebase de 60 kHz Logical High Level Internal Depletion Device to Vgg Vss-1 Vss Vss v = Logical Low Level Voo voo | Vss—10 v = | adn 7-Segment Outputs ad Logical High Level Loaded 2 k2 to Vpp 2.0 20 MA source Logical Low Level 0.01 | mA source
3 Digital Enable Outputs
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. SAE ee eet OES AO RE Se eS OREM ETS, Fits Re ee GR nn Se eR | RAR ee Functional Description : = A block diagram of the MM5309 digital clock is shown @-digit select input, the divider determines whether data g in Figure 1. MM5311, MM5312, MM5313, MMB314-—_will be output for 4 or 6 digits. A zero-blanking circuit and MMS315 clocks are bonding options of MM5309 suppresses the zero that would otherwise sometimes ba clock, Table 1 shows the pin-outs for these clocks. appear in the tens-oF-hours display; blanking is effective = only in the 12hour format. The multiplexer addresses z 50 or 60 Hz Input: This input is applied to a Schmitt _also become the display digit-enable outputs, The multi- Trigger shaping circuit which provides approximately _plexer outputs are applied to a decoder which is used SV of hysteresis and allows using a filtered sinewave to address a programmable (code converting) ROM. input. A simple RC fitter such as shown in Figure 10 This ROM generates the final output codes, i.e., BCD ard should be used to remove possible line voltage transients and 7-segment, The sequential output. order is. from = that could either cause the clock to gain time or damage digit 6 (unit seconds) through digit 1 (tens of hours). = the device. The shaper output drives a counter chain which performs the timekeeping function. Muttiplex Timing Input: The multiplex oscillator is = -_ shown in Figure 2. Adding an external resistor and g 50 or 60 Hz Select Input: This input programs the capacitor to this circuit via the multiplex timing input hed Prescale counter to divide by either 50 or 60 to obtain a (as shown in Figure 4a) produces a relaxation oscillator, r 1 Hz timebase. The counter is programmed for 60 Hz The waveform at this input is a quasi-sawtooth that is Operation by connecting this input to Vpp. An internal ‘squared by the shaping action of the Schmitt Trigger in z depletion device is common to this pin; simply leaving Figure 2. Figure 3 provides guidelines for selecting the this input unconnected programs the clock for 50 Hz external components relative to desired multiplex operation. As shown in Figure 1, the prescale counter frequency. Provides both 1. Hz and 10 Hz signals, which can be 3 brought out as bonding options, Figure 4 also illustrates two methods of synchronizing a. the multiplex oscillator to an external timebase. The - Time Setting Inputs: Both fast and slow setting inputs, external RC timing components may be omitted and 2 as well as a hold input, are provided. Internal depletion this input may. be driven by an external timebase; the = devicés provide the normal timekeeping function. ‘required logic levels are the same as 60 or 60 Hz input. a Switching any of these inputs (one at a time) to Vop " results in the desired time setting function. Reset: Applying Vpp to this input resets the counters g The three gates in the counter chain (Figure 1) are £0, 0:00:00.00 in 12-hour format and 00:00:00.00 in > Used for setting time. During normal operation, gate A 24-hour formats leaving the input unconnected (internal . connects the shaper output to a prescale counter (+50 ‘“‘ePletion pull-up) selects normal operation. Proper = ‘ ec reset will be ensured when Vpp to Vgg slew rate is or +60); gates B and C cascade the remaining counters. 4 r Gate A is used to inhibit the input to the counters for Po faster than, one volt Pert tern renee incn | the duration of slow, fast or hold time:setting input Pe vecomelished with @ capacitor from the reset input a activity. Gate B is used to connect the shaper output Ss. = directly to a seconds counter (+60), the condition for ‘ a slow Noe! Likewise, gate C 0), the the shaper 4 or 6-Digit Select Input: Like the other contro! inputs, output directly to a minutes counter (+60) for fast this input is provided with an internal depletion pull-up advance. device. With no input connection the glock outputs data for a 4:digit display. Applying Vip ‘to this input.pro- Fast set then, advances hours information at one hour _—Vides a G-digit display. Per second and slow set advances minutes information at one minute per second, Output Enable Input: With this pin unconnected the BCD and 7-segment outputs are enabled (via an internal 12 or 24-Hour Select Input: This input is used to pro- depletion pull-up). Switching Vpp to'this input inhibits gram the hours counter to divide by either 12 or 24, these outputs. (Not applicable to M5312, MM5313, thereby providing the desired display format. The and MM8315 clocks.) 12-hour display format is selected by connecting this input to VDD; leaving the input unconnected (internal Output Circuits: Figure Se illustrates the circuit used depletion device) selects the 24-hour format. for the BCD and 7-segment outputs. Figure 5b shows the digit enable output circuit. Figure 6 illustrates Output Multiplexer Operation: The seconds, minutes, interfacing these outputs to standard and low power and hours counters continuously reflect the time of day. TTL. Figures 7 and & illustrate methods of interfacing Outputs from each counter (indicative of both units _these outputs to common anode and common cathode and tens of seconds, minutes, and hours) are time- LED displays, respectively. A method of interfacing division multiplexed to provide digitsequential access _these clocks to gas discharge display tubes is shown in to the time data. Thus, instead of requiring 42 leads to Figure 9. When driving gas discharge displays which interconnect a 6-digit clock and its display (7 segments enclose more than one digit in a common gas envelope, per digit), only 13 output leads are required. The multi _it is necessary to inhibit the segment drive voltage(s) Blexer is addressed by a multiplex divider decoder, during inter-digit transitions. Figure 9 also illustrates a which is driven by a multiplex oscillator. The oscillator method of generating a voltage for application to the and external timing components set the frequency of output enable input to accomplish the required inter- the multiplexing function and, as controlled by the 4 or —_—_digit blanking. 5-15
5 Functional Description (conta) Seu wad
FIGURE 1. MMB5309 Digital Clock Block Diagram FIGURE 2. 50/60 Hz Shaping Circut/Multiplex Oxillator
2 Functional Description (cont’s) :
(M8861, OME863 or equivalent segment/digit drivers. FIGURE 7. Interfacing Common Anode LED Dispteys FIGURE 8. Interfecing Common Cathode LED Disptays