MM5298BN-2

MM5298 NSC | Alldatasheet

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National NMOS RAMs | = ae . MM5298"* 8192-Bit (8192 x 1) Dynamic RAM General Description Features ‘The MMB5298 is an B192x bk dynamic RAM. It features ™ 100% DC and AC compatible with MM5290 2 multiplexed address input with separate row and col- umn strobes. This added flexibility allows the MM5298 = Only 64 Refresh cycles every 2 ms to be used in page mode operation, The MM5208 - employs the same masks and highly reliable production: = Access Times: 150 ns, 200 ns, 260 ns proven 2iayer polysilicon NMOS technology as the MM5290. so noe os = Low power: 528 mW max ‘As shown in the block diagram, the MM5298 is available ‘TL compatible: all inputs and output as cither the upper or lower half of the MM5290. Address. sw Gated CAS—noncritical timin: AS selects the operating half. For MM529BA, AS should monenitical timing be low (VjL) during row address hold time (tRAH). For = Read, Write, Read-Modify-Write and RAS-only MM52988, A5 should be high (ViH) during tRAH. The Refresh cycles MM5298 requires only 64 cycles of Refresh every 2 ms. This can be accomplished by performing any cycle Page mode operation which brings the RAS active including an RAS-only cycle at each of the 64 row addresses used. = Industry standard 16-pin configuration Fa ted Block Diagram w— Voo Ye Mss Van . 8 a= a a wo oo WW — WRITE “— toes ‘ — ‘toces AOORESS LATCH caren row clocks couuwn a| [8 tons : 2] [| memory annar Connection Diagram Logic Diagram Pin Names Dual-In-Line Package RAS Row Address Strobe . TAS —Colurnn Address Strobe ‘ is 10 WE — Write Enable ‘" ‘s a . AO-AG Address Inputs oe 1° ay or Data Input 4 “ i" Do Data Output bad 90 a o Vop Power (12V) ~~~ 5 om Das M Voc Power.(5v) — : n Vss” “Ground ry , : a ‘ Ves Power (—5V) — aD Me ct) _ 5 . us Order Number MMS298AJ-2, MM5298BJ-2, “ fas MM5298AJ-3, MM5298BJ-3, Yoo sce lw MMS5298AJ-4 or MM5298BJ-4 See NS. Package JI6A torview Order Number MMS298AN-2, MM5298BN-2, * MM65298AN-3, MMS298BN-3, For MMB29BA AS must be ot Vj during tal For MM6298B AS must be at Viqj during thay. MM5298AN-4 or MM5298BN-4 ** Seo the MST™ Program page 3. See NS Package N16A 161

g Absolute Maximum Ratings (note 1) Lp | Storage Temperature 65°C to +150°C = Power Dissipation iw . . Voltage on Any Pin Relative to Vgg--0.3V to +20V = | ss - Vee > 4.5V) . Lead Temperature (Soldering, 10 seconds) 300°C Recommended DC Operating Conditions SYMBOL PARAMETER [ wn | max | _ units NOTES Vop Supply Voltages 10.8 13.2 v 2.3 Veco 45 55 v 2,3 Yss ° 0 v 2,3 Vee : -45 “65 v 23 VIHC Input High Voltage, RAS, CAS, WE 27 7.0 v 2 Vin Input High Voltage, AO—A6, DI 24 7.0 v 2 SYMBOL PARAMETER [| min [max | units NOTES loot Operating Current 40 mA 4 loca Average Power Supply Operating Current 5 Ips (RAS, CAS Cycling: tae = tRC MIN) 200 ~ A Ipp2 Standby Current 15 ma Los loca Power Supply Standby Current (RAS ~ Vic, 19 we Ige2 DO= High impedance) 100 ua loos Refresh Current 30 mA 4 loca Average Power Supply Current, Refresh Mode 10 my 'ge3 (RAS Cycling, CAS = Vic: tac = 1RC MIN) 200 uA topa Page Mode Current 32 ma 4 loca Average Power Supply Current, Page Made 5 Ippa (RAS = Vy,, CAS Cycling; tpe = 225 ns) 200 wh . ne Input Leakage wa Input Leakage Current, Any Input (Vgp = -5V, OV < Vin < 7V, All Other . Pins not Under Test = OV) . low Output Leakage - uA Output Leakage Current (DO is Disabled, OV <Voyt <5.5V) . . Output Levels Vou Output High Voltage (Igyt = —5 mA) 24 v Vou Output Low Voitage (IguT = 4.2 mA) Vv CAPACITANCE ‘ _ Ge Input Capacitance RAS, CAS, WE ee Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply thet the devices should be operated at these limits. The table of “Recommended DC Operating Conditions” provides conditions for actuat device operation. Note 2: All voltages referenced to Vgg. When applying voltages to the device, Vpp. Voc or Vgg should never be 0.3V more negative than Vag. Note 3: Several cycles are required after power-up before proper device operation is achieved. Any 8 RAS cycles are adequate for this purpose. Note 4: Ipp1. !pp3. and Ipp4 depend on cycle rate. Note 5: I¢g depende on output load. Note: Capacitance measured with Boonton Meter or effective capacitance calculated from the equation C * |4t/AV. Capacitance is quarnteed by periodic testing. 762

Over the range of Recommended DC Operating Conditions unless otherwise noted a MM5298-2A, (MM5298-34, MM5298-4, 3 syMBoL PARAMETER MM5298-28 MM5298-38 MMS298-4B UNITS | NOTES TRC Random Read or Write Cycle Time 375 378 410 8 7.8 two Read Write Cycle Time 375 375 515 ns 1.8 tec Page Mode Cycle Time 170 225 275 ns tRAC Access Time from RAS. 150 200 250 ns ait 'cAc Access Time from CAS, 100 135 165 ns 10,11 tOFF Output Buffer Turn-Ott Delay o | 40 0 |so o eo 1s 12 T Transitian Time (Rise and Fat!) 3 135 3 [so 3 {so ns tre RAS Precharge Time 100 120 150 ns tras RAS Pulse width : 150 | 10,000 | 200 | 10,000 | 250 | 10,000 ns tRSH RAS Hold Time 100 135 165 ns TCAS CAS Pulse Width 100 | 10,000 } 135 |10,000 | 165 10,000 ns tACD RAS to CAS Delay Time 20 50 By 65 35 85 ns 9 TcRP CAS to RAS Precharge Time -20 -20 -20 ns tah Row Address Set-Up Time o ° 0 rs tRAH Row Address Hold Time 20 & cr ns tasc Column Address Set-Up Time -10 “10 10 ns tcaH Column Address Hold Time 45 3 8 ns tar Column Address Hold Time Referenced to RAS 95 120 160 ns tres Read Command Set-Up Time 0 o o ns tRCH Read Command Hold Time o ° ° ne ‘wou Write Command Hold Time 45° 55 78 ns wor Write Command Hold Time Referenced to RAS | 95 120 160 ns . ‘we Write Command Pulse Width 45 55 18 ns tAWL Write Command to RAS Lead Time 60 80 100 ns tow Write Command to GAS Lead Time 60 80 100 ns tos Date-In Set-Up Time 0 o ° ns 13,14 ‘OH Date-tn Hold Time 45 55 75 ns 13,14 ‘OHR Data-In Hold Time Referenced to RAS. 95 120 160 os tcp TAS Precharge Time (for Page Mode 60> 80 100 ns Cycle Only) tREF Retresh Period 2 2 2 ms twes WE to CAS Set-Up Time —40 |. 40 40 ns 14 towo CRS to WE Delay 70 95 125 ns 15 tRWD RAS to WE Delay 120 160 200 ns 15 Note 7: The specifications for tac(mIN) @"¢ TRWC(MIN) 4'@ used only to indicate cycle time at which proper operation over the full tempera: ture range is guaranteed. Note 8: Transition times are measured between Vi} oF V4} and Vix. Timing measurements are mode between ViHCIMIN) OF VaHinmiNy) and VILIMAX), and assume ty = 5 ns. Note 9: Assumes row-limited access, i.. {RCD S 'RCDIMAX): If this condition is not satisfied, then note 10 applies. Note 10: Assumes column-limited access, i.€., tac > tRCD(MAX)- : Note 11: Equivalent load is 2 standard TTL inputs plus 100 pF. - Note 12: GAS going high disables the Oata Output. tor F is the delay to the high impedance state. Note 13: These parameters are referenced to the negative edge of CAS in an early-write cycie and to the negative edge of WE in a Read-Modity- Write cycle. (See Note 14 below). Note 14: If twos > 'WCS(MIN), the Data Output is guaranteed to remain in the high impedance state for the duration of the cycle. This is the “early-write” cycle, Note 18: 16 town > tcwOIMin) 2nd ERY > tRWDIMIN): the Dota Ourput will contain the original data im the selected Celt, This is the Read: Modity-Write cycle. If either of these conditions Is not satisfied, the ourput will be indeterminate uniess the early-write condition of Note 12 is met. 163

g Switching Time Waveforms = Read Cycle = Re. oo RP J ‘ore ni : T - | +

Switching Time Waveforms (continued) = Read-Write Cycle, Read-Modify-Write Cycle 3 ee), Ge 77 (ae Uddin lal, ge ae de vay We | =

8 Switching Time Waveforms (continued)

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