MM5290

MM5290 NSC | Alldatasheet

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*. . . MM5290'16,384-Bit (16,384 x 1) Dynamic RAM General Description The MM5290 is a 16,384 x 1 bit dynamic RAM. It by the use of @ 16-pin dual-in-line package for the features a multiplexed address input with separate row MM5290. and column strobes. This added flexibility allows the MM5290 to be used in page mode operation. Features The MM5290 must be refreshed every 2ms, This canbe Access times: 150-ns, 200 ns, 250 ns accomplished by performing any cyélé Which brings the = Low power: 628 mW max Row Address Strobe active including a RAS-only cycle = TTL compatible: all inputs and output at each of the 128 row addresses: > "Gated CAS—noncritical timing ~N-channel double-paly silicon gate technology, developed = Read, Write, Read-Modify-Write and RAS-onty by National, is used in the manufacture of the MMS290. Refresh cycles This process combines high density and performance ‘Page mode operation with reliability, Greater system densities are achievable Industry standard 16-pin configuration Block Diagram . a Yoo Yee. ‘s Vem o a oo 1 a wo Nw wy a write 1 ctoces a— Stocks AoonESS LATER rot) now non locas co a s ttoexs z Connection Diagram Logic Diagram Pin Names Dual-in-Line Package FAS Row Address Strobe CAS — Column Address Strobe mt sy, WE — Writa Enable an is ; . AO-AG Address Inputs o om DI Data Input A « DO Data Output " 2 be Voo Power (12V) m— ny Vec Power (5V) 5 2 Vss Ground ” “ Vee Power (SV) at ona . : 1 ae Order Number MM5290J-2, MM5290J-3, q “ ‘or MM5290)-4 o vo + Vee See NS Package J16A o Order Number MM5290N-2, MM5290N-3, ror wow ‘or MM5290N-4 *See the MST™ Program page 3. See NS Package N16A 155

& Absolute Maximum Ratings (note 1) wo Storage Temperature 65°C to +150°C - S | Power Dissipation w Voltage on Any Pin Relative to Vgg 0.3 to +20V = | (vss Vas > 4.6v) Lead Temperature (Soldering, 10 seconds) 300°C Recommended DC Operating Conditions Ta | Aenbine Tampere Toe Yop Supply Voltages 10.8 v 2,3 Voc 45 Vv 2,3 Vss o v 2.3 Vee 45 v 2,3 ViHC Input High Voltage, RAS, CAS, WE 27 7.0 v 2 Vi Input High Voltage, AO-AG, DI 24 7.0 v 2 SYMBOL PARAMETER [ min] max | units NOTES Ipp1 Operating Current 35 mA 4 Iect Average Power Supply Operating Current 5 'gB1 (RAS, CAS Cycling; tac = tRC MIN) 200 uA loz Standby Current mA loca Power Supply Standby Current (RAS = Vir, uA tae2 DO= High impedance) BA loos Refresh Current mA 4 lec3 ‘Average Power Supply Current, Refresh Mode uA 'gB3 (RAS Cycling, CAS = Vic: tRc = tre MIN) BA Ippa Page Mode Current 2 mA 4 'eca Average Power Supply Current, Page Mode 5 'BBa (RAS = Vi, CAS Cycling; tpc = 225 ns) 200 uA Wu Input Leakage uA Input Leakage Current, Any Input (VpB - -5V. OV < Vin <7V, All Other Ping not Under Test = OV} toy Output Leakage 10 HA Output Leakage Current (DO is Disabled, OV < Vour <5.5Vb : Output Levels Vou Output High Voltage (gut = 5 mA) v Vou Output Low Voltage (lout = 4.2 mA) v CAPACITANCE G1 Input Capacitance AD-AG, DI es ee ee c Input Capacitance RAS, CAS, WE a Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed, Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Recommended DC Operating Conditions” provides conditions for actual device operation. Note 2: Alll voltages referenced to Vgg. When applying voltages to the device, Vp, Vcc oF Vsg should never be 0.3V more negative than Ves: Note 3: Several cycles are required after power-up before proper device operation is achieved. Any 8 RAS cycles are adequate for this purpose. Note 4: 1pp1. |Dp3. 2nd Ipp4 depend on cycle rate. Note 5: leg depends on output load. Note 6: Capacitance meesured with Boonton Meter or effective capacitance calculated from the equation C = 14t/AV. Capacitance is guaranteed by periodic testing. 156

‘Over the range of Recommended DC Operating Conditions unless otherwise noted a symBoL PARAMETER [amen [inns | antes} ars | NOTES 8 tre Random Read or Write Cycle Time 375 375 410 ns 78 tawe Read Write Cycle Time 375 375 515 ns 7.8 tC Page Mode Cycle Time 170 225 278 ns trac Access Time from RAS 150 200 260 ns an tcac | Access Time trom GAS 100 136 165 ns 10,11 torr Output Buffer Turn-Off Delay 0 440 o {so 0 }6o ns 12 : T ‘Transition Time (Rise and Fall) 3 | 358 3 {so 3 |s0 ns tap RAS Precharge Time 100 120 150 ns tRAS RAS Pulse Width 150 | 10,000} 200 | 10,000 | 250 {10,000 ns TASH RAS Hold Time 100 135 165 ns tCSH CAS Hold Time 150 200 250 ns tcas CAS Pulse Width 100 | 10,000 | 135 | 10,000 | 165 | 10,000 ns taco RAS to GAS Delay Time 20 «| 50 26 «| 65 35 85 ns 9 'cRP TAS to RAS Precharge Time -20 -20 -20 ns tasR Row Address Set-Up Time 0 o ° ns 'RAH Row Address Hold Time 20 26 Ey os tasc Column Address Set-Up Time 10 10 =10 os ‘CAH Column Address Hold Time 45 55 78 ns TAR Column Address Hold Time Referenced to RAS | 95 120 160 98 tacs Read Command Ser-Up Time 0 0 0 ns tRcH Read Command Hold Time ° 0 0 ns ‘wen Write Command Hold Time 45 55 78 ns wWCR Write Command Hold Time Referenced to RAS. 95 120 160 ns ‘we Write Command Pulse Width 45 55 76 ns tRWL Write Command to RAS Lead Time 60 80 100 ns tow Write Command to CAS Lead Time 60 80 100 ns tos Data-in Set-Up Time ° ° o ns 13,14 tOH Data-In Hold Time 45 65 5 ns 13,14 1DHR Data-In Hold Time Referenced to RAS 95 120 160 ns tor CAS Precharge Time (for Page Mode 60 80 100 as Cycle Only) tREE Refresh Period 2 2 2 ms ‘wes WE to CAS Set-Up Time ~20 ~20 -20 ns “4 ‘wo CAS to WE Delay 70 95 125 ns 15 ‘AWD RAS to WE Delay 120 160 200 ns 18 Note 7: The specifications for tacimin) and tRWCIMIN) @ré used only to indicate cycle time at which proper operation over the full tempera- ture range is guaranteed. Note 8: Transition times are measured between Vjjic oF Vi} and Vii. Timing measurements ere made between ViHC(MIN) OF VIH(MIN) and VILIMAX), and assume ty = 5 ns. Note 9: Assumes row-limited access, ie., tcp < tRCDIMAX!: If this condition is not satisfied, then note 10 applies. Note 10: Assumes column-Hmited access, 2. tRCD > *RCDIMAX)- Note 11: Equivalent load is 2 standard TTL inputs plus 100 pF. Note 12: CAS going high disables the Data Output. tore is the delay to the high impedance state. Note 13: These parameters are referenced to the negative edge of CAS in an early-write cycle and to the negative edge of WE in a Read-Modity- Write cycle. (See Note 12). Note 14: If twos > tWCsiMiN). the Data Output is guaranteed to remain in the high impedance state for the duration of the cycle. This is the “early-write” cycle. Nowe 18: If tcwp > tcwDIMIN) 8nd tR~YD = tRYDIMIN: the Data Output will contain the original data in the selected cell. This is the Read. Modify.Write cycle. If either of these conditions is not satisfied, the output will be indeterminate unless the early-wwrite condition of Note 12 is met. 157

Fa Switching Time Waveforms = Read Cycle , = ‘ee os SH y / SS

Switching Time Waveforms (continues) ‘ 4 o Read-Write Cycle, Read-Modify-Write Cycle 3 oe), Ge 77 1: YMMMaMsdwq@-, ee //// a CMM

g Switching Time Waveforms (continued) ) w = Page Mode Read Cycle ~: EOE 2 QUID = che Lan at