MM2101

MM2101 NSC | Alldatasheet

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GY MOS RAMs |§ NATIONAL 2 MM2101, MM2101-1, MM2101-2 1024-bit (256 x 4) static MOS RAM g with separate I/O = general description features = The National MM2101 is a 256 word by 4 bit static = Organization 256 Words by 4 Bits 3 random access memory element fabricated using N- i Channel enhancement mode Silicon Gate technology Access Time — 0.5 to 1.0 us Max. Static storage cells eliminate the need for refresh and ® Single +5 V Supply Voltage the additional peripheral circuitry associated with refresh. @ Directly TTL Compatible — All Inputs and Outputs The data is read out nondestructively and has the same polarity as the input data, ® Static MOS — No Clocks or Refreshing Required The 2101 is directly TTL compatible in all respects: ™ Simple Memory Expansion — Chip Enable Input inputs, outputs, and a single +5 V supply. Two chip- © Low Cost Packaging — 22 Pin Epoxy B Dual-In-Line enables allow easy selection of an individual package Configuration when outputs are OR-tied. An output disable is provided | ow Power — Typically 150 mW so that data inputs and outputs can be tied for common ® 1/0 systems. The features of this memory device canbe ™ Tri-State © Output ~ OR-Tie Capability combined to make a low cost, high performance, and — ™ Output Disable Provided for Ease of Use in Common easy to manufacture memory system Data Bus Systems National's silicon gate technology also provides protec- tion against contamination, and permits the use of low cost Epoxy B packaging. block and connection diagrams no >| 0 vee “ vec 3 ’ ne Me a = —_—o wo re Rw 2 cow CELL ARRAY " ” Dea] sttter 32 ROWS, ro m fi m2 coLUMNS i" a Ws C a ” ce Me == i» 0 a a A ono oe E wrur voz o 0 on a a rk " 2 a BH conrnot rarer

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ou = a} DIy-Dig DATA INPUT = Ag: Ay ADDRESS INPUTS a =o PS on Rw?) READIWRITE INPUT [* Cet, ce2 CHIP ENABLE cet D> Db; oo OUTPUT DISABLE 1" 00-004 DATA OUTPUT oo Do Vee POWER (+5 V) Order Number MM2101D, MiM2101-1D or MM2101-2D ‘See Package 5 Order Number MM2101-N, MMM2101-1N or MM2101-2N ‘See Package 17

&S | absolute maximum ratings W | Ambient Temperature Under Bias 0°C to +70°C S | Storage Temperature ~65°C to +150°C Ss Voltage on Any Pin With Respect to Ground -0.5 V to +7. V Power Dissipation 1 Watt x] . =| dc electrical characteristics tT, = 0°c to +70°c, Vcc = 5 V + 5% unless otherwise specified. N tu Input Current 10 | vA | Vin=0t05.25V s 'LOH 1/0 Leakage Current!2] 15 BA CE1= 2.2 V, VouT=4.0V Ss ILOL | 1/0 Leakage Current(2! -50 | wA | CE1=22V, VoyT=045V lect Power Supply Current 60 | mA | ViN=5.25V, 19 =0mA Ta = 25°C Icc2 | Power Supply Current 70 | mA |. ViN=5.25V,19=0mA Ta=0°C ~ Vit Input “Low” Voltage 0.5 +0.65, v Vin Input “High” Voltage 22 Veco Vv Vo Output “Low” Voltage 40.45) Vi | IoL=2.0maA VOH Output “High” Voltage 22 v 10H = -150 nA Note 1: Typical values are for Ta = 25°C and nominal supply voltage. Note 2: Input and Output tied together capacitance T,= 25°C, f= 1 MHz Limits (pF) CIN Input Capacitance (All Input Pins) Vin = 0 V 8 Cout | Output Capacitance VouT = 0 V 12 switching time waveforms READ CYCLE (R/W=""1") WRITE CYCLE(2! + ———tncy +) ‘wey. i CD sooness KF ‘00 (common 1/0) 9) ‘OH: hed boa" al orl. —-| rw Note 1: tpg is with respect to the trailing edge of GE1, CE2, or OD, whichever occurs first. Note 2: During the write cycte, OD is a logical 1 for common 1/0 and “don't care" for separate 1/0 operation. Note 3: OD should be tied low for teparate 1/0 operation.

ac electrical characteristics T= 0°C to +70°C, Vcc = 5 V + 5%, unless otherwise specified. FS S MM2101 g READ CYCLE 2 tRCY Read Cycle 1,000 Input Pulse Levels: +0.65 to+2.2V | N tA Access Time 1,000 Input Pulse Rise and Fall Times: Sg tco Chip Enable to Output 800 20 ns > top Output Disable to Output 700 Timing Measurement Reference = tor!) | Data Output to High Z State 0 200 Level: 1.5V 2 toH Previous Data Read Valid after 0 Output Load: : TTL Gate and FY change of Address CL = 100 p 3 WRITE CYCLE 3 g twcy Write Cycle 1,000 Input Pulse Levels: +0.65 to +2.2V | Rp taw Write Delay 150 Input Pulse Rise and Fall Times: tew Chip Enable to Write 900 20ns tow Data Setup 700 Timing Measurement Reference toH Data Hold 100 Level: 1.5 V twp Write Pulse 750 Output Load: 1 TTL Gate and twR Write Recovery 50 CL = 100 pF MM2101-1 (500 ns Access Time) READ CYCLE trcy Read Cycle 500 Input Pulse Levels: +0.65 to +2.2 V ta Access Time 500 Input Pulse Rise and Fall Times: tco Chip Enable to Output 350 20 ns top Output Disable to Output 300 Timing Measurement Reference < toglt Data Output to High Z State i) 150 Level: 1.5.V toH Previous Data Read Valid after oO Output Load: erm Gate and change of Address CL= 100 WRITE CYCLE twey | Write Cycle 500 Input Pulse Levels: +0.65 to +2.2 V taw Write Delay 100 Input Pulse Rise and Fall Times: tow Chip Enable to Write 400 20 ns tow Data Setup 280 Timing Measurement Reference {DH Data Hold 100 Level: 1.5 V ‘we Write Pulse 300 Output Load: 1 TTL Gate and twR Write Recovery 50 CL = 100 pF MM2101-2 (650 ns Access Time) Symbol | __ Parmeter | win [ Typ [ Wine [ Unit [Ton Conditions READ CYCLE tRCY Read Cycle 650 Input Pulse Levels: +0.65 to +2.2 V tA Access Time 650 Input Pulse Rise and Fall Times: tco Chip Enable to Output 400 20ns top Output Disable to Output 350 Timing Measurement Reference tpl! | Data Output to High Z State 0 150 Level: 1.5V tOH Previous Data Read Valid after 0 Output Load: 1 TTL Gate and change of Address CL = 100 pF WRITE CYCLE twcy Write Cycle 650 Input Pulse Levels: +0.65 to +2.2 V tTAW. Write Delay 150 Input Pulse Rise and Fall Times: tow Chip Enable to Write 550 20 ns tow Data Setup 400 Timing Measurement Reference ‘DH Data Hold 100 Level: 1.5 V . ‘we Write Pulse 400 Output Load: 1 TTL Gate and vtWR Write Recovery 560 C= 100 pF Note 1: tof is with respect to the trailing edge of CET, CE2, or OD, whichever occurs firs.