Microcontroller

MKW38A512VFT4

NXP Semiconductors

An ultra low-power, highly integrated Bluetooth짰 Low Energy 5.0 wireless microcontroller Rev. 7, 03/2020

Manufacturer: NXP Semiconductors

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Technical content

An ultra low-power, highly integrated Bluetooth® Low Energy 5.0 wireless microcontroller Multi-Standard Radio

2.4 GHz Bluetooth Low Energy (Bluetooth LE) version 5.0 compliant supporting up to 8 simultaneous hardware connections and all optional features including:
High speed (2M PHY)
Long range
Advertising Extension
High duty cycle non-connectable advertising
Channel selection algorithm #2
Typical Bluetooth LE Receiver Sensitivity
Bluetooth LE 2 Mbit/s: –95.5 dBm
Bluetooth LE 1 Mbit/s: –98 dBm
Bluetooth LE LR 500 kbit/s: –101 dBm
Bluetooth LE LR 125 kbit/s: –105 dBm
Generic FSK modulation
Data Rate: 250, 500, 1000 and 2000 kbit/s
Modulations: GFSK BT = 0.5, MSK
Modulation Index: 0.32, 0.5, 0.7, and 1.0
Typical Receiver Sensitivity (250 kbit/s GFSK-
Programmable Transmitter Output Power: –30 dBm to +5 dBm
Low external component count for low-cost application
On-chip balun with single ended bidirectional RF port System peripherals
Nine MCU low-power modes to provide power optimization based on application requirements
DC-DC Converter supporting Buck and Bypass operating modes
Direct Memory Access (DMA) controller
Computer Operating Properly (COP) watchdog
Serial Wire Debug (SWD) Interface and Micro Trace buffer
Bit Manipulation Engine (BME) Timers
16-bit Low-power Timer (LPTMR)
3 Timer/PWM Modules(TPM): One 4 channel TPM and two 2 channel TPMs
Programmable Interrupt Timer (PIT)
Real-Time Clock (RTC) Communication interfaces
2 Serial Peripheral Interface (SPI) modules
2 Inter-integrated Circuit (I2C) modules
Low-power UART (LPUART) module with LIN support (2x LPUART on KW38)
Carrier Modulator Timer (CMT)
FlexCAN module (with CAN FD support up to 3.2 Mbit/s baudrate) on KW38 MKW39A512VFT4 MKW38A512VFT4 MKW38Z512VFT4 MKW37A512VFT4 MKW37Z512VFT4 48 "Wettable" HVQFN 7x7 mm Pitch 0.5 mm NXP Semiconductors MKW39A512 Data Sheet: Technical Data Rev. 7, 03/2020 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

16-bit Analog-to-Digital Converter (ADC)
6-bit High-Speed Analog Comparator (CMP)
1.2 V Voltage Reference (VREF) MCU and Memories
256 KB program flash memory plus 256 KB FlexNVM on KW39/38
512 KB program flash memory on KW37
8 KB FlexRAM supporting EEPROM emulation on KW39/38
8 KB program acceleration RAM on KW37
On-chip 64 KB SRAM
Up to 48 MHz Arm® Cortex®-M0+ core Low-power Consumption
Transceiver current (DC-DC buck mode, 3.6 V supply)
Typical Rx current: 6.3 mA
Typical Tx current: 5.7 mA
Low-power Mode (VLLS0) Current: 266.6 nA Security
AES-128 Hardware Accelerator (AESA)
True Random Number Generator (TRNG)
Advanced flash security on Program Flash
80-bit unique identification number per chip
40-bit unique Media Access Control (MAC) sub- address
LE Secure Connections Clocks
26 and 32 MHz supported for Bluetooth LE and Generic FSK modes
32.768 kHz Crystal Oscillator Operating Characteristics
Voltage range: 1.71 V to 3.6 V
Ambient temperature range: –40 to 105 °C
AEC Q100 Grade 2 Automotive Qualification
Industrial Qualification Human-machine Interface (HMI)
General-purpose input/output (GPIO) KW39/38/37 Part Numbers Device Qualification Tier CAN FD 512 KB P-Flash

256 KB P-

MKW39A512VFT4 Auto AEC-Q100 Grade 2 N N Y N Y 7X7 mm 48- pin "Wettable" HVQFNMKW38A512VFT4 Auto AEC-Q100 Grade 2 Y N Y Y Y MKW38Z512VFT4 Industrial Y N Y Y Y MKW37A512VFT4 Auto AEC-Q100 Grade 2 N Y N N N MKW37Z512VFT4 Industrial N Y N N N Related Resources Type Description Product Selector The Product Selector lets you find the right Kinetis part for your design. Fact Sheet The Fact Sheet gives overview of the product key features and its uses. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal connections. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Package drawing Package dimensions are available in package drawings. 2 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

MKW39/38/37 Data Sheet, Rev. 7, 03/2020 3 NXP Semiconductors

6.2.6 Diagram: Typical IDD_RUN operating behavior46

4 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

1 Introduction

The KW39/38/37 wireless microcontrollers (MCU), which includes the KW39A, KW38A/Z and KW37A/Z families of devices, are highly integrated single-chip devices that enable Bluetooth Low Energy 5.0 and Generic FSK connectivity for automotive, and industrial embedded systems. To meet the stringent requirements of automotive applications, the KW39/38/37 is fully AEC Q100 Grade 2 Automotive Qualified. The target applications center on wirelessly bridging the embedded world with mobile devices to enhance the human interface experience, share embedded data between devices and the cloud and enable wireless firmware updates. Leading the automotive applications is the Digital Key, where a smartphone can be used by the owner as an alternative to the key FOB for unlocking and personalizing the driving experience. For a car sharing experience, the owner can provide selective, temporary authorization for access to the car allowing the authorized person to unlock, start, and operate the car using their mobile device using Bluetooth LE. The KW39/38/37 Wireless MCU integrates an Arm® Cortex-M0+ CPU with up to 512 KB flash and 64 KB SRAM and a 2.4 GHz radio that supports Bluetooth LE 5.0 and Generic FSK modulations. The Bluetooth LE radio supports up to 8 simultaneous connections in any master/slave combination. The KW38 includes an integrated FlexCAN module enabling seamless integration into a cars in-vehicle or an industrial CAN communication network, enabling communication with external control and sensor monitoring devices over Bluetooth LE. The FlexCAN module can support CAN’s flexible data-rate (CAN FD) protocol for increased bandwidth and lower latency required by many automotive applications. The KW39/38/37 devices can be used as a "BlackBox" modem to add Bluetooth LE or Generic FSK connectivity to an existing host MCU or MPU (microprocessor). The devices may also be used as a standalone smart wireless sensor with embedded application where no host controller is required. The RF circuit of the KW39/38/37 is optimized to require very few external components, achieving the smallest RF footprint possible on a printed circuit board. Extremely long battery life is achieved through the efficiency of code execution in the Cortex-M0+ CPU core and the multiple low-power operating modes of the KW39/38/37. For power critical applications, an integrated DC-DC converter enables operation from a single coin cell or Li-ion battery with a significant reduction of peak receive and transmit current consumption. Introduction MKW39/38/37 Data Sheet, Rev. 7, 03/2020 5 NXP Semiconductors

2 Feature Descriptions

2.1 Block Diagram

4 MHz

64 KByte

Figure 1. KW39 Detailed Block Diagram Figure 2. KW38 Detailed Block Diagram

Figure 3. KW37 Detailed Block Diagram Table 1. List of IPs in block diagrams Table continues on the next page...

Table 1. List of IPs in block diagrams (continued)

2.2 Radio features

2.4 GHz ISM band (2400-2483.5 MHz)
Medical Body Area Network frequency band (MBAN) 2360-2400 MHz Supported standards:
Bluetooth Low Energy Version 5.0 compliant radio supporting all mandatory and optional features including:
Bluetooth LE 4.2 errata
2 Mbit/s high-speed mode
Long range coded PHY (125/500 kbit/s)
Advertising Extensions
High duty cycle non-connectable advertising
Channel selection algorithm #2
Support for up to 8 simultaneous Bluetooth LE hardware connections in any master, slave combination
Bluetooth LE Application Profiles
Generic FSK modulation supporting data rates of 250, 500, 1000 and 2000 kbit/s Other features:
Programmable transmit output power up to +5 dBm with greater than 30 dB power control dynamic range Feature Descriptions 8 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK modes
Up to 26 devices supported by whitelist in hardware
Up to 8 private resolvable addresses supported in hardware
Supports DMA capture of IQ data and phase for localization applications
Support for distance estimation and direction finding applications
Integrated on-chip balun
Single ended bidirectional RF port shared by transmit and receive
Low external component count
Supports transceiver range extension using external PA and/or LNA

2.3 Microcontroller features

Up to 48 MHz CPU
As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles per instruction)
Supports up to 32 interrupt request sources
Binary compatible instruction set architecture with the Cortex-M0 core
Thumb instruction set combines high code density with 32-bit performance
Serial Wire Debug (SWD) reduces the number of pins required for debugging
Micro Trace Buffer (MTB) provides lightweight program trace capabilities using system RAM as the destination memory Nested Vectored Interrupt Controller (NVIC)
32 vectored interrupts, 4 programmable priority levels
Includes a single non-maskable interrupt Wake-up Interrupt Controller (WIC)
Supports interrupt handling when system clocking is disabled in low-power modes
Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep
A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked interrupt is detected Debug Controller Feature Descriptions MKW39/38/37 Data Sheet, Rev. 7, 03/2020 9 NXP Semiconductors

Two-wire Serial Wire Debug (SWD) interface
Hardware breakpoint unit for 2 code addresses
Hardware watchpoint unit for 2 data items
Micro Trace Buffer for program tracing On-Chip Memory
Up to 512 KB Flash
KW39/38 contains 256 KB program flash with ECC and 256 KB FlexNVM enabling EEPROM emulation.
KW37 contains 512 KB program flash with ECC.
Flash implemented as two equal blocks each of 256 KB block. Code can execute or read from one block while the other block is being erased or programmed on KW37 only.
Firmware distribution protection. Program flash can be marked execute-only on a per-sector (8 KB) basis to prevent firmware contents from being read by third parties.
64 KB SRAM
KW39/38 contains 8 KB FlexRAM enabling EEPROM emulation.
KW37 contains 8 KB program acceleration RAM.
Security circuitry to prevent unauthorized access to RAM and flash contents through the debugger

2.4 System features

Power Management Control Unit (PMC)

Programmable power saving modes
Available wake-up from power saving modes via internal and external sources
Integrated Power-on Reset (POR)
Integrated Low Voltage Detect (LVD) with reset (brownout) capability
Selectable LVD trip points
Programmable Low Voltage Warning (LVW) interrupt capability
Individual peripheral clocks can be gated off to reduce current consumption
Internal Buffered bandgap reference voltage
Factory programmed trim for bandgap and LVD
1 kHz Low-power Oscillator (LPO) DC-DC Converters Feature Descriptions 10 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Internal switched mode power supply supporting Buck and Bypass operating modes
Buck operation supports external voltage sources of 2.1 V to 3.6 V
When DC-DC is not used, the device supports an external voltage range of 1.5 V to 3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_RF3 and VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1, and VDDA pins)
An external inductor is required to support the Buck mode
The DC-DC Converter VDD_1P8OUT current drive for external devices (MCU in RUN mode, Radio is enabled, other peripherals are disabled)
Up to 45 mA in buck mode with VDD_1P8OUT = 1.8 V
Up to 27 mA in buck mode with VDD_1P8OUT = 3.0 V Direct Memory Access (DMA) Controller
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses and transfer size
Support for enhanced addressing modes
4-channel implementation that performs complex data transfers with minimal intervention from a host processor
Internal data buffer, used as temporary storage to support 16- and 32-byte transfers
Connections to the crossbar switch for bus mastering the data movement
Transfer Control Descriptor (TCD) organized to support two-deep, nested transfer operations
32-byte TCD stored in local memory for each channel
An inner data transfer loop defined by a minor byte transfer count
An outer data transfer loop defined by a major iteration count
Channel activation via one of three methods:
Explicit software initiation
Initiation via a channel-to-channel linking mechanism for continuous transfers
Peripheral-paced hardware requests, one per channel
Fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
One interrupt per channel, optionally asserted at completion of major iteration count
Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller
Optional support for scatter/gather DMA processing
Support for complex data structures Feature Descriptions MKW39/38/37 Data Sheet, Rev. 7, 03/2020 11 NXP Semiconductors

DMA Channel Multiplexer (DMA MUX)

4 independently selectable DMA channel routers
2 periodic trigger sources available
Each channel router can be assigned to 1 of the peripheral DMA sources COP Watchdog Module
Independent clock source input (independent from CPU/bus clock)
Choice between two clock sources
LPO oscillator
Bus clock System Clocks
Both 26 MHz and 32 MHz crystal reference oscillator supported for Bluetooth LE and Generic FSK modes
MCU can derive its clock either from the crystal reference oscillator or the Frequency-locked Loop (FLL)1
32.768 kHz crystal reference oscillator used to maintain precise Bluetooth Low Energy timing in low-power modes
Multipurpose Clock Generator (MCG)
Internal reference clocks — Can be used as a clock source for other on-chip peripherals
On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 3% accuracy across full temperature range
On-chip 4 MHz oscillator with 11% accuracy across full temperature range
Frequency-locked Loop (FLL) controlled by internal or external reference
20 MHz to 48 MHz FLL output Unique Identifiers
80-bit Unique ID represents a unique identifier for each chip
40-bit unique Media Access Control (MAC) address, which can be used to build a unique 48-bit Bluetooth Low Energy MAC address

2.5 Peripheral features

16-bit Analog-to-Digital Converter (ADC)

Linear successive approximation algorithm with 16-bit resolution
Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode 1. Clock options can have restrictions based on the chosen SoC configuration. Feature Descriptions 12 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode
Single or continuous conversion
Configurable sample time and conversion speed/power
Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
Input clock selection
Operation in low-power modes for lower noise operation
Asynchronous clock source for lower noise operation
Selectable asynchronous hardware conversion trigger
Automatic compare with interrupt for less-than, or greater than, or equal to programmable value
Temperature sensor
Battery voltage measurement
Hardware average function
Selectable voltage reverence
Self-calibration mode High-Speed Analog Comparator (CMP)
6-bit DAC programmable reference generator output
Up to eight selectable comparator inputs; each input can be compared with any input by any polarity sequence
Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
Two performance modes:
Shorter propagation delay at the expense of higher power
Low-power, with longer propagation delay
Operational in all MCU power modes except VLLS0 mode Voltage Reference(VREF1)
Programmable trim register with 0.5 mV steps, automatically loaded with factory trimmed value upon reset
Programmable buffer mode selection:
Off
Bandgap enabled/standby (output buffer disabled)
High-power buffer mode (output buffer enabled)
1.2 V output at room temperature
VREF_OUT output signal Low-power Timer (LPTMR)
One channel
Operation as timer or pulse counter Feature Descriptions MKW39/38/37 Data Sheet, Rev. 7, 03/2020 13 NXP Semiconductors

Selectable clock for prescaler/glitch filter
1 kHz internal LPO
External low-power crystal oscillator
Internal reference clock
Configurable glitch filter or prescaler
Interrupt generated on timer compare
Hardware trigger generated on timer compare
Functional in all power modes Timer/PWM (TPM)
TPM0: 4 channels, TPM1 and TPM2: 2 channels each
Selectable source clock
Programmable prescaler
16-bit counter supporting free-running or initial/final value, and counting is up or up-down
Input capture, output compare, and edge-aligned and center-aligned PWM modes
Input capture and output compare modes
Generation of hardware triggers
TPM1 and TPM2: Quadrature decoder with input filters
Global time base mode shares single time base across multiple TPM instances Programmable Interrupt Timer (PIT)
Up to 2 interrupt timers for triggering ADC conversions
32-bit counter resolution
Clocked by bus clock frequency Real-Time Clock (RTC)
32-bit seconds counter with 32-bit alarm
Can be invalidated on detection of tamper detect
16-bit prescaler with compensation
Register write protection
Hard Lock requires MCU POR to enable write access
Soft lock requires POR or software reset to enable write/read access
Capable of waking up the system from low-power modes Inter-Integrated Circuit (I2C)
Two channels
Compatible with I2C bus standard and SMBus Specification Version 2 features
Up to 400 kHz operation Feature Descriptions 14 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Multi-master operation
Software programmable for one of 64 different serial clock frequencies
Programmable slave address and glitch input filter
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Bus busy detection broadcast and 10-bit address extension
Address matching causes wake-up when processor is in low-power mode LPUART
One channel (2 channels on KW38)
Full-duplex operation
Standard mark/space Non-return-to-zero (NRZ) format
13-bit baud rate selection with fractional divide of 32
Programmable 8-bit or 9-bit data format
Programmable 1 or 2 stop bits
Separately enabled transmitter and receiver
Programmable transmitter output polarity
Programmable receive input polarity
13-bit break character option
11-bit break character detection option
Two receiver wake-up methods:
Idle line wake-up
Address mark wake-up
Address match feature in receiver to reduce address mark wake-up ISR overhead
Interrupt or DMA driven operation
Receiver framing error detection
Hardware parity generation and checking
Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection
Operation in low-power modes
Hardware Flow Control RTS\\CTS
Functional in Stop/VLPS modes
Break detect supporting LIN Serial Peripheral Interface (SPI)
Two independent SPI channels
Master and slave mode
Full-duplex, three-wire synchronous transfers
Programmable transmit bit rate Feature Descriptions MKW39/38/37 Data Sheet, Rev. 7, 03/2020 15 NXP Semiconductors

Double-buffered transmit and receive data registers
Serial clock phase and polarity options
Slave select output
Control of SPI operation during wait mode
Selectable MSB-first or LSB-first shifting
Support for both transmit and receive by DMA Carrier Modulator Timer (CMT)
Four modes of operation
Time; with independent control of high and low times
Baseband
Frequency shift key (FSK)
Direct software control of CMT_IRO signal
Extended space operation in time, baseband, and FSK modes
Selectable input clock divider
Interrupt on end of cycle
Ability to disable CMT_IRO signal and use as timer interrupt General Purpose Input/Output (GPIO)
Hysteresis and configurable pull up device on all input pins
Independent pin value register to read logic level on digital pin
All GPIO pins can generate IRQ and wake-up events
Configurable drive strength on some output pins
GPIO can be configured to function as a interrupt driven keyboard scanning matrix; in the 48-pin package there are a total of 25 digital pins FlexCAN (for KW38 only)
Full implementation of the CAN with Flexible Data Rate (CAN FD) protocol specification and CAN protocol specification, Version 2.0 B
Flexible Message Buffers (MBs); there are total 32 MBs of 8 bytes data length each, configurable as Rx or Tx, all supporting standard and extended messages
Programmable clock source to the CAN Protocol Interface, either peripheral clock or oscillator clock
Capability to select priority between mailboxes and Rx FIFO during matching process Feature Descriptions 16 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either 128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual masking capability
Each individual MB forms by 16, 24, 40, or 72 bytes, depending on the quantity of data bytes allocated for the message payload: 8, 16, 32, or 64 data bytes, respectively

2.6 Security Features

Advanced Encryption Standard Accelerator(AES-128 Accelerator) The Advanced Encryption Standard Accelerator (AESA) module is a standalone hardware coprocessor capable of accelerating the 128-bit advanced encryption standard (AES) cryptographic algorithms. The AESA engine supports the following cryptographic features. LTC includes the following features:

Cryptographic authentication
Message Authentication Codes (MAC)
Cipher-based MAC (AES-CMAC)
Extended cipher block chaining message authentication code (AES- XCBC-MAC)
Auto padding
Integrity Check Value(ICV) checking
Authenticated encryption algorithms
Counter with CBC-MAC (AES-CCM)
Symmetric key block ciphers
AES (128-bit keys)
Cipher modes:
AES-128 modes
Electronic Codebook (ECB)
Cipher Block Chaining (CBC)
Counter (CTR)
Secure scan True Random Number Generator (TRNG) True Random Number Generator (TRNG) is a hardware accelerator module that constitutes a high-quality entropy source. Feature Descriptions MKW39/38/37 Data Sheet, Rev. 7, 03/2020 17 NXP Semiconductors

TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-consuming module, such as a deterministic random number generator.
TRNG output can be read and used by a deterministic pseudo-random number generator (PRNG) implemented in software.
TRNG-PRNG combination achieves NIST-compliant true randomness and cryptographic-strength random numbers using the TRNG output as the entropy source.
A fully FIPS 180 compliant solution can be realized using the TRNG together with a FIPS-compliant deterministic random number generator and the SoC-level security. Flash Memory Protection The on-chip flash memory controller enables the following useful features:
Program flash protection scheme prevents accidental program or erase of stored data.
Automated, built-in, program and erase algorithms with verify.
Read access to one program flash block is possible while programming or erasing data in the other program flash block.

3 Transceiver Description

Direct Conversion Receiver (Zero IF)
Constant Envelope Transmitter
Low Transmit and Receive Current Consumption
Low bill of material (BOM) radio

3.1 Transceiver Functions

The receiver architecture is Zero IF (ZIF) where the received signal after passing through RF front end is down-converted to a baseband signal. The signal is filtered and amplified before it is fed to analog-to-digital converter. The digital signal then decimates to a baseband clock frequency before it digitally processes, demodulates and passes on to packet processing/link-layer processing. Transmit Transceiver Description 18 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

The transmitter transmits GFSK/FSK modulation having power and channel selection adjustment per user application. After the channel of operation is determined, coarse and fine-tuning is executed within the Frac-N PLL to engage signal lock. After signal lock is established, the modulated buffered signal is routed to a multi-stage amplifier for transmission..

3.2 Key Specifications

KW39/38/37 meets or exceeds all Bluetooth Low Energy version 5.0 performance specifications. The key specifications for the KW39/38/37 are: Frequency Band:

ISM Band: 2400 to 2483.5 MHz
MBAN Band: 2360 to 2400 MHz Full Bluetooth Low Energy version 5.0 modulation scheme:
Symbol rate: Uncoded PHY (1, 2 Mbit/s), Coded PHY (125, 500 kbit/s)
Modulation: GFSK BT=0.5, h=0.5
Receiver sensitivity: –98 dBm, typical for Bluetooth LE 1 Mbit/s, –105 dBm for Bluetooth LE-LR 125 kbit/s; for all other modes, refer Receiver Feature Summary.
Programmable transmitter output power: –30 dBm to +5 dBm Generic FSK modulation scheme:
Symbol rate: 250, 500, 1000, and 2000 kbit/s MSK
Receiver Sensitivity: Mode and data rate dependent. –101 dBm typical for GFSK (r=250 kbit/s, BT = 0.5, h = 0.5)

3.3 Channel Map Frequency Plans

MKW39/38/37 Data Sheet, Rev. 7, 03/2020 19 NXP Semiconductors

3.3.1 Channel Plan for Bluetooth Low Energy

MBAN bands for Bluetooth Low Energy.

2.4 GHz ISM Channel numbering:

where k is the channel number. Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations Table continues on the next page...

Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)

ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
Per FCC guideline rules, Bluetooth Low Energy single mode operation is allowed in these channels.

3.3.2 Other Channel Plans

4 Transceiver Electrical Characteristics

4.1 Radio operating conditions

Table 3. Radio operating conditions Table continues on the next page...

Table 3. Radio operating conditions (continued)

The recommended crystal accuracy is ±40 ppm including initial accuracy, mechanical, temperature, and aging factors.

4.2 Receiver Feature Summary

Table 4. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise Table continues on the next page...

offset (Wanted signal at –67 dBm, BER <0.1%. Table continues on the next page...

offset (Wanted signal at –67 dBm, BER <0.1%. offset (Wanted signal at –67 dBm, BER <0.1%. offset (Wanted signal at –67 dBm, BER <0.1%. offset (Wanted signal at –67 dBm, BER <0.1%. offset (Wanted signal at –67 dBm, BER <0.1%. Table continues on the next page...

offset (Wanted signal at –67 dBm, BER <0.1%.

All the Rx parameters are measured at the KW39/38/37 RF pins.
Transceiver power consumption.
With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.
With one point calibration over frequency and temperature.
Exceptions allowed for twice the reference clock frequency(fref) multiples.
Measured at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.
Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.
Exceptions allowed for carrier frequency sub harmonics.
Exceptions allowed for carrier frequency harmonics.

Table 5. Receiver Specifications with Generic FSK Modulations

Selectivity measured with an unmodulated blocker.

4.3 Transmit and PLL Feature Summary

Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN frequency bands
Fast PLL Lock time: < 25 µs
Reference Frequency:
26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK modes

Table 6. Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise Table continues on the next page...

All the Tx parameters are measured at test hardware SMA connector.
Transceiver power consumption.

Measured at KW39/38/37 RF pins, with Vdd_RFx over 1.44 V and assuming an average Tx duty cycle <=24%. For Tx

output over +3.5 dBm, powered Vdd_RFx has to be higher than 1.44 V.

Measured at the KW39/38/37 RF pins.
Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.
Harmonic levels based on recommended 2 component match. Transmit harmonic levels depend on the quality of

matching components. Additional harmonic margin using a third matching component (1x shunt capacitor) is possible.

Measured at Pout = +5 dBm and recommended Tx match.

Figure 4. TX Pout (dBm) as function TX-PA Power Code at RF pins Table 7. Transmit Output Power as a function of PA_POWER[5:0] Table continues on the next page...

Table 7. Transmit Output Power as a function of PA_POWER[5:0] (continued)

Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.

Figure 5. TX Pout (dBm) as function TX-PA Power Code at RF pins (LDO-HF bumped) Table 8. Transmit Output Power as a function of PA_POWER[5:0] at elevated PA supply Table continues on the next page...

Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.

5 System and Power Management

5.1 Power Management

5.1.1 DC-DC Converter

The features of the DC-DC converter include the following:

Single inductor, multiple outputs.
Buck mode (pin selectable; CFG=VDCDC_IN).
Continuous or pulsed operation (hardware/software configurable).
Power switch input to allow external control of power up, and to select DC-DC bypass mode in which all the SoC power supplies (see Table 4) are externally provided.
Output signal to indicate power stable. Purpose is for the rest of the chip to be used as a POR.
Scaled battery output voltage suitable for SAR ADC utilization.
Internal oscillator for support when the reference oscillator is not present.

5.2 Modes of Operation

The Arm Cortex-M0+ core in the KW39/38/37 has three primary modes of operation: Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop mode. Wait modes are similar to Arm sleep modes. Stop modes are similar to Arm deep sleep modes. The very low-power run (VLPR) operation mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. The WFI instruction invokes both wait and stop modes. The primary modes are augmented in a number of ways to provide lower power based on application needs.

5.2.1 Power modes

The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, various stop modes are available that provide state retention, partial power down, or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The following table compares the various power modes available. System and Power Management 32 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

lower power based on application needs. Table 9. Power modes (At 25 deg C) to go to sleep reducing power. PMC also remain in Run or VLPRun mode. PMC also remain in Run or VLPRun mode. module off, execution from flash). in the way of radio operation. Places MCU in static state with LVD operation off. functional. LPTMR, RTC, CMP can be operational. Table continues on the next page...

Table 9. Power modes (At 25 deg C) (continued) Gates(SOG) logic is in state retention. radio SOG logic is in state retention. and Radio Tx/Rx RAM keeps state retention. SRAM can be configurable power gated. file remains powered for customer-critical data. LLWU, LPTMR, RTC, CMP can be operational. file remains powered for customer-critical data. LLWU, LPTMR, RTC, CMP can be operational. VLLS0 is not supported with DC-DC.

Biasing is disabled, but the Flash is in a low-power mode for VLPx, so this configuration can realize some power savings
DSM refers to Radio's deep sleep mode. DSM does not refer to the Arm sleep deep mode.

6 KW39/38/37 Electrical Characteristics

6.1 AC electrical characteristics

Figure 6. Input signal measurement reference output pins have the following characteristics.

C L=30 pF loads
Slew rate disabled
Normal drive strength

6.2 Nonswitching electrical specifications

6.2.1 Voltage and current operating requirements

Table 10. Voltage and current operating requirements Table continues on the next page...

Table 10. Voltage and current operating requirements (continued)

2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
V IN < VSS–0.3V –3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
Negative current injection –25 — mA VODPU Open drain pullup voltage level VDD VDD V 3 VRAM VDD voltage required to retain RAM 1.2 — V 1. This limit applies in any DCDC mode. 2. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS–0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 3. Open drain outputs must be pulled to VDD.

6.2.2 LVD and POR operating requirements

Table 11. V DD supply LVD and POR operating requirements

Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V Table continues on the next page... KW39/38/37 Electrical Characteristics 36 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Table 11. V DD supply LVD and POR operating requirements (continued)

Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low-power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

6.2.3 Voltage and current operating behaviors

Table 12. Voltage and current operating behaviors

2.7 V ≤ V DD ≤ 3.6 V, IOH = -5 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -2.5 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -1 mA VDD – 0.5 VDD – 0.5 VDD – 0.35 V V V 1, 2 VOH Output high voltage — High drive pad (except RESET_b)
2.7 V ≤ V DD ≤ 3.6 V, IOH = -20 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 VDD – 0.5 V V 1, 2 IOHT Output high current total for all ports — 100 mA VOL Output low voltage — Normal drive pad
2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 2.5 mA 0.5 0.5 V V VOL Output low voltage — High drive pad 0.5 V Table continues on the next page... KW39/38/37 Electrical Characteristics MKW39/38/37 Data Sheet, Rev. 7, 03/2020 37 NXP Semiconductors

Table 12. Voltage and current operating behaviors (continued)

2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 10 mA — 0.5 V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 500 nA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 5 μA 3 RPU Internal pullup resistors 20 50 kΩ 4 1. PTB0-1, PTC1-4, PTC6-7, PTC16-19 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull-up device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V. 4. Measured at VDD supply voltage = VDD min and Vinput = VSS.

6.2.4 Power mode transition operating behaviors

CPU and system clocks = 48 MHz
Bus and flash clock = 24 MHz
FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 13. Power mode transition operating behaviors operating temperature range of the chip.

VLLS0 → RUN 169.0 μs
VLLS1 → RUN 168.9 μs
VLLS2 → RUN 97.3 μs Table continues on the next page... KW39/38/37 Electrical Characteristics 38 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Table 13. Power mode transition operating behaviors (continued)

VLLS3 → RUN 97.3 μs
LLS → RUN 6.3 μs
VLPS → RUN 6.2 μs
STOP → RUN 6.2 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300 case where VDD_1P5 = VDD_1P8, TPOR did not meet the 300 µs maximum spec when the supply slew rate <=100 V/s.

6.2.5 Power consumption operating behaviors

Table 14. Power consumption operating behaviors - Bypass Mode

0 IDDA Analog supply current — See note mA 1

1 IDD_RUNCO_CM Run mode current in compute operation - 48

2 IDD_RUNCO Run mode current in compute operation - 48

3 IDD_RUN_CM Run mode current - 48 MHz core/24 MHz bus

4 IDD_RUN Run mode current - 48 MHz core / 24 MHz bus

5 IDD_RUN Run mode current - 48 MHz core / 24 MHz bus

Table continues on the next page...

Table 14. Power consumption operating behaviors - Bypass Mode (continued)

6 IDD_WAIT Wait mode current - core disabled / 48 MHz

7 IDD_WAIT Wait mode current - core disabled / 24 MHz

8 IDD_PSTOP2 Stop mode current with partial stop 2 clocking

9 IDD_VLPRCO_CM Very-low-power run mode current in compute

10 IDD_VLPRCO Very-low-power run mode current in compute

11 IDD_VLPR_CM Very-low-power run mode current -4 MHz

12 IDD_VLPR Very-low-power run mode current - 4 MHz

13 IDD_VLPR Very-low-power run mode current - 4 MHz

14 IDD_VLPW Very-low-power wait mode current - core

16 IDD_VLPS Very-low-power stop mode current at Bypass

Table continues on the next page...

17 IDD_LLS3 Low-leakage stop mode 3 current at Bypass

18 IDD_LLS2 Low-leakage stop mode 2 current at Bypass

19 IDD_VLLS3 Very-low-leakage stop mode 3 current at

20 IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at

21 IDD_VLLS2_32KB Very-low-leakage stop mode 2 current at

22 IDD_VLLS2_16KB

23 IDD_VLLS2_16KB

Table continues on the next page...

24 IDD_VLLS1 Very-low-leakage stop mode 1 current at

25 IDD_VLLS0 Very-low-leakage stop mode 0 current

26 IDD_VLLS0 Very-low-leakage stop mode 0 current

The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

specifications of each module for its supply current.

MCG configured for FEI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized for
MCG configured for FEI mode.
Incremental current consumption from peripheral activity is not included.
MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized
MCG configured for BLPI mode.

Table 15. Power consumption operating behaviors - Buck Mode Table continues on the next page...

Table 15. Power consumption operating behaviors - Buck Mode (continued)

9 IDD_VLPRCO_C

11 IDD_VLPR_CM Very-low-power run mode current - 4 MHz

12 IDD_VLPR Very-low-power run mode current - 4 MHz core /

0.8 MHz bus and flash, all peripheral clocks

13 IDD_VLPR Very-low-power run mode current - 4 MHz core /

Table continues on the next page...

16 IDD_VLPS Very-low-power stop mode current at Buck

17 IDD_LLS3 Low-leakage stop mode 3 current at Buck

18 IDD_LLS2 Low-leakage stop mode 2 current at Buck

19 IDD_VLLS3 Very-low-leakage stop mode 3 current at Buck

20 IDD_VLLS2_16KB Very-low-leakage stop mode 2 current at Buck

21 IDD_VLLS2_32KB Very-low-leakage stop mode 2 current at Buck

Table continues on the next page...

24 IDD_VLLS1 Very-low-leakage stop mode 1 current at Buck

The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See specification of each module for its supply current.

MCG configured for FEI mode.
Incremental current consumption from peripheral activity is not included.
MCG configured for BLPI mode.

Table 16. Low power mode peripheral adders — typical value (Bypass Mode)

1 IIREFSTEN4MHz 4 MHz internal reference clock (IRC)

VLPS mode with 4 MHz IRC enabled.

2 IIREFSTEN32KHz 32 kHz internal reference clock (IRC)

mode with the 32 kHz IRC enabled.

3 IEREFSTEN32KHz External 32 kHz crystal clock adder by

4 ICMP CMP peripheral adder measured by

a single external input for compare. Table continues on the next page...

Table 16. Low power mode peripheral adders — typical value (Bypass Mode) (continued)

5 IRTC RTC peripheral adder measured by

the RTC ALARM set for 1 minute.

6 ILPUART LPUART peripheral adder measured

7 ILPTMR LPTMR peripheral adder measured by

8 ITPM TPM peripheral adder measured by

9 IBG Bandgap adder when BGEN bit is set

10 IADC ADC peripheral adder combining the

6.2.6 Diagram: Typical IDD_RUN operating behavior

No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA NOTE The results in the following graphs are obtained using the device in Bypass mode.

Figure 7. Run mode supply current vs. core frequency

Figure 8. VLPR mode current vs. core frequency

6.2.7 SoC Power Consumption

Table 17. SoC Power Consumption Table continues on the next page...

Table 17. SoC Power Consumption (continued)

MCU configured to use an FLL-based 20 MHz clock.

6.2.8 Designing with radiated emissions in mind

Perform a keyword search for “KW38, HW guideline, RF system evaluation.”

6.2.9 Capacitance attributes

Table 18. Capacitance attributes

6.3 Switching electrical specifications

6.3.1 Device clock specifications

Table 19. Device clock specifications

The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

6.3.2 General switching specifications

LPUART, CAN (for KW38 only), CMT and I2C signals. Table 20. General switching specifications

Slew enabled — ns ns 4, 5 Table continues on the next page... KW39/38/37 Electrical Characteristics 50 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Table 20. General switching specifications (continued)

1.71 ≤ VDD ≤ 2.7 V
Slew disabled
1.71 ≤ VDD ≤ 2.7 V ns ns Port rise and fall time(low drive strength)
Slew enabled
1.71 ≤ VDD ≤ 2.7 V
Slew disabled
1.71 ≤ VDD ≤ 2.7 V ns ns ns ns 6, 7 1. This is the minimum pulse width that guarantees to pass through the pin synchronization circuitry in run modes. 2. The greater of synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that guarantees to be recognized. 4. PTB0, PTB1, PTC1, PTC2, PTC3, PTC4, PTC6, PTC7, PTC16, PTC17, PTC18, PTC19. 5. 75 pF load. 6. Ports A, B, and C. 7. 25 pF load.

6.4 Thermal specifications

6.4.1 Thermal operating requirements

Table 21. Thermal operating requirements

Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

determine TJ is: TJ = TA + RθJA × chip power dissipation.

6.4.2 Thermal attributes

Table 22. Thermal attributes

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
Determined according to JEDEC Standard JESD51-2A.
Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2A. where TT is the thermocouple temperature at the top of the package.

6.5 Peripheral operating requirements and behaviors

6.5.1 Core modules

6.5.1.1 SWD electricals

Table 23. SWD full voltage range electricals

Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns Table continues on the next page... KW39/38/37 Electrical Characteristics 52 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Table 23. SWD full voltage range electricals (continued) Figure 9. Serial wire clock input timing Figure 10. Serial wire data timing

6.5.2 System modules

There are no specifications necessary for the device's system modules.

6.5.3 Clock modules

6.5.3.1 MCG specifications

Table 24. MCG specifications

f VCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 KW39/38/37 Electrical Characteristics 54 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the following changes: FLL reference source or reference divider, trim value, DMX32 bit, DRS bits, or FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is used as the reference, this specification assumes it is already running.

6.5.3.2 Reference Oscillator Specification

The KW39/38/37 has been designed to meet targeted standard specifications for frequency error over the life of the part, which includes the temperature, mechanical and aging effects. The table below lists the recommended crystal specifications. Note that these are recommendations only and deviation may be allowed. However, deviations may result in degraded RF performance or possibly a failure to meet RF protocol certification standards. Designers must ensure that the crystal(s) they use meet the requirements of their application. Table 25. Recommended Crystal and Oscillator Specification

applications

–50 — 50 –50 — 50 ppm 6 CL Load capacitance 7 10 13 7 10 13 pF 2, 7 Cm1 Motional capacitance Lm1 Motional inductance Table continues on the next page... KW39/38/37 Electrical Characteristics MKW39/38/37 Data Sheet, Rev. 7, 03/2020 55 NXP Semiconductors

Table 25. Recommended Crystal and Oscillator Specification (continued)

Full temperature range of this device. A reduced range can be chosen to meet application needs.
Recommended crystal specification.
Combination of frequency stability variation over desired temperature range and frequency variation due to aging over
Variation due to temperature, process, and aging of MCU.
Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB

manufacturing variation must not exceed this value.

Typical is target. 30% tolerances shown.
Time from oscillator enable to clock ready. Dependent on the complete hardware configuration of the oscillator.

Figure 11. Crystal Electrical Model

Table 26. 32 kHz Crystal and Oscillator Specifications

Full temperature range of this device. A reduced range can be chosen to meet application needs.
Recommended crystal specification.
Sum of crystal initial frequency tolerance, crystal frequency stability, and aging tolerances given by crystal vendor.
Time from oscillator enable to clock stable. Dependent on the complete hardware configuration of the oscillator.
External oscillator connected to EXTAL32K. XTAL32K must be unconnected.
The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the

applied clock must be within the range of VSS to VDD.

6.5.4 Memories and memory interfaces

6.5.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

6.5.4.1.1 Flash timing specifications — commands

Table 27. Flash command timing specifications

256 KB program/data flash ms trd1sec2k Read 1s Section execution time (2 KB flash) — — 75 μs tpgmchk Program Check execution time — — 95 μs Table continues on the next page... KW39/38/37 Electrical Characteristics MKW39/38/37 Data Sheet, Rev. 7, 03/2020 57 NXP Semiconductors

Table 27. Flash command timing specifications (continued)

256 KB program/data flash 125 2125 ms tersscr Erase Flash Sector execution time — 12 130 ms 2 tpgmsec2k Program Section execution time (2 KB flash) — 10 — ms trd1allx trd1alln Read 1s All Blocks execution time
FlexNVM devices
Program flash only devices 3.5 3.5 ms ms trdonce Read Once execution time — — 30 μs tpgmonce Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 262 4380 ms 2 tvfykey Verify Backdoor Access Key execution time — — 35 μs tersallu Erase All Blocks Unsecure execution time — 262 4380 ms 2 tswapx01 tswapx02 tswapx04 tswapx08 tswapx10 Swap Control execution time
control code 0x01
control code 0x02
control code 0x04
control code 0x08
control code 0x10 280 100 100 100 235 235 235 μs μs μs μs μs tpgmpart32k tpgmpart256k Program Partition for EEPROM execution time
32 KB EEPROM backup
256 KB EEPROM backup 252 262 ms ms tsetramff tsetram32k tsetram256k Set FlexRAM Function execution time:
Control Code 0xFF
32 KB EEPROM backup
256 KB EEPROM backup 115 0.8 4.5 1.2 6.1 μs ms ms teewr8b32k teewr8b256k Byte-write to FlexRAM execution time:
32 KB EEPROM backup
256 KB EEPROM backup 385 1015 1700 3800 μs μs teewr16b32k teewr16b256k 16-bit write to FlexRAM execution time:
32 KB EEPROM backup
256 KB EEPROM backup 385 1015 1700 3800 μs μs teewr32bers 32-bit write to erased FlexRAM location execution time — 360 2000 μs 3 Table continues on the next page... KW39/38/37 Electrical Characteristics 58 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

32 KB EEPROM backup
256 KB EEPROM backup 630 1890 2000 4100 μs μs 1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/ external clocks). 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. First time EERAM writes after a Reset or SETRAM command may incur additional overhead for EEE cleanup, resulting in up to 2x the times shown. NOTE Under certain circumstances maximum times for writes to FlexRAM may be exceeded. In this case the user or application may wait, or assert reset to the FTFE module to stop the operation.

6.5.4.1.2 Reliability specifications (Automotive)

Table 28. NVM reliability specifications

EEPROM backup to FlexRAM used ratio =
EEPROM backup to FlexRAM used ratio = 256 100 K 1.6 M writes writes 4, 5, 6 1. Data retention period per block begins upon initial user factory programming or after each subsequent erase. 2. Program and Erase are supported across product temperature specification. Cycling endurance is per flash sector. 3. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years. 4. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product temperature specification. Greater write endurance may be achieved with larger ratios of EEPROM backup to FlexRAM. 5. For usage of any EEE driver other than the FlexMemory feature, the endurance specification falls back to the Data Flash endurance value of 1 K. 6. FlexMemory calculator tool is available on the NXP web site for help in estimating the maximum write endurance achievable at specific EEPROM/FlexRAM ratios. The "In Spec" portions of the online calculator refer to the NVM reliability specifications section of the data sheet. This calculator only applies to the Kinetis FlexMemory feature. KW39/38/37 Electrical Characteristics MKW39/38/37 Data Sheet, Rev. 7, 03/2020 59 NXP Semiconductors

6.5.4.1.3 Reliability specifications (Industrial)

Table 29. NVM reliability specifications

EEPROM backup to FlexRAM ratio = 16
EEPROM backup to FlexRAM ratio = 128
EEPROM backup to FlexRAM ratio = 512
EEPROM backup to FlexRAM ratio = 2,048 140 K 1.26 M 5 M 20 M 400 K 3.2 M 12.8 M 50 M writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C. 3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ 125 °C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.

6.5.4.1.4 Write endurance to FlexRAM for EEPROM

size can be set to any of several non-zero values.

the entire lifetime of a given application.

6.5.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

6.5.6 Analog

6.5.6.1 ADC electrical specifications

Table 30. 16-bit ADC operating conditions

1.13 VDDA VDDA V 3

All other modes VSSA VSSA 31/32 × VREFH VREFH V CADIN Input capacitance
16-bit mode
8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 5 Table continues on the next page... KW39/38/37 Electrical Characteristics MKW39/38/37 Data Sheet, Rev. 7, 03/2020 61 NXP Semiconductors

Table 30. 16-bit ADC operating conditions (continued)

Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

time constant should be kept to < 1 ns.

To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Figure 12. ADC input impedance equivalency diagram

Table 31. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

ADLPC=1, ADHSC=0
ADLPC=1, ADHSC=1
ADLPC=0, ADHSC=0
ADLPC=0, ADHSC=1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
12-bit modes
<12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
12-bit mode; Buck Mode6
12-bit mode; Bypass Mode ±0.7 ±0.5 –1.1 to +1.9 –1.1 to +1.9 LSB4 5 INL Integral non- linearity
12-bit mode; Buck Mode6
12-bit mode; Bypass Mode ±1.0 ±0.6 –2.7 to +1.9 –2.7 to +1.9 LSB4 5 EFS Full-scale error • 12-bit modes
<12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode; Buck Mode6
Avg = 32
Avg = 4 16-bit single-ended mode; Buck Mode6
Avg = 32
Avg = 4 16-bit differential mode; Bypass Mode
Avg = 32
Avg = 4 16-bit single-ended mode; Bypass Mode 11.25 9.5 12.5 11.25 12.75 11.75 11.5 10.5 11.75 bits Table continues on the next page... KW39/38/37 Electrical Characteristics MKW39/38/37 Data Sheet, Rev. 7, 03/2020 63 NXP Semiconductors

Table 31. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

Avg = 32
Avg = 4 10 10.5 — SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode; Buck Mode6
Avg = 32 16-bit single-ended mode; Buck Mode6
Avg = 32 16-bit differential mode; Bypass Mode
Avg = 32 16-bit single-ended mode; Bypass Mode
Avg = 32 –90 –88 –89 –87 dB SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB SFDR Spurious free dynamic range distortion 16-bit differential mode; Buck Mode6
Avg = 32 16-bit single-ended mode; Buck Mode6
Avg = 32 16-bit differential mode; Bypass Mode
Avg = 32 16-bit single-ended mode; Bypass Mode
Avg = 32 dB EIL Input leakage error IIn × RAS mV IIn = leakage current (see Voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device C Table continues on the next page... KW39/38/37 Electrical Characteristics 64 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

All accuracy numbers assume that the ADC is calibrated with VREFH = VDDA.
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low-

1 MHz ADC conversion clock speed.

1 LSB = (VREFH - VREFL)/2N.
ADC conversion clock < 16 MHz, maximum hardware averaging (AVGE = %1, AVGS = %11).
VREFH = Output of Voltage Reference(VREF).
Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
ADC conversion clock < 3 MHz.

6.5.6.2 Voltage reference electrical specifications

Table 32. VREF full-range operating requirements

CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
The load capacitance should not exceed +/–25% of the nominal specified CL value over the operating temperature

Table 33. VREF full-range operating behaviors Table continues on the next page...

Table 33. VREF full-range operating behaviors (continued)

current = ± 1.0 mA — 200 — Tstup Buffer startup time — — 100 µs Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms Vvdrift Voltage drift (Vmax –Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 34. VREF limited-range operating requirements Table 35. VREF limited-range operating behaviors

6.5.6.3 CMP and 6-bit DAC electrical specifications

Table 36. Comparator and 6-bit DAC electrical specifications

CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V Table continues on the next page... KW39/38/37 Electrical Characteristics 66 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Table 36. Comparator and 6-bit DAC electrical specifications (continued)

Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

6.5.7 Timers

See General switching specifications.

6.5.8 Communication interfaces

6.5.8.1 CAN switching specifications

See General switching specifications.

6.5.8.2 DSPI switching specifications (limited voltage range)

formats used for communicating with slower peripheral devices. Table 37. Master mode DSPI timing (limited voltage range)

The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 15. DSPI classic SPI timing — master mode Table 38. Slave mode DSPI timing (limited voltage range) Table continues on the next page...

Table 38. Slave mode DSPI timing (limited voltage range) (continued) Figure 16. DSPI classic SPI timing — slave mode

6.5.8.3 DSPI switching specifications (full voltage range)

used for communicating with slower peripheral devices. Table 39. Master mode DSPI timing (full voltage range) Table continues on the next page...

Table 39. Master mode DSPI timing (full voltage range) (continued)

The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 17. DSPI classic SPI timing — master mode Table 40. Slave mode DSPI timing (full voltage range)

Figure 18. DSPI classic SPI timing — slave mode

6.5.8.4 Inter-Integrated Circuit Interface (I2C) timing

Table 41. I 2C timing Hold time (repeated) START condition.

The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
Input signal Slew = 10 ns and Output Load = 50 pF.
Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.

A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
Cb = total capacitance of the one bus line in pF.

Figure 19. Timing definition for fast and standard mode devices on the I2C bus

6.5.8.5 LPUART

See General switching specifications.

6.5.9 Human-machine interfaces (HMI)

6.5.9.1 GPIO

specification, see General switching specifications.

6.6 DC-DC Converter Operating Requirements

Table 42. DC-DC Converter operating conditions Table continues on the next page...

Table 42. DC-DC Converter operating conditions (continued)

In Buck mode, DC-DC converter needs 2.1 V minimum to start, the supply can drop to 1.8 V after DC-DC converter
In Buck mode, DC-DC converter generates 1.8 V at VDD_1P8OUT and 1.5 V at VDD_1P5OUT_PMCIN pins.

VDD_RF2. VDD_RF3 can be either supplied by 1.5 V or 1.8 V. Table 43. DC-DC Converter Specifications

1.8 V Output Voltage

1.8 V Output Current5, 6

1.5 V <= VDC_1P5

1.5 V Output Current5, 8 IDD_1P5_buck — — 45 mA

Table continues on the next page...

Table 43. DC-DC Converter Specifications (continued)

This is the steady state DC output power. Excessive transient current load from external device will cause 1p8V and

1P5 output voltage unregulated temporary.

This is the frequency that is observed at LN and LP pins.
The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.
In Buck mode, the maximum VDD_1P8 output is the minimum of either VDCDC_IN_BUCK minus 50 mV or 3.5 V. For
The output current specification in buck mode represents the maximum current the DC-DC converter can deliver. The

current for external device depends on the energy consumed by the internal peripherals in KW39/38/37.

When using DC-DC in low-power mode (pulsed mode), current load must be less than 1 mA.
User needs to program DCDC_VDD1P5CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case

minimum of 1.5 V is available as VDD_1P5_buck. VDD_1P5 must not be programmed higher than VDD_1P8.

1.5 V is intended to supply power to KW39/38/37. It is not designed to supply power to an external device.
Turn on time is measured from the application of power (to DCDC_IN) till the DCDC_REG0[DCDC_STS_DC_OK] bit

specification is not guaranteed until the bit sets.

6.7 Ratings

6.7.1 Thermal handling ratings

Table 44. Thermal handling ratings

Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.7.2 Moisture handling ratings

Table 45. Moisture handling ratings

Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.7.3 ESD handling ratings

Table 46. ESD handling ratings

Determined according to JEDEC Standard JS001, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Determined according to JEDEC Standard JS002, Field-Induced Charged-Device Model Test Method for Electrostatic-

Discharge-Withstand Thresholds of Microelectronic Components.

Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

6.7.4 Voltage and current operating ratings

Table 47. Voltage and current operating ratings

7 Pin Diagrams and Pin Assignments

7.1 KW39/37 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control and Interrupt module is used to select the functionality for each GPIO pin. ALT0 is reserved for analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high impedance after reset – their input and output buffers are disabled. "Wett able" HVQ FN Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

1 PTA0 SWD_DIO PTA0/

RF_ACTIVE SPI0_PCS1 TPM1_CH0 SWD_DIO

2 PTA1 SWD_CLK PTA1/

RF_ STATUS SPI1_PCS0 TPM1_CH1 SWD_CLK

3 PTA2 RESET_b PTA2 TPM0_CH3 RESET_b

4 PTA16 DISABLED PTA16/

LLWU_P4 SPI1_SOUT TPM0_CH0

5 PTA17 DISABLED PTA17/

LLWU_P5 SPI1_SIN TPM_ CLKIN1

6 PTA18 DISABLED PTA18/

LLWU_P6 SPI1_SCK TPM2_CH0

7 PTA19 ADC0_SE5ADC0_SE5PTA19/

LLWU_P7 SPI1_PCS0 TPM2_CH1

8 PSWITCHPSWITCHPSWITCH

9 DCDC_

VDCDC_IN DCDC_ CFG/ VDCDC_IN DCDC_ CFG/ VDCDC_IN

10 DCDC_LPDCDC_LPDCDC_LP

11 DCDC_GNDDCDC_GNDDCDC_GND

12 DCDC_LNDCDC_LNDCDC_LN

13 VDD_

VDD_ 1P8OUT VDD_ 1P8OUT

14 DCDC_LNDCDC_LNDCDC_LN

15 VDD_

1P5OUT_ PMCIN VDD_ 1P5OUT_ PMCIN VDD_ 1P5OUT_ PMCIN

16 PTB0 DISABLED PTB0/

LLWU_P8/ RF_ RFOSC_EN I2C0_SCLCMP0_OUTTPM0_CH1 CLKOUT Pin Diagrams and Pin Assignments MKW39/38/37 Data Sheet, Rev. 7, 03/2020 77 NXP Semiconductors

"Wett able" HVQ FN Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

17 PTB1 ADC0_SE1/

CMP0_IN5 ADC0_SE1/ CMP0_IN5 PTB1/ RF_ PRIORITY DTM_RX I2C0_SDALPTMR0_ ALT1 TPM0_CH2 CMT_IRO

18 PTB2 ADC0_SE3/

CMP0_IN3 ADC0_SE3/ CMP0_IN3 PTB2/ RF_NOT_ ALLOWED/ LLWU_P9 DTM_TX TPM0_CH0TPM1_CH0 TPM2_CH0

19 PTB3 ADC0_SE2/

CMP0_IN4 ADC0_SE2/ CMP0_IN4 PTB3/ ERCLK32K/ RF_ACTIVE TPM0_CH1CLKOUT TPM1_CH1 RTC_ CLKOUT TPM2_CH1

20 VDD_0 VDD_0 VDD_0

21 PTB16 EXTAL32KEXTAL32KPTB16 I2C1_SCL TPM2_CH0

22 PTB17 XTAL32KXTAL32KPTB17 I2C1_SDA TPM2_CH1

23 PTB18 NMI_b ADC0_SE4/

CMP0_IN2 PTB18 I2C1_SCLTPM_ CLKIN0 TPM0_CH0 NMI_b

24 ADC0_DP0ADC0_DP0/

CMP0_IN0 ADC0_DP0/ CMP0_IN0

25 ADC0_DM0ADC0_DM0/

CMP0_IN1 ADC0_DM0/ CMP0_IN1

26 VREFL/

27 VREFH/

VREF_OUT VREFH/ VREF_OUT VREFH/ VREF_OUT

28 VDDA VDDA VDDA

29 XTAL_OUTXTAL_OUTXTAL_OUT

30 EXTAL EXTAL EXTAL

31 XTAL XTAL XTAL

32 VDD_RF3VDD_RF3VDD_RF3

33 ANT ANT ANT

34 GANT GANT GANT

35 VDD_RF2VDD_RF2VDD_RF2

36 VDD_RF1VDD_RF1VDD_RF1

37 PTC1 DISABLED PTC1/

RF_EARLY_ WARNING ANT_B I2C0_SDALPUART0_ RTS_b TPM0_CH2 SPI1_SCK

38 PTC2 DISABLED PTC2/

LLWU_P10 TX_ SWITCH I2C1_SCLLPUART0_ RX CMT_IRO DTM_RX SPI1_SOUT

39 PTC3 DISABLED PTC3/

LLWU_P11 RX_ SWITCH I2C1_SDALPUART0_ TX TPM0_CH1 DTM_TX SPI1_SIN

40 PTC4 DISABLED PTC4/

LLWU_P12/ RF_ACTIVE ANT_A EXTRG_INLPUART0_ CTS_b TPM1_CH0 I2C0_SCLSPI1_PCS0 Pin Diagrams and Pin Assignments 78 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

"Wett able" HVQ FN Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

41 PTC5 DISABLED PTC5/

LLWU_P13/ RF_NOT_ ALLOWED/ RF_ PRIORITY LPTMR0_ ALT2 LPUART0_ RTS_b TPM1_CH1

42 PTC6 DISABLED PTC6/

LLWU_P14/ RF_ RFOSC_EN I2C1_SCLLPUART0_ RX TPM2_CH0

43 PTC7 DISABLED PTC7/

LLWU_P15 SPI0_PCS2I2C1_SDALPUART0_ TX TPM2_CH1

44 VDD_1 VDD_1 VDD_1

45 PTC16 DISABLED PTC16/

LLWU_P0/ RF_ STATUS SPI0_SCKI2C0_SDALPUART0_ RTS_b TPM0_CH3

46 PTC17 DISABLED PTC17/

LLWU_P1/ RF_EXT_ OSC_EN SPI0_SOUTI2C1_SCLLPUART0_ RX DTM_RX

47 PTC18 DISABLED PTC18/

LLWU_P2 SPI0_SINI2C1_SDALPUART0_ TX DTM_TX

48 PTC19 DISABLED PTC19/

LLWU_P3/ RF_EARLY_ WARNING SPI0_PCS0I2C0_SCLLPUART0_ CTS_b

49 Ground NA

7.2 KW38 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control and Interrupt module is used to select the functionality for each GPIO pin. ALT0 is reserved for analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high impedance after reset – their input and output buffers are disabled. Pin Diagrams and Pin Assignments MKW39/38/37 Data Sheet, Rev. 7, 03/2020 79 NXP Semiconductors

"Wett able" HVQ FN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 RF_ACTIVE SPI0_PCS1 TPM1_CH0 SWD_DIO RF_STATUS SPI1_PCS0 TPM1_CH1 SWD_CLK LLWU_P4 SPI1_SOUTLPUART1_ RTS_b TPM0_CH0 LLWU_P5 SPI1_SINLPUART1_ RX CAN0_TXTPM_ CLKIN1 LLWU_P6 SPI1_SCKLPUART1_ TX CAN0_RXTPM2_CH0 LLWU_P7 SPI1_PCS0LPUART1_ CTS_b TPM2_CH1

9 DCDC_CFG/

VDCDC_IN DCDC_CFG/ VDCDC_IN DCDC_CFG/ VDCDC_IN VDD_ 1P8OUT VDD_ 1P8OUT 1P5OUT_ PMCIN VDD_ 1P5OUT_ PMCIN VDD_ 1P5OUT_ PMCIN LLWU_P8/ RF_ RFOSC_EN I2C0_SCLCMP0_OUTTPM0_CH1 CLKOUT CAN0_TX CMP0_IN5 ADC0_SE1/ CMP0_IN5 PTB1/ RF_ PRIORITY DTM_RX I2C0_SDALPTMR0_ ALT1 TPM0_CH2 CMT_IROCAN0_RX CMP0_IN3 ADC0_SE3/ CMP0_IN3 PTB2/ RF_NOT_ ALLOWED/ LLWU_P9 DTM_TX TPM0_CH0TPM1_CH0 TPM2_CH0 CMP0_IN4 ADC0_SE2/ CMP0_IN4 PTB3/ ERCLK32K/ RF_ACTIVE LPUART1_ RTS_b TPM0_CH1CLKOUT TPM1_CH1 RTC_ CLKOUT TPM2_CH1

21 PTB16 EXTAL32KEXTAL32KPTB16 LPUART1_

I2C1_SCL TPM2_CH0

22 PTB17 XTAL32KXTAL32KPTB17 LPUART1_

I2C1_SDA TPM2_CH1 Pin Diagrams and Pin Assignments 80 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

"Wett able" HVQ FN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 CMP0_IN2 PTB18 LPUART1_ CTS_b I2C1_SCLTPM_ CLKIN0 TPM0_CH0 NMI_b CMP0_IN0 ADC0_DP0/ CMP0_IN0 CMP0_IN1 ADC0_DM0/ CMP0_IN1 VREF_OUT VREFH/ VREF_OUT VREFH/ VREF_OUT RF_EARLY_ WARNING ANT_B I2C0_SDALPUART0_ RTS_b TPM0_CH2 SPI1_SCK LLWU_P10 TX_SWITCHI2C1_SCLLPUART0_ RX CMT_IRO DTM_RX SPI1_SOUT LLWU_P11 RX_ SWITCH I2C1_SDALPUART0_ TX TPM0_CH1 DTM_TX SPI1_SINCAN0_TX LLWU_P12/ RF_ACTIVE ANT_A EXTRG_INLPUART0_ CTS_b TPM1_CH0 I2C0_SCLSPI1_PCS0CAN0_RX LLWU_P13/ RF_NOT_ ALLOWED/ RF_ PRIORITY LPTMR0_ ALT2 LPUART0_ RTS_b TPM1_CH1 LLWU_P14/ RF_ RFOSC_EN I2C1_SCLLPUART0_ RX TPM2_CH0 LLWU_P15 SPI0_PCS2I2C1_SDALPUART0_ TX TPM2_CH1 Pin Diagrams and Pin Assignments MKW39/38/37 Data Sheet, Rev. 7, 03/2020 81 NXP Semiconductors

"Wett able" HVQ FN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 LLWU_P0/ RF_STATUS SPI0_SCKI2C0_SDALPUART0_ RTS_b TPM0_CH3 LPUART1_ RTS_b LLWU_P1/ RF_EXT_ OSC_EN SPI0_SOUTI2C1_SCLLPUART0_ RX DTM_RX LPUART1_ RX LLWU_P2 SPI0_SINI2C1_SDALPUART0_ TX DTM_TX LPUART1_ TX LLWU_P3/ RF_EARLY_ WARNING SPI0_PCS0I2C0_SCLLPUART0_ CTS_b LPUART1_ CTS_b

7.3 KW39/38/37 Pinouts

KW39/38/37 device pinouts are shown in the figure below. Pin Diagrams and Pin Assignments 82 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Figure 20. 48-pin "Wettable" HVQFN pinout diagram

7.4 Module Signal Description Tables

7.4.1 Core Modules

This section contains tables describing the core module signal descriptions. Table 48. SWD Module Signal Descriptions

Pulled up internally by default
Pulled down internally by default

7.4.2 Radio Modules

This section contains tables describing the radio signals. Table 49. Radio Module Signal Descriptions and remains asserted for the duration of the event. needs access to the 2.4 GHz antenna. measurement before a Bluetooth LE event. NOTE: This is a GPIO, not a dedicated PIN. RX_SWITCH O RX_SWITCH Front End Module receive mode signal. TX_SWITCH O TX_SWITCH Front End Module transmit mode signal.

Table 50. Radio Module Miscellaneous Pin Descriptions

7.4.3 System Modules

This section contains tables describing the system signals. Table 51. System Module Signal Descriptions Table 52. LLWU Module Signal Descriptions

7.4.4 Clock Modules

This section contains tables for Clock signal descriptions. Table 53. Clock Module Signal Descriptions

7.4.5 Analog Modules

This section contains tables for Analog signal descriptions. Table 54. ADC0 Signal Descriptions Table 55. CMP0 Signal Descriptions

Table 56. VREF Signal Descriptions

7.4.6 Timer Modules

This section contains tables describing timer module signals. Table 57. TPM0 Module Signal Descriptions Table 58. TPM1 Module Signal Descriptions Table 59. TPM2 Module Signal Descriptions Table 60. LPTMR0 Module Signal Descriptions Table 61. RTC Module Signal Descriptions

7.4.7 Communication Interfaces

This section contains tables for the signal descriptions for the communication modules. Table 62. SPI0 Module Signal Descriptions Table 63. SPI1 Module Signal Descriptions Table 64. I2C0 Module Signal Descriptions Table 65. I2C1 Module Signal Descriptions Table 66. CAN0 Signal Descriptions (KW38 only)

Table 67. LPUART0 Module Signal Descriptions

This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or

Table 68. LPUART1 Module Signal Descriptions (KW38 only)

This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or

7.4.8 Human-Machine Interfaces(HMI)

This section contains tables describing the HMI signals. Table 69. GPIO Module Signal Descriptions

8 Package Information

Package Information

MKW39/38/37 Data Sheet, Rev. 7, 03/2020 89 NXP Semiconductors

8.1 Obtaining package dimensions

Package dimensions are available in package drawings. Table 70. Packaging Dimensions

9 Part identification

9.1 Description

values of these fields to determine the specific part you have received.

9.2 Format

9.3 Fields

Table 71. Part number fields descriptions

P = Prequalification KW## Kinetis Wireless family • KW39
KW38
KW37 Table continues on the next page... Part identification 90 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Table 71. Part number fields descriptions (continued)

Z = Industrial Qualification FFF Program flash memory size • 512 = 512 KB T Temperature range (°C) • V = –40 to 105
C = –40 to 85 CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • (Blank) = Tray
R = Tape and reel

9.4 Example

Table 72. Revision History Rev 7 03/2020 • Replaced VDD_XTAL with VDD_RF3.

Preceded Tx output power value, 5 dBM, with a plus "+" sign.
Added "256 KB P-Flash" to the fifth column name in the KW39/38/37 Part Numbers table.
Corrected Figure 3 to show Prg Acc RAM 8 KB in place of FlexRAM 8 KB. Also added "Prg Acc RAM" entry in Table 1.
Corrected accuracy percentage of on-chip 4 MHz oscillator to 11% in System Clocks.
Updated minimum and typical values in Table 4 - Top-Level Receiver Specifications.
Updated maximum and typical values in Table 6 - Top-Level Transmitter Specifications. Also updated footnote 3 as follows: "Measured at KW39/38/37 RF pins, with Vdd_RFx over 1.44 V and assuming an average Tx duty cycle <=24%. For Tx output over +3.5 dBm, powered Vdd_RFx has to be higher than 1.44 V.".
Added V DD_1P5 specification in Voltage and current operating requirements.
Added V POR_VDD_1P5 specification in LVD and POR operating requirements.
Updated maximum value of Frequency deviation of internal reference clock to ± 11 in MCG specifications.
In Power consumption operating behaviors :
Removed the following note: "The maximum values specified in the following tables represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma)."
Updated maximum values of Power consumption operating behaviors - Bypass and Buck Modes in Table 14 and Table 15. Table continues on the next page...

Revision History

MKW39/38/37 Data Sheet, Rev. 7, 03/2020 91 NXP Semiconductors

Table 72. Revision History (continued)

Added V DD_1P5 symbol to "Bypass Mode Supply Voltage (RF and Analog)" in DC- DC Converter operating conditions.
Updated minimum value to 1.5 V and removed typical value in "1.5 V Voltage Output" in Table 43. Also updated the corresponding footnote with the correct value of 1.5 V. Rev 6 01/2020 • Updated Low-power Mode (VLLS0) current value to 266.6 nA in front page features under "Low-power Consumption" section.
Updated through out typical value of Bluetooth LE Receiver Sensitivity (2 Mbit/s and 1 Mbit/s) to -95.5 dBm and -98 dBm respectively.
Updated typical values of Top-level receiver specifications in Table 4.
Updated typical and maximum values in Table 14 and Table 15.
Updated typical values of Tx (at 5 dBm) radio state at STOP and RUN MCU states in SoC Power Consumption.
Updated V CDM ratings in ESD handling ratings. Also updated the JEDEC standard to JS001 and JS002. Rev 5 12/2019 • Editorial fixes.
Specified typical value of Rx current as 6.3 mA in front page features of the Data sheet (under Low-power Consumption section). Also added 256 KB FlexNVM column in KW39/38/37 Part Numbers table.
Added Table 1.
Corrected accuracy percentage of RC oscillator and on-chip 4 MHz oscillator to 3% and 6% respectively in System Clocks.
Updated receiver sensitivity value to -101 dBm in Key Specifications.
In section 4.2 - Receiver Feature Summary:
Specified typical values of I Rxon with respect to DC-DC converter buck and bypass modes in Table 4.
Updated receiver specifications with generic FSK modulations in Table 5.
Updated V OH - Normal drive pad in Voltage and current operating behaviors to include output high voltage at -1 mA.
Added the following paragraph to Power consumption operating behaviors : "The maximum values specified in the following tables represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma)." Also updated units of IDD_VLLS1 typical values in Table 15.
Updated maximum values in Table 14 and Table 15. Also updated mode# 20 and 21, IDD_VLLS2 and IDD_VLLS2_16KB_16KB, to IDD_VLLS2_16KB and IDD_VLLS2_32KB.
Updated Run mode supply current/VLPR mode current vs. core frequency images in Diagram: Typical IDD_RUN operating behavior.
Updated Table 26 to include operating temperature (TA), load capacitance (CL), and ESR specifications.
Updated value of V DCDC_IN to 2.1 V for IDD_1P8_buck3 in 1.8V Output Current row in Table 43. Rev 4 08/2019 • Updated value of Typical Receiver Sensitivity to -101 dBm.
Corrected radio block in KW39 Detailed Block Diagram. Also M1 port (connected from AXBS to Data Stream) corrected to M3. FlexCAN section in Peripheral features.
Updated typical values in Receiver Feature Summary.
In Transmit and PLL Feature Summary :
Specified typical value of "Bluetooth LE 2 Mbit/s Adjacent Channel Transmit Power at 4 MHz and >=6 MHz offset".
Updated Figure 4. TX Pout (dBm) as function TX-PA Power Code at RF pins. Table continues on the next page...

92 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

Updated numbers of "Transmit Output Power as a function of PA_POWER[5:0]" in Table 7 and Table 8.
Added Figure 5. TX Pout (dBm) as function TX-PA Power Code at RF pins (LDO-HF bumped).
Updated numbers in Table 16.
Replaced "EMC design" with "KW38, HW guideline, RF system evaluation" in Designing with radiated emissions in mind.
Updated maximum value of Δfintf_ft to ±6 in MCG specifications.
Updated Table 43 with the following:
Added conditions, V DCDC_IN above 2.7 V and below 2.7 V, in the first row, "DC-DC Converter Output Power".
Updated conditions in the "1.8 V Output Current" row. Also added IDD_1P8_buck3 condition to the row and updated maximum values.
Updated "1.5 V Output Current" maximum value to 45 mA.
Updated footnote 5 as follows: " The output current specification in buck mode Rev 3 06/2019 • Removed "Input Voltage High/Low" rows from Radio operating conditions.
Removed the following footnote from Table 14 - "Supported through the connectivity software in its pre-defined Deep Sleep Modes". Also updated Typical values in Table 14 and Table 15.
Removed "Flash timing specifications – program and erase" and "Flash high voltage current behaviors" tables.
Updated 48-pin "Wettable" HVQFN pinout diagram - added ground pin 49 to the diagram. Rev 2 04/2019 • Updated typical value of Bluetooth LE Receiver sensitivity at 2 Mbit/s from -94 to -95 dBm.
Updated pin package drawing.
Updated Low-power Mode (VLLS0) Current value to 252 nA and typical value of Tx current to 5.7 mA.
Added "512 KB P-Flash" column to this table. Also modified column name to "8 KB FlexRAM EEPROM" from 8 KB EEPROM.
Replaced "Prg Acc RAM 8 KB" with "FlexRAM 8 KB" in KW37 Detailed Block Diagram.
Removed "Galois counter mode (AES-GCM)" and "DES modes" features of LTC from Security Features.
Updated typical values in Receiver Feature Summary. Also updated measurement resolution to 2 MHz from 1 MHz in "Bluetooth LE uncoded 2 Mbit/s (High Speed)" section.
Updated typical values in Table 5.
Updated typical values of I TX0dBm, ITX0dBmb, ITX3.5dBm, ITX3.5dBmb, ITX5dBm, and ITX5dBmb. Also updated minimum value of TXBWBLE2M to 2.2 MHz in Table 6.
Removed 48-pin LQFN package from Thermal attributes and specified values for HVQFN48. Also replaced JESD51-2 standard with JESD51-2A in footnotes.
In Table 14 and Table 15 :
Added "Mode#" column.
Added the following measurements—IDD_RUN_CM, IDD_VLPR_CM, IDD_VLLS2_16KB_16KB, IDD_VLLS2_16KB_RF_Tx_RAM, IDD_VLLS2_16KB_RF_Rx_RAM.
Updated typical values.
Added "Adder#" column to Table 16.
Updated minimum and maximum values of "1.5 V Output Voltage" in Table 43. Also specified the condition as "Consumed by Radio.".
Removed support of DIAG1-3 signals and updated "DEFAULT" column to correct "DISABLED" status of PTA19, PTB1/2/3 pin names in Signal Multiplexing and Pin Assignments tables. Table continues on the next page...

MKW39/38/37 Data Sheet, Rev. 7, 03/2020 93 NXP Semiconductors

Updated Typical Receiver Sensitivity value of BLE LR 500 kbit/s from -99 to -101 dBm.
Added 0.7 in the Generic FSK modulation index.
Updated topic Radio features.
Restructured section 3 Transceiver Description.
Updated Full Bluetooth Low Energy version 5.0 modulation and Generic FSK modulation values in Key Specifications.
Updated Table 4, Table 5, and Table 6. Added Table 8.
Added the following footnote in : "Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.". Rev 1 Draft 11/2018 • Removed the following part numbers: MKW38A512VHT4, MKW38Z512VHT4, and MKW37Z512VHT4.
Added the following part numbers: MKW38Z512VFT4 and MKW37Z512VFT4.
Removed 48-pin LQFN package.
Changed 48 "Wettable" QFN to 48 "Wettable" HVQFN throughout.
Applied new NXP Brand Guidelines for Bluetooth Low Energy. Removed references of BLE and replaced with Bluetooth LE.
Updated Features list on the front page:
Corrected Typical Receiver Sensitivity value of BLE LR 500 kbit/s from -100.5 to -99 dBm.
Corrected Typical Receiver Sensitivity (250 kbit/s GFSK-BT=0.5, h=0.5) from -100 to -103 dBm.
Added 8 KB program acceleration RAM on KW37 to MCU and Memories section.
Updated topic 2.2 Radio Features.
Updated topic 2.3 Microcontroller features in the "On-Chip Memory" section to include support of EEPROM emulation.
Updated values of VDD_1P8OUT=1.8 V and VDD_1P8OUT=3.0 V to 45 mA and 27 mA.
Updated maximum value of Programmable transmitter output power to 5 dBm.
Updated typical value of RF Output power control range to 35 dB in Table 5. Top level Transmitter Specifications.
Removed silicon revision (R) field from Table 71. Part number fields descriptions. Rev 0 09/2018 Initial Internal Release

94 MKW39/38/37 Data Sheet, Rev. 7, 03/2020 NXP Semiconductors

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Product Information

MKW38A512VFT4 specifications and overview.

Summary

An ultra low-power, highly integrated Bluetooth짰 Low Energy 5.0 wireless microcontroller Rev. 7, 03/2020

Description

An ultra low-power, highly integrated Bluetooth짰 Low Energy 5.0 wireless microcontroller Rev. 7, 03/2020

Source title MKW38A512VFT4 Datasheet(PDF) - NXP Semiconductors

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