MKW41Z512 NXP | Alldatasheet

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Technical content

A Bluetooth® Low Energy, IEEE® Standard 802.15.4, Generic FSK System on a Chip (SoC) Supports the following: MKW41Z512VHT4, MKW31Z512VHT4, MKW21Z512VHT4, MKW41Z256VHT4, MKW31Z256VHT4, MKW21Z256VHT4,MKW41Z512CAT4,MKW31Z512CAT4 Multi-Standard Radio

  • 2.4 GHz Bluetooth Low Energy ver. 4.2 compliant supporting up to 2 simultaneous hardware connections
  • IEEE Std. 802.15.4 compliant with dual-PAN support
  • Generic FSK modulation
  • Data Rate: 250, 500 and 1000 kbps
  • Modulations: GFSK BT = 0.3, 0.5, 0.7; FSK/MSK
  • Modulation Index: 0.32, 0.5, or 0.7
  • Typical Receiver Sensitivity (BLE) = -95 dBm
  • Typical Receiver Sensitivity (802.15.4) = -100 dBm
  • Typical Receiver Sensitivity (250 kbps GFSK-BT=0.5, h=0.5) = -100 dBm
  • Prog Transmitter Output Power: -30 dBm to 3.5 dBm
  • Low external component counts for low cost application
  • On-chip balun with single ended bidirectional RF port MCU and Memories
  • Up to 48 MHz ARM® Cortex-M0+ core
  • On-chip 512/256 KB Flash memory
  • On-chip 128/64 KB SRAM Low Power Consumption
  • Transceiver current (DC-DC buck mode, 3.6 V supply)
  • Typical Rx Current: 6.8 mA
  • Typical Tx current: 6.1 mA (0 dBm output)
  • Low Power Mode (VLLS0) Current: 182 nA System peripherals
  • Nine MCU low-power modes to provide power optimization based on application requirements
  • DC-DC Converter supporting Buck, Boost, and Bypass operating modes
  • Direct memory access(DMA) Controller
  • Computer operating properly(COP) watchdog
  • Serial wire debug(SWD) Interface and Micro Trace buffer
  • Bit Manipulation Engine (BME) Analog Modules
  • 16-bit Analog-to-Digital Converter (ADC)
  • 12-bit Digital-to-Analog Converter (DAC)
  • 6-bit High Speed Analog Comparator (CMP)
  • 1.2 V voltage reference (VREF) Timers
  • 16-bit low-power timer (LPTMR)
  • 3 Timers Modules(TPM): One 4 channel TPM and two 2 channel TPMs
  • Programmable Interrupt Timer (PIT)
  • Real-Time Clock (RTC) Communication interfaces
  • 2 serial peripheral interface (SPI) modules
  • 2 inter-integrated circuit (I2C) modules MKW41Z512 MKW31Z512 MKW21Z512 MKW41Z256 MKW31Z256 MKW21Z256

48 LQFN

7 x 7 x 0.98 mm Pitch 0.5 mm

75 WLCSP

3.893 x 3.797 x 0.564 mm Pitch 0.4 mm NXP Semiconductors MKW41Z512 Data Sheet: Technical Data Rev. 4, 03/2018 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

  • 26 and 32 MHz supported for BLE and FSK modes
  • 32 MHz supported for IEEE Standard 802.15.4
  • 32.768 kHz Crystal Oscillator Operating Characteristics
  • Voltage range: 0.9 V to 4.2 V
  • Temperature range:
  • –40 to 105 °C (Laminate-QFN)
  • –40 to 85 °C (WLCSP) Human-machine interface
  • Touch sensing input
  • General-purpose input/output
  • Low Power UART module
  • Carrier Modulator Timer (CMT) Security
  • AES-128 Hardware Accelerator (AESA)
  • True Random Number Generator (TRNG)
  • Advanced flash security
  • 80-bit unique identification number per chip
  • 40-bit unique media access control (MAC) sub- address
  • Bluetooth-LE v4.2 Secure Connections
  • IEEE Standard 802.15.4-2011 compliant security 2 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

7.2.6 Diagram: Typical IDD_RUN operating

MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 3 NXP Semiconductors

1 Introduction

The KW41Z/31Z/21Z (called KW41Z throughout this document) is an ultra low-power, highly integrated single-chip device that enables Bluetooth low energy (BLE), Generic FSK (at 250, 500 and 1000 kbps) or IEEE Standard 802.15.4 RF connectivity for portable, extremely low-power embedded systems. Applications include portable health care devices, wearable sports and fitness devices, AV remote controls, computer keyboards and mice, gaming controllers, access control, security systems, smart energy and home area networks. The KW41Z SoC integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz range supporting a range of FSK/GFSK and O-QPSK modulations, an ARM Cortex- M0+ CPU, up to 512 KB Flash and up to 128 KB SRAM, BLE Link Layer hardware, 802.15.4 packet processor hardware and peripherals optimized to meet the requirements of the target applications. The KW41Z SoC’s radio frequency transceiver is compliant with Bluetooth version 4.2 for Low Energy (aka Bluetooth Smart or BLE), Generic FSK and the IEEE Standard 802.15.4 using O-QPSK in the 2.4 GHz ISM band. NXP provides fully certified Bluetooth Low Energy and IEEE Standard 802.15.4 protocol stacks, including Zigbee 3.0, Thread, and application profiles to support KW41Z. The KW41Z SoC can be used in applications as a "BlackBox" modem by simply adding BLE or IEEE Standard 802.15.4 connectivity to an existing embedded controller system, or used as a stand-alone smart wireless sensor with embedded application where no host controller is required. KW41Z has 512/256 KB of on-chip Flash and 128/64 KB of on-chip SRAM memory available to be used by customer applications and chosen communication protocol stack using a choice of either NXP or 3rd party software development tools. The RF section of the KW41Z SoC is optimized to require very few external components, achieving the smallest RF footprint possible on a printed circuit board. Extremely long battery life is achieved though efficiency of code execution in the Cortex-M0+ CPU core and the multiple low power operating modes of the KW41Z SoC. Additionally, an integrated DC-DC converter enables a wide operating range from 0.9 V to 4.2 V. The DC-DC in Buck mode enables KW41Z to operate from a single coin cell battery with a significant reduction of peak Rx and Tx current consumption. The DC-DC in boost mode enables a single alkaline battery to be used throughout its entire useful voltage range of 0.9 V to 1.795 V. Introduction 4 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

2 Ordering Information

Table 1. Orderable parts details

128 KB SRAM

64 KB SRAM

3 Feature Descriptions

This section provides a simplified block diagram and highlights the KW41Z features.

Ordering Information

MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 5 NXP Semiconductors

3.1 Block Diagram

4 MHzDMA MUX

Figure 1. KW41Z Detailed Block Diagram

3.2 Radio features

  • 2.4 GHz ISM band (2400-2483.5 MHz)
  • MBAN 2360-2400 MHz Supported standards:
  • Bluetooth v4.2 Low Energy compliant 1 Mbps GFSK modulation supporting up to 2 simultaneous connections in hardware (master-slave, master-master, slave-slave)
  • IEEE Standard 802.15.4-2011 compliant O-QPSK modulation and security features
  • Zigbee 3.0
  • Thread Networking Stack
  • Bluetooth Low Energy(BLE) Application Profiles Receiver performance:
  • Receive sensitivity of -95 dBm for BLE
  • Receive sensitivity of -100 dBm typical for IEEE Standard 802.15.4
  • Receive sensitivity of up to -100 dBm for a 250 kbps GFSK mode with a modulation index of 0.5. Receive sensitivity in generic FSK modes depends on mode selection and data rate. Other features: Feature Descriptions 6 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors
  • Programmable transmit output power from -30 dBm to 3.5 dBm
  • Integrated on-chip balun
  • Single ended bidirectional RF port shared by transmit and receive
  • Low external component count
  • Supports transceiver range extension using external PA and/or LNA
  • 26 and 32 MHz supported for BLE and FSK modes
  • 32 MHz supported for IEEE Standard 802.15.4
  • Bluetooth Low Energy ver. 4.2 Link Layer hardware with 2 independent hardware connection engines
  • Hardware acceleration for IEEE Standard 802.15.4 packet processing/link layer
  • Hardware acceleration for Generic FSK packet processing
  • Supports dual PAN for IEEE Standard 802.15.4 with hardware-assisted address matching acceleration
  • Generic FSK modulation at 250, 500 and 1000 kbps
  • Supports antenna diversity option for IEEE Std. 802.15.4

3.3 Microcontroller features

  • Up to 48 MHz CPU
  • As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles per instruction)
  • Supports up to 32 interrupt request sources
  • Binary compatible instruction set architecture with the Cortex-M0 core
  • Thumb instruction set combines high code density with 32-bit performance
  • Serial Wire Debug (SWD) reduces the number of pins required for debugging
  • Micro Trace Buffer (MTB) provides lightweight program trace capabilities using system RAM as the destination memory Nested Vectored Interrupt Controller (NVIC)
  • 32 vectored interrupts, 4 programmable priority levels
  • Includes a single non-maskable interrupt Wake-up Interrupt Controller (WIC)
  • Supports interrupt handling when system clocking is disabled in low power modes Feature Descriptions MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 7 NXP Semiconductors
  • Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep
  • A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked interrupt is detected Debug Controller
  • Two-wire Serial Wire Debug (SWD) interface
  • Hardware breakpoint unit for 2 code addresses
  • Hardware watchpoint unit for 2 data items
  • Micro Trace Buffer for program tracing On-Chip Memory
  • 512/256 KB
  • Firmware distribution protection. Program flash can be marked execute-only on a per-sector (8 KB) basis to prevent firmware contents from being read by third parties
  • Flash implemented as two equal blocks each of 256 KB block. Code can execute or read from one block while the other block is being erased or programmed.
  • 128/64 KB SRAM
  • Security circuitry to prevent unauthorized access to RAM and flash contents through the debugger

3.4 System features

Power Management Control Unit (PMC)

  • Programmable power saving modes
  • Available wake-up from power saving modes via internal and external sources
  • Integrated Power-on Reset (POR)
  • Integrated Low Voltage Detect (LVD) with reset (brownout) capability
  • Selectable LVD trip points
  • Programmable Low Voltage Warning (LVW) interrupt capability
  • Individual peripheral clocks can be gated off to reduce current consumption
  • Internal Buffered bandgap reference voltage
  • Factory programmed trim for bandgap and LVD
  • 1 kHz Low Power Oscillator (LPO) DC-DC Converters Feature Descriptions 8 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors
  • Internal switched mode power supply supporting Buck, Boost, and Bypass operating modes
  • Buck operation supports external voltage sources of 2.1 V to 4.2 V. This reduces peak current consumption during Rx and Tx by ~25%, ideal for single coin-cell battery operation (typical CR2032 cell).
  • Boost operation supports external voltage sources of 0.9 V to 1.795 V, which is efficiently increased to the static internal core voltage level, ideal for single battery operation (typical AA or AAA alkaline cell).
  • When DC-DC is not used, the device supports an external voltage range of 1.5 V to 3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_XTAL and VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1 and VDDA pins)
  • An external inductor is required to support the Buck or Boost modes
  • The DC-DC Converter 1.8 V output current drive for external devices (MCU in RUN mode, Radio is enabled, other peripherals are disabled)
  • Up to 44 mA in buck mode with VDD_1P8 = 1.8 V
  • Up to 31.4 mA in buck mode with VDD_1P8 = 3.0 V Direct Memory Access (DMA) Controller
  • All data movement via dual-address transfers: read from source, write to destination
  • Programmable source and destination addresses and transfer size
  • Support for enhanced addressing modes
  • 4-channel implementation that performs complex data transfers with minimal intervention from a host processor
  • Internal data buffer, used as temporary storage to support 16- and 32-byte transfers
  • Connections to the crossbar switch for bus mastering the data movement
  • Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
  • 32-byte TCD stored in local memory for each channel
  • An inner data transfer loop defined by a minor byte transfer count
  • An outer data transfer loop defined by a major iteration count
  • Channel activation via one of three methods:
  • Explicit software initiation
  • Initiation via a channel-to-channel linking mechanism for continuous transfers
  • Peripheral-paced hardware requests, one per channel
  • Fixed-priority and round-robin channel arbitration
  • Channel completion reported via optional interrupt requests Feature Descriptions MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 9 NXP Semiconductors
  • One interrupt per channel, optionally asserted at completion of major iteration count
  • Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller
  • Optional support for scatter/gather DMA processing
  • Support for complex data structures DMA Channel Multiplexer (DMA MUX)
  • 4 independently selectable DMA channel routers
  • 2 periodic trigger sources available
  • Each channel router can be assigned to 1 of the peripheral DMA sources COP Watchdog Module
  • Independent clock source input (independent from CPU/bus clock)
  • Choice between two clock sources
  • LPO oscillator
  • Bus clock System Clocks
  • Both 26 MHz and 32 MHz crystal reference oscillator supported for BLE and FSK radio modes
  • 32 MHz crystal reference oscillator supported for IEEE 802.15.4 radio mode
  • MCU can derive its clock either from the crystal reference oscillator or the frequency locked loop (FLL)1
  • 32.768 kHz crystal reference oscillator used to maintain precise Bluetooth radio time in low power modes
  • Multipurpose Clock Generator (MCG)
  • Internal reference clocks — Can be used as a clock source for other on-chip peripherals
  • On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy across full temperature range
  • On-chip 4MHz oscillator with 5% accuracy across full temperature range
  • Frequency-locked loop (FLL) controlled by internal or external reference
  • 20 MHz to 48 MHz FLL output Unique Identifiers
  • 10 bytes(or 80-bits) of the Unique ID represents a unique identifier for each chip
  • 40 bits of unique media access control (MAC) address, which can be used to build a unique 48-bit Bluetooth-LE or 64-bit IEEE 802.15.4 device address 1. Clock options can have restrictions based on the chosen SoC configuration. Feature Descriptions 10 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

3.5 Peripheral features

16-bit Analog-to-Digital Converter (ADC)

  • Linear successive approximation algorithm with 16-bit resolution
  • Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode
  • Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode
  • Single or continuous conversion
  • Configurable sample time and conversion speed / power
  • Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
  • Input clock selection
  • Operation in low power modes for lower noise operation
  • Asynchronous clock source for lower noise operation
  • Selectable asynchronous hardware conversion trigger
  • Automatic compare with interrupt for less-than, or greater than, or equal to programmable value
  • Temperature sensor
  • Battery voltage measurement
  • Hardware average function
  • Selectable voltage reverence
  • Self-calibration mode 12-Bit Digital-to-Analog Converter (DAC)
  • 12-bit resolution
  • Guaranteed 6-sigma monotonicity over input word
  • High- and low-speed conversions
  • 1 μs conversion rate for high speed, 2 μs for low speed
  • Power-down mode
  • Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth
  • Automatic mode allows programmable period, update rate, and range
  • DMA support with configurable watermark level High-Speed Analog Comparator (CMP)
  • 6-bit DAC programmable reference generator output
  • Up to eight selectable comparator inputs; each input can be compared with any input by any polarity sequence
  • Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output Feature Descriptions MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 11 NXP Semiconductors
  • Two performance modes:
  • Shorter propagation delay at the expense of higher power
  • Low power, with longer propagation delay
  • Operational in all MCU power modes except VLLS0 mode Voltage Reference(VREF1)
  • Programmable trim register with 0.5 mV steps, automatically loaded with factory trimmed value upon reset
  • Programmable buffer mode selection:
  • Off
  • Bandgap enabled/standby (output buffer disabled)
  • High power buffer mode (output buffer enabled)
  • 1.2 V output at room temperature
  • VREF_OUT output signal Low Power Timer (LPTMR)
  • One channel
  • Operation as timer or pulse counter
  • Selectable clock for prescaler/glitch filter
  • 1 kHz internal LPO
  • External low power crystal oscillator
  • Internal reference clock
  • Configurable glitch filter or prescaler
  • Interrupt generated on timer compare
  • Hardware trigger generated on timer compare
  • Functional in all power modes Timer/PWM (TPM)
  • TPM0: 4 channels, TPM1 and TPM2: 2 channels each
  • Selectable source clock
  • Programmable prescaler
  • 16-bit counter supporting free-running or initial/final value, and counting is up or up-down
  • Input capture, output compare, and edge-aligned and center-aligned PWM modes
  • Input capture and output compare modes
  • Generation of hardware triggers
  • TPM1 and TPM2: Quadrature decoder with input filters
  • Global time base mode shares single time base across multiple TPM instances Programmable Interrupt Timer (PIT) Feature Descriptions 12 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors
  • Up to 2 interrupt timers for triggering ADC conversions
  • 32-bit counter resolution
  • Clocked by bus clock frequency Real-Time Clock (RTC)
  • 32-bit seconds counter with 32-bit alarm
  • Can be invalidated on detection of tamper detect
  • 16-bit prescaler with compensation
  • Register write protection
  • Hard Lock requires MCU POR to enable write access
  • Soft lock requires POR or software reset to enable write/read access
  • Capable of waking up the system from low power modes Inter-Integrated Circuit (I2C)
  • Two channels
  • Compatible with I2C bus standard and SMBus Specification Version 2 features
  • Up to 400 kHz operation
  • Multi-master operation
  • Software programmable for one of 64 different serial clock frequencies
  • Programmable slave address and glitch input filter
  • Interrupt driven byte-by-byte data transfer
  • Arbitration lost interrupt with automatic mode switching from master to slave
  • Calling address identification interrupt
  • Bus busy detection broadcast and 10-bit address extension
  • Address matching causes wake-up when processor is in low power mode LPUART
  • One channel
  • Full-duplex operation
  • Standard mark/space non-return-to-zero (NRZ) format
  • 13-bit baud rate selection with fractional divide of 32
  • Programmable 8-bit or 9-bit data format
  • Programmable 1 or 2 stop bits
  • Separately enabled transmitter and receiver
  • Programmable transmitter output polarity
  • Programmable receive input polarity
  • 13-bit break character option
  • 11-bit break character detection option
  • Two receiver wakeup methods: Feature Descriptions MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 13 NXP Semiconductors
  • Idle line wakeup
  • Address mark wakeup
  • Address match feature in receiver to reduce address mark wakeup ISR overhead
  • Interrupt or DMA driven operation
  • Receiver framing error detection
  • Hardware parity generation and checking
  • Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection
  • Operation in low power modes
  • Hardware Flow Control RTS\\CTS
  • Functional in Stop/VLPS modes Serial Peripheral Interface (DSPI)
  • Two independent SPI channels
  • Master and slave mode
  • Full-duplex, three-wire synchronous transfers
  • Programmable transmit bit rate
  • Double-buffered transmit and receive data registers
  • Serial clock phase and polarity options
  • Slave select output
  • Control of SPI operation during wait mode
  • Selectable MSB-first or LSB-first shifting
  • Support for both transmit and receive by DMA Carrier Modulator Timer (CMT)
  • Four modes of operation
  • Time; with independent control of high and low times
  • Baseband
  • Frequency shift key (FSK)
  • Direct software control of CMT_IRO signal
  • Extended space operation in time, baseband, and FSK modes
  • Selectable input clock divider
  • Interrupt on end of cycle
  • Ability to disable CMT_IRO signal and use as timer interrupt General Purpose Input/Output (GPIO)
  • Hysteresis and configurable pull up device on all input pins
  • Independent pin value register to read logic level on digital pin
  • All GPIO pins can generate IRQ and wakeup events
  • Configurable drive strength on some output pins Feature Descriptions 14 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

Touch Sensor Input (TSI)

  • Support up to 16 external electrodes
  • Automatic detection of electrode capacitance across all operational power modes
  • Internal reference oscillator for high-accuracy measurement
  • Configurable software or hardware scan trigger
  • Capability to wake MCU from low power modes
  • Compensate for temperature and supply voltage variations
  • High sensitivity change with 16-bit resolution register
  • Configurable up to 4096 scan times
  • Support DMA data transfer Keyboard Interface
  • GPIO can be configured to function as a interrupt driven keyboard scanning matrix
  • In the 48-pin package there are a total of 26 digital pins
  • These pins can be configured as needed by the application as GPIO, LPUART, SPI, I2C, ADC, timer I/O as well as other functions

3.6 Security Features

Advanced Encryption Standard Accelerator(AES-128 Accelerator) The advanced encryption standard accelerator (AESA) module is a standalone hardware coprocessor capable of accelerating the 128-bit advanced encryption standard (AES) cryptographic algorithms. The AESA engine supports the following cryptographic features. LTC includes the following features:

  • Cryptographic authentication
  • Message authentication codes (MAC)
  • Cipher-based MAC (AES-CMAC)
  • Extended cipher block chaining message authentication code (AES- XCBC-MAC)
  • Auto padding
  • Integrity Check Value(ICV) checking
  • Authenticated encryption algorithms
  • Counter with CBC-MAC (AES-CCM)
  • Galois counter mode (AES-GCM) Feature Descriptions MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 15 NXP Semiconductors
  • Symmetric key block ciphers
  • AES (128-bit keys)
  • Cipher modes:
  • AES-128 modes
  • Electronic codebook (ECB)
  • Cipher block chaining (CBC)
  • Counter (CTR)
  • DES modes
  • Electronic codebook (ECB)
  • Cipher block chaining (CBC)
  • Cipher feedback (CFB)
  • Output Feedback (OFB)
  • Secure scan True Random Number Generator (TRNG) True Random Number Generator (TRNG) is a hardware accelerator module that constitutes a high-quality entropy source.
  • TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-consuming module, such as a deterministic random number generator.
  • TRNG output can be read and used by a deterministic pseudo-random number generator (PRNG) implemented in software.
  • TRNG-PRNG combination achieves NIST compliant true randomness and cryptographic-strength random numbers using the TRNG output as the entropy source.
  • A fully FIPS 180 compliant solution can be realized using the TRNG together with a FIPS compliant deterministic random number generator and the SoC-level security. Flash Memory Protection The on-chip flash memory controller enables the following useful features:
  • Program flash protection scheme prevents accidental program or erase of stored data.
  • Program flash access control scheme prevents unauthorized access to selected code segments.
  • The flash can be protected from mass erase even when the MCU is not secured.
  • Automated, built-in, program and erase algorithms with verify.
  • Read access to one program flash block is possible while programming or erasing data in the other program flash block. Feature Descriptions 16 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

4 Transceiver Description

  • Direct Conversion Receiver
  • Constant Envelope Transmitter
  • 2.36 GHz to 2.483 GHz PLL Range
  • Low Transmit and Receive Current Consumption
  • Low BOM

4.1 Key Specifications

The KW41Z SoC meets or exceeds all Bluetooth Low Energy v4.2 and IEEE 802.15.4 performance specifications applicable to 2.4 GHz ISM and MBAN (Medical Band Area Network) bands. Key specification for the KW41 are: Frequency Band:

  • ISM Band: 2400 to 2483.5MHz
  • MBAN Band: 2360 to 2400MHz Bluetooth Low Energy v4.2 modulation scheme:
  • Symbol rate: 1000 kbps
  • Modulation: GFSK
  • Receiver sensitivity: -95 dBm, typical
  • Programmable transmitter output power: -30 dBm to 3.5 dBm IEEE Standard 802.15.4 2.4 GHz modulation scheme:
  • Chip rate: 2000 kbps
  • Data rate: 250 kbps
  • Symbol rate: 62.5 kbps
  • Modulation: OQPSK
  • Receiver sensitivity: -100 dBm, typical (@1% PER for 20 byte payload packet)
  • Single ended bidirectional RF input/output port with integrated transmit/receive switch
  • Programmable transmitter output power: -30 dBm to 3.5 dBm Generic FSK modulation scheme:
  • Symbol rate: 250, 500 and 1000 kbps Transceiver Description MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 17 NXP Semiconductors
  • Receiver Sensitivity: Mode and data rate dependant. -100 dBm typical for GFSK (r=250 kbps, BT = 0.5, h = 0.5)

4.2 Channel Map Frequency Plans

4.2.1 Channel Plan for Bluetooth Low Energy

MBAN bands for Bluetooth Low Energy.

2.4 GHz ISM Channel numbering:

where k is the channel number. Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations Table continues on the next page...

Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)

  1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
  2. Per FCC guideline rules, IEEE (R) 802.15.1 and Bluetooth Low Energy single mode operation is allowed in these

MBAN bands for IEEE 802.15.4. where k is the channel number. Table 3. 2.4 GHz ISM and MBAN frequency plan and channel designations

2.4 GHz ISM MBAN1

  1. Usable channel spacing to assit in co-existence.

4.2.3 Other Channel Plans

4.3 Transceiver Functions

and passed on to packet processing/link-layer processing.

5 Transceiver Electrical Characteristics

5.1 Radio operating conditions

Table 4. Radio operating conditions Table continues on the next page...

Table 4. Radio operating conditions (continued)

  1. VDDINT is the internal LDO regulated voltage supplying various circuit blocks, VDDINT=1.2 V

5.2 Receiver Feature Summary

Table 5. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise dBm , BER <0.1%. Measurement resolution 1 MHz). Table continues on the next page...

signal 3 dB over reference sensitivity level , PER <1%. Table continues on the next page...

  1. All the RX parameters are measured at the KW41 RF pins
  2. Transceiver power consumption
  3. Measured at 0.1% BER using 37 byte long packets in max gain mode and nominal conditions
  4. In max gain mode and nominal conditions
  5. RSSI performance in narrowband mode
  6. With one point calibration over frequency and temperature
  7. BLE Adjacent and Block parameters are measured with modulated interference signals
  8. Exceptions allowed for carrier frequency harmonics.
  9. Exception to the 10 MHz > freq offset <= 80 MHz out-of-band blocking limit allowed for frequency offsets of twice the
  10. Exceptions allowed for twice the reference clock frequency(fref) multiples.

Table 6. Receiver Specifications with Generic FSK Modulations Table continues on the next page...

  1. Selectivity measured with an unmodulated blocker

5.3 Transmit and PLL Feature Summary

  • Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN frequency bands
  • Fast PLL Lock time: < 25 µs
  • Reference Frequency:
  • 26 and 32 MHz supported for BLE and FSK modes
  • 32 MHz supported for IEEE Standard 802.15.4

Table 7. Top level Transmitter Specifications (TA=25°C, nominal process unless otherwise Table continues on the next page...

  1. All the TX parameters are measured at test hardware SMA connector
  2. Transceiver power consumption
  3. Measured at the KW41Z RF pins
  4. Measured as per IEEE Standard 802.15.4
  5. Offset EVM is computed at one point per symbol, by combining the I value from the beginning of each symbol and the Q
  6. Measured at Pout = 5dBm and recommended TX match
  7. Maximum drift of carrier frequency of the PLL during a BLE packet with a nominal 32MHz reference crystal
  8. Harmonic Levels based on recommended 2 component match. Transmit harmonic levels depend on the tolerances and

quality of the matching components.

Table 8. Transmit Output Power as a function of PA_POWER[5:0] Table continues on the next page...

Table 8. Transmit Output Power as a function of PA_POWER[5:0] (continued)

6 System and Power Management

6.1 Power Management

retention while the core is in various stop modes. It can make sure the device can stay in low current consumption mode while the RF radio can wakeup quick enough for communication.

6.1.1 DC-DC Converter

The features of the DC-DC converter include the following:

  • Single inductor, multiple outputs.
  • Boost mode (pin selectable; CFG=GND).
  • Buck mode (pin selectable; CFG=VDCDC_IN).
  • Continuous or pulsed operation (hardware/software configurable).
  • Power switch input to allow external control of power up, and to select bypass mode.
  • Output signal to indicate power stable. Purpose is for the rest of the chip to be used as a POR.
  • Scaled battery output voltage suitable for SAR ADC utilization.
  • Internal oscillator for support when the reference oscillator is not present.
  • 1.8 V output is capable of supplying the external device a maximum of 38.9 mA (VDD_1P8OUT = 1.8 V, VDCDC_IN = 3.0 V) and 20.9 mA (VDD_1P8OUT = 3.0 V, VDCDC_IN = 3.0 V), with MCU in RUN mode, peripherals are disabled.

6.2 Modes of Operation

The ARM Cortex-M0+ core in the KW41Z has three primary modes of operation: Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes are similar to ARM deep sleep modes. The very low power run (VLPR) operation mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. The WFI instruction invokes both wait and stop modes. The primary modes are augmented in a number of ways to provide lower power based on application needs.

6.2.1 Power modes

The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. System and Power Management MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 29 NXP Semiconductors

compares the various power modes available. to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. when the maximum bus frequency is not required to handle the application needs. lower power based on application needs. Table 9. Power modes (At 25 deg C) retains all registers while maintaining LVD protection. PMC also remain in Run or VLPRun mode. PMC also remain in Run or VLPRun mode. module off, execution from flash). in the way of radio operation. Table continues on the next page...

Table 9. Power modes (At 25 deg C) (continued) Places MCU in static state with LVD operation off. file remains powered for customer-critical data. LLWU, LPTMR, RTC, CMP can be operational. file remains powered for customer-critical data. LLWU, LPTMR, RTC, CMP, TSI can be operational. interrupt only. Radio logic is power gated. interrupt only. Radio logic is power gated.

  1. Biasing is disabled, but the Flash is in a low power mode for VLPx, so this configuration can realize some power
  2. DSM refers to Radio's deepsleep mode. DSM does not refer to the ARM sleep deep mode.

7.1 AC electrical characteristics

Figure 2. Input signal measurement reference output pins have the following characteristics.

  • C L=30 pF loads
  • Slew rate disabled
  • Normal drive strength

7.2 Nonswitching electrical specifications

7.2.1 Voltage and current operating requirements

Table 10. Voltage and current operating requirements Table continues on the next page...

Table 10. Voltage and current operating requirements (continued)

  • 2.7 V ≤ V DD ≤ 3.6 V
  • 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
  • 2.7 V ≤ V DD ≤ 3.6 V
  • 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
  • V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
  • Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

7.2.2 LVD and POR operating requirements

Table 11. V DD supply LVD and POR operating requirements

  • Level 1 falling (LVWV = 00)
  • Level 2 falling (LVWV = 01)
  • Level 3 falling (LVWV = 10)
  • Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V Low-voltage warning thresholds — low range 1 Table continues on the next page... MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 33 NXP Semiconductors

Table 11. V DD supply LVD and POR operating requirements (continued)

  • Level 1 falling (LVWV = 00)
  • Level 2 falling (LVWV = 01)
  • Level 3 falling (LVWV = 10)
  • Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

7.2.3 Voltage and current operating behaviors

Table 12. Voltage and current operating behaviors

  • 2.7 V ≤ V DD ≤ 3.6 V, IOH = -5 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 VDD – 0.5 V V 1, 2 VOH Output high voltage — High drive pad (except RESET_b)
  • 2.7 V ≤ V DD ≤ 3.6 V, IOH = -20 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 VDD – 0.5 V V 1, 2 IOHT Output high current total for all ports — 100 mA VOL Output low voltage — Normal drive pad
  • 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOL = 2.5 mA 0.5 0.5 V V VOL Output low voltage — High drive pad
  • 2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOL = 10 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 500 nA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 5 μA 3 Table continues on the next page... 34 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

Table 12. Voltage and current operating behaviors (continued)

  1. PTB0-1 and PTC0-3, PTC6, PTC7, PTC17, PTC18 I/O have both high drive and normal drive capability selected by

the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

  1. The reset pin only contains an active pull up device when configured as the RESET signal or as a GPIO. When

configured as a GPIO output, it acts as a pseudo open drain output.

  1. Measured at VDD supply voltage = VDD min and Vinput = VSS

7.2.4 Power mode transition operating behaviors

  • CPU and system clocks = 48 MHz
  • Bus and flash clock = 24 MHz
  • FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 13. Power mode transition operating behaviors operating temperature range of the chip.

  • VLLS0 → RUN 147 μs
  • VLLS1 → RUN 144 μs
  • VLLS2 → RUN μs
  • VLLS3 → RUN μs
  • LLS2 → RUN 5.8 μs
  • LLS3 → RUN 5.8 μs Table continues on the next page... MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 35 NXP Semiconductors

Table 13. Power mode transition operating behaviors (continued)

  • VLPS → RUN 6.2 μs
  • STOP → RUN 6.2 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300µs VDD_1P5 = VDD_1P8, TPOR did not meet the 300µs maximum spec when the supply slew rate <=100V/s.

7.2.5 Power consumption operating behaviors

Table 14. Power consumption operating behaviors - Bypass Mode

24 MHz bus / flash disabled (flash doze enabled), all

Table continues on the next page...

Table 14. Power consumption operating behaviors - Bypass Mode (continued) Table continues on the next page...

  1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

  1. MCG configured for FEImode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized for
  2. MCG configured for FEI mode.
  3. Incremental current consumption from peripheral activity is not included.
  4. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized
  5. MCG configured for BLPI mode.

Table 15. Power consumption operating behaviors - Buck Mode Table continues on the next page...

Table 15. Power consumption operating behaviors - Buck Mode (continued) Table continues on the next page...

  1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

  1. MCG configured for FEI mode.
  2. Incremental current consumption from peripheral activity is not included.
  3. MCG configured for BLPI mode.

Table 16. Power consumption operating behaviors - Boost Mode Table continues on the next page...

Table 16. Power consumption operating behaviors - Boost Mode (continued) Table continues on the next page...

  1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

  1. MCG configured for FEI mode.
  2. Incremental current consumption from peripheral activity is not included.
  3. MCG configured for BLPI mode.

Table 17. Low power mode peripheral adders — typical value VLPS mode with 4 MHz IRC enabled. with the 32 kHz IRC enabled. Table continues on the next page...

Table 17. Low power mode peripheral adders — typical value (continued) 6-bit DAC power consumption. kHz external crystal) power consumption. selected clock source power consumption. placing the device in STOP or VLPS mode.

7.2.6 Diagram: Typical IDD_RUN operating behavior

  • No GPIOs toggled
  • Code execution from flash with cache enabled
  • For the ALLOFF curve, all peripheral clocks are disabled except FTFA

Figure 3. Run mode supply current vs. core frequency

Figure 4. VLPR mode current vs. core frequency

7.2.7 SoC Power Consumption

Table 18. SoC Power Consumption Table continues on the next page...

Table 18. SoC Power Consumption (continued)

7.2.8 Designing with radiated emissions in mind

  1. Perform a keyword search for “EMC design.”

7.2.9 Capacitance attributes

Table 19. Capacitance attributes

7.3 Switching electrical specifications

7.3.1 Device clock specifications

Table 20. Device clock specifications Table continues on the next page...

Table 20. Device clock specifications (continued)

  1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
  2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

7.3.2 General switching specifications

LPUART, CMT and I2C signals. Table 21. General switching specifications

  • Slew enabled
  • 1.71 ≤ VDD ≤ 2.7 V
  • Slew disabled
  • 1.71 ≤ VDD ≤ 2.7 V ns ns ns ns 4, 5 Port rise and fall time(low drive strength)
  • Slew enabled 6, 7 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 47 NXP Semiconductors
  • 1.71 ≤ VDD ≤ 2.7 V
  • Slew disabled
  • 1.71 ≤ VDD ≤ 2.7 V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes. 2. The greater of synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized. 4. PTB0, PTB1, PTC0, PTC1, PTC2, PTC3, PTC6, PTC7, PTC17, PTC18. 5. 75 pF load. 6. Ports A, B, and C. 7. 25 pF load.

7.4 Thermal specifications

7.4.1 Thermal operating requirements

Table 22. Thermal operating requirements

  • For Laminate QFN package –40 125 °C TJ Die junction temperature
  • For WLCSP package –40 95 °C TA Ambient temperature
  • For Laminate QFN package –40 105 °C 1 TA Ambient temperature
  • For WLCSP package –40 85 °C 1 1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to determine TJ is: TJ = TA + RθJA × chip power dissipation. 48 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

7.4.2 Thermal attributes

Table 23. Thermal attributes

  1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Method Environmental Conditions—Forced Convection (Moving Air).

  1. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
  2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.

  1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

between the top of the package and the cold plate.

  1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

  1. Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.

7.5 Peripheral operating requirements and behaviors

7.5.1 Core modules

7.5.1.1 SWD electricals

Table 24. SWD full voltage range electricals

  • Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
  • Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)

Figure 5. Serial wire clock input timing

Figure 6. Serial wire data timing

7.5.2 System modules

There are no specifications necessary for the device's system modules.

7.5.3 Clock modules

7.5.3.1 MCG specifications

Table 25. MCG specifications Table continues on the next page...

Table 25. MCG specifications (continued)

  • f VCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

7.5.3.2 Reference Oscillator Specification

meet the requirements of their application. Table 26. Recommended Crystal Specification

Figure 7. Crystal Electrical Block Diagram Table 27. 32 kHz oscillator frequency specifications

  1. Proper PC board layout procedures must be followed to acheive specifications.
  2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

  1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied

clock must be within the range of VSS to VDD.

7.5.4 Memories and memory interfaces

7.5.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

7.5.4.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 28. NVM program/erase timing specifications

  1. Maximum time based on expectations at cycling end-of-life.

7.5.4.1.2 Flash timing specifications — commands

Table 29. Flash command timing specifications

  • 256 KB program flash 1.7 ms trd1sec2k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersblk256k Erase Flash Block execution time
  • 256 KB program flash 250 1500 ms tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 1.8 ms 1 trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 100 — μs — tersall Erase All Blocks execution time — 500 3000 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 500 3000 ms 2 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 55 NXP Semiconductors

7.5.4.1.3 Flash high voltage current behaviors

Table 30. Flash high voltage current behaviors

7.5.4.1.4 Reliability specifications

Table 31. NVM reliability specifications

  1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
  2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

7.5.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

7.5.6 Analog

7.5.6.1 ADC electrical specifications

Table 32. 16-bit ADC operating conditions Table continues on the next page...

Table 32. 16-bit ADC operating conditions (continued)

1.13 VDDA VDDA V 3

  • All other modes VSSA VSSA 31/32 × VREFH VREFH V CADIN Input capacitance
  • 16-bit mode
  • 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 5 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 5 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 kS/s Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 kS/s 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 57 NXP Semiconductors

Figure 8. ADC input impedance equivalency diagram Table 33. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

  • ADLPC=1, ADHSC=0
  • ADLPC=1, ADHSC=1
  • ADLPC=0, ADHSC=0
  • ADLPC=0, ADHSC=1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
  • 12-bit modes
  • <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
  • 12-bit mode; Buck Mode6
  • 12-bit mode; Boost Mode6
  • 12-bit mode; Bypass Mode ±0.7 ±0.5 ±0.5 –1.1 to +1.9 –1.1 to +1.9 –1.1 to +1.9 LSB4 5 Table continues on the next page... 58 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

Table 33. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

  • 12-bit mode; Buck Mode6
  • 12-bit mode; Boost Mode6
  • 12-bit mode; Bypass Mode ±1.0 ±0.7 ±0.6 –2.7 to +1.9 –2.7 to +1.9 –2.7 to +1.9 LSB4 5 EFS Full-scale error • 12-bit modes
  • <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
  • ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode; Buck Mode6
  • Avg = 32
  • Avg = 4 16-bit single-ended mode; Buck Mode6
  • Avg = 32
  • Avg = 4 16-bit differential mode; Boost Mode6
  • Avg = 32
  • Avg = 4 16-bit single-ended mode; Boost Mode6
  • Avg = 32
  • Avg = 4 16-bit differential mode; Bypass Mode
  • Avg = 32
  • Avg = 4 16-bit single-ended mode; Bypass Mode
  • Avg = 32
  • Avg = 4 11.25 9.5 11.5 9.75 9.75 12.5 11.25 12.75 11.75 11.5 10.5 11.5 10.5 11.75 10.5 bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode; Buck Mode6
  • Avg = 32 — -90 — dB Table continues on the next page... MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 59 NXP Semiconductors
  • Avg = 32 16-bit differential mode; Boost Mode6
  • Avg = 32 16-bit single-ended mode; Boost Mode6
  • Avg = 32 16-bit differential mode; Bypass Mode
  • Avg = 32 16-bit single-ended mode; Bypass Mode
  • Avg = 32 -88 -89 -89 -89 -87 SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB SFDR Spurious free dynamic range distortion 16-bit differential mode; Buck Mode6
  • Avg = 32 16-bit single-ended mode; Buck Mode6
  • Avg = 32 16-bit differential mode; Boost Mode6
  • Avg = 32 16-bit single-ended mode; Boost Mode6
  • Avg = 32 16-bit differential mode; Bypass Mode
  • Avg = 32 16-bit single-ended mode; Bypass Mode
  • Avg = 32 dB EIL Input leakage error IIn × RAS mV IIn = leakage current Table continues on the next page... 60 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors
  1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA.
  2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

  1. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

1 MHz ADC conversion clock speed.

  1. 1 LSB = (VREFH - VREFL)/2N.
  2. ADC conversion clock < 16 MHz, maximum hardware averaging (AVGE = %1, AVGS = %11).
  3. VREFH = Output of Voltage Reference(VREF).
  4. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
  5. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
  6. ADC conversion clock < 3 MHz.

7.5.6.2 Voltage reference electrical specifications

Table 34. VREF full-range operating requirements

  1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
  2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature

Table 35. VREF full-range operating behaviors Table continues on the next page...

Table 35. VREF full-range operating behaviors (continued)

  • current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 36. VREF limited-range operating requirements Table 37. VREF limited-range operating behaviors

7.5.6.3 CMP and 6-bit DAC electrical specifications

Table 38. Comparator and 6-bit DAC electrical specifications

  • CR0[HYSTCTR] = 00 — 5 — mV Table continues on the next page... 62 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

Table 38. Comparator and 6-bit DAC electrical specifications (continued)

  • CR0[HYSTCTR] = 01
  • CR0[HYSTCTR] = 10
  • CR0[HYSTCTR] = 11 mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 HYSTCTR Setting 0.1 Vin level (V) CMP Hystereris (V) 0.05 0.01 0.02 0.03 0.08 0.07 0.06 0.04

Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 39. 12-bit DAC operating requirements

  1. The DAC reference can be selected to be VDDA or VREF_OUT.
  2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Table 40. 12-bit DAC operating behaviors

  • High power (SP HP)
  • Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
  • High power (SP HP)
  • Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 65 NXP Semiconductors

Figure 11. Typical INL error vs. digital code

Figure 12. Offset at half scale vs. temperature

7.5.7 Timers

See General switching specifications.

7.5.8 Communication interfaces

7.5.8.1 DSPI switching specifications (limited voltage range)

used for communicating with slower peripheral devices. Table 41. Master mode DSPI timing (limited voltage range)

  1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
  2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 13. DSPI classic SPI timing — master mode Table 42. Slave mode DSPI timing (limited voltage range) Table continues on the next page...

Table 42. Slave mode DSPI timing (limited voltage range) (continued) Figure 14. DSPI classic SPI timing — slave mode

7.5.8.2 DSPI switching specifications (full voltage range)

formats used for communicating with slower peripheral devices. Table 43. Master mode DSPI timing (full voltage range) Table continues on the next page...

Table 43. Master mode DSPI timing (full voltage range) (continued)

  1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

  1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
  2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 15. DSPI classic SPI timing — master mode Table 44. Slave mode DSPI timing (full voltage range)

Figure 16. DSPI classic SPI timing — slave mode

7.5.8.3 Inter-Integrated Circuit Interface (I2C) timing

Table 45. I 2C timing Hold time (repeated) START condition.

  1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
  2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
  3. Input signal Slew = 10 ns and Output Load = 50 pF.
  4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.
  5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
  1. Cb = total capacitance of the one bus line in pF.

Figure 17. Timing definition for fast and standard mode devices on the I2C bus

7.5.8.4 LPUART

See General switching specifications.

7.5.9 Human-machine interfaces (HMI)

7.5.9.1 TSI electrical specifications

Table 46. TSI electrical specifications

7.5.9.2 GPIO

specification, see General switching specifications.

7.6 DC-DC Converter Operating Requirements

Table 47. DC-DC Converter Recommended operating conditions

  1. VDD_1P5 is 1.8 V by default in Boost mode. VDD_1P8OUT should supply to VDD1, VDD2 and VDDA.
  2. In boost mode, DC-DC converter needs minimum 1.1 V to start, the supply can drop to 0.9 V after the DC-DC
  3. In Buck mode, DC-DC converter needs 2.1 V min to start, the supply can drop to 1.8 V after DC-DC converter settles
  4. When 3.6 V < VDDDCDC_IN / DCDC_CFG / PSWITCH <= 4.25 V, TA and TJ are constrained to a maximum of +45 °C

PSWITCH <= 3.6 V, TA and TJ are constrained to a maximum of +105 °C and +125 °C respectively.

  1. In both Buck and Boost modes, LN and LP are connected to external inductor. In boost mode, LP is also shorted to

Table 48. DC-DC Converter Specifications

1.8 V Output Voltage VDD_1P8_boos

Table continues on the next page...

Table 48. DC-DC Converter Specifications (continued)

1.8 V Output Current4, 5

1.5 V Output Current4, 8 VDD_1P5_boos

1.8 V Output Voltage

Table continues on the next page...

1.5 V Output Voltage Radio section

1.5 V Output Current4, 8 IDD_1P5_buck — — 30 mA

  1. This is the steady state DC output power. It requires VDCDC_IN >= 1.7V in boost mode. Excessive transient current

load from external device will cause 1p8V and 1P5 output voltage unregulated temporary.

  1. This is the frequency that will be observed at LN and LP pins.
  2. The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.
  3. The output current specification in both buck and boost modes represents the maximum current the DC-DC converter

consumed by the internal peripherals in KW41Z.

  1. When using DC-DC in low power mode(pulsed mode), current load must be less than 0.5 mA.
  2. The minimum VDD_1P5_boost is the maximum of either what is programmed using
  3. 1.8 V is the default value of the DC-DC 1.5 V output voltage in boost mode. The user can program

radio operation, a voltage level of 1.425 V is required. VDD_1P5 must not be programmed higher than VDD_1P8.

  1. 1.5 V is intended to supply power to KW41Z only. It is not designed to supply power to an external device.
  2. Turn on time is measured from the application of power (to DCDC_IN) to when the

DCDC_REG0[DCDC_STS_DC_OK] bit is set. Full device specification is not guaranteed until the bit sets.

  1. In Buck mode, the maximum VDD_1P8 output is the minimum of either VDCDC_IN_BUCK minus 50 mV or 3.5 V. For
  1. 1.5 V is the default value of DCDC VDD_1P5 in buck mode. The user can program DCDC_VDD1P5CTRL_TRG_BUCK

field in register DCDC_REG3 to control 1P5 output voltage level. For Radio operation, minimum 1.425 V is required. VDD_1P5 must not be programmed higher than VDD_1P8.

7.7 Ratings

7.7.1 Thermal handling ratings

Table 49. Thermal handling ratings

  1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
  2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

7.7.2 Moisture handling ratings

Table 50. Moisture handling ratings

  1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

7.7.3 ESD handling ratings

Table 51. ESD handling ratings

  1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
  2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

  1. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

7.7.4 Voltage and current operating ratings

Table 52. Voltage and current operating ratings

8 Pin Diagrams and Pin Assignments

8.1 Pinouts

Device pinout are shown in figures below.

25 ADC0_DM0

26 VSSA

27 VREFH/VREF_OUT

28 VDDA

29 XTAL_OUT

30 EXTAL

31 XTAL

32 VDD_RF3

33 ANT

34 GANT

35 VDD_RF2

36 VDD_RF1

37 PTC1

38 PTC2

39 PTC3

40 PTC4

41 PTC5

42 PTC6

43 PTC7

44 VDD_1

45 PTC16

46 PTC17

47 PTC18

48 PTC19

Figure 18. 48-pin Laminate QFN pinout diagram

Figure 19. KW41 75-pin WLCSP Pinout Diagram

8.2 Signal Multiplexing and Pin Assignments

for selecting which ALT functional is available on each PTxy pin.

should be tied together external to the device. Table 53. KW41Z Pin Assignments

1 D8 PTA0 SWD_DIO TSIO_CH8 PTA0 SPI0_P

2 B9 PTA1 SWD_CL

3 C9 PTA2 RESET_b PTA2 TPM

4 E7 PTA16 DISABLE

5 D9 PTA17 DISABLE

6 E8 PTA18 DISABLE

7 E9 PTA19 DISABLE

8 F9 PSWITCH PSWITCH PSWITCH

9 F8 DCDC_C

10 G9 VDCDC_I

11 H9 DCDC_L

12 H8 DCDC_L

13 G8 DCDC_G

14 G7 VDD_1P8

15 VDD_1P5

Table continues on the next page...

Table 53. KW41Z Pin Assignments (continued)

16 J6 PTB0 DISABLE

17 H6 PTB1 DISABLE

18 G6 PTB2 DISABLE

19 G5 PTB3 DISABLE

20 J5 VDD_0 VDD_0 VDD_0

21 H4 PTB16 EXTAL32

22 H3 PTB17 XTAL32K XTAL32K PTB17 I2C1_

23 F3 PTB18 NMI_b DAC0_OUT/

24 J1 ADC0_DP

25 H1 ADC0_D

26 G1, G2 VSSA VSSA VSSA

27 F2 VREFH/

28 F1 VDDA VDDA VDDA

29 E1 XTAL_OU

Table continues on the next page...

30 D1 EXTAL EXTAL EXTAL

31 C1 XTAL XTAL XTAL

32 C2 VDD_RF3 VDD_RF3 VDD_RF3

33 B2 ANT ANT ANT

34 B1 GANT GANT GANT

35 B3 VDD_RF2 VDD_RF2 VDD_RF2

36 B4 VDD_RF1 VDD_RF1 VDD_RF1

37 C6 PTC1 DISABLE

38 B6 PTC2 DISABLE

39 A5 PTC3 DISABLE

40 A6 PTC4 DISABLE

41 C7 PTC5 DISABLE

42 B7 PTC6 DISABLE

43 A7 PTC7 DISABLE

44 E6, D7 VDD_1 VDD_1 VDD_1

45 A8 PTC16 DISABLE

46 B8 PTC17 DISABLE

47 A9 PTC18 DISABLE

Table continues on the next page...

48 C8 PTC19 DISABLE

8.3 Module Signal Description Tables

in the module's chapter. They also briefly describe the signal function and direction.

8.3.1 Core Modules

This section contains tables describing the core module signal descriptions. Table 54. SWD Module Signal Descriptions

  1. Pulled up internally by default
  2. Pulled down internally by default

8.3.2 Radio Modules

This section contains tables describing the radio signals. Table 55. Radio Module Signal Descriptions

8.3.3 System Modules

This section contains tables describing the system signals. Table 56. System Module Signal Descriptions Table continues on the next page...

Table 56. System Module Signal Descriptions (continued)

  1. VDD_1P5_CAP and VDD_1P5_PMCIN should always be connected together via PCB trace. System designers

should take care to ensure this connection is as short as possible. Table 57. LLWU Module Signal Descriptions

8.3.4 Clock Modules

This section contains tables for Clock signal descriptions. Table 58. Clock Module Signal Descriptions Table continues on the next page...

Table 58. Clock Module Signal Descriptions (continued)

8.3.5 Analog Modules

This section contains tables for Analog signal descriptions. Table 59. ADC0 Signal Descriptions Table 60. CMP0 Signal Descriptions Table 61. DAC0 Signal Descriptions Table 62. VREF Signal Descriptions

8.3.6 Timer Modules

This section contains tables describing timer module signals. Table 63. TPM0 Module Signal Descriptions Table 64. TPM1 Module Signal Descriptions Table 65. TPM2 Module Signal Descriptions Table 66. LPTMR0 Module Signal Descriptions Table 67. RTC Module Signal Descriptions

8.3.7 Communication Interfaces

This section contains tables for the signal descriptions for the communication modules. Table 68. SPI0 Module Signal Descriptions Table 69. SPI1 Module Signal Descriptions Table 70. I2C0 Module Signal Descriptions Table 71. I2C1 Module Signal Descriptions Table 72. LPUART0 Module Signal Descriptions

  1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or

8.3.8 Human-Machine Interfaces(HMI)

This section contains tables describing the HMI signals. Table 73. GPIO Module Signal Descriptions Table 74. TSI0 Module Signal Descriptions

9 Package Information

9.1 Obtaining package dimensions

Package dimensions are provided in package drawings. Table 75. Packaging Dimensions

Package Information

MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 89 NXP Semiconductors

Table 76. MKW41Z Revision History

  • Updated Flash memory protection

features

  • Updated Table 12 Voltage and current operating behaviors footnotes
  • Corrected Table 21 typos
  • Updated Table 26 Reference crystal specifications verbiage
  • Updated Temperature sensor slow information (Table 33 16-bit ADC characteristics)
  • Updated DCDC converter operating requirements and specifications
  • Added DCDC pin voltage operating range to Table 52. Voltage and current operating ratings Rev 3 07/2017 Added "32 kHz oscillator frequency specifications" table in Clock Modules section. Rev 2 07/2017 • Added WLCSP package details
  • Updated "DC-DC Converter Specifications" table Rev 1 10/2016 Initial Release

Revision History

90 MKW41Z/31Z/21Z Data Sheet, Rev. 4, 03/2018 NXP Semiconductors

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