MKW40Z160 NXP | Alldatasheet
Document overview
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Technical content
A Bluetooth® Low Energy and IEEE®
802.15.4 System on a Chip (SoC)
Supports the following: MKW40Z160VHT4, MKW30Z160VHM4, MKW20Z160VHT4 Key features
- Multi-Standard Radio – 2.4 GHz Bluetooth Low Energy version 4.1 compliant – IEEE Standard 802.15.4 2011 compliant – Typical Receiver Sensitivity (BLE) = -91 dBm – Typical Receiver Sensitivity (802.15.4) = -102 dBm – Programmable Transmitter Output Power: -18 dBm to +5 dBm – Low external component counts for low cost application
- MCU and Memories – Up to 48 MHz ARM® Cortex-M0+ core – On-chip 160 KB Flash memory – On-chip 20 KB SRAM
- Low Power Consumption – Typical Rx Current: 6.5 mA (DCDC in buck mode,
3.6 V supply)
– Typical Tx Current: 8.4 mA (DCDC in buck mode,
3.6 V supply) for a 0 dBm output
– Low Power Mode (VLLS0) Current: 206 nA
- Clocks – 32 MHz Crystal Oscillator – 32 kHz Crystal Oscillator
- System peripherals – Nine low-power modes to provide power optimization based on application requirements – DCDC Converter supporting Buck, Boost, and Bypass modes – DMA Controller – COP Software watchdog – SWD Interface and Micro Trace buffer – Bit Manipulation Engine (BME)
- Human-machine interface – Touch Sensing Input – General-purpose input/output
- Analog modules – 16-bit Analog-to-Digital Converter (ADC) – 12-bit Digital-to-Analog Converter (DAC) – 6-bit High Speed Analog Comparator (CMP)
- Timers – 16-bit low-power timer (LPTMR) – 3 Timers Modules(TPM): One 4 channels TPM and Two 2 channels TPMs – Programmable Interrupt Timer (PIT) – Real-Time Clock (RTC)
- Communication interfaces – 2 SPI modules – 2 I2C modules – Low Power UART module – Carrier Modulator Timer (CMT)
- Security – AES-128 Accelerator (AESA) – True Random Number Generator (TRNG)
- Operating Characteristics – DCDC Converter supporting Buck, Boost, and Bypass modes – Temperature range (ambient): -40 to 85°C Freescale Semiconductor Document Number MKW40Z160 Data Sheet: Advance Information Rev. 1.1, 10/2015 © 2015 Freescale Semiconductor, Inc.
MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 2 Freescale Semiconductor, Inc.
The KW40Z/30Z/20Z (called KW40Z throughout this document) is an ultra low-power, highly integrated single-chip device that enables Bluetooth low energy (BLE) or IEEE Standard 802.15.4 RF connectivity for portable, extremely low-power embedded systems. Applications include portable health care devices, wearable sports and fitness devices, AV remote controls, computer keyboards and mice, gaming controllers, access control, security systems, smart energy and home area networks. The KW40Z SoC integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz range supporting a range of FSK/GFSK and O-QPSK modulations, an ARM Cortex-M0+ CPU, 160 KB Flash and 20 KB SRAM, BLE Link Layer hardware, 802.15.4 packet processor hardware and peripherals optimized to meet the requirements of the target applications. The KW40Z SoC’s radio frequency transceiver is compliant with Bluetooth version 4.1 for Low Energy (aka Bluetooth Smart), and the IEEE standard 802.15.4-2011 using O- QPSK in the 2.4 GHz ISM band. The KW40Z SoC can be used in applications as a "BlackBox" modem by simply adding BLE or IEEE Std. 802.15.4 connectivity to an existing embedded controller system, or used as a stand-alone smart wireless sensor with embedded application where no host controller is required. Freescale provides fully certified protocol stacks and application profiles to support KW40Z. The KW40Z Flash and SRAM memory are available for applications and communication protocols using a choice of Freescale or 3rd party software development tools. The RF section of the KW40Z SoC is optimized to require very few external components, achieving the smallest RF footprint possible on a printed circuit board. Extremely long battery life is achieved though efficiency of code execution in the Cortex- M0+ CPU core and the multiple low power operating modes of the KW40Z SoC. Additionally, an integrated DC-DC converter enables a wide operating range from 0.9 V to 4.2 V. The DC-DC in Buck mode enables KW40Z to operate from a single coin cell battery with a significant reduction of peak Rx and Tx current consumption. The DC-DC in boost mode enables a single alkaline battery to be used throughout its entire useful voltage range of 0.9 V to 1.795 V. MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 3
1 Ordering information
Table 1. Orderable parts details
2 Feature Descriptions
Ordering information
MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 4 Freescale Semiconductor, Inc.
2.1 Block diagram
Figure 1. KW40Z/KW30Z/KW20Z simplified block diagram
2.2 Radio features
- 2.4 GHz ISM band (2400-2483.5 MHz)
- MBAN 2360-2400 MHz Supported standards:
- Bluetooth v4.1 Low Energy compliant 1 Mbps GFSK modulation
- IEEE Std. 802.15.4-2011 compliant O-QPSK modulation
- Freescale Thread Networking Stack
- Bluetooth Low Energy(BLE) Application Profiles
- ZigBee PRO and application profiles Receiver performance: Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 5
- Receive sensitivity of -91 dBm for BLE
- Receive sensitivity of -102 dBm typical for IEEE Std. 802.15.4 Other features:
- Programmable transmit output power from -18 dBm to +5 dBm with DC/DC bypass and buck modes of operation
- Bluetooth Low Energy Link Layer hardware
- Hardware acceleration for IEEE Std. 802.15.4 packet processing
- 32 MHz crystal reference oscillator
- Supports antenna diversity option for IEEE Std. 802.15.4
- Supports dual PAN for IEEE Std. 802.15.4 with hardware-assisted address matching acceleration
- Differential RF port shared by transmit and receive
- Low external component count
- Supports transceiver range extension using external PA and/or LNA
2.3 Microcontroller features
- Up to 48 MHz CPU
- As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles per instruction)
- Supports up to 32 interrupt request sources
- Binary compatible instruction set architecture with the Cortex-M0 core
- Thumb instruction set combines high code density with 32-bit performance
- Serial Wire Debug (SWD) reduces the number of pins required for debugging
- Micro Trace Buffer (MTB) provides lightweight program trace capabilities using system RAM as the destination memory Nested Vectored Interrupt Controller (NVIC)
- 32 vectored interrupts, 4 programmable priority levels
- Includes a single non-maskable interrupt Wake-up Interrupt Controller (WIC)
- Supports interrupt handling when system clocking is disabled in low power modes Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 6 Freescale Semiconductor, Inc.
- Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very-deep-sleep
- A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-masked interrupt is detected Debug Controller
- Two-wire Serial Wire Debug (SWD) interface
- Hardware breakpoint unit for 2 code addresses
- Hardware watchpoint unit for 2 data items
- Micro Trace Buffer for program tracing On-Chip Memory
- 160 KB Flash
- Firmware distribution protection. Flash can be marked execute-only on a per- sector (4 KB) basis to prevent firmware contents from being read by 3rd parties
- Flash implemented as one 128 KB block and one 32 KB block. Code can execute or read from one block while the other block is being erased or programmed
- 20 KB SRAM
- Security circuitry to prevent unauthorized access to RAM and flash contents through the debugger
2.4 System features
Power Management Control Unit (PMC)
- Programmable power saving modes
- Available wake-up from power saving modes via internal and external sources
- Integrated Power-on Reset (POR)
- Integrated Low Voltage Detect (LVD) with reset (brownout) capability
- Selectable LVD trip points
- Programmable Low Voltage Warning (LVW) interrupt capability
- Individual peripheral clocks can be gated off to reduce current consumption
- Internal Buffered bandgap reference voltage
- Factory programmed trim for bandgap and LVD
- 1 kHz Low Power Oscillator (LPO) DC-DC Converter
- Internal switch mode power supply supporting Buck, Boost, and Bypass operating modes Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 7
- Buck operation supports external voltage sources of 2.1 V to 4.2 V. This reduces peak current consumption during Rx and Tx by ~25%, ideal for single coin-cell battery operation (typical CR2032 cell).
- Boost operation supports external voltage sources of 0.9V to 1.795V, which is efficiently increased to the static internal core voltage level, ideal for single battery operation (typical AA or AAA alkaline cell).
- When DCDC is not used, the device supports an external voltage range of 1.45V to 3.6V (1.45 - 3.6V on VDD_RF1, VDD_RF2, VDD_XTAL and VDD_1P45OUT_PMCIN pins. 1.71 - 3.6V on VDD_0, VDD_1 and VDDA pins)
- An external inductor is required to support the Buck or Boost modes
- The DCDC Converter 1.8V output current drive for external devices (MCU in RUN mode, Radio is enabled, other peripherals are disabled)
- Up to 44mA in buck mode with VDD_1P8 = 1.8V
- Up to 31.4mA in buck mode with VDD_1P8 = 3.0V DMA Controller
- Four independently programmable DMA controller channels provides the means to directly transfer data between system memory and I/O peripherals
- DMA controller is capable of functioning in run and wait modes of operation
- Dual-address transfers via 32-bit master connection to the system bus
- Data transfers in 8-, 16-, or 32-bit blocks
- Continuous-mode or cycle-steal transfers from software or peripheral initiation DMA Channel Multiplexer (DMA MUX)
- 4 independently selectable DMA channel routers
- 2 periodic trigger sources available
- Each channel router can be assigned to 1 of the peripheral DMA sources COP Watchdog Module
- Independent clock source input (independent from CPU/bus clock)
- Choice between two clock sources
- LPO oscillator
- Bus clock System Clocks
- 32 MHz crystal reference oscillator provides clock for the radio, and is the main clock option for the MCU
- 32/32.768 kHz crystal reference oscillator used to maintain precise Bluetooth radio time in low power modes
- Multipurpose Clock Generator (MCG) Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 8 Freescale Semiconductor, Inc.
- Internal reference clocks — Can be used as a clock source for other on-chip peripherals
- On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy across full temperature range
- On-chip 4MHz oscillator with 5% accuracy across full temperature range
- Frequency-locked loop (FLL) controlled by internal or external reference
- 20 MHz to 48 MHz FLL output Unique Identifiers
- 10 bytes of the Unique ID represents a unique identifier for each chip
- 40 bits of unique MAC address can be used to generate BLE or 802.15.4 device address
2.5 Peripheral features
16-bit Analog-to-Digital Converter (ADC)
- Linear successive approximation algorithm with 16-bit resolution
- Output formatted in 16-, 12-, 10-, or 8-bit right justified format
- Single or continuous conversion
- Configurable sample time and conversion speed / power
- Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
- Input clock selection
- Operation in low power modes for lower noise operation
- Asynchronous clock source for lower noise operation
- Selectable asynchronous hardware conversion trigger
- Automatic compare with interrupt for less-than, or greater than, or equal to programmable value
- Temperature sensor
- Battery voltage measurement
- Hardware average function
- Selectable voltage reverence
- Self-calibration mode 12-Bit Digital-to-Analog Converter (DAC)
- 12-bit resolution
- Guaranteed 6-sigma monotonicity over input word
- High- and low-speed conversions
- 1 μs conversion rate for high speed, 2 μs for low speed
- Power-down mode Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 9
- Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth
- Automatic mode allows programmable period, update rate, and range
- DMA support with configurable watermark level High-Speed Analog Comparator (CMP)
- 6-bit DAC programmable reference generator output
- Up to eight selectable comparator inputs; each input can be compared with any input by any polarity sequence
- Selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output
- Two performance modes:
- Shorter propagation delay at the expense of higher power
- Low power, with longer propagation delay
- Operational in all MCU power modes Low Power Timer (LPTMR)
- One channel
- Operation as timer or pulse counter
- Selectable clock for prescaler/glitch filter
- 1 kHz internal LPO
- External low power crystal oscillator
- Internal reference clock
- Configurable glitch filter or prescaler
- Interrupt generated on timer compare
- Hardware trigger generated on timer compare
- Functional in all power modes Timer/PWM (TPM)
- TPM0: 4 channels, TPM1 and TPM2: 2 channels each
- Selectable source clock
- Programmable prescaler
- 16-bit counter supporting free-running or initial/final value, and counting is up or up- down
- Input capture, output compare, and edge-aligned and center-aligned PWM modes
- Input capture and output compare modes
- Generation of hardware triggers
- TPM1 and TPM2: Quadrature decoder with input filters
- Global time base mode shares single time base across multiple TPM instances Programmable Interrupt Timer (PIT) Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 10 Freescale Semiconductor, Inc.
- Up to 2 interrupt timers for triggering ADC conversions
- 32-bit counter resolution
- Clocked by system clock frequency Real-Time Clock (RTC)
- 32-bit seconds counter with 32-bit alarm
- Can be invalidated on detection of tamper detect
- 16-bit prescaler with compensation
- Register write protection
- Hard Lock requires MCU POR to enable write access
- Soft lock requires system reset to enable write/read access
- Capable of waking up the system from low power modes Inter-Integrated Circuit (I2C)
- Two channels
- Compatible with I2C bus standard and SMBus Specification Version 2 features
- Up to 1 Mbps operation
- Multi-master operation
- Software programmable for one of 64 different serial clock frequencies
- Programmable slave address and glitch input filter
- Interrupt driven byte-by-byte data transfer
- Arbitration lost interrupt with automatic mode switching from master to slave
- Calling address identification interrupt
- Bus busy detection broadcast and 10-bit address extension
- Address matching causes wake-up when processor is in low power mode LPUART
- One channel
- Full-duplex operation
- Standard mark/space non-return-to-zero (NRZ) format
- 13-bit baud rate selection with fractional divide of 32
- Programmable 8-bit or 9-bit data format
- Programmable 1 or 2 stop bits
- Separately enabled transmitter and receiver
- Programmable transmitter output polarity
- Programmable receive input polarity
- 13-bit break character option
- 11-bit break character detection option
- Two receiver wakeup methods:
- Idle line wakeup
- Address mark wakeup Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 11
- Address match feature in receiver to reduce address mark wakeup ISR overhead
- Interrupt or DMA driven operation
- Receiver framing error detection
- Hardware parity generation and checking
- Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise detection
- Operation in low power modes
- Hardware Flow Control RTS\\CTS
- Functional in Stop/VLPS modes Serial Peripheral Interface (DSPI)
- Two independent SPI channels
- Master and slave mode
- Full-duplex, three-wire synchronous transfers
- Programmable transmit bit rate
- Double-buffered transmit and receive data registers
- Serial clock phase and polarity options
- Slave select output
- Control of SPI operation during wait mode
- Selectable MSB-first or LSB-first shifting
- Support for both transmit and receive by DMA Carrier Modulator Timer (CMT)
- Four modes of operation
- Time; with independent control of high and low times
- Baseband
- Frequency shift key (FSK)
- Direct software control of CMT_IRO signal
- Extended space operation in time, baseband, and FSK modes
- Selectable input clock divider
- Interrupt on end of cycle
- Ability to disable CMT_IRO signal and use as timer interrupt General Purpose Input/Output (GPIO)
- Hysteresis and configurable pull up device on all input pins
- Independent pin value register to read logic level on digital pin
- All GPIO pins can generate IRQ and wakeup events
- Configurable drive strength on some output pins Touch Sensor Input (TSI)
- Support up to 16 external electrodes
- Automatic detection of electrode capacitance across all operational power modes Feature Descriptions MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 12 Freescale Semiconductor, Inc.
- Internal reference oscillator for high-accuracy measurement
- Configurable software or hardware scan trigger
- Fully support Freescale touch sensing software (TSS) library
- Capability to wake MCU from low power modes
- Compensate for temperature and supply voltage variations
- High sensitivity change with 16-bit resolution register
- Configurable up to 4096 scan times
- Support DMA data transfer Keyboard Interface
- GPIO can be configured to function as a interrupt driven keyboard scanning matrix
- In the 48pin package there are a total of 28 digital pins
- In the 32pin package there are a total of 15 digital pins
- These pins can be configured as needed by the application as GPIO, UART, SPI, I2C, ADC, timer I/O as well as other functions AES Accelerator (AESA)
- The Advanced Encryption Standard Accelerator (AESA) is a stand-alone symmetric encryption accelerator supporting 128- bit key and data size and the following modes:
- Electronic Codebook (ECB)
- Cipher Block Chaining (CBC)
- Counter (CTR)
- CTR & CBC-MAC (CCM and CCM*)
- Cipher-base MAC (CMAC)
- Extended Cipher Block Chaining Message Authentication Code (XCBC-MAC)
- The AESA supports all BLE and IEEE 802.15.4 packet sizes
- The AESA supports DMA and interrupt-driven operation True Random Number Generator (TRNG)
- The TRNG is an entropy source
- The TRNG output is intended to be read and used as an input to a deterministic random number generator
- The deterministic random number general will be implemented in software
- A FIPS 180 compliant solution can be realized using the TRNG together with a FIPS compliant determinstic random number generator and SoC-level security
3 Transceiver Description
MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 13
- Direction Conversion Receiver
- Constant Envelope Transmitter
- 2.36 GHz to 2.483 GHz PLL Range
- Low Transmit and Receive Current Consumption
- Low BOM
3.1 Key Specifications
The KW40Z SoC meets or exceeds all Bluetooth Low Energy v4.1 and IEEE 802.15.4 performance specifications applicable to 2.4 GHz ISM and MBAN (Medical Band Area Network) bands. Key specification for the KW40Z are: Frequency Band:
- ISM Band: 2400 to 2483.5MHz
- MBAN Band: 2360 to 2400MHz Bluetooth Low Energy v4.1 modulation scheme:
- Symbol rate: 1000kbps
- Modulation: GFSK
- Receiver sensitivity: -91 dBm, typical
- Programmable transmitter output power: -18 dBm to +5 dBm IEEE Standard 802.15.4 2.4 GHz modulation scheme:
- Chip rate: 2000kbps
- Data rate: 250kbps
- Symbol rate: 62.5kbps
- Modulation: OQPSK
- Receiver sensitivity: -102dBm, typical (@1% PER for 20 byte payload packet)
- Differential bidirectional RF input/output port with integrated transmit/receive switch
- Programmable transmitter output power: -18 dBm to +5 dBm
3.2 Frequency Plan for Bluetooth Low Energy
This section describes the frequency plan / channels associated with 2.4GHz ISM and MBAN bands for Bluetooth Low Energy. 2.4GHz ISM Channel numbering: Transceiver Description MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 14 Freescale Semiconductor, Inc.
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations Table continues on the next page...
Table 2. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
- ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
- Per FCC guideline rules, IEEE (R) 802.15.1 and Bluetooth Low Energy V4.0 single mode operation is allowed in these
Table 3. 2.4 GHz ISM and MBAN frequency plan and channel designations
2.4 GHz ISM MBAN1
Table continues on the next page... 16 Freescale Semiconductor, Inc.
Table 3. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
- Usable channel spacing to assit in co-existence.
3.4 Transceiver Functions
- The receiver architecture is Zero IF (ZIF) where the received signal after passing through RF front end is down-converted to a baseband signal. The signal is filtered and amplified before it is fed to a sigma-delta analog-to-digital converter. The digital signal is then decimated to a baseband clock frequency before it is digitally processed, demodulated and passed on to packet processing. Transmit
- The transmitter transmits O-QPSK or GFSK/FSK modulation having power and channel selection adjustment per user application. After the channel of operation is determined, coarse and fine tuning is executed within the Frac-N PLL to engage signal lock. After signal lock is established, the modulated buffered signal is then routed to a multi-stage amplifier for transmission. The differential signals at the output of the PA (RF_P, RF_N) are converted as single ended (SE) signals with off chip components as required.
4 System and Power Management
4.1 Power Management
The KW40Z SoC includes internal power management features that can be used to control the power usage. The power management of the KW40Z includes power management controller (PMC) and a DCDC converter which can operate in a buck, boost or bypass configuration. The PMC is designed such that the RF radio will remain in state- retention while the core is in various stop modes. It can make sure the device can stay in low current consumption mode while the RF radio can wakeup quick enough for communication.
4.1.1 DCDC Converter
The features of the DCDC converter include the following:
- Single inductor, multiple outputs
- Buck and boost modes (pin selectable; CFG=VDCDC_IN -> buck; CFG=GND -> boost)
- Continuous or pulsed operation (hardware/software configurable)
- Power switch input to allow external control of power up, and to select bypass mode
- Output signal to indicate power stable. Purpose is for the rest of the chip to use as a POR
- Scaled battery output voltage suitable for SAR ADC utilization
- Internal oscillator for support when the reference oscillator is not present
- 1.8V output is capable to supply external device: max 38.9mA (V1P8 = 1.8V, VDCDC_IN = 3.0V) and 20.9mA (V1P8 = 3.0V, VDCDC_IN = 3.0V), with MCU in RUN mode, peripherals are disabled
4.2 Modes of Operation
The ARM Cortex-M0+ core in the KW40Z SoC has three primary modes of operation: Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes are similar to ARM deep sleep modes. The very low power run (VLPR) operation mode can drastically reduce runtime power when the maximum bus frequency is note required to handle the application needs. The WFI instruction invokes both wait and stop modes for KW40Z. The primary modes are augmented in a number of ways to provide lower power based on application needs. System and Power Management MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 18 Freescale Semiconductor, Inc.
4.2.1 Power modes
user to optimize power consumption for the level of functionality needed. compares the various power modes available. to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. when the maximum bus frequency is not required to handle the application needs. number of ways to provide lower power based on application needs. Table 4. Power modes (At 25 deg C) retains all registers while maintaining LVD protection. PMC also remain in Run or VLPRun mode. PMC also remain in Run or VLPRun mode. module off, execution from flash). in the way of radio operation. Table continues on the next page...
Table 4. Power modes (At 25 deg C) (continued) Places MCU in static state with LVD operation off. Partial SRAM retention. 4KBytes of RAM retained. file remains powered for customer-critical data. file remains powered for customer-critical data. LLWU, LPTMR, RTC, CMP, TSI can be operational. interrupt only. Radio logic is power gated. interrupt only. Radio logic is power gated.
- Biasing is disabled, but the Flash is in a low power mode for VLPx, so this configuration can realize some power savings
- DSM refers to BTLL's deepsleep mode. DSM does not refer to the ARM sleep deep mode.
20 Freescale Semiconductor, Inc.
5 Transceiver Electrical Characteristics
5.1 Recommended radio operating conditions
Table 5. Recommended operating conditions
- VDDINT is the internal LDO regulated voltage supplying various circuit blocks, VDDINT=1.2 V
5.2 Receiver Feature Summary
Table 6. Top Level Receiver Specifications (TA=25°C, nominal process Table continues on the next page...
Table 6. Top Level Receiver Specifications (TA=25°C, nominal process unless otherwise BER <0.1%. Measurement resolution 1 MHz).
- All the RX parameters are measured at the KW40 RF pins
- Transceiver power consumption
22 Freescale Semiconductor, Inc.
- Measured at 0.1% BER using 37 byte long packets in max gain mode and nominal conditions
- In max gain mode and nominal conditions
- BLE Adjacent and Block parameters are measured with modulated interference signals
- Exceptions allowed for reference frequency multiples
5.3 Transmit and PLL Feature Summary
- Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN frequency bands
- Fast PLL Lock time: < 50 µs
- Reference Frequency: 32 MHz
- Low Integrated Phase Noise: -81 dBVrms (1 kHz to 1 MHz)
Table 7. Top level Transmitter Specifications (TA=25°C, nominal process
- All the TX parameters are measured at test hardware SMA connector
- Transceiver power consumption, Pout = 0 dBm
- Measured at the KW40 RF pins
- Measured as per IEEE Std. 802.15.4-2011
- Offset EVM is computed at one point per symbol, by combining the I value from the beginning of each symbol and the Q
- Measured at Pout = 5dBm and recommended TX match
- Maximum drift of carrier frequency of the PLL during a BLE packet with a nominal 32MHz reference crystal
6.1 AC electrical characteristics
Figure 2. Input signal measurement reference output pins have the following characteristics.
- C L=30 pF loads
- Slew rate disabled
- Normal drive strength
6.2 Nonswitching electrical specifications
6.2.1 Voltage and current operating requirements
Table 8. Voltage and current operating requirements Table continues on the next page... 24 Freescale Semiconductor, Inc.
Table 8. Voltage and current operating requirements (continued)
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
- V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
- Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.
6.2.2 LVD and POR operating requirements
Table 9. V DD supply LVD and POR operating requirements
- Level 1 falling (LVWV = 00)
- Level 2 falling (LVWV = 01)
- Level 3 falling (LVWV = 10)
- Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — Low-voltage warning thresholds — low range 1 Table continues on the next page... MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 25
Table 9. V DD supply LVD and POR operating requirements (continued)
- Level 1 falling (LVWV = 00)
- Level 2 falling (LVWV = 01)
- Level 3 falling (LVWV = 10)
- Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage
6.2.3 Voltage and current operating behaviors
Table 10. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -5 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 VDD – 0.5 V V VOH Output high voltage — High drive pad (except RESET_b)
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -20 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — Normal drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 2.5 mA 0.5 0.5 V V VOL Output low voltage — High drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 10 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 65 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 4 MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 26 Freescale Semiconductor, Inc.
- PTB0-1 and PTC0-3 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE]
control bit. All other GPIOs are normal drive only.
- The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
- Measured at VDD supply voltage = VDD min and Vinput = VSS
6.2.4 Power mode transition operating behaviors
- CPU and system clocks = 48 MHz
- Bus and flash clock = 24 MHz
- FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 11. Power mode transition operating behaviors operating temperature range of the chip.
- VLLS0 → RUN 147 μs
- VLLS1 → RUN 144 μs
- VLLS3 → RUN μs
- LLS → RUN 5.8 μs
- VLPS → RUN 6.2 μs
- STOP → RUN 6.2 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DCDC converter is in bypass mode, TPOR will not meet the 300µs where VDD_1P45 = VDD_1P8, TPOR did not meet the 300µs maximum spec when the supply slew rate <=100V/s. MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 27
6.2.5 Power consumption operating behaviors
Table 12. Power consumption operating behaviors
- at 3.0 V 6.1 7.2 mA IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash
- at 3.0 V 3.8 5.2 mA IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash
- at 3.0 V 4.8 6.3 mA IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash
- at 3.0 V
- at 25 °C
- at 85 °C 6.1 6.3 6.4 6.6 mA mA IDD_WAIT Wait mode current - core disabled / 48 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
- at 3.0 V 3.0 4.4 mA IDD_WAIT Wait mode current - core disabled / 24 MHz system /
- at 3.0 V 2.3 3.7 mA IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus
- at 3.0 V 2.2 3.7 mA IDD_VLPRCO_ CM Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, LPTMR running with 4 MHz internal reference clock, CoreMark benchmark code executing from flash
- at 3.0 V 0.732 2.5 mA IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code of while(1) loop executing from flash
- at 3.0 V 145 485 μA Table continues on the next page... MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 28 Freescale Semiconductor, Inc.
Table 12. Power consumption operating behaviors (continued)
- at 3.0 V 180 515 μA IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash
- at 3.0 V 227 572 μA 4, 6 IDD_VLPW Very-low-power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
- at 3.0 V 125 515 μA 6 IDD_STOP Stop mode current at 3.0 V at 25 °C at 50 °C at 70 °C at 85 °C 200 217 251 304 215 239 304 405 μA μA μA μA IDD_VLPS Very-low-power stop mode current at Bypass mode(3.0 V), 25 °C Very low power stop mode current at Buck mode7, 25°C Very low power stop mode current at Boost mode8, 25°C 2.9 2.3 4.3 6.6 14.3 μA μA μA IDD_LLS3 Low-leakage stop mode 3 current at Bypass mode(3.0 V), 25 °C Low-leakage stop mode 3 current at Buck mode7, 25°C Low-leakage stop mode 3 current at Boost mode8, 25°C 2.2 3.07 5.11 2.7 10.4 8.71 μA μA μA IDD_LLS2 Low-leakage stop mode 2 current at Bypass mode(3.0 V), at 25 °C Low-leakage stop mode 2 current at Buck mode7, 25°C Low-leakage stop mode 2 current at Boost mode8, 25°C 2.1 2.30 5.06 2.4 6.92 8.92 μA μA μA IDD_VLLS3 Very-low-leakage stop mode 3 current at Bypass mode(3.0 V), at 25 °C Very-low-leakage stop mode 3 current at Buck mode7, 25°C Very-low-leakage stop mode 3 current at Boost mode8, 25°C 1.7 1.39 3.70 2.1 2.44 6.31 μA μA μA IDD_VLLS2 Very-low-leakage stop mode 2 current at Bypass mode(3.0 V), at 25 °C 1.6 1.43 1.8 2.19 μA μA Table continues on the next page... MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 29
- The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
- MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for
- MCG configured for FEI mode.
- Incremental current consumption from peripheral activity is not included.
- MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for
- MCG configured for BLPI mode.
- DCDC_IN = 3.0V, VDD1P8 = 1.8V, VDD1P45 = 1.45V with 10uF on both VDD1P8 and VDD1P45 pins
- DCDC_IN = 1.3V, VDD1P8 = 1.8V, VDD1P45 = 1.45V with 10uF on both VDD1P8 and VDD1P45 pins
Table 13. Low power mode peripheral adders — typical value IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. with the 32 kHz IRC enabled. Table continues on the next page... 30 Freescale Semiconductor, Inc.
Table 13. Low power mode peripheral adders — typical value (continued) entering all modes with the crystal enabled. kHz external crystal) power consumption. clock source power consumption. compare generating 100 Hz clock signal. placing the device in STOP or VLPS mode.
6.2.6 Diagram: Typical IDD_RUN operating behavior
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFA Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE Run Mode Current VS Core Frequency CLK Ratio Flash-Core Core Freq (MHz) All Off All On Current Consumption on V DD (A) 7.00E-03 6.00E-03 5.00E-03 4.00E-03 3.00E-03 2.00E-03 1.00E-03 000.00E+00 '1-1 1 2 3 4 6 12 24 48 All Peripheral CLK Gates
Figure 3. Run mode supply current vs. core frequency 32 Freescale Semiconductor, Inc.
Figure 4. VLPR mode current vs. core frequency
6.2.7 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
6.2.8 Capacitance attributes
Table 14. Capacitance attributes
6.3 Switching electrical specifications
6.3.1 Device clock specifications
Table 15. Device clock specifications
- The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
- The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
6.3.2 General switching specifications
Table continues on the next page... 34 Freescale Semiconductor, Inc.
- Slew enabled
- 1.71 ≤ VDD ≤ 2.7 V
- Slew disabled
- 1.71 ≤ VDD ≤ 2.7 V ns ns ns ns 4, 5 Port rise and fall time(low drive strength)
- Slew enabled
- 1.71 ≤ VDD ≤ 2.7 V
- Slew disabled
- 1.71 ≤ VDD ≤ 2.7 V ns ns ns ns 6, 7 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes. 2. The greater of synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized 4. PTB0, PTB1, PTC0, PTC1, PTC2, PTC3. 5. 75 pF load. 6. Ports A, B, and C. 7. 25 pF load.
6.4 Thermal specifications
6.4.1 Thermal operating requirements
Table 16. Thermal operating requirements
- Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
6.4.2 Thermal attributes
Table 17. Thermal attributes Table continues on the next page...
Table 17. Thermal attributes (continued)
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
- Per JEDEC JESD51-6 with the board horizontal.
- Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
- Thermal characterization parameter indicating the temperature difference between package top and the junction
- Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.
6.5 Peripheral operating requirements and behaviors
6.5.1 Core modules
6.5.1.1 SWD electricals
Table 18. SWD full voltage range electricals Table continues on the next page... 36 Freescale Semiconductor, Inc.
6.5.2 System modules
There are no specifications necessary for the device's system modules.
6.5.3 Clock modules
6.5.3.1 MCG specifications
Table 19. MCG specifications
- f VCO = 48 MHz — 180 — ps Table continues on the next page... MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 38 Freescale Semiconductor, Inc.
Table 19. MCG specifications (continued)
- This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
- The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
6.5.3.2 Reference Oscillator Specification
KW40Z. NDK EXS00A-CS07637 32 MHz crystal is recommended. Table 20. Reference Crystal Specification
6.5.4 Memories and memory interfaces
6.5.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.5.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 21. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
6.5.4.1.2 Flash timing specifications — commands
Table 22. Flash command timing specifications
- 32 KB program flash
- 128 KB program flash 0.5 1.7 ms ms trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs tpgm4 Program Longword execution time — 65 145 μs — tersblk32k tersblk128k Erase Flash Block execution time
- 32 KB program flash
- 128 KB program flash 500 600 ms ms tersscr Erase Flash Sector execution time — 14 114 ms trd1all Read 1s All Blocks execution time — — 1.8 ms 1 trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 150 1200 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 40 Freescale Semiconductor, Inc.
6.5.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
6.5.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
- Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
6.5.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.5.6 Analog
6.5.6.1 ADC electrical specifications
Table 25. 16-bit ADC operating conditions Table continues on the next page...
Table 25. 16-bit ADC operating conditions (continued)
1.13 VDDA VDDA V
- All other modes VREFL VREFL 31/32 × VREFH VREFH V CADIN Input capacitance • 16-bit mode
- 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 5 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSSA. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 42 Freescale Semiconductor, Inc.
Figure 7. ADC input impedance equivalency diagram Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC = 1, ADHSC = 0
- ADLPC = 1, ADHSC = 1
- ADLPC = 0, ADHSC = 0
- ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12-bit modes
- <12-bit modes ±1.4 ±6.8 ±2.1 LSB DNL Differential non- linearity
- 12-bit modes
- <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB3 4 INL Integral non-linearity • 12-bit modes
- <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB3 4 Table continues on the next page... MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 43
Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- <12-bit modes –1.4 –5.4 –1.8 LSB3 VADIN = VDDA4 EQ Quantization error • 16-bit modes
- ≤13-bit modes –1 to 0 ±0.5 LSB3 ENOB Effective number of bits 16-bit differential mode
- Avg = 32
- Avg = 4 16-bit single-ended mode
- Avg = 32
- Avg = 4 11.54 10.33 10.3 9.22 13.5 12.5 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
- Avg = 32 16-bit single-ended mode
- Avg = 32 -88 -80 dB dB SFDR Spurious free dynamic range 16-bit differential mode
- Avg = 32 16-bit single-ended mode
- Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 6 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 3. 1 LSB = (VREFH - VREFL)/2N 4. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 5. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 6. ADC conversion clock < 3 MHz MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 44 Freescale Semiconductor, Inc.
6.5.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 45
Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 46 Freescale Semiconductor, Inc.
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 28. 12-bit DAC operating requirements
- The DAC reference can be selected to be VDDA or VREFH.
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Table 29. 12-bit DAC operating behaviors Table continues on the next page...
Table 29. 12-bit DAC operating behaviors (continued)
- High power (SP HP)
- Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
- High power (SP HP)
- Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 48 Freescale Semiconductor, Inc.
Figure 10. Typical INL error vs. digital code
Figure 11. Offset at half scale vs. temperature
6.5.7 Timers
See General switching specifications.
6.5.8 Communication interfaces
50 Freescale Semiconductor, Inc.
6.5.8.1 DSPI switching specifications (limited voltage range)
used for communicating with slower peripheral devices. Table 30. Master mode DSPI timing (limited voltage range)
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 12. DSPI classic SPI timing — master mode Table 31. Slave mode DSPI timing (limited voltage range) Table continues on the next page...
Table 31. Slave mode DSPI timing (limited voltage range) (continued) Figure 13. DSPI classic SPI timing — slave mode
6.5.8.2 DSPI switching specifications (full voltage range)
used for communicating with slower peripheral devices. Table 32. Master mode DSPI timing (full voltage range) Table continues on the next page... 52 Freescale Semiconductor, Inc.
Table 32. Master mode DSPI timing (full voltage range) (continued)
- The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 14. DSPI classic SPI timing — master mode Table 33. Slave mode DSPI timing (full voltage range)
Figure 15. DSPI classic SPI timing — slave mode
6.5.8.3 Inter-Integrated Circuit Interface (I2C) timing
Table 34. I 2C timing Hold time (repeated) START condition.
- The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
- The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
- A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
- Cb = total capacitance of the one bus line in pF.
54 Freescale Semiconductor, Inc.
Figure 16. Timing definition for fast and standard mode devices on the I2C bus
6.5.8.4 UART
See General switching specifications.
6.5.9 Human-machine interfaces (HMI)
6.5.9.1 TSI electrical specifications
Table 35. TSI electrical specifications
6.5.9.2 GPIO
specification, see General switching specifications.
7.1 DCDC Converter Recommended Electrical Characteristics
Table 36. DCDC Converter Recommended operating conditions
- In Buck and Boost modes, DCDC converter will generate 1.8V at VDD_1P8OUT and 1.45V at VDD_1P45OUT_PMCIN
- In Buck mode, DCDC converter needs 2.1V min to start, the supply can drop to 1.8V after DCDC converter settles
Table 37. DCDC Converter Specifications Table continues on the next page... 56 Freescale Semiconductor, Inc.
Table 37. DCDC Converter Specifications (continued)
- This is the steady state DC output power. It requires VDCDC_IN >= 1.7V in boost mode. Excessive transient current load
from external device will cause 1p8V and 1p45 output voltage unregulated temporary.
- DCDC converter requires slightly higher input voltage during startup. VDCDC_IN_boost_startup is the minimum startup
startup sequence. Typical startup time is 50ms and it varies with the loading of the converter.
- The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.
- The output current specification in both buck and boost modes represents the maximum current the DCDC converter can
internal peripherals in KW40Z. See application note AN5025 for detail explanation.
- When using DCDC in low power mode(pulsed mode), current load must be less than 1mA.
- In Boost mode, the minimum 1.45V output is the maximum of either what is programmed using
- 1.8V is default value of the DCDC 1.45V output voltage in boost mode. The user can program
radio operation, a voltage level of 1.425V is required.
- 1.45V is intended to supply power to KW40Z only. It is not designed to supply power to an external device.
- DCDC converter requires slightly higher input voltage during startup. VDCDC_IN_buck_startup is the minimum startup
startup sequence. Typical startup time is 50ms and it varies with the loading of the converter.
- In Buck mode, the maximum 1.8V output is the minimum of either VDCDC_IN_BUCK or 3V. For example, if VDCDC_IN =
- User needs to program DCDC_VDD1P45CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case
minimum of 1.425V is available as VDD_1P45_buck for radio operation.
7.2.1 Thermal handling ratings
Table 38. Thermal handling ratings
- Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.2.2 Moisture handling ratings
Table 39. Moisture handling ratings
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
7.2.3 ESD handling ratings
Table 40. ESD handling ratings
- Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
- Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
- Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
7.2.4 Voltage and current operating ratings
Table 41. Voltage and current operating ratings
8 Pin Diagrams and Pin Assignments
58 Freescale Semiconductor, Inc.
8.1 Pinouts
Device pinout are shown in figures below.
25 ADC0_DM0
26 VSSA
27 VREFH
28 VDDA
29 EXTAL_32M
30 XTAL_32M
31 VDD_XTAL
32 VDD_RF2
33 RF_N
34 RF_P
35 VDD_RF1
36 PTC0
37 PTC1
38 PTC2
39 PTC3
40 PTC4
41 PTC5
42 PTC6
43 PTC7
44 VDD_1
45 PTC16
46 PTC17
47 PTC18
48 PTC19
Figure 17. 48-pin Laminate QFN pinout diagram
17 PTB18
18 VDDA
19 EXTAL_32M
20 XTAL_32M
21 VDD_RF2
22 RF_N
23 RF_P
24 VDD_RF1
25 PTC0
26 PTC1
27 PTC2
28 PTC3
29 VDD_1
30 PTC16
31 PTC17
32 PTC18
Figure 18. 32-pin Laminate QFN pinout diagram
8.2 Signal Multiplexing and Pin Assignments
selecting which ALT functional is available on each PTxy pin. Table 42. KW40Z Pin Assignments Table continues on the next page... 60 Freescale Semiconductor, Inc.
Table 42. KW40Z Pin Assignments (continued) Table continues on the next page...
Table continues on the next page... 62 Freescale Semiconductor, Inc.
- LLWU_Px signals are active in LLS/VLLSx power modes
9 Package Information
9.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
Package Information
MKW40Z/30Z/20Z Data Sheet, Rev. 1.1, 10/2015 Freescale Semiconductor, Inc. 63
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