MKW01Z128

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© Freescale Semiconductor, Inc., 2014. All rights reserved. Freescale Semiconductor Advance Information This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Document Number: MKW01Z128 Rev. 5, 3/2014 MKW01Z128

Package Information

Ordering Information

Device Device Marking Package MKW01Z128CHN MKW01Z128CHN LGA-60

1 Introduction

The MKW01 device is highly-integrated, cost-effective, smart radio, sub-1 GHz wireless node solution composed of a transceiver supporting FSK, GFSK, MSK, or OOK modulations with a low-power ARM® Cortex M0+ CPU. The highly integrated RF transceiver operates over a wide frequency range including 315 MHz, 433 MHz,

470 MHz, 868 MHz, 915 MHz, 928 MHz, and 955 MHz

in the license-free Industrial, Scientific and Medical (ISM) frequency bands. This configuration allows users to minimize the use of external components. The MKW01 is targeted for the following low-power wireless applications:

• Automated Meter Reading
• Wireless Sensor Networks
• Home and Building Automation
• Wireless Alarm and Security Systems
• Industrial Monitoring and Control Freescale supplements the MKW01 with tools and software that include hardware evaluation and MKW01Z128 Highly-integrated, cost-effective single-package solution for sub-1 GHz applications 4 Smart Radio Sub-1 GHz Wireless Node . . . . 5

5 MKW01 Pin Assignments and Connections 9

2 Freescale Semiconductor

Freescale’s IEEE 802.15.4 compatible MAC and SMAC. This section provides a simplified block diagram and highlights MKW01 features.

2.1 Block Diagram

Figure 1 shows a simplified block diagram of the MKW01. Figure 1. MKW01 Simplified Block Diagram

2.2 Features Summary

• RF Transceiver Features — Operating V oltage from 1.8V to 3.6V . — Programmable bit ra te up to 600kbps (FSK) — High Sensitivity: down to -120 dBm at 1.2 kbps — High Selectivity: 16-tap FIR Channel Filter Kinetis MKW01 Wireless MCU Core ARM Cortex-M0+

48 MHz

128 KB Flash

16 KB RAM

32 MHz

66 Byte

MKW01Z128 Advance Information, Rev. 5 Freescale Semiconductor 3 — Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image Frequency response — Low current: Rx = 16mA, 100nA register retention — Programmable Pout : -18 to +17 dBm in 1 dB steps — Constant RF performance over voltage range of chip — Fully integrated synthesizer with a resolution of 61 Hz — FSK, GFSK, MSK, GMSK and OOK modulations — Built-in Bit Synchronizer performing Clock recovery — Incoming Sync Word Recognition — Automatic RF Sense with ultra-fast AFC — Packet engine with CRC, AE S-128 encryption and 66-byte FIFO — Built-in temperature sensor and Low battery indicator — 32 MHz crystal oscillator clock source — Dedicated I/O’s for connection w ith an external 32 kHz crystal

• MCU Features System: — 48 MHz Max. Central Proce ssor Unit (CPU) frequency — 24 MHz Max. Bus frequency — Vectored Interrupt Controller (NVIC) with 32 core-vectored interrupts with 4 programmable interrupt priority levels — Asynchronous Wake-up Interrupt Controller (AWIC) — 4 channel Direct Memory Access (DMA) — DMA request multiplex — Non Maskable Interrupt (NMI) — COP Watchdog — Low leakage Wake-up Unit (LLWU) — Debug and Trace – 2-pin Serial Wire Debug (SWD) — 80-bit wide ID number Memory: — 128 KB P-Flash with 64 byte flash cache — 16 KB RAM Clocks: — External crystal osc illator or resonator: – 32 - 40 kHz low range, low power or full swing – 3 MHz - 32 MHz high range, low power or full swing — DC - 48 MHz external square wave input clock

MKW01Z128 Advance Information, Rev. 5

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— Internal clock references: – 31.25 kHz to 39.063 kHz oscillator with +/ – 1.5% max. deviation from 0 to +70C – 4 MHz oscillator with +/– 3% max. deviation across temperature – 1 kHz oscillator — Phase Locked Loop (PLL) with up to 100 MHz VCO — Frequency Locked Loop (FLL): – Low range: 20 - 25 MHz – Mid range: 40 - 48 MHz Analog: — Power Management Controller (PMC) with low voltage warning (LVW) and detect with selectable trip points. — 16-bit analog to digital converter – 11 single ended channels available – 2 status, control and results registers – DMA support — 1 High Speed Comparator (HSCMP) with inte rnal 6-bit digital to analog converters (DAC) — One 12-bit DAC with DMA support and 2 word data buffer Timers: — Six channel Timer/PWM (TPM) — Periodic interrupt timers — 16-bit low-power timer (LPTMR) can be configured to operate as a time counter or as a pulse counter, across all power modes, including the low-leakage modes — Real-time clock 32-bit timer Wired Communication Interface: — One Serial Peripheral Interface (SPI) available externally — Two Inter-Integrated Circuits (I 2C) with DMA support — Three Universal Asynchronous Receiver / Transmitter (UART) with DMA Support – UART0 supports sta ndard features plus:

• TxD pin can be configured as ps eudo open drain for 1-wire half-duplex
• x4 to x32 oversampling
• Functional in VLPS mode
• LIN slave operation – UART1 and UART2 support standard features Human Machine Interface (HMI) — General Purpose Input/O utput (GPIO) supporting:

MKW01Z128 Advance Information, Rev. 5 Freescale Semiconductor 5 – Default to disabled (no leakage) – 4 pins with 18 mA high current drive capability – Hysteresis and configurable pull up device on all input pins – Slew rate and drive stre ngth fixed on all output pins – Single cycle GPIO control via IOPORT — Touch Sensor Inputs (TSI) – 9-channel – Selectable single channel wakeup source available in all modes – DMA support — Pin Interrupt 1.8 V to 3.6 V operating voltage with on-chip voltage regulators Temperature range of –40C to 85C 60-pin LGA (8x8 mm) package

3 Software Solutions

Freescale will support the MKW01 platform with several software solutions:

• A radio utility GUI will be available that allows testing of various features and setting registers. A connectivity test firmware will allow a limited set of testing controlled with a terminal emulator on any computer.
• SMAC (Simple Media Access Cont roller) — This codebase provi des simple communication and test apps based on drivers/PHY utilities available as source code. This environment is useful for hardware and RF debug, hardware standards certification, and developing proprietary applications.
• Additional software will be avai lable through 3rd party providers.

4 Smart Radio Sub-1 GHz Wireless Node

The MKW01 brings together a transceiver chip and an MCU chip on a single substrate to provide a small footprint, cost-effective sub-1 GHz wireless node. The transceiver is controlled by the MCU through a dedicated SPI interface. The SPI bus interface and some status signals are connected in-package the substrate to eliminate the need for external connections. The SPI supports bit order swapping providing hardware support for bit endianess reducing processing overhead.

4.1 RF Transceiver

The transceiver (see Figure 2) is a single-chip integrated circuit ideally suited for today's high performance ISM band RF applications. Its advanced features set, including state of the art packet engine, greatly simplifies system design while the high level of integration reduces the external RF component bill of material (BOM) to a handful of passive de-coupling and matching components. It is intended for use as a high-performance, low-cost FSK, GFSK, MSK, GMSK, and OOK RF transceiver for robust, frequency agile, half-duplex bi-directional RF links.

6 Freescale Semiconductor

complies with both ETSI and FCC regulatory requirements. Figure 2. MKW01 Transceiver Block Diagram for low power consumption while offering high RF output power and channelized operation.

4.2 ARM ® 32-bit Cortex M0+ CPU

set the operational modes of the transceiver which include sleep, standby, and radio operational modes.

• Low power, battery-operated sta ndalone wireless node - a common example of this configuration would be a remote sensor monitor. The wireless node programmed for standalone operation, typically has a low active-mode duty cycle, and is designed for long battery life, i.e., lowest power.
• Communication channel to a higher level cont roller - in this example, the wireless node implements the lower levels of a communications stack and is subordinate to the primary controller. Typically the MKW01 is connected to the controller through a command channel implemented via a UART/SCI port or other serial communication port.

4.3 System Clock Configuration

• Pins 46 & 47 are provided to input a 32 or 30 MHz crystal for the transceiver reference clock source (required) as shown in Figure 3.
• The transceiver can be programmed to provide a programmable frequency clock output (DIO5 which alternates as CLKOUT, pin 54) that can be used as an external source to the CPU (see Figure 3 and Figure 4). As a result, a single crystal system clock solution is possible where the transceiver reference clock source. Routing CLKOUT to the MCU without dividing it is recommended, but it can be divided by 2, 4, 8, 16 and 32.
• The MCU provides a trimmable internal referen ce clock and also supports an external clock source. An optional on-chip frequency locked loop (FLL) can be used with either clock source to support a CPU clock as high as 48 MHz at 3.6 V .
• Pins 16 and 15 are available to provide an external 32.768 kHz external clock source for the MCU.

Figure 3. MKW01 Single Crystal System Clock Connection

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Figure 4. MKW01 Two Crystal System Clock Connection

5 MKW01 Pin Assignments and Connections

Figure 5 shows the MKW01 pinout. Figure 5. MKW01 Pinout (Top View)

10 Freescale Semiconductor

5.1 Pin Definitions

Table 1 details the MKW01 pinout and functionality. Table 1. Pin Function Description (Sheet 1 of 5)

1 VREFH Input MCU high reference voltage for ADC

2 VREFL Input MCU low reference voltage for ADC

3 VSSA Power Input MCU ADC Ground Connect to ground

4 VSS Power Input MCU Ground Connect to ground

5 PTE16/ADC0_DP1/ADCO_S

6 PTE17/ADC0_DM1/ADCO_S

7 PTE18/ADC0_DP2/ADC0_SE

0 MOSI / IIC0 Bus Data / SPI module 0

8 PTE19/ADC0_DM2/

9 PTE30/DAC0_OUT/

10 PTA0/SWD_CLK/TSI0_CH1/T

11 PTA3/SWD_DIO/TSI0_CH4/

12 PTA4/NMI_b/TSI0_CH5/

13 PTA2/TSI0_CH3/UART0_TX/

14 PTA1/TSI0_CH2/UART0_RX/

15 PTA18/EXTAL0/UART1_RX/

16 PTA19/XTAL0/UART1_TX/TP

1 Transmit / TPM module Clock In 1

17 PTB0/ADC0_SE8/TSI0_CH0/

18 PTB1/ADCO_SE9/TSI0_CH6/

19 VDD Power Input MCU VDD supply input Connect to system VDD

20 VSS Power Input MCU Ground Connect to ground

21 PTB2/ADC0_SE12/TSI0_CH7

22 PTB17/TSI0_CH10/SPI1_MIS

23 PTC4/LLWU_P8/SPI0_PCS0/

24 PTC1/ADC0_SE15/TSI0_CH1

25 PTC2/ADC0_SE11/TSI0_CH1

Table 1. Pin Function Description (Sheet 2 of 5)

12 Freescale Semiconductor

26 PTC3/LLWU_P7/UART1_RX/

27 PTD4/LLWU_P14/SPI1_PCS0

28 PTD5/ADC0_SE6b/SPI1_SC

29 PTD6/ADC0_SE7b/LLWU_P1

30 NC No Connect

31 PTD7/SPI0_MISO/UART0_TX

32 PTE0/SPI1_MISO/UART1_TX

33 PTA20/RESETB Digital

34 PTE1 / SPI1_MOSI /

35 VBAT2 (RF) Power Input Transceiver VDD Connect to system VDD

36 GND/SCAN (RF) Power Input Transceiver Ground Connect to ground

37 RXTX (RF) Digital

38 GND_PA2 (RF) Power Input Transceiver RF Ground Connect to ground

39 RFIO (RF) RF Input /

40 GND_PA1 (RF) Power Input Transceiver RF Ground Connect to ground

41 PA_BOOST (RF) RF Output Transceiver Optional High-Power PA

42 VR_PA (RF) Power

43 VBAT1 (RF) Power Input Transceiver VDD for RF circuitry Connect to system VDD

Table 1. Pin Function Description (Sheet 3 of 5)

44 VR_ANA (RF) Power

45 VR_DIG (RF) Power

46 XTA (RF) Xtal Osc Transceiver crystal reference oscillator Connect to 32 MHz

47 XTB (RF) Xtal Osc Transceiver crystal reference oscillator Connect to 32 MHz

48 RESET (RF) Digital Input Transceiver hardware reset input Typically driven from

49 DIO0/PTE2/SPI1_SCK Digital

50 DIO1/PTE3/SPI1_MISO/SPI1

51 DIO2 Digital

52 DIO3 Digital

53 DIO4 Digital

54 DIO5/CLKOUT Digital

55 VDD Power Input MCU VDD supply Connect to VDD supply

56 VDDAD Power Input MCU Analog supply Connect to Analog

57 MISO/PTC7/SPI0_MISO/SPI0

• MCU IO and Transceiver IO connected in-package
• MCU IO must be configured for this connection

58 NSS/PTD0/SPI0_PCS0 Digital

• MCU IO and Transceiver IO connected in-package
• MCU IO must be configured for this connection

59 SCK/PTC5/SPI0_SCK Digital

• MCU IO and Transceiver IO connected in-package
• MCU IO must be configured for this connection

Table 1. Pin Function Description (Sheet 4 of 5)

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5.2 Internal Functional Interconnects

are brought out to external pads.

• As shown in Table 2, the MCU SPI Port pin selection must be configured by software.
• The transceiver DIO pins must be programmed to provide desired status.
• Enhanced performance can be achie ved by additionally routing some DIO pins externally to other GPIO pins.

5.3 External Functional Interconnects

60 MOSI/PTC6/SPI0_MOSI/

• MCU IO and Transceiver IO connected in-package
• MCU IO must be configured for this connection FLAG VSS Power input External package flag. Common VSS Connect to ground. 1 Refer to ADD Table 1-3 for additional pin-out information on default and alternate setting selections.

Table 2. MKW01 Internal Functional Interconnects

49 DIO0/PTE2/SPI1_

50 DIO1/PTE3/SPI1_

57 MISO/PTC7/SPI0_

58 NSS/PTD0/SPI0_

59 SCK/PTC5/SPI0_

60 MOSI/PTC6/SPI0_

Table 1. Pin Function Description (Sheet 5 of 5)

MKW01Z128 Advance Information, Rev. 5 Freescale Semiconductor 15 1. Freescale recommends driving/controlling the transceiver reset from an MCU GPIO - This allows overriding control of the transceiver from the system application. 2. The other DIO2-DIO4 status a nd RXTX signals can prove useful for monitoring the transceiver operation - the DIO2-DIO4 signals must be programmed to provide operational status. All signals must be connected externally to appropriate MCU GPIO for this function.

6 System and Power Management

The MKW01 consists of an independent transceiver and MCU. The MCU controls the transceiver through programming of the SPI Port, and sets its operational mode through this control channel. Total current draw for the MKW01 is dependent on the operation mode of both devices where different modes allow for different levels of power-down. Some additional features supported are:

• Transceiver Sleep with MCU se t at the lowest power state.
• The transceiver mode selection being i ndependent of the MCU’s mode selection.
• The transceiver uses/powers-up the tr ansmitter or receiver only as required.
• MCU peripheral control clock gating being di sabled on a module-by-module basis to provide lowest power.
• RTC can be used as wake-up timer.
• LLWU (Low Leakage Wake-up Unit) available.

6.1 MCU Power Modes

The MCU has 9 different modes of operation to allow the user to optimize power consumption for the level of functionality needed. Depending on the STOP requirements of the user application, a variety of STOP modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. Table 3 outlines the various available power modes of MCU operation. For each RUN mode there is a corresponding WAIT and STOP mode. WAIT modes are similiar to ARM sleep modes. STOP modes (VLPS, STOP) are similiar to ARM sleep deep mode. The very low power run (VLPR) operating mode can greatly reduce runtime power when the maximum bus frequency is not required to handle application needs. The 3 primary modes of operation are RUN, WAIT and STOP. The WFI instruction invokes both WAIT and STOP modes for the MCU. The primary modes are augmented in a number of ways to provide lower power based on application needs.

16 Freescale Semiconductor

Table 3. MCU power modes onchip voltage regulator is on. peripherals continue to be clocked. only enough power to run the chip at a reduced frequency. external clock or the crystal oscillator providing the clock source. power; NVIC remains sensitive to interrupts (FCLK = ON). only enough power to run the chip at a reduced frequency. are stopped, but OSC, LPTMR, RTC, CMP, TSI can be used. stop mode on an LLS recovery. All SRAM is operating (content retained and I/O states held).

All of SRAM_U and SRAM_L are powered off. 1 Resumes normal run mode operation by executing the LLWU interrupt service routine. 2 Follows the reset flow with the LLWU interrupt flag set for the NVIC.

18 Freescale Semiconductor

6.1.1 Power mode transitions

Figure 6. Power mode state transition diagram 6.2 Transceiver modes of operation. be selected directly by disabling the automatic sequencer.

• Sleep - provides lowest power consumpt ion and is the full power down state.
• Idle - provides very low standby power consumpt ion and has the main voltage regulator and the RC oscillator enabled.
• Standby - similar to Idle with low standby power consumption but has the main voltage regulator and the crystal oscillator enabled.
• FS (Frequency synthesizer) - the fre quency synthesizer is alive to shorten startup time to transmit or receive states.
• Transmit - transmitter is active.
• Receive - receiver is active.

6.3 System Protection

• Standard COP Watchdog reset with opt ion to run from dedicated 1 kHz internal clock source or bus clock. The COP watchdog is intended to force a system reset when the application software fails to execute as expected.
• LVD protection with reset or in terrupt; selectable trip points.
• HardFault exception on attempts to execute undefi ned instructions or access to undefined memory space.
• LOCKUP reset resource from core.
• Flash protection

Table 4. Basic Transceiver modes

20 Freescale Semiconductor

7 Development Environment

• Two-wire Serial Wire Debug (SWD) interface Table 5 presents a brief description of the serial wire debug description. NOTE Electrical specifications for the SWD lines can be found in the appendix.

8 System Electrical Specification

DC characteristics, and AC characteristics for the modem, and the MCU.

8.1 LGA Package Maximum Ratings

damage to the device. For functional operating conditions, refer to the remaining tables in this section. pull-up resistor associated with the pin is enabled. Table 6 shows the maximum ratings for the 60 Pin LGA package. Table 5. Debug Components Description Debug mode. This pin is pulled down internally. debug tool for communication and devive control. This pin is pulled up internally.

8.2 ESD Protection and Latch-Up Immunity

CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. of static without suffering any permanent damage. model (HBM), the machine model (MM) and the charge device model (CDM). All latchup testing is in conformity with the JESD78 IC Latch-Up Test. Table 6. LGA Package Maximum Ratings Note: Maximum Ratings are those values beyond which damage to the device may occur. or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV. RF input/output pins have no ESD protection. Table 7. ESD and Latch-up Test Conditions

1 This number represents a minimum number for both positive pulse(s) and negative pulse(s)

22 Freescale Semiconductor

8.3 Transceiver Electrical Characteristics

terminated in a matched 50 Ohm impedance, unless otherwise specified.

8.3.1 Transceiver Recommen ded Operating Conditions

Table 8. ESD and Latch-Up Protection Characteristics

1 Parameter is achieved by design characterization on a small sample size from typical devices

under typical conditions unless otherwise noted.

1 Human body model (HBM) V HBM 2000 — V

2 Machine model (MM) V MM 200 — V

3 Charge device model (CDM) V CDM 500 — V

4 Latch-up current at T A = 85CI LAT 100 — mA

Table 9. Recommended Operating Conditions

8.3.2 Transceiver Power Consumption

8.3.3 Transceiver Frequency Synthesis

Table 10. Power Supply Current Table 11. Frequency Synthesizer Specification

1 MHz step

5 MHz step

7 MHz step

12 MHz step

20 MHz step

25 MHz step

24 Freescale Semiconductor

8.3.4 Receiver

IIP2, IIP3 and AMR tests is set 3 dB above the nominal sensitivity level. Table 12. Receiver Specification

8.3.5 Transmitter

9 Typical Applications Circuit

1. The two metal flags on the package bottom are i ndependent (unconnected), and as a result, both

must be connected to ground.

1. The topology of the external RF matching components is consistent across various frequency

bandwidths. Only the component values differ as determined by the desired frequency range.

1. Freescale recommends using a single crystal design (as shown) to minimize systems costs - the

ware control of the transceiver. Figure 7 shows GPIO PTE3 (preferred), but any GPIO can be used.

1 Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver

Table 13. Transmitter Specidication

MKW01Z128 Advance Information, Rev. 5

26 Freescale Semiconductor

1. The MKW01 provides in-package connection for the DIO1-DIO0 status to the MCU. External connection of DIO4-DIO2 status to MCU GPIO may be useful or required to implement a wireless node communication algorithm. Enhanced performance can be achieved by routing DIO1 and DIO0 externally to GPIO pins PTC4 and PTC3. 5. The transceiver reference oscillator uses the specified 32 MHz 1 crystal (pins XTA and XTB). 6. A debug port connector will beprovided for programming the MKW01 MCU FLASH and debugging code via the SWD interface. Two common RF wiring options are shown in Figure 7: 1. Bi-directional single port operation - this mode uses the bi-directional RF port pin of the MKW01 designated as RFIO. The device transmits and receives through this single port. — Typical +13 dBm TX output power — An inductor acts to provide DC pow er to the transmitter’s output amplifier while also acting as an AC signal block. — A circuit topology consis ting of inductors and capacitors will provide: – Impedance matching between the RFIO port and the antenna – Low pass filtering for the transmit output pa th — when fully populat ed can implement an elliptic-function low pass filter. NOTE

• The topology for the RF matching ne twork can be used over the various bands of interest with changes in component values
• Not all indicated components are used at all frequencies
• R e f e r t o MKW01 Sub 1 GHz Low Power Transceiver plus Microcontroller Reference Manual (MKW01xxRM.pdf) for additional information 2. Dual port operation with external amplification - this mode uses the RFIO port pin of the MKW01 typically as the RX input and the auxiliary port PA_BOOST as the TX output. An external PA can optionally be inserted into the transmit path and an external antenna switch is also required. — The PA_BOOST has typical +17 dBm output power - this is +4 dBm higher than the RFIO and helps achieve higher power at the PA output — The PA_BOOST transmit path has a similar filter matching network discussed in the single-port to do low pass filtering and impedance match. The above note about components values also applies. — With separate transmit and rece ive paths, an antenna switch is required - the RXTX signal or another programmed GPIO can be used to switch paths depending on radio operation. — The receive side matching netw ork can be simplified as no low pass filtering or harmonic trapping is required as with the transmit and single port networks 1. Or 30 MHz, in some cases.

Figure 7. MKW01 Application Circuit Options

Supports the following: MKW01Z128

Features

• Operating Characteristics – Voltage range: 1.8 to 3.6 V – Flash write voltage range: 1.8 to 3.6 V – Temperature range (ambient): -40 to 85°C
• Performance – Up to 48 MHz ARM® Cortex-M0+ core
• Memories and memory interfaces – 128 KB program flash memory – 16 KB RAM
• Clocks – 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator – Multi-purpose clock source
• System peripherals – Nine low-power modes to provide power optimization based on application requirements – 4-channel DMA controller, supporting up to 63 request sources – COP Software watchdog – Low-leakage wakeup unit – SWD interface and Micro Trace buffer – Bit Manipulation Engine (BME)
• Security and integrity modules – 80-bit unique identification (ID) number per chip
• Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
• Analog modules – 16-bit SAR ADC – 12-bit DAC – Analog comparator (CMP) containing a 6-bit DAC and programmable reference input
• Timers – Six channel Timer/PWM (TPM) – Two 2-channel Timer/PWM (TPM) – Periodic interrupt timers – 16-bit low-power timer (LPTMR) – Real-time clock
• Communication interfaces – One 16-bit serial peripheral communcation (SPI) module available externally – Two I2C modules – One low power UART module – Two UART modules Freescale Semiconductor Document Number: MKW01Z128 Data Sheet: Advance Information Rev. 5, 3/2014 This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2013, 2014 Freescale Semiconductor, Inc.

MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 2 Freescale Semiconductor, Inc.

1 General

1.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
• V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
• Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

1.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements Table continues on the next page... MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Table 2. V DD supply LVD and POR operating requirements (continued)

• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage

1.3 Voltage and current operating behaviors

Table 3. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -5 mA
• 1.8 V ≤ V DD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 VDD – 0.5 V V 1, 2 VOH Output high voltage — High drive pad (except RESET_b)
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -20 mA
• 1.8 V ≤ V DD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 VDD – 0.5 V V 1 , 2 IOHT Output high current total for all ports — 100 mA Table continues on the next page... General MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 4 Freescale Semiconductor, Inc.

Table 3. Voltage and current operating behaviors (continued)

• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
• 1.8 V ≤ V DD ≤ 2.7 V, IOL = 2.5 mA 0.5 0.5 V V VOL Output low voltage — High drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA
• 1.8 V ≤ V DD ≤ 2.7 V, IOL = 10 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 65 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 4 1. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 2. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS

1.4 Power mode transition operating behaviors

• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 4. Power mode transition operating behaviors Table continues on the next page... MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Table 4. Power mode transition operating behaviors (continued)

• VLLS0 → RUN 106 120 μs
• VLLS1 → RUN 105 117 μs
• VLLS3 → RUN μs
• LLS → RUN 4.5 5.0 μs
• VLPS → RUN 4.5 5.0 μs
• STOP → RUN 4.5 5.0 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11).

1.5 Power consumption operating behaviors

Table 5. Power consumption operating behaviors

• at 3.0 V 6.1 mA IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash
• at 3.0 V 3.8 5.9 mA IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash
• at 3.0 V 4.6 6.1 mA Table continues on the next page... General MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 6 Freescale Semiconductor, Inc.

Table 5. Power consumption operating behaviors (continued)

• at 3.0 V
• at 25 °C
• at 70 °C
• at 125 °C 6.0 6.2 6.3 6.5 6.8 7.1 mA mA mA 3, 4 IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
• at 3.0 V — 2.7 5.7 mA IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
• at 3.0 V — 2.1 5.5 mA IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus
• at 3.0 V — 2.2 4.1 mA IDD_VLPRCO _CM Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, LPTMR running with 4 MHz internal reference clock, CoreMark benchmark code executing from flash
• at 3.0 V — 732 — μA IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code of while(1) loop executing from flash
• at 3.0 V — 161 367 μA IDD_VLPR Very-low-power run mode current - 4 MHz core /

0.8 MHz bus and flash, all peripheral clocks

• at 3.0 V — 185 372 μA IDD_VLPR Very-low-power run mode current - 4 MHz core /
• at 3.0 V — 256 420 μA 4, 6 IDD_VLPW Very-low-power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
• at 3.0 V — 110 355 μA 6 Table continues on the next page... General MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. Freescale Semiconductor, Inc. 7

MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 8 Freescale Semiconductor, Inc.

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

1. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for
2. MCG configured for FEI mode.
3. Incremental current consumption from peripheral activity is not included.
4. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized for
5. MCG configured for BLPI mode.

Table 6. Low power mode peripheral adders — typical value IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. with the 32 kHz IRC enabled. IEREFSTEN4MHz External 4 MHz crystal clock adder. modes with the crystal enabled. kHz external crystal) power consumption. clock source power consumption. Table continues on the next page... MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Table 6. Low power mode peripheral adders — typical value (continued) compare generating 100 Hz clock signal. placing the device in STOP or VLPS mode.

1.5.1 Diagram: Typical IDD_RUN operating behavior

• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA General MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 10 Freescale Semiconductor, Inc.

Figure 1. Run mode supply current vs. core frequency MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Figure 2. VLPR mode current vs. core frequency

1.6 Designing with radiated emissions in mind

1. Perform a keyword search for “EMC design.”

1.7 Capacitance attributes

Table 7. Capacitance attributes MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 12 Freescale Semiconductor, Inc.

1.8 Switching specifications

1.8.1 Device clock specifications

Table 8. Device clock specifications

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

1.8.2 General switching specifications

Table 9. General switching specifications Table continues on the next page... MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Table 9. General switching specifications (continued)

1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.

2 Peripheral operating requirements and behaviors

2.1 Core modules

2.1.1 SWD electricals

Table 10. SWD full voltage range electricals

• Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
• Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)

Figure 3. Serial wire clock input timing MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 14 Freescale Semiconductor, Inc.

Figure 4. Serial wire data timing

2.2 System modules

There are no specifications necessary for the device's system modules.

2.3 Clock modules

2.3.1 MCG specifications

Table 11. MCG specifications Table continues on the next page... MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Table 11. MCG specifications (continued)

• f VCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
• PLL at 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) — 1060 — µA 9 Ipll PLL operating current
• PLL at 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) — 600 — µA 9 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter (RMS)
• f vco = 48 MHz
• f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
• f vco = 48 MHz
• f vco = 100 MHz 1350 600 ps ps Table continues on the next page... Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 16 Freescale Semiconductor, Inc.

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation

(Δfdco_t) over voltage and temperature must be considered.

1. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
2. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
3. This specification is based on standard deviation (RMS) of period or frequency.
4. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

1. Excludes any oscillator currents that are also consuming power while PLL is in operation.
2. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

1. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

2.3.2 Oscillator electrical specifications

2.3.2.1 Oscillator DC electrical specifications

Table 12. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA Table continues on the next page... Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. Freescale Semiconductor, Inc. 17

Table 12. Oscillator DC electrical specifications (continued)

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 18 Freescale Semiconductor, Inc.

2.3.2.2 Oscillator frequency specifications

Table 13. Oscillator frequency specifications

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

2.4 Memories and memory interfaces

2.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

2.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Table 14. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

2.4.1.2 Flash timing specifications — commands

Table 15. Flash command timing specifications

1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.

2.4.1.3 Flash high voltage current behaviors

Table 16. Flash high voltage current behaviors

2.4.1.4 Reliability specifications

Table 17. NVM reliability specifications Table continues on the next page... MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 20 Freescale Semiconductor, Inc.

Table 17. NVM reliability specifications (continued)

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.

2.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

2.6 Analog

2.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 18. 16-bit ADC operating conditions

1.13 VDDA VDDA V 3

• All other modes VREFL VREFL 31/32 * VREFH VREFH V CADIN Input capacitance • 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF Table continues on the next page... Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. Freescale Semiconductor, Inc. 21

Table 18. 16-bit ADC operating conditions (continued)

1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

1. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
2. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

time constant should be kept to < 1 ns.

1. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 22 Freescale Semiconductor, Inc.

Figure 5. ADC input impedance equivalency diagram Table 19. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
• 12-bit modes
• <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. Freescale Semiconductor, Inc. 23

Table 19. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
• 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 24 Freescale Semiconductor, Inc.

2.6.2 CMP and 6-bit DAC electrical specifications

Table 20. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 26 Freescale Semiconductor, Inc.

Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 21. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 28 Freescale Semiconductor, Inc.

Table 22. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. Freescale Semiconductor, Inc. 29

Figure 10. Typical INL error vs. digital code MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 30 Freescale Semiconductor, Inc.

Figure 11. Offset at half scale vs. temperature

2.7 Timers

See General switching specifications.

2.8 Communication interfaces

2.8.1 SPI switching specifications

communicating with slower peripheral devices. MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 23. SPI master mode timing on slew rate disabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).

Table 24. SPI master mode timing on slew rate enabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).

MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 32 Freescale Semiconductor, Inc.

Table 25. SPI slave mode timing on slew rate disabled pads (continued)

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

Table 26. SPI slave mode timing on slew rate enabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 34 Freescale Semiconductor, Inc.

Figure 14. SPI slave mode timing (CPHA = 0) Figure 15. SPI slave mode timing (CPHA = 1)

2.8.2 Inter-Integrated Circuit Interface (I2C) timing

Table 27. I 2C timing Table continues on the next page... MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

Table 27. I 2C timing (continued) Hold time (repeated) START condition.

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must

= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

1. Cb = total capacitance of the one bus line in pF.

Figure 16. Timing definition for fast and standard mode devices on the I2C bus

2.8.3 UART

See General switching specifications. MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014. 36 Freescale Semiconductor, Inc.

2.9 Human-machine interfaces (HMI)

2.9.1 TSI electrical specifications

Table 28. TSI electrical specifications MKW01 MCU Section Data Sheet Data Sheet, Rev. 5, 3/2014.

28 Freescale Semiconductor

10 Mechanical Drawings

Figure 8. Mechanical Drawing (1 of 2)

Figure 9. Mechanical Drawing (2 of 2)

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