MKL82Z128VLH7

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Technical content

Kinetis KL82 Microcontroller

72 MHz ARM® Cortex®-M0+ with 128 KB Flash and 96 KB

The KL82 MCU family's high performance, encryption features and ultra-low power capabilities extend its reach beyond traditional mPOS pin pads and terminals into more power- restricted payment applications, such as smartphone and tablet attach readers, as well as those embedded in wearable technology. The product offers:

• Hardware asymmetric cryptography – high-speed, code- and power-efficient data authentication with support for latest encryption protocols
• EMV®-compatible with ISO7816-3 SIM interfaces – architected for EMV compliance and supported by an EMV Level 1 software stack
• QSPI interface to expand program memory
• Sleep mode power consumption from 2.5 µA with the SRAM content retained and RTC enabled
• Crystal-less USB OTG controller, 16-bit ADC and multiple serial communication interfaces can all function autonomously in low-power modes with minimal CPU intervention
• FlexIO to support any standard and customized serial peripheral emulation Core Processor
• 72 MHz ARM® Cortex®-M0+ core ( up to 96 MHz for high- speed run) Memories
• 128 KB program flash memory
• 96 KB SRAM
• 32 KB ROM with built-in boot loader
• 32 B backup register
• QSPI to expand program code in external high-speed serial NOR flash memory System
• 8-channel asynchronous enhanced DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin serial wire debug (SWD) programming and debugging interface
• Micro trace buffer
• Bit manipulation engine
• Interrupt controller Peripherals
• USB full-speed 2.0 OTG controller supporting crystal-less operation and keeping connection alive under ultra-low power
• Three low-power UART modules supporting asynchronous operation in low-power modes
• Two I2C modules supporting up to 1 Mbps
• Two 16-bit SPI modules supporting up to 24Mbps
• One FlexIO module supporting emulation of additional UART, SPI, I2C, I2S, PWM and other serial modules, etc. up to 32 channels
• One 16-bit ADC module with high accurate internal voltage reference and up to 16 channels
• High-speed analog comparator containing a 6- bit DAC for programmable reference input
• One 12-bit DAC module
• Two EMVSIM modules supporting EMV L1 compatible interface
• Touch sensing interface up to 16 channels MKL82Z128Vxx7(R) 121 & 64 MAPBGA (MC&MP) 8x8x1.43 mm Pitch 0.65 mm 5x5x1.23 mm Pitch 0.5 mm 100 & 80 & 64 LQFP (LL&LK&LH) 14x14 x1.7 mm Pitch 0.5mm 12x12x1.6 mm Pitch 0.5 mm 10x10x1.6 mm Pitch 0.5 mm NXP Semiconductors Document Number: KL82P121M72SF0 Data Sheet: Technical Data Rev. 4, 12/2016 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Memory protection unit
• SRAM bit-banding Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference clock for high-speed run
• 4 MHz high accuracy (up to 2%) internal reference clock for low-speed run
• 32 kHz internal reference clock
• 1 kHz internal reference clock
• 32–40 kHz and 3–32 MHz crystal oscillator
• PLL/FLL Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• Two low-power timers
• 4-channel periodic interrupt timer
• Independent real time clock Security
• 128-bit unique identification number per chip
• Advanced flash security and access control
• Hardware CRC module
• Low-power trusted crypto engine supporting AES128/256, DES, 3DES, SHA256, RSA and ECC, with hardware DPA
• True random number generator I/O
• Up to 85 General-purpose input/output pins (GPIO) Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C Low Power
• Down to 125 µA/MHz in Run mode
• Down to 272 nA in Stop mode (RAM and RTC retained)
• Six flexible static modes Packages
• 121 MAPBGA 8mm x 8mm, 0.65mm pitch, 1.43mm max thickness
• 80 LQFP 12mm x 12mm, 0.5mm pitch, 1.6mm max thickness
• 100 LQFP 14mm x 14mm, 0.5mm pitch, 1.7mm max thickness (Package Your Way)
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm max thickness (Package Your Way)
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm max thickness (Package Your Way) NOTE The 100-, 64-pin LQFP and 64-pin MAPBGA packages supporting MKL82Z128VLL7, MKL82Z128VLH7 and MKL82Z128VMP7 part numbers for this product are not yet available. However, these packages are included in Package Your Way program for Kinetis MCUs. Visit nxp.com/KPYW for more details. Related resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL82P121M72SF0RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KL82P121M72SF01 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. xN51R2 Package drawing Package dimensions are provided in package drawings. MAPBGA 121-pin: 98ASA00423D MAPBGA 64-pin: 98ASA00420D LQFP 100-pin: 98ASS23308W LQFP 80-pin: 98ASS23174W LQFP 64-pin: 98ASS23234W 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the "x" replaced by the revision of the device you are using. Kinetis KL82 Microcontroller, Rev. 4, 12/2016 3 NXP Semiconductors

5.1.4 Relationship between ratings and operating

5.1.5 Guidelines for ratings and operating

4 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

1 Ordering information

The following chips are available for ordering. Table 1. Ordering information

1. INT: interrupt pin numbers; HD: high drive pin numbers

nxp.com/KPYW for more details.

2 Overview

Ordering information

Kinetis KL82 Microcontroller, Rev. 4, 12/2016 5 NXP Semiconductors

32 KB ROM

Figure 1. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure.

2.1 System features

The following sections describe the high-level system features.

2.1.1 ARM Cortex-M0+ core

The enhanced ARM Cortex M0+ is the member of the Cortex-M series of processors targeting microcontroller cores focused on very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also has hardware debug functionality including support for simple program trace capability. The processor supports the ARMv6-M instruction set (Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward compatible with other Cortex-M profile processors.

2.1.2 NVIC

The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It also differs in number of interrupt sources and supports 32 interrupt vectors. The Cortex-M family uses a number of methods to improve interrupt latency to up to 15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and VLPW modes.

2.1.3 AWIC

The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous wake-up events in Stop mode and signal to clock control logic to resume system clocking. After clock restarts, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. The AWIC can be used to wake MCU core from Stop and VLPS modes. Wake-up sources are listed as below: Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 7 NXP Semiconductors

Table 2. AWIC Partial Stop, Stop and VLPS wake-up sources

2.1.4 Memory

• 96 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.
• The non-volatile memory is divided into two arrays
• 128 KB of embedded program memory
• 32 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI interfaces) The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 1 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. The security circuitry prevents unauthorized access to RAM or flash contents from debug port.
• System register file Overview 8 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

This device contains a 32-byte register file that is powered in all power modes.

2.1.5 Reset and boot

The following table lists all the reset sources supported by this device. Table 3. Reset source

1. The VBAT POR asserts on a VBAT POR reset source. It affects only the modules withinthe VBAT power domain: RTC

and VBAT Register File. These modules are notaffected by the other reset types.

1. Only if RESET is used to wake from VLLS mode.
2. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
3. Except RCM_RPFC, RCM_RPFW, RCM_FM

• internal flash
• ROM The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows the user to customize the operation of the MCU at boot time. The register contains read- only bits that are loaded from the NVM's option byte in the flash configuration field. Below is boot flow chart for this device. 00 = Internal Flash 01 = Reserved 10 = ROM -> QSPI Y es 11 = ROM -> QSPI No POWER ON [BOOTSRC_SEL] = 0x Chip Flash? Boot from On- QSPI ? Configure RESET module BOOT ROM module present? QSPI Configure and boot from internal flash. Power On Reset(POR) Reset to Processor Load BCA Image Download with timeout [BOOTSRC_SEL] =1x Y es No Configure QSPI No Config Failure Y es No Y es Jump to PC in vector table FOPT [BOOTSRC_SEL]: [BOOTSRC_SEL] =11 [BOOTSRC_SEL] =10 detect mode or boot pin Peripheral asserted? (Boot Configuration Area) BOOTPIN_OPT=0? BOOTCFG Pin assert? Y es No Y es No

Figure 2. Boot Flow For Devices with QSPI address, otherwise, it remaps to flash address.

If booting from ROM, the device executes in boot loader mode or proceeds with a secondary boot to a QSPI device connected to QSPI0.

2.1.6 Clock options

This chip provides a wide range of sources to generate the internal clocks. These sources include internal resistor capacitor (IRC) oscillators, external oscillators, external clock sources, ceramic resonators, phase-locked loop (PLL) and frequency- locked loop (FLL). These sources can be configured to provide the required performance and optimize the power consumption. The IRC oscillators include the 48 MHz internal resister capacitor (IRC48M) oscillator, the 4 MHz internal resister capacitor (4 MHz IRC) oscillator, the 32 kHz internal resister capacitor (32 kHz IRC) oscillator, and the low power oscillator (LPO). The 48 MHz internal resister capacitor (IRC48M) oscillator generates a 48 MHz clock and synchronizes with the USB clock in full speed mode to achieve the required accuracy. The 4 MHz internal resister capacitor (4 MHz IRC) oscillator generates a 4 MHz clock. It can serve as the low power, low speed system clock under very low power run (VLPR) mode or very low power wait (VLPW) mode. It can also be provided as clock source for other on-chip modules. The 4 MHz IRC cannot be used in any VLLS modes. The 32 kHz internal resister capacitor (32 kHz IRC) oscillator generates a 32 kHz clock. It can be used as FLL internal reference clock or can be provided as low power clock source to other on-chip modules. The 32 kHz IRC cannot be used in any VLLS modes. The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode. The system oscillator supports low frequency crystals (32 kHz to 40 kHz), high frequency crystals (1 MHz to 32 MHz), and ceramic resonators (1 MHz to 32 MHz). An external clock source, DC to 48 MHz, can be used as the system clock through the EXTAL0 pin. The external oscillator also supports a low speed external clock (32.768 kHz) on the RTC_CLKIN pin for use with the RTC. The frequency-locked loop (FLL) can generate clock up to four programmable different frequency ranges (20–25 MHz, 40–50 MHz, 60–75 MHz or 80–100 MHz) with low speed (31.25–39.0625 kHz) internal or external reference clock. The FLL can be used as the system clock or clock source for other on-chip modules. Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 11 NXP Semiconductors

clock or clock source for other on-chip modules. For more details on the clock operations and configurations, see Reference Manual.

4 MHz IRC

Note: See subsequent sections for details on where these clocks are used. Figure 3. Clocking diagram during operation in various operational modes.

The following table summarizes the clocks associated with each module. Table 4. Module clocks Table continues on the next page...

Table 4. Module clocks (continued)

2.1.7 Security

flash information via ROM boot loader commands. factory and loaded to SIM register after power-on reset.

2.1.8 Power management

The Power Management Controller (PMC) expands upon ARM’s operational modes of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can be used to optimize current consumption for a wide range of applications. The WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current configuration. For more information on ARM’s operational modes, See the ARM® Cortex User Guide. The PMC provides High Speed Run (HSRUN), Run (Run), and Very Low Power Run (VLPR) configurations in ARM’s Run operation mode. In these modes, the MCU core is active and can access all peripherals. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The configuration that matches the power versus performance requirements of the application can be selected. The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive, all of the peripherals can be enabled and operate as programmed. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop (LLS), and Very Low Leakage Stop (VLLS) configurations in ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the peripherals are disabled. Depending on the requirements of the application, different portions of the analog, logic, and memory can be retained or disabled to conserve power. The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are used to wake up the MCU from low power states. The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU core from STOP and VLPS modes. The LLWU is used to wake up the MCU core from LLS and VLLSx modes. For additional information regarding operational modes, power management, the NVIC, AWIC, or the LLWU, please refer to the Reference Manual. The following table provides information about the state of the peripherals in the various operational modes and the modules that can wake MCU from low power modes. Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 15 NXP Semiconductors

Table 6. Peripherals states in different operational modes Run In Run mode, all device modules are operational. except the Low Voltage Detect (LVD) monitor, which is disabled. core is placed into Sleep mode. Deep sleep Stop In Stop mode, most peripheral clocks are disabled and placed in a static state. but the AWIC can be used to wake up from an interrupt. are retained. The CMP (low speed), LLWU, LPTMR, and RTC are operational. drive their previous values. RTC are operational in all VLLS modes. and VREF are not operational but continue driving. not operational but continue driving. POR detection circuit can be enabled or disabled.

2.1.9 LLWU

continues to detect wake-up events until the user has acknowledged the wake-up event.

Table 7. Wakeup sources for LLWU inputs Table continues on the next page...

Table 7. Wakeup sources for LLWU inputs (continued)

1. A wakeup source of LLWU, USB0_DP or USB0_DM is available only when the chip is in USB host mode.
2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU_ME[WUMEn] (n=0-7) bit enables the

internal module flag a wakeup inputs. After wakeup, the flags are cleared based on the peripheral clearing mechanism.

2.1.10 Debug controller

breakpoints and 2 watchpoints. simple execution trace capability for the Cortex-M0+ processor.

2.1.11 INTMUX

• Supports 4 multiplex channels
• Each channel receives 32 interrupt sources and has one interrupt output
• Each interrupt source can be enabled or disabled
• Each channel supports logic AND or logic OR of all enabled interrupt sources Overview 18 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

2.1.12 Watch dog

The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. The WDOG has the following features:

• Clock source input independent from CPU/bus clock. Choice between low-power oscillator (LPO) and external system clock.
• Unlock sequence for allowing updates to write-once WDOG control/configuration bits.
• All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked.
• Programmable time-out period specified in terms of number of WDOG clock cycles.
• Ability to test WDOG timer and reset with a flag indicating watchdog test.
• Windowed refresh option.
• Robust refresh mechanism.
• Count of WDOG resets as they occur.
• Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles.

2.2 Peripheral features

The following sections describe the features of each peripherals of the chip.

2.2.1 BME

The Bit Manipulation Engine (BME) provides hardware support for atomic read- modify-write memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for bit-oriented operations to peripheral registers. The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit, bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized data type. Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 19 NXP Semiconductors

2.2.2 eDMA and DMAMUX The eDMA controller module enables fast transfers of data, which provides an efficient way to move blocks of data with minimal processor interaction. The eDMA controller in this device implements eight channels which can be routed from up to 63 DMA request sources through DMA MUX module. Some of the peripheral request sources have asynchronous eDMA capability which can be used to wake MCU from Stop mode. The peripherals which have such capability include FlexIO, LPUART0, LPUART1, LPUART2, TPM0, TPM1, TPM2, PORTA-PORTE, ADC0, and CMP0. The DMA channel 0 t0 3 can be periodically triggered by PIT via DMA MUX. Main features are listed below:

• Dual-address transfers via 32-bit master connection to the system bus and data transfers in 8-, 16-, or 32-bit blocks
• 8-channel implementation that performs complex data transfers with minimal intervention from a host processor
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
• Provide the selectable channel activation methods.
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• Programmable support for scatter/gather DMA processing
• Support for complex data structures

2.2.3 TPM

This device contains three low power TPM modules (TPM). All TPM modules are functional in Stop/VLPS mode if the clock source is enabled. The TPM features include:

• TPM clock mode is selectable from external clock input or internal clock source, HIRC48M clock, external crystal input clock, MCGIRCLK, MCGPLLCLK, or MCGFLLCLK.
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare, edge- aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter overflow Overview 20 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

• Support selectable trigger input to optionally reset or cause the counter to start or stop incrementing
• Support the generation of hardware triggers when the counter overflows and per channel

2.2.4 ADC

this device contains one ADC module. This ADC module supports hardware triggers from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features:

• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16- bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-Calibration mode

2.2.5 VREF

The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically) trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage to external devices or used internally as a reference to analog peripherals such as the ADC, DAC or CMP. The VREF supports the following programmable buffer modes: Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 21 NXP Semiconductors

• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled A 100 nF capacitor must always be connected between VERF output (VREFO) pin and VSSA if the VREF is used. This capacitor must be as close to VREFO pin as possible.

2.2.6 CMP

The device contains one high-speed comparator and two 8-input multiplexers for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. The CMP includes one 6-bit DAC, which provides a selectable voltage reference for various user application cases. Besides, the CMP also has several module-to-module interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces. The CMP has the following features:

• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for internal functions
• Two software selectable performance levels: shorter propagation delay at the expense of higher power and Low power with longer propagation delay
• DMA transfer support
• Functional in all modes of operation except in VLLS0 mode
• The window and filter functions are not available in Stop, VLPS, LLS, or VLLSx modes
• Integrated 6-bit DAC with selectable supply reference source and can be power down to conserve power
• Two 8-to-1 channel mux Overview 22 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

2.2.7 RTC

The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator or clock directly from RTC_CLKIN pin. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. During chip power-down, RTC is powered from the backup power supply (VBAT), electrically isolated from the rest of the chip, continues to increment the time counter (if enabled) and retain the state of the RTC registers. The RTC registers are not accessible. The RTC module has the following features

• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
• 64-bit monotonic counter with roll-over protection

2.2.8 PIT

The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It has four independent channels and each channel has a 32-bit counter. Two channels can be chained together to form a 64-bit counter. The PIT module can trigger a DMA transfer on the first four DMA channels. and also can be selected as ADC, TPM, and DAC trigger source. The PIT module has the following features:

• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 23 NXP Semiconductors

2.2.9 LPTMR

The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features:

• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter

2.2.10 CRC

This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The CRC module has the following features:

• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface

2.2.11 LPUART

This product contains three Low-Power UART modules, both of their clock sources are selectable fromIRC48M, MCGFLLCLK, MCGPLLCLK, MCGIRCCLK or external crystal clock, and can work in Stop and VLPS modes. They also support 4x to 32x data oversampling rate to meet different applications. The LPUART module has the following features:

• Full-duplex, standard non-return-to-zero (NRZ) format Overview 24 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

• Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods: idle line wakeup, address mark wakeup, receive data match
• Automatic address matching to reduce ISR overhead
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters
• Selectable transmitter output and receiver input polarity
• Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width

2.2.12 SPI

This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes. FIFO function is available only on SPI1 module. The SPI modules have the following features:

• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 25 NXP Semiconductors

2.2.13 I2C

This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer features, and address match to wake MCU from the low power mode. I2C modules support DMA transfer, and the interrupt condition can trigger DMA request when DMA function is enabled. The I2C modules have the following features:

• Support for system management bus (SMBus) Specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Programmable input glitch filter
• Low power mode wakeup on slave address match
• Range slave address support
• DMA support
• Double buffering support to achieve higher baud rate

2.2.14 USB

This device contains one USB module which implements a USB2.0 full-speed compliant peripheral and interfaces to the on-chip USBFS transceiver. It implements keep-alive feature to avoid re-enumerating when exiting from low power modes and enables HIRC48M to allow crystal-less USB operation. The USBFS has the following features:

• USB 1.1 and 2.0 compatible FS device controller
• 16 bidirectional endpoints
• DMA or FIFO data stream interfaces
• Low-power consumption Overview 26 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

• IRC48M with clock-recovery is supported to eliminate the 48 MHz crystal. It is used for USB device-only implementation.
• Keep-alive feature is supported to power down system bus and CPU. USB can respond to IN with NAK and wake up for SETUP/OUT.

2.2.15 FlexIO

The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to LPUART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM/ Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. It also supports to work in VLPR, VLPW, Stop, and VLPS modes when clock source remains enabled. The FlexIO module has the following features:

• Array of 32-bit shift registers with transmit, receive and data match modes
• Double buffered shifter operation for continuous data transfer
• Shifter concatenation to support large transfer sizes
• Automatic start/stop bit generation
• 1, 2, 4, 8, 16 or 32 multi-bit shift widths for parallel interface support
• Interrupt, DMA or polled transmit/receive operation
• Programmable baud rates independent of bus clock frequency, with support for asynchronous operation during stop modes
• Highly flexible 16-bit timers with support for a variety of internal or external trigger, reset, enable and disable conditions
• Programmable logic mode for integrating external digital logic functions on-chip or combining pin/shifter/timer functions to generate complex outputs
• Programmable state machine for offloading basic system control functions from CPU with support for up to 8 states, 8 outputs and 3 selectable inputs per state

2.2.16 DAC

The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, OPAMPS or ADC. DAC module has the following features:

• On-chip programmable reference generator output. The voltage output range is from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage. Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 27 NXP Semiconductors

• V in can be selected from two reference sources
• Static operation in Normal Stop mode
• 16-word data buffer supported with configurable watermark and multiple operation modes
• DMA support

2.2.17 EMV-SIM

The EMV_SIM (Euro/Mastercard/Visa/SIM Serial Interface Module) is designed to facilitate communication to Smart Cards compatible to the EMV ver4.3 standard (Book 1) and Smart Cards compatible with ISO/IEC 7816-3 Standard. EMV-SIM module has the following features:

• Supports Smart Cards based on the EMV Standard v4.3 and ISO 7816-3 standard
• Independent clock for SIM logic (transmitter + receiver) and independent clock for register read-write interface
• 16 byte deep FIFO for transmitter and receiver
• Automatic NACK generation on parity error and receiver FIFO overflow error
• Support for both Inverse and Direct conventions
• Re-transmission of byte upon Smart Card NACK request with programmable threshold of re-transmissions
• Auto detection of Initial Character in receiver and setting of data format (inverse or direct)
• NACK detection in receiver
• Independent timers to measure character wait time, block wait time and block guard time
• Two general purpose counters available for use by software application with programmable clock selection for the counters
• DMA support available to transfer data to/from FIFOs. Programmable option available to select interrupt or DMA feature
• Programmable Prescaler to generate the desired frequency for Card Clock and Baud Rate Divisor to generate the internal ETU clocks for transmitter and receiver for any F/D ratio
• Deep sleep wake-up via Smart Card presence detect interrupt
• Manual control of all Smart Card interface signals Overview 28 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

• Automatic power down of port logic on Smart Card presence detect
• Support for 8-bit LRC and 16-bit CRC generation for bytes sent out from transmitter and checking incoming message checksum for receiver

2.2.18 LTC

LP Trusted Cryptography (LTC) is a hardware accelerate module dedicate for the popular encryption algorithm. LTC module has the following features:

• Cryptographic authentication
• Authenticated encryption algorithms
• AES-CCM (counter with CBC-MAC)
• AES-GCM (Galois counter mode)
• Symmetric key block ciphers
• Public key cryptography
• Secure Scan

2.2.19 TRNG

The Standalone True Random Number Generator (SA-TRNG) is hardware accelerator module that generates a 512-bit entropy as needed by an entropy consuming module or by other post processing functions.

2.2.20 TSI

The touch sensing input (TSI) module provides capacitive touch sensing detection with high sensitivity and enhanced robustness. TSI module has the following features:

• Support up to 16 external electrodes
• Automatic detection of electrode capacitance across all operational power modes
• Internal reference oscillator for high-accuracy measurement
• Configurable software or hardware scan trigger
• Fully support NXP touch sensing software (TSS) library, see www.nxp.com/ touchsensing.
• Capability to wake MCU from low power modes
• Compensate for temperature and supply voltage variations Overview Kinetis KL82 Microcontroller, Rev. 4, 12/2016 29 NXP Semiconductors

• High sensitivity change with 16-bit resolution register
• Configurable up to 4096 scan times.
• Support DMA data transfer

2.2.21 QuadSPI

The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to one single or two external serial flash devices, each with up to eight bidirectional data lines. This device contains one QSPI module, which supports singles, dual, quad or octal data lines in single (SDR) or double (DDR) data rate configurations. The QuadSPI clock frequencies support up to 96 MHz in SDR mode and up to 72 MHz in DDR mode. The QuadSPI has the following features:

• Flexible sequence engine to support various flash vendor devices.
• Single, dual, quad and octal modes of operation.
• DDR/DTR mode wherein the data is generated on every edge of the serial flash clock.
• Support for flash data strobe signal for data sampling in DDR and SDR mode.
• Support for parallel writes via register mapped interface in single I/O mode.
• Two identical serial flash devices can be connected and accessed in parallel for data read operations, forming one (virtual) flash memory with doubled readout bandwidth.
• DMA support to read RX Buffer data via AMBA AHB bus (64-bit width interface) or IP registers space (32-bit access) and DMA support to fill TX Buffer via IPS register space (32-bit access).
• Multimaster accesses with priority
• Multiple interrupt conditions
• Memory mapped read access to connected flash devices.
• Programmable sequence engine to cater to future command/protocol changes and able to support all existing vendor commands and operations.

3 Memory map

This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. The following figure shows the system memory and peripheral locations Memory map 30 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Figure 4. Memory map

4 Pinouts

4.1 KL82 signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 121 MAP BGA 100 LQFP LQFP MAP BGA LQFP Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 B1 1 1 A1 1 PTE0 DISABLED PTE0 SPI1_PCS1LPUART1_ TX QSPI0A_ DATA3 I2C1_SDARTC_ CLKOUT C2 2 2 B1 2 PTE1/ LLWU_P0 DISABLED PTE1/ LLWU_P0 SPI1_SCKLPUART1_ RX QSPI0A_ SCLK I2C1_SCLSPI1_SIN C1 3 3 C5 3 PTE2/ LLWU_P1 DISABLED PTE2/ LLWU_P1 SPI1_SOUTLPUART1_ CTS_b QSPI0A_ DATA0 SPI1_SCK D2 4 4 D2 4 PTE3 DISABLED PTE3 SPI1_PCS2LPUART1_ RTS_b QSPI0A_ DATA2 SPI1_SOUT F7 5 5 C4 5 VSS VSS VSS E5 6 6 D3 6 VDDIO_EVDDIO_EVDDIO_E D1 7 7 E2 7 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_SIN QSPI0A_ DATA1 E2 8 8 D1 8 PTE5 DISABLED PTE5 SPI1_PCS0 QSPI0A_ SS0_B USB0_ SOF_OUT E1 9 — — — PTE6/ LLWU_P16 DISABLED PTE6/ LLWU_P16 SPI1_PCS3 QSPI0B_ DATA3 F3 10 9 — — PTE7 DISABLED PTE7 QSPI0B_ SCLK QSPI0A_ SS1_B F2 11 10 — — PTE8 DISABLED PTE8 QSPI0B_ DATA0 F1 12 — — — PTE9/ LLWU_P17 DISABLED PTE9/ LLWU_P17 QSPI0B_ DATA2 G2 13 — — — PTE10/ LLWU_P18 DISABLED PTE10/ LLWU_P18 QSPI0B_ DATA1 G1 14 11 — — PTE11 DISABLED PTE11 QSPI0B_ SS0_B QSPI0A_ DQS — 15 12 — — VDDIO_EVDDIO_EVDDIO_E — 16 13 — 9 VSS VSS VSS H3 — — F3 — VSS VSS VSS H2 17 14 E1 10 USB0_DPUSB0_DPUSB0_DP H1 18 15 F1 11 USB0_DMUSB0_DMUSB0_DM Pinouts 32 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 J1 19 16 F2 12 USB_VDDUSB_VDDUSB_VDD J2 20 — — — NC NC NC — 21 — — — NC K2 — — — — ADC0_DP0ADC0_DP0ADC0_DP0 K1 — — — — ADC0_DM0ADC0_DM0ADC0_DM0 F5 22 17 G2 13 VDDA VDDA VDDA G5 23 18 H3 14 VREFH VREFH VREFH G6 24 19 H2 15 VREFL VREFL VREFL F6 25 20 G1 16 VSSA VSSA VSSA L2 26 21 H1 17 ADC0_DP1ADC0_DP1ADC0_DP1 L1 27 22 G3 18 ADC0_DM1ADC0_DM1ADC0_DM1 L3 28 23 F4 19 VREF_OUT/ CMP0_IN5/ ADC0_SE22 VREF_OUT/ CMP0_IN5/ ADC0_SE22 VREF_OUT/ CMP0_IN5/ ADC0_SE22 K4 29 24 G4 20 DAC0_OUT/ ADC0_SE23 DAC0_OUT/ ADC0_SE23 DAC0_OUT/ ADC0_SE23 H6 — — — — NC NC NC K5 30 25 F5 21 RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B L4 31 26 H4 22 XTAL32 XTAL32 XTAL32 L5 32 27 H5 23 EXTAL32EXTAL32EXTAL32 K6 33 28 G5 24 VBAT VBAT VBAT — 34 — — — VDD VDD VDD — 35 — — — VSS VSS VSS L7 36 29 D4 25 PTA0 SWD_CLKTSI0_CH1PTA0 LPUART0_ CTS_b TPM0_CH5 FXIO0_D10EMVSIM0_ CLK SWD_CLK H8 37 30 D5 26 PTA1 TSI0_CH2TSI0_CH2PTA1 LPUART0_ RX FXIO0_D11EMVSIM0_ IO J7 38 31 E5 27 PTA2 TSI0_CH3TSI0_CH3PTA2 LPUART0_ TX FXIO0_D12EMVSIM0_ PD H9 39 32 H6 28 PTA3 SWD_DIOTSI0_CH4PTA3 LPUART0_ RTS_b TPM0_CH0 FXIO0_D13EMVSIM0_ RST SWD_DIO J8 40 33 G6 29 PTA4/ LLWU_P3 NMI_b TSI0_CH5PTA4/ LLWU_P3 TPM0_CH1 FXIO0_D14EMVSIM0_ VCCEN NMI_b K7 41 — — — PTA5 DISABLED PTA5 USB0_ CLKIN TPM0_CH2 FXIO0_D15 L10 — — — — VDD VDD VDD K10 — — — — VSS VSS VSS J9 — — — — PTA10/ LLWU_P22 DISABLED PTA10/ LLWU_P22 TPM2_CH0EMVSIM1_ VCCEN FXIO0_D16 H7 — — — — PTA11/ LLWU_P23 DISABLED PTA11/ LLWU_P23 TPM2_CH1 FXIO0_D17 Pinouts Kinetis KL82 Microcontroller, Rev. 4, 12/2016 33 NXP Semiconductors

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 K8 42 — — — PTA12 DISABLED PTA12 TPM1_CH0 FXIO0_D18 L8 43 — — — PTA13/ LLWU_P4 DISABLED PTA13/ LLWU_P4 TPM1_CH1 FXIO0_D19 K9 44 34 — — PTA14 DISABLED PTA14 SPI0_PCS0LPUART0_ TX FXIO0_D20 L9 45 35 — — PTA15 DISABLED PTA15 SPI0_SCKLPUART0_ RX FXIO0_D21 J10 46 36 — — PTA16 DISABLED PTA16 SPI0_SOUTLPUART0_ CTS_b FXIO0_D22 H10 47 37 — — PTA17 DISABLED PTA17 SPI0_SINLPUART0_ RTS_b FXIO0_D23 E6 48 38 H7 30 VDD VDD VDD G7 49 39 G7 31 VSS VSS VSS L11 50 40 H8 32 PTA18 EXTAL0 EXTAL0 PTA18 TPM_ CLKIN0 K11 51 41 G8 33 PTA19 XTAL0 XTAL0 PTA19 TPM_ CLKIN1 LPTMR0_ ALT1/ LPTMR1_ ALT1 J11 52 42 F8 34 RESET_bRESET_bRESET_b H11 — — — — PTA29 DISABLED PTA29 G11 53 43 E6 35 PTB0/ LLWU_P5 ADC0_SE8/ TSI0_CH0 ADC0_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCLTPM1_CH0 FXIO0_D0 G10 54 44 — — PTB1 ADC0_SE9/ TSI0_CH6 ADC0_SE9/ TSI0_CH6 PTB1 I2C0_SDATPM1_CH1 FXIO0_D1 G9 55 — — — PTB2 ADC0_ SE12/ TSI0_CH7 ADC0_ SE12/ TSI0_CH7 PTB2 I2C0_SCLLPUART0_ RTS_b FXIO0_D2 G8 56 — — — PTB3 ADC0_ SE13/ TSI0_CH8 ADC0_ SE13/ TSI0_CH8 PTB3 I2C0_SDALPUART0_ CTS_b FXIO0_D3 B11 — 45 F7 36 PTB4 DISABLED PTB4 EMVSIM1_ IO C11 — 46 F6 37 PTB5 DISABLED PTB5 EMVSIM1_ CLK F11 — 47 E7 38 PTB6 DISABLED PTB6 EMVSIM1_ VCCEN E11 — 48 E8 39 PTB7 DISABLED PTB7 EMVSIM1_ PD D11 — 49 D7 40 PTB8 DISABLED PTB8 EMVSIM1_ RST E10 57 — — — PTB9 DISABLED PTB9 SPI1_PCS1 D10 58 — — — PTB10 DISABLED PTB10 SPI1_PCS0 FXIO0_D4 C10 59 50 — — PTB11 DISABLED PTB11 SPI1_SCK FXIO0_D5 L6 60 — — — VSS VSS VSS Pinouts 34 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E7 61 — — — VDD VDD VDD B10 62 51 — — PTB16 TSI0_CH9TSI0_CH9PTB16 SPI1_SOUTLPUART0_ RX TPM_ CLKIN0 EWM_IN E9 63 52 — — PTB17 TSI0_CH10TSI0_CH10PTB17 SPI1_SINLPUART0_ TX TPM_ CLKIN1 EWM_OUT_ b D9 64 53 D6 41 PTB18 TSI0_CH11TSI0_CH11PTB18 TPM2_CH0 FXIO0_D6 C9 65 54 C7 42 PTB19 TSI0_CH12TSI0_CH12PTB19 TPM2_CH1 FXIO0_D7 F10 66 — — — PTB20 DISABLED PTB20 CMP0_OUTFXIO0_D8 F9 67 — — — PTB21 DISABLED PTB21 FXIO0_D9 F8 68 — — — PTB22 DISABLED PTB22 FXIO0_D10 E8 69 — — — PTB23 DISABLED PTB23 SPI0_PCS5 FXIO0_D11 B9 70 55 D8 43 PTC0 ADC0_ SE14/ TSI0_CH13 ADC0_ SE14/ TSI0_CH13 PTC0 SPI0_PCS4EXTRG_INUSB0_ SOF_OUT FXIO0_D12 D8 71 56 C6 44 PTC1/ LLWU_P6 ADC0_ SE15/ TSI0_CH14 ADC0_ SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3LPUART1_ RTS_b TPM0_CH0 FXIO0_D13 C8 72 57 B7 45 PTC2 ADC0_ SE4b/ TSI0_CH15 ADC0_ SE4b/ TSI0_CH15 PTC2 SPI0_PCS2LPUART1_ CTS_b TPM0_CH1 B8 73 58 C8 46 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 SPI0_PCS1LPUART1_ RX TPM0_CH2CLKOUT — 74 59 E3 47 VSS VSS VSS — 75 60 E4 48 VDD VDD VDD A8 76 61 B8 49 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0LPUART1_ TX TPM0_CH3 D7 77 62 A8 50 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2/ LPTMR1_ ALT2 CMP0_OUTTPM0_CH2 C7 78 63 A7 51 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTEXTRG_IN FXIO0_D14 B7 79 64 B6 52 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SINUSB0_ SOF_OUT FXIO0_D15 A7 80 65 A6 53 PTC8 CMP0_IN2CMP0_IN2PTC8 FXIO0_D16 D6 81 66 B5 54 PTC9 CMP0_IN3CMP0_IN3PTC9 FXIO0_D17 C6 82 67 B4 55 PTC10 DISABLED PTC10 I2C1_SCL FXIO0_D18 C5 83 68 A5 56 PTC11/ LLWU_P11 DISABLED PTC11/ LLWU_P11 I2C1_SDA FXIO0_D19 B6 84 69 — — PTC12 DISABLED PTC12 TPM_ CLKIN0 A6 85 70 — — PTC13 DISABLED PTC13 TPM_ CLKIN1 A5 86 — — — PTC14 DISABLED PTC14 FXIO0_D20 Pinouts Kinetis KL82 Microcontroller, Rev. 4, 12/2016 35 NXP Semiconductors

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 B5 87 — — — PTC15 DISABLED PTC15 FXIO0_D21 — 88 — — — VSS VSS VSS — 89 — — — VDD VDD VDD D5 — 71 — — PTC16 DISABLED PTC16 C4 90 72 — — PTC17 DISABLED PTC17 B4 — — — — PTC18 DISABLED PTC18 A4 — — — — PTC19 DISABLED PTC19 D4 91 73 C3 57 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0LPUART2_ RTS_b FXIO0_D22 D3 92 74 A4 58 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKLPUART2_ CTS_b FXIO0_D23 C3 93 75 C2 59 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTLPUART2_ RX I2C0_SCL B3 94 76 B3 60 PTD3 DISABLED PTD3 SPI0_SINLPUART2_ TX I2C0_SDA A3 95 77 A3 61 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1LPUART0_ RTS_b TPM0_CH4 EWM_IN SPI1_PCS0 A2 96 78 C1 62 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2LPUART0_ CTS_b TPM0_CH5 EWM_OUT_ b SPI1_SCK B2 97 79 B2 63 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3LPUART0_ RX SPI1_SOUT — 98 — — — VSS VSS VSS — 99 — — — VDD VDD VDD A1 100 80 A2 64 PTD7 DISABLED PTD7 LPUART0_ TX SPI1_SIN A10 — — — — PTD8/ LLWU_P24 DISABLED PTD8/ LLWU_P24 I2C0_SCL FXIO0_D24 A9 — — — — PTD9 DISABLED PTD9 I2C0_SDA FXIO0_D25 E4 — — — — PTD10 DISABLED PTD10 FXIO0_D26 E3 — — — — PTD11/ LLWU_P25 DISABLED PTD11/ LLWU_P25 FXIO0_D27 F4 — — — — PTD12 DISABLED PTD12 FXIO0_D28 G3 — — — — PTD13 DISABLED PTD13 FXIO0_D29 G4 — — — — PTD14 DISABLED PTD14 FXIO0_D30 H4 — — — — PTD15 DISABLED PTD15 FXIO0_D31 A11 — — — — NC NC NC J6 — — — — NC NC NC J4 — — — — NC NC NC H5 — — — — NC NC NC J3 — — — — NC NC NC J5 — — — — NC NC NC K3 — — — — NC NC NC Pinouts 36 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 121 100 80 64 64

4.2 Pin properties

The following table lists the pin properties.

121 MAPBGA

100 LQFP

80 LQFP

64 LQFP

64 MAPBGA

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt B1 1 1 1 A1 PTE0 ND Hi-Z — FS N N Y C2 2 2 2 B1 PTE1/LLWU_P0 ND Hi-Z — FS N N Y C1 3 3 3 C5 PTE2/LLWU_P1 ND Hi-Z — FS N N Y D2 4 4 4 D2 PTE3 ND Hi-Z — FS N N Y D1 7 7 7 E2 PTE4/LLWU_P2 ND Hi-Z — FS N N Y E2 8 8 8 D1 PTE5 ND Hi-Z — FS N N Y E1 9 PTE6/LLWU_P16 ND Hi-Z — FS N N Y F3 10 9 PTE7 ND Hi-Z — FS N N Y F2 11 10 PTE8 ND Hi-Z — FS N N Y F1 12 PTE9/LLWU_P17 ND Hi-Z — FS N N Y G2 13 PTE10/LLWU_P18 ND Hi-Z — FS N N Y G1 14 11 PTE11 ND Hi-Z — FS N N Y Table continues on the next page... Pinouts Kinetis KL82 Microcontroller, Rev. 4, 12/2016 37 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt K2 ADC0_DP0 ND Hi-Z — FS N N — K1 ADC0_DM0 ND Hi-Z — FS N N — L2 26 21 17 H1 ADC0_DP1 ND Hi-Z — FS N N — L1 27 22 18 G3 ADC0_DM1 ND Hi-Z — FS N N — L3 28 23 19 F4 VREF_OUT/ CMP0_IN5/ ADC0_SE22 ND Hi-Z — FS N N — K4 29 24 20 G4 DAC0_OUT/ ADC0_SE23 ND Hi-Z — FS N N — K5 30 25 21 F5 RTC_WAKEUP_B ND Hi-Z — FS N Y — L4 31 26 22 H4 XTAL32 ND Hi-Z — FS N N Y L5 32 27 23 H5 EXTAL32 ND Hi-Z — FS N N Y L7 36 29 25 D4 PTA0 ND L PU FS N N Y H8 37 30 26 D5 PTA1 ND H PU FS N N Y J7 38 31 27 E5 PTA2 ND H PU FS N N Y H9 39 32 28 H6 PTA3 ND H PU FS N N Y J8 40 33 29 G6 PTA4/LLWU_P3 ND H PU FS Y N Y K7 41 PTA5 ND H PU FS N N Y Table continues on the next page... Pinouts 38 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt J9 PTA10/LLWU_P22 ND Hi-Z — FS N N Y H7 PTA11/LLWU_P23 ND Hi-Z — FS N N Y K8 42 PTA12 ND Hi-Z — FS N N Y L8 43 PTA13/LLWU_P4 ND Hi-Z — FS N N Y K9 44 34 PTA14 ND Hi-Z — FS N N Y L9 45 35 PTA15 ND Hi-Z — FS N N Y J10 46 36 PTA16 ND Hi-Z — FS N N Y H10 47 37 PTA17 ND Hi-Z — FS N N Y L11 50 40 32 H8 PTA18 ND Hi-Z — FS N N Y K11 51 41 33 G8 PTA19 ND Hi-Z — FS N N Y J11 52 42 34 F8 RESET_b ND H PU FS N Y N H11 PTA29 ND Hi-Z — FS N N Y G11 53 43 35 E6 PTB0/LLWU_P5 ND Hi-Z — FS N N Y G10 54 44 PTB1 ND Hi-Z — FS N N Y G9 55 PTB2 ND Hi-Z — FS N N Y G8 56 PTB3 ND Hi-Z — FS N N Y B11 45 36 F7 PTB4 ND Hi-Z — FS N N Y C11 46 37 F6 PTB5 ND Hi-Z — FS N N Y F11 47 38 E7 PTB6 ND Hi-Z — FS N N Y E11 48 39 E8 PTB7 ND Hi-Z — FS N N Y D11 49 40 D7 PTB8 ND Hi-Z — FS N N Y E10 57 PTB9 ND Hi-Z — FS N N Y D10 58 PTB10 ND Hi-Z — FS N N Y C10 59 50 PTB11 ND Hi-Z — FS N N Y B10 62 51 PTB16 ND Hi-Z — FS N N Y Table continues on the next page... Pinouts Kinetis KL82 Microcontroller, Rev. 4, 12/2016 39 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt E9 63 52 PTB17 ND Hi-Z — FS N N Y D9 64 53 41 D6 PTB18 ND Hi-Z — FS N N Y C9 65 54 42 C7 PTB19 ND Hi-Z — FS N N Y F10 66 PTB20 ND Hi-Z — FS N N Y F9 67 PTB21 ND Hi-Z — FS N N Y F8 68 PTB22 ND Hi-Z — FS N N Y E8 69 PTB23 ND Hi-Z — FS N N Y B9 70 55 43 D8 PTC0 ND Hi-Z — FS N N Y D8 71 56 44 C6 PTC1/LLWU_P6 ND Hi-Z — FS N N Y C8 72 57 45 B7 PTC2 ND Hi-Z — FS N N Y B8 73 58 46 C8 PTC3/LLWU_P7 ND Hi-Z — FS N N Y A8 76 61 49 B8 PTC4/LLWU_P8 ND Hi-Z — FS N N Y D7 77 62 50 A8 PTC5/LLWU_P9 ND Hi-Z — FS N N Y C7 78 63 51 A7 PTC6/LLWU_P10 ND Hi-Z — FS N N Y B7 79 64 52 B6 PTC7 ND Hi-Z — FS N N Y A7 80 65 53 A6 PTC8 ND Hi-Z — FS N N Y D6 81 66 54 B5 PTC9 ND Hi-Z — FS N N Y C6 82 67 55 B4 PTC10 ND Hi-Z — FS N N Y C5 83 68 56 A5 PTC11/LLWU_P11 ND Hi-Z — FS N N Y B6 84 69 PTC12 ND Hi-Z — FS N N Y A6 85 70 PTC13 ND Hi-Z — FS N N Y A5 86 PTC14 ND Hi-Z — FS N N Y B5 87 PTC15 ND Hi-Z — FS N N Y D5 71 PTC16 ND Hi-Z — FS N N Y C4 90 72 PTC17 ND Hi-Z — FS N N Y Table continues on the next page... Pinouts 40 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Pullup/ pulldown setting after POR Slew rate after POR Passive pin filter after POR Open drain Pin interrupt B4 PTC18 ND Hi-Z — FS N N Y A4 PTC19 ND Hi-Z — FS N N Y D4 91 73 57 C3 PTD0/LLWU_P12 ND Hi-Z — FS N N Y D3 92 74 58 A4 PTD1 ND Hi-Z — FS N N Y C3 93 75 59 C2 PTD2/LLWU_P13 ND Hi-Z — FS N N Y B3 94 76 60 B3 PTD3 ND Hi-Z — FS N N Y A3 95 77 61 A3 PTD4/LLWU_P14 ND Hi-Z — FS N N Y A2 96 78 62 C1 PTD5 ND Hi-Z — FS N N Y B2 97 79 63 B2 PTD6/LLWU_P15 ND Hi-Z — FS N N Y A1 100 80 64 A2 PTD7 ND Hi-Z — FS N N Y A10 PTD8/LLWU_P24 ND Hi-Z — FS N N Y A9 PTD9 ND Hi-Z — FS N N Y E4 PTD10 ND Hi-Z — FS N N Y E3 PTD11/LLWU_P25 ND Hi-Z — FS N N Y F4 PTD12 ND Hi-Z — FS N N Y G3 PTD13 ND Hi-Z — FS N N Y G4 PTD14 ND Hi-Z — FS N N Y H4 PTD15 ND Hi-Z — FS N N Y Pinouts Kinetis KL82 Microcontroller, Rev. 4, 12/2016 41 NXP Semiconductors

1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or

LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain configurable.

1. PTA20 is a true open drain pin that must never be pulled above VDD.

4.3 Module signal description tables

the module's chapter. They also briefly describe the signal function and direction.

4.3.1 Core Modules

Table 9. SWD Signal Descriptions

4.3.2 System modules

Table 10. System signal descriptions Table 11. EWM signal descriptions EWM_CTRL[ASSIN] bit. The default polarity is active-low. Table 12. LLWU signal descriptions Table 13. EMVSIM0 signal descriptions

Table 14. EMVSIM1 signal descriptions

4.3.3 Clock Modules

Table 15. OSC signal descriptions Table 16. RTC OSC signal descriptions

4.3.4 Memories and memory interfaces

Table 17. QSPI signal description Table continues on the next page...

Table 17. QSPI signal description (continued) and Dual Instructions are executed. and Dual Instructions are executed.

4.3.5 Analog

Table 18. ADC0 Signal Descriptions

1. See ADC channel assignment for the n.

Table 19. CMP0 Signal Descriptions There is no CMP0_IN[4] coming from pad. Table 20. DAC0 Signal Descriptions Table 21. VREF Signal Descriptions

4.3.6 Timer Modules

Table 22. LPTMR0 Signal Descriptions Table 23. LPTMR1 Signal Descriptions Table 24. RTC Signal Descriptions Table 25. TPM0 Signal Descriptions otherwise the TPM channel pin is an input. Table 26. TPM1 Signal Descriptions otherwise the TPM channel pin is an input.

Table 27. TPM2 Signal Descriptions otherwise the TPM channel pin is an input.

4.3.7 Communication interfaces

Table 28. USB FS OTG signal descriptions frame available for external synchronization. Table 29. SPI0 signal descriptions

Table 30. SPI1 signal descriptions Table 31. I2C0 signal descriptions Table 32. I2C1 signal descriptions Table 33. LPUART0 signal descriptions disabled or transmit direction is configured for receive data. Table 34. LPUART1 signal descriptions Table continues on the next page...

Table 34. LPUART1 signal descriptions (continued) disabled or transmit direction is configured for receive data. Table 35. LPUART2 signal descriptions or transmit direction is configured for receive data. Table 36. FlexIO signal descriptions Table 37. EMVSIM0 signal descriptions Table 38. EMVSIM1 signal descriptions Table continues on the next page...

Table 38. EMVSIM1 signal descriptions (continued)

4.3.8 Human-machine interfaces (HMI)

Table 39. GPIO signal descriptions

1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO

Table 40. TSI0 signal descriptions electrode pins TSI[15:0] can operate as GPIO pins.

4.4 KL82 Pinouts

signals can be used on which pin, see the previous section.

Figure 5. KL82 121-pin MAPBGA pinout diagram

98 VSS

97 PTD6/LLWU_P15

96 PTD5

95 PTD4/LLWU_P14

94 PTD3

93 PTD2/LLWU_P13

92 PTD1

91 PTD0/LLWU_P12

90 PTC17

89 VDD

88 VSS

80 PTC8

83 PTC11/LLWU_P11

84 PTC12

85 PTC13

86 PTC14

87 PTC15

100 PTD7

Figure 6. KL82 100-pin LQFP pinout diagram

Figure 7. KL82 80-pin LQFP pinout diagram

Figure 8. KL82 64-pin MAPBGA pinout diagram

Figure 9. KL82 64-pin LQFP pinout diagram nxp.com/KPYW for more details.

4.5 Package dimensions

Figure 10. 64-pin LQFP package dimensions 1

Figure 11. 64-pin LQFP package dimensions 2

Figure 12. 64-pin MAPBGA package dimension

Figure 13. 80-pin LQFP package dimension 1

Figure 14. 80-pin LQFP package dimension 2

Figure 15. 100-pin LQFP package dimension 1

Figure 16. 100-pin LQFP package dimension 2

Figure 17. 121-pin MAPBGA package dimension

5 Electrical characteristics

Electrical characteristics

64 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.1 Terminology and guidelines

5.1.1 Definitions

Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

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5.1.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE

5.1.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V 66 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.1.4 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

5.1.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

5.2 Ratings

5.2.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Kinetis KL82 Microcontroller, Rev. 4, 12/2016 67 NXP Semiconductors

5.2.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

5.2.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

5.2.4 Voltage and current operating ratings

Symbol Description Min. Max. Unit VDD Digital supply voltage 1 –0.3 3.8 V VDDIO VDDIO is an independent voltage supply for PORTE 2 –0.3 3.8 V IDD Digital supply current — 300 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VDD + 0.3 V VAIO Analog3, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V ID Maximum current single pin limit (applies to all digital pins) –25 25 mA VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB0_DP USB0_DP input voltage –0.3 3.63 V VUSB0_DM USB0_DM input voltage –0.3 3.63 V VBAT RTC battery supply voltage –0.3 3.8 V 1. It applies for all port pins. 2. VDDIO is independent of VDD domain and can operate at a voltage independent of VDD. However, it is required that VDD domain be powered up first prior to VDDIO. VDDIO must never be higher than VDD during power ramp up, or power down. VDD and VDDIO may ramp together if tied to the same power supply. 68 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5.3 General

5.3.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% VIL Input Signal VIH Fall Time HighLow Rise Time Midpoint1 The midpoint is VIL + (VIH - VIL) / 2 Figure 18. Input signal measurement reference

5.3.2 Nonswitching electrical specifications

5.3.2.1 Voltage and current operating requirements

Table 41. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage — 0.35 × VDD V Table continues on the next page...

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Table 41. Voltage and current operating requirements (continued)

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V — 0.3 × VDD V VHYS Input hysteresis 0.06 × VDD — V IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. The ripple limit for USB_VDD is 100 mV.

5.3.2.2 LVD and POR operating requirements

Table 42. V DD supply LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 60 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 40 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs

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1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 43. VBAT power operating requirements

5.3.2.3 Voltage and current operating behaviors

Table 44. Voltage and current operating behaviors

1. This is applicanble for all GPIO pins except PTE
2. This is applicable for PTE pins only.
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD

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5.3.2.4 Power mode transition operating behaviors

All specifications except tPOR, and VLLSx –> RUN recovery times in the following table assume this clock configuration:

• CPU and system clocks = 72 MHz
• Bus clock = 24 MHz
• Flash clock = 24 MHz
• MCG mode=FEI

Table 45. Power mode transition operating behaviors

• VLLS0 –> RUN — 138 µs
• VLLS1 –> RUN — 138 µs
• VLLS2 –> RUN — 76 µs
• VLLS3 –> RUN — 76 µs
• LLS2 –> RUN — 6.1 µs
• LLS3 –> RUN — 6.1 µs
• VLPS –> RUN — 5.6 µs
• STOP –> RUN — 5.6 µs 1. Normal boot (FTFA_FOPT[LPBOOT]=1)

Table 46. Low power mode peripheral adders — typical value IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. Table continues on the next page... 72 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Table 46. Low power mode peripheral adders — typical value (continued) IEREFSTEN4MHz External 4 MHz crystal clock adder. external crystal) power consumption. Kinetis KL82 Microcontroller, Rev. 4, 12/2016 73 NXP Semiconductors

internal clock and continuous conversions.

1. Only LQFP and MAPBGA packages support the data in this column.

5.3.2.5 Power consumption operating behaviors

equivalent to the mean plus three times the standard deviation (mean + 3 sigma). The data at 105 °C is for MAPBGA and LQFP packages only. Table 47. Power consumption operating behaviors

96 MHz, bus at 24 MHz, flash at 24

72 MHz, bus at 24 MHz, flash at 24

Table continues on the next page... 74 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Table 47. Power consumption operating behaviors (continued) Table continues on the next page... Kinetis KL82 Microcontroller, Rev. 4, 12/2016 75 NXP Semiconductors

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1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

1. CoreMark benchmark compiled using IAR 7.40 with optimization level high, optimized for balanced.
2. MCG configured for PEE mode.
3. MCG configured for FEE mode.
4. MCG configured for PBE mode.
5. MCG configured for BLPE mode.
6. MCG configured for FEI mode.

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5.3.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA 6.00E -03 8.00E -03 10.00E -03 12.00E -03 14.00E -03 16.00E -03 C urrent C onsumption (A) R un C urrent V s C ore F requency E NABL E- ALL OF F E NABL E- ALL ON C ache -- C G Temperature = 25, VDD = 3V 000.00E +00 2.00E -03 4.00E -03 6.00E -03 8.00E -03 10.00E -03 12.00E -03 14.00E -03 16.00E -03 1 2 4 6 12 24 48 72 96 C urrent C onsumption (A) R un C urrent V s C ore F requency E NABL E- ALL OF F E NABL E- ALL ON -- C ore F req --C ore:Bus:F lash:QS P I C ache -- C G Temperature = 25, VDD = 3V

Figure 19. Run mode supply current vs. core frequency Kinetis KL82 Microcontroller, Rev. 4, 12/2016 81 NXP Semiconductors

150.00E -06 200.00E -06 250.00E -06 300.00E -06 350.00E -06 400.00E -06 450.00E -06 500.00E -06 C urrent C onsumption (A) VLP R C urrent V s C ore F req AL LOF F - E NABL E AL LON - E NABLE C ache -- C G Temperature = 25, VDD= 3V 000.00E +00 50.00E -06 100.00E -06 150.00E -06 200.00E -06 250.00E -06 300.00E -06 350.00E -06 400.00E -06 450.00E -06 500.00E -06 1 2 4 C urrent C onsumption (A) VLP R C urrent V s C ore F req AL LOF F - E NABL E AL LON - E NABLE C ache -- C G -- C ore F req --C ore:Bus:F lash:QS P I Temperature = 25, VDD= 3V Figure 20. VLPR mode supply current vs. core frequency

5.3.2.6 EMC performance

specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems
• KL-QRUG (Kinetis L-series Quick Reference).

82 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.3.2.7 EMC Radiated Emissions Web Search Procedure boilerplate

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.nxp.com. 2. Perform a keyword search for "EMC design"

5.3.2.8 Capacitance attributes

Table 48. Capacitance attributes

5.3.3 Switching specifications

5.3.3.1 Device clock specifications

Table 49. Device clock specifications

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

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5.3.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, LPUART, timers, and I2C signals. Table 50. General switching specifications

1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and
4. This is applicable for Port E pins
5. This is applicable for Ports A, B, C, and D.

5.3.4 Thermal specifications

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5.3.4.1 Thermal operating requirements

Table 51. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

5.3.4.2 Thermal attributes

80 LQFP 64

Table continues on the next page... Kinetis KL82 Microcontroller, Rev. 4, 12/2016 85 NXP Semiconductors

Board type Symbol Descriptio n 121 MAPBGA (natural convection) — RθJB_CSB Thermal characterizati on parameter, junction to package top outside center (natural convection) 14.6 — 19.5 °C/W 5 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). 5. Thermal resistance between the die and the central solder balls on the bottom of the package based on simulation.

5.4 Peripheral operating requirements and behaviors

5.4.1 Core modules

5.4.1.1 Debug trace timing specifications

Table 52. Debug trace operating behaviors 86 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.4.1.2 SWD electricals

Table 53. SWD full voltage range electricals

• Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
• Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)

Figure 21. Serial wire clock input timing Kinetis KL82 Microcontroller, Rev. 4, 12/2016 87 NXP Semiconductors

SWD_CLK SWD_DIO SWD_DIO SWD_DIO SWD_DIO Figure 22. Serial wire data timing

5.4.2 Clock modules

5.4.2.1 MCG specifications

Table 54. MCG specifications Table continues on the next page... 88 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Table 54. MCG specifications (continued) Table continues on the next page... Kinetis KL82 Microcontroller, Rev. 4, 12/2016 89 NXP Semiconductors

• f DCO = 48 MHz
• f DCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fpll_ref PLL reference frequency range 8 — 16 MHz fvcoclk_2x VCO output frequency 180 — 360 MHz fvcoclk PLL output frequency 90 — 180 MHz fvcoclk_90 PLL quadrature output frequency 90 — 180 MHz Ipll PLL operating current
• VCO at 184 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 23) — 2.8 — mA 8 Ipll PLL operating current
• VCO at 360 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) — 3.6 — mA 8 Table continues on the next page...

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• f vco = 180 MHz
• f vco = 360 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
• f vco = 180 MHz
• f vco = 360 MHz 1350 600 ps ps Dunl Lock exit frequency tolerance ±4.47 — ±5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

5.4.2.2 IRC48M specifications

Table 55. IRC48M specifications

• Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 0.5 ± 1.5 ± 1.5 %firc48m Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over temperature ± 0.5 ± 1.5 %firc48m Table continues on the next page...

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Table 55. IRC48M specifications (continued)

• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) Δfirc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature — — ± 0.1 %fhost 1 Jcyc_irc48m Period Jitter (RMS) — 35 150 ps tirc48mst Startup time — 2 3 μs 2 1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11

5.4.2.3 Oscillator electrical specifications

5.4.2.3.1 Oscillator DC electrical specifications

Table 56. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 600 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 7.5 500 650 2.5 3.25 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 Table continues on the next page...

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Table 56. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

5.4.2.3.2 Oscillator frequency specifications

Table 57. Oscillator frequency specifications Table continues on the next page... Kinetis KL82 Microcontroller, Rev. 4, 12/2016 93 NXP Semiconductors

Table 57. Oscillator frequency specifications (continued)

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

and cannot be moved into high power/gain mode. Table 58. 32kHz oscillator DC electrical specifications

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. 94 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.4.2.4.2 32 kHz oscillator frequency specifications Table 59. 32 kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the

applied clock must be within the range of VSS to VBAT.

5.4.3 Memories and memory interfaces

5.4.3.1 QuadSPI AC specifications

• All data is based on a negative edge data launch from the device and a positive edge data capture, as shown in the timing diagrams in this section.
• Measurements are with a load of 15pf (1.8V) and 35pf (3V) on output pins. Input slew: 1ns
• Timings assume a setting of 0x0000_000x for QuadSPI _SMPR register (see the reference manual for details). The following table lists the QuadSPI delay chain read/write settings. Please see the device reference manual for register and bit descriptions.

Table 60. QuadSPI delay chain read/write settings Kinetis KL82 Microcontroller, Rev. 4, 12/2016 95 NXP Semiconductors

Figure 23. QuadSPI input timing (SDR mode) diagram

• The below timing values are with default settings for sampling registers like QuadSPI_SMPR.
• A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad.
• The below timing are for a load of 15pf (1.8V) and 35pf (3V) or output pads
• All board delays need to be added appropriately
• Input hold time being negative does not have any implication or max achievable frequency

Table 61. QuadSPI input timing (SDR mode) specifications 96 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

• Numbers are for a load of 15pf (1.8V) and 35pf (3V)
• The numbers are for setting of hold condition in register QuadSPI_SMPR[DDRSNP]

Table 63. QuadSPI input timing (DDR mode) specifications Figure 26. QuadSPI output timing (DDR mode) diagram Table 64. QuadSPI output timing (DDR mode) specifications 98 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Table 66. QuadSPI output timing (Hyperflash mode) specifications (continued) Maximum clock frequency = 72 MHz.

5.4.3.2 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

5.4.3.2.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 67. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

5.4.3.2.2 Flash timing specifications — commands

Table 68. Flash command timing specifications Table continues on the next page... 100 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Table 68. Flash command timing specifications (continued)

1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.

5.4.3.2.3 Flash high voltage current behaviors

Table 69. Flash high voltage current behaviors

5.4.3.2.4 Reliability specifications

Table 70. NVM reliability specifications

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

5.4.4 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

5.4.5 Analog

5.4.5.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Kinetis KL82 Microcontroller, Rev. 4, 12/2016 101 NXP Semiconductors

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 5.4.5.1.1 16-bit ADC operating conditions Table 71. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• All other modes VREFL VREFL 31/32 × VREFH VREFH V — CADIN Input capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns.

102 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

1. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. RAS VAS CAS ZAS VADIN ZADIN RADIN RADIN RADIN RADIN CADIN Pad leakage due to input protection INPUT PIN INPUT PIN INPUT PIN SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT SIMPLIFIED CHANNEL SELECT CIRCUIT ADC SAR ENGINE

Figure 29. ADC input impedance equivalency diagram Table 72. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 Table continues on the next page...

Kinetis KL82 Microcontroller, Rev. 4, 12/2016 103 NXP Semiconductors

Table 72. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA

104 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.4.5.2 CMP and 6-bit DAC electrical specifications

Table 73. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64

106 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

0.1 Vin level (V) CMP Hystereris (V) 0.05 0.01 0.02 0.03 0.08 0.07 0.06 0.04 Figure 32. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Kinetis KL82 Microcontroller, Rev. 4, 12/2016 107 NXP Semiconductors

0.1 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 Vin level (V) CMP Hysteresis (V) Figure 33. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 74. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

108 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.4.5.3.2 12-bit DAC operating behaviors Table 75. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV

Kinetis KL82 Microcontroller, Rev. 4, 12/2016 109 NXP Semiconductors

1. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Digital Code DAC12 INL (LSB) 500 1000 1500 2000 2500 3000 3500 4000

Figure 34. Typical INL error vs. digital code 110 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Temperature °C DAC12 Mid Level Code Voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 Figure 35. Offset at half scale vs. temperature

5.4.5.4 Voltage reference electrical specifications

Table 76. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature

Kinetis KL82 Microcontroller, Rev. 4, 12/2016 111 NXP Semiconductors

Table 77. VREF full-range operating behaviors

• current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 78. VREF limited-range operating requirements Table 79. VREF limited-range operating behaviors

5.4.6 Timers

See General switching specifications.

5.4.7 Communication interfaces

112 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.4.7.1 EMV SIM specifications

Each EMV SIM module interface consists of a total of five pins. The interface is designed to be used with synchronous Smart cards, meaning the EMV SIM module provides the clock used by the Smart card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the EMV SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate. There is no timing relationship between the clock and the data. The clock that the EMV SIM module provides to the Smart card is used by the Smart card to recover the clock from the data in the same manner as standard UART data exchanges. All five signals of the EMV SIM module are asynchronous with each other. There are no required timing relationships between signals in normal mode. The smart card is initiated by the interface device; the Smart card responds with Answer to Reset. Although the EMV SIM interface has no defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed information see ISO/IEC 7816). EMVSIMn_PD EMVSIMn_RST EMVSIMn_CLK EMVSIMn_IO EMVSIMn_VCCEN SI7 SI8 SI9 SI10 Figure 36. EMV SIM Clock Timing Diagram Kinetis KL82 Microcontroller, Rev. 4, 12/2016 113 NXP Semiconductors

The following table defines the general timing requirements for the EMV SIM interface. Table 80. Timing Specifications, High Drive Strength

5.4.7.1.1 EMV SIM Reset Sequences

the reset sequences in these two cases.

• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• The card must send a response on EMVSIMn_IO acknowledging the reset between 400–40000 clock cycles after T0.

114 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

EMVSIMn_CLK EMVSIMn_IO RESPONSE EMVSIMn_VCCEN Figure 37. Internal Reset Card Reset Sequence The following table defines the general timing requirements for the SIM interface. Table 81. Timing Specifications, Internal Reset Card Reset Sequence

• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those 40,000 clock cycles)
• EMVSIMn_RST is asserted (at time T1)
• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on EMVSIMn_IO between 400 and 40,000 clock cycles after T1.

Kinetis KL82 Microcontroller, Rev. 4, 12/2016 115 NXP Semiconductors

EMV SIMn_VCCEN EMVSIMn_CLK EMVSIMn_IO RESPONSE EMVSIMn_RST Figure 38. Active-Low-Reset Smart Card Reset Sequence Table 82. Timing Specifications, Internal Reset Card Reset Sequence

5.4.7.1.2 EMVSIM Power-Down Sequence

83 table shows the timing requirements for parameters (SI7–SI10) shown in the figure.

• EMVSIMn_SIMPD port detects the removal of the Smart Card
• EMVSIMn_RST is negated
• EMVSIMn_CLK is negated
• EMVSIM_IO is negated
• EMVSIMx_VCCENy is negated Each of the above steps requires one RTC CLK period (usually 32 kHz). Power-down may be initiated by a Smart card removal detection; or it may be launched by the processor.

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EMVSIMn_PD EMVSIMn_RST EMVSIMn_CLK EMVSIMn_IO EMVSIMn_VCCEN SI7 SI8 SI9 SI10 Figure 39. Smart Card Interface Power Down AC Timing Table 83. Timing Requirements for Power-down Sequence initiated. See Reference Manual for reference.

5.4.7.2 USB electrical specifications

date standards, visit usb.org. Kinetis KL82 Microcontroller, Rev. 4, 12/2016 117 NXP Semiconductors

The MCGPLLCLK meets the USB jitter and signaling rate specifications for certification with the use of an external clock/crystal for both Device and Host modes. The IRC48M meets the USB jitter and signaling rate specifications for certification in Device mode when the USB clock recovery mode is enabled. It does not meet the USB signaling rate specifications for certification in Host mode operation.

5.4.7.3 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 84. Master mode DSPI timing (limited voltage range)

1. The SPI can run at a maximum frequency of 24 MHz serial clocks on PORTE interface, and up to 18 MHz on other
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

118 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

5.4.7.4 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Table 86. Master mode DSPI timing (full voltage range)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 42. DSPI classic SPI timing — master mode 120 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Table 87. Slave mode DSPI timing (full voltage range) Figure 43. DSPI classic SPI timing — slave mode

5.4.7.5 Inter-Integrated Circuit Interface (I2C) timing

Table 88. I2C timing Hold time (repeated) START condition. Table continues on the next page... Kinetis KL82 Microcontroller, Rev. 4, 12/2016 121 NXP Semiconductors

Table 88. I2C timing (continued)

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the

normal drive pins and VDD ≥ 2.7 V.

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

1. Cb = total capacitance of the one bus line in pF.

• To counter the effects of clock stretching, the I2C baud Rate select bits can be configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.

Table 89. I 2C 1Mbit/s timing period, the first clock pulse is generated. Table continues on the next page... 122 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

Table 89. I 2C 1Mbit/s timing (continued)

1. Cb = total capacitance of the one bus line in pF.

Figure 44. Timing definition for devices on the I2C bus

5.4.7.6 LPUART switching specifications

See General switching specifications.

5.4.8 Human-machine interfaces (HMI)

5.4.8.1 TSI electrical specifications

Table 90. TSI electrical specifications Kinetis KL82 Microcontroller, Rev. 4, 12/2016 123 NXP Semiconductors

6 Design considerations

6.1 Hardware design considerations

This device contains protective circuitry to guard against damage due to high static voltage or electric fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit.

6.1.1 Printed circuit board recommendations

• Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages.

6.1.2 Power delivery system

Consider the following items in the power delivery system:

• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential segments.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins.
• The USB_VDD voltage range is 3.0 V to 3.6 V. It is recommended to include a filter circuit with one bulk capacitor (no less than 2.2 μF) and one 0.1 μF capacitor at the USB_VDD pin to improve USB performance. Design considerations 124 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

• Take special care to minimize noise levels on the VREFH/VREFL inputs. An option is to use the internal reference voltage (output 1.2 V typically) as the ADC reference.
• VDDIO_E, which is dedicated to powering PORTE, must be powered after VDD and must be greater than or equal to VDD voltage.

6.1.3 Analog design

small compared to the sample period. Figure 45. RC circuit for ADC input Figure 46. High voltage measurement with an ADC input

6.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).

• RESET_b pin The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An external RC circuit is recommended to filter noise as shown in the following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to reject spurious noise. D D C C B B A A EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR MCU ADCx MCU ADCx MCU RESET_b MCU NMI_b MCU RESET_b Supervisor Chip OUT Active high, open drain RESET_b SWD_DIO SWD_CLK Analog input High voltage input RESET_b VDD VDD VDD VDD VDD VDD Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 R 1 2 0.1uF 1 2 Cx 0.1uF RESONATOR 1 3 Cy Cx CRYSTAL HDR_5X2 1 2 3 4 7 8 9 10 Cy 10k 10k CRYSTAL 0.1uF 10k CRYSTAL 1 2 1 2 C RESONATOR 1 3 1 2 10k 10k RF 1 2 RS BAT54SW 1 2 RS RS C RF 1 2 RS 1 2 RF 1 2 CRYSTAL

Figure 47. Reset circuit supervisor chip must have an active high, open-drain output.

Figure 50. SWD debug interface

• Low leakage stop mode wakeup Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the low leakage stop modes (LLS/VLLSx). See for pin selection.
• Unused pin Unused GPIO pins must be left floating (no electrical connections) with the MUX field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital input path to the MCU. If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM) floating. Connect USB_VDD to ground through a 10 kΩ resistor if the USB module is not used.

6.1.5 Crystal oscillator

MCU clock system, refer to the following table and diagrams. external feedback is required when using high gain (HGO=1) mode. Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786kHz) mode. high frequency crystals and resonators.

Figure 54. Crystal connection – Diagram 4

6.2 Software considerations

software enablement solutions, which can reduce development costs and time to market. more information and supporting collateral.

• NXP Freedom Development Platform: http://www.nxp.com/freedom
• Tower System Development Platform: http://www.nxp.com/tower IDEs for Kinetis MCUs
• Kinetis Design Studio IDE: http://www.nxp.com/kds
• Partner IDEs: http://www.nxp.com/kide Development Tools
• PEG Graphics Software: http://www.nxp.com/peg
• Processor Expert Software and Embedded Components: http://www.nxp.com/ processorexpert ) Run-time Software
• Kinetis SDK: http://www.nxp.com/ksdk
• Kinetis Bootloader: http://www.nxp.com/kboot
• ARM mbed Development Platform: http://www.nxp.com/mbed
• MQX RTOS: http://www.nxp.com/mqx Design considerations 130 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

For all other partner-developed software and tools, visit http://www.nxp.com/partners.

6.3 Soldering temperature

Base on JEDEC/IPC J-STD-020 Industry Standard, refer to AN3298: Solder Joint Temperature and Package Peak Temperature for soldering guideline of different packages.

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format: Q KL## A FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification KL## Kinetis KL family • KL82 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 128 = 128 KB R Silicon revision • (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105 Table continues on the next page... Part identification Kinetis KL82 Microcontroller, Rev. 4, 12/2016 131 NXP Semiconductors

• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm) CC Maximum CPU frequency (MHz) • 7 = 72 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

7.4 Example

This is an example part number: MKL82Z128VMC7

8 Revision history

The following table provides a revision history for this document. Table 92. Revision history

• Updated USB electrical specifications 4 12/2016 • Updated the Pin properties.
• Added a note to the T A in the Thermal operating requirements
• Updated the description of R PU and RPD in the Voltage and current operating behaviors

Revision history

132 Kinetis KL82 Microcontroller, Rev. 4, 12/2016 NXP Semiconductors

How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customerʼs technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, the Energy Efficient Solutions logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM powered logo, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2015 - 2016 NXP B.V. Document Number KL82P121M72SF0 Revision 4, 12/2016