MKL36Z256VMP4

KL36P121M48SF4 NXP | Alldatasheet

Document overview

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Technical content

48 MHz Cortex-M0+ Based Microcontroller

Designed with efficiency in mind. Compatible with all other Kinetis L families as well as Kinetis K3x family. General purpose MCU with segment LCD, featuring market leading ultra low- power to provide developers an appropriate entry-level 32-bit solution. This product offers:

• Run power consumption down to 50 μA/MHz in very low power run mode
• Static power consumption down to 2 μA with full state retention and 4.5 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48 MHz with industry leading throughput
• Memory option is up to 256 KB Flash and 32 KB RAM
• Energy-saving architecture is optimized for low power with 90 nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance
• 48 MHz ARM ® Cortex®-M0+ core Memories and memory interfaces
• Up to 256 KB program flash memory
• Up to 32 KB SRAM System peripherals
• Nine low-power modes to provide power optimization based on application requirements
• COP Software watchdog
• 4-channel DMA controller, supporting up to 63 request sources
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine Clocks
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• Multi-purpose clock source Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C Human-machine interface
• Segment LCD controller supporting up to 47 frontplanes and 8 backplanes, or 51 frontplanes and 4 backplanes
• Low-power hardware touch sensor interface (TSI)
• Up to 84 general-purpose input/output (GPIO) Communication interfaces
• Two 16-bit SPI modules
• I2S (SAI) module
• One low power UART module
• Two UART modules
• Two I2C module Analog Modules
• 16-bit SAR ADC
• 12-bit DAC
• Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Timers
• Six channel Timer/PWM (TPM)
• Two 2-channel Timer/PWM modules
• Periodic interrupt timers MKL36ZxxxVLH4 MKL36Z256VMP4, MKL36ZxxxVLL4 MKL36ZxxxVMC4 64-pin LQFP (LH) 10 x 10 x 1.4 Pitch 0.5 mm 64-pin MAPBGA (MP) 5 x 5 x 1.23 Pitch 0.5 mm 100-pin LQFP (LL) 14 x 14 x 1.4 Pitch 0.5 mm 121-pin MAPBGA (MP) 8 x 8 x 0.8 Pitch 0.65 mm Freescale Semiconductor, Inc. Document Number: KL36P121M48SF4 Data Sheet: Technical Data Rev 5 08/2014 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2014 Freescale Semiconductor, Inc. All rights reserved.

• 16-bit low-power timer (LPTMR)
• Real time clock Security and integrity modules
• 80-bit unique identification number per chip Ordering Information 1 Part Number Memory Maximum number of I\\O's Flash (KB) SRAM (KB) MKL36Z64VLH4 64 8 54 MKL36Z128VLH4 128 16 54 MKL36Z256VLH4 256 32 54 MKL36Z256VMP4 256 32 54 MKL36Z64VLL4 64 8 84 MKL36Z128VLL4 128 16 84 MKL36Z256VLL4 256 32 84 MKL36Z128VMC4 128 16 84 MKL36Z256VMC4 256 32 84 1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number search. Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL36P121M48SF4RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KL36P121M48SF41 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_L_xN40H2 Package drawing Package dimensions are provided in package drawings. LQFP 64-pin: 98ASS23234W1 MAPBGA 64-pin: 98ASA00420D1 LQFP 100-pin: 98ASS23308W1 MAPBGA 121-pin: 98ASA00344D1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x” replaced by the revision of the device you are using. 2 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

8.6 Relationship between ratings and operating

Kinetis KL36 Sub-Family, Rev5 08/2014. 3 Freescale Semiconductor, Inc.

1 Ratings

1.1 Thermal handling ratings

Table 1. Thermal handling ratings

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 2. Moisture handling ratings

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Table 3. ESD handling ratings

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

1. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

1.4 Voltage and current operating ratings

Table 4. Voltage and current operating ratings

2 General

2.1 AC electrical characteristics

Figure 2. Input signal measurement reference pins have the following characteristics.

• C L=30 pF loads
• Slew rate disabled
• Normal drive strength

2.2 Nonswitching electrical specifications

Freescale Semiconductor, Inc.

2.2.1 Voltage and current operating requirements

Table 5. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
• V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
• Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 6. V DD supply LVD and POR operating requirements Table continues on the next page... 6 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 6. V DD supply LVD and POR operating requirements (continued)

• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 7. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 VDD – 0.5 V V 1, 2 VOH Output high voltage — High drive pad (except RESET_b)
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -20 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 VDD – 0.5 V V 1, 2 IOHT Output high current total for all ports — 100 mA VOL Output low voltage — Normal drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 2.5 mA 0.5 0.5 V V Table continues on the next page... General Kinetis KL36 Sub-Family, Rev5 08/2014. 7 Freescale Semiconductor, Inc.

Table 7. Voltage and current operating behaviors (continued)

• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 10 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 4 1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS

2.2.4 Power mode transition operating behaviors

• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 8. Power mode transition operating behaviors

• VLLS0 → RUN 113 124 μs Table continues on the next page... General 8 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 8. Power mode transition operating behaviors (continued)

• VLLS1 → RUN — 112 124 μs
• VLLS3 → RUN μs
• LLS → RUN 4.5 5.0 μs
• VLPS → RUN 4.5 5.0 μs
• STOP → RUN 4.5 5.0 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11).

2.2.5 Power consumption operating behaviors

equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Table continues on the next page... Freescale Semiconductor, Inc.

Table 9. Power consumption operating behaviors (continued) Table continues on the next page... 10 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

1. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
2. MCG configured for FEI mode.
3. Incremental current consumption from peripheral activity is not included.
4. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
5. MCG configured for BLPI mode.

Freescale Semiconductor, Inc.

Table 10. Low power mode peripheral adders — typical value IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. IEREFSTEN4MHz External 4 MHz crystal clock adder. external crystal) power consumption. Table continues on the next page... 12 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 10. Low power mode peripheral adders — typical value (continued) internal clock and continuous conversions. OSC0_CR[EREFSTEN, EREFSTEN] bits.

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA General Kinetis KL36 Sub-Family, Rev5 08/2014. 13 Freescale Semiconductor, Inc.

Figure 3. Run mode supply current vs. core frequency 14 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Figure 4. VLPR mode current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 11. EMC radiated emissions operating behaviors

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,

whole number, from among the measured orientations in each frequency range.

1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

Freescale Semiconductor, Inc.

2.2.7 Designing with radiated emissions in mind

1. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 12. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 13. Device clock specifications 16 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

2.3.2 General switching specifications

Table 14. General switching specifications

1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 15. Thermal operating requirements Freescale Semiconductor, Inc.

2.4.2 Thermal attributes

Table 16. Thermal attributes

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Environmental Conditions—Forced Convection (Moving Air).

1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

the top of the package and the cold plate.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

18 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

3.1.1 SWD electricals

Table 17. SWD full voltage range electricals

• Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
• Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)

Figure 5. Serial wire clock input timing Freescale Semiconductor, Inc.

Figure 6. Serial wire data timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG specifications

Table 18. MCG specifications Table continues on the next page... 20 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 18. MCG specifications (continued)

• f VCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
• PLL at 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

• PLL at 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 24)

• f vco = 48 MHz
• f vco = 100 MHz 120 ps ps Table continues on the next page... Peripheral operating requirements and behaviors Kinetis KL36 Sub-Family, Rev5 08/2014. 21 Freescale Semiconductor, Inc.

• f vco = 48 MHz
• f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

3.3.2 Oscillator electrical specifications

3.3.2.1 Oscillator DC electrical specifications

Table 19. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz 500 200 300 950 1.2 nA μA μA μA mA Table continues on the next page... Peripheral operating requirements and behaviors 22 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 19. Oscillator DC electrical specifications (continued)

• 24 MHz
• 32 MHz — 1.5 — mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation Peripheral operating requirements and behaviors Kinetis KL36 Sub-Family, Rev5 08/2014. 23 Freescale Semiconductor, Inc.

1. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For

all other cases external capacitors must be used.

1. When low power mode is selected, RF is integrated and must not be attached externally.
2. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.3.2.2 Oscillator frequency specifications

Table 20. Oscillator frequency specifications

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module. 24 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

3.4.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 21. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 22. Flash command timing specifications

• 128 KB program flash 1.7 ms trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersblk128k Erase Flash Block execution time
• 128 KB program flash 600 ms tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 1.8 ms — trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 175 1300 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. Peripheral operating requirements and behaviors Kinetis KL36 Sub-Family, Rev5 08/2014. 25 Freescale Semiconductor, Inc.

3.4.1.3 Flash high voltage current behaviors

Table 23. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 24. NVM reliability specifications

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. 26 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 25. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• All other modes VREFL VREFL 31/32 * VREFH VREFH V — CADIN Input capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 Ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 Ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Peripheral operating requirements and behaviors Kinetis KL36 Sub-Family, Rev5 08/2014. 27 Freescale Semiconductor, Inc.

Figure 7. ADC input impedance equivalency diagram Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC =
• ADLPC = 1, ADHSC =
• ADLPC = 0, ADHSC =
• ADLPC = 0, ADHSC = 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors 28 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• 12-bit modes
• <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
• 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 Peripheral operating requirements and behaviors Kinetis KL36 Sub-Family, Rev5 08/2014. 29 Freescale Semiconductor, Inc.

3.6.2 CMP and 6-bit DAC electrical specifications

Table 27. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors Kinetis KL36 Sub-Family, Rev5 08/2014. 31 Freescale Semiconductor, Inc.

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 32 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 28. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Freescale Semiconductor, Inc.

Table 29. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors 34 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Figure 12. Typical INL error vs. digital code Freescale Semiconductor, Inc.

Figure 13. Offset at half scale vs. temperature

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

36 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

3.8.1 SPI switching specifications

used for communicating with slower peripheral devices. as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 30. SPI master mode timing on slew rate disabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).

Table 31. SPI master mode timing on slew rate enabled pads Table continues on the next page... Freescale Semiconductor, Inc.

Table 31. SPI master mode timing on slew rate enabled pads (continued)

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. If configured as an output.

Figure 14. SPI master mode timing (CPHA = 0) 38 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Figure 15. SPI master mode timing (CPHA = 1) Table 32. SPI slave mode timing on slew rate disabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

Freescale Semiconductor, Inc.

Table 33. SPI slave mode timing on slew rate enabled pads

1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

Figure 16. SPI slave mode timing (CPHA = 0) 40 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Figure 17. SPI slave mode timing (CPHA = 1)

3.8.2 Inter-Integrated Circuit Interface (I2C) timing

Table 34. I2C timing Hold time (repeated) START condition.

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High

Freescale Semiconductor, Inc.

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

1. Cb = total capacitance of the one bus line in pF.

Figure 18. Timing definition for fast and standard mode devices on the I2C bus

3.8.3 UART

See General switching specifications.

3.8.4 I2S/SAI switching specifications

(BCLK) and/or the frame sync (FS) signal shown in the following figures. 42 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

3.8.4.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 35. I2S/SAI master mode timing Figure 19. I2S/SAI timing — master modes Freescale Semiconductor, Inc.

Table 36. I2S/SAI slave mode timing

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 20. I2S/SAI timing — slave modes

3.8.4.2 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. 44 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 37. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes Figure 21. I2S/SAI timing — master modes Table 38. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full Table continues on the next page... Freescale Semiconductor, Inc.

Table 38. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 22. I2S/SAI timing — slave modes

3.9 Human-machine interfaces (HMI)

3.9.1 TSI electrical specifications

Table 39. TSI electrical specifications Table continues on the next page... 46 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 39. TSI electrical specifications (continued)

3.9.2 LCD electrical characteristics

Table 40. LCD electricals

• GCR[FFR]=0
• GCR[FFR]=1 23.3 46.6 73.1 146.2 Hz Hz CLCD LCD charge pump capacitance — nominal value — 100 — nF 1 CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1 CGlass LCD glass capacitance — 2000 8000 pF 2 VIREG VIREG
• RVTRIM=0000
• RVTRIM=1000
• RVTRIM=0100
• RVTRIM=1100
• RVTRIM=0010
• RVTRIM=1010
• RVTRIM=0110
• RVTRIM=1110
• RVTRIM=0001
• RVTRIM=1001
• RVTRIM=0101
• RVTRIM=1101
• RVTRIM=0011
• RVTRIM=1011 0.91 0.92 0.93 0.94 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.05 1.06 1.07 V 3 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis KL36 Sub-Family, Rev5 08/2014. 47 Freescale Semiconductor, Inc.

Table 40. LCD electricals (continued)

• RVTRIM=0111
• RVTRIM=1111 1.08 1.09 ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG IVIREG VIREG current adder — RVEN = 1 — 1 — µA 4 IRBIAS RBIAS current adder
• LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) µA µA RRBIAS RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) 0.28 2.98 MΩ MΩ VLL1 VLL1 voltage — — VIREG V 5 VLL2 VLL2 voltage — — 2 x VIREG V 5 VLL3 VLL3 voltage — — 3 x VIREG V 5 VLL1 VLL1 voltage — — VDDA / 3 V 6 VLL2 VLL2 voltage — — VDDA / 1.5 V 6 VLL3 VLL3 voltage — — VDDA V 6 1. The actual value used could vary with tolerance. 2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter within the device's reference manual. 3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V 4. 2000 pF load LCD, 32 Hz frame frequency 5. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump is enabled (GCR[CPSEL]=1). 6. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = V DDA through the internal power switch (GCR[VSUPPLY]=0).
• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is connected to VDDA externally (GCR[VSUPPLY]=1).

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings. 48 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 64-pin LQFP 98ASS23234W 64-pin MAPBGA 98ASA00420D 100-pin LQFP 98ASS23308W 121-pin MAPBGA 98ASA00344D

5 Pinout

5.1 KL36 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 121 BGA 100 LQFP BGA LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 E4 1 A1 1 PTE0 DISABLEDLCD_P48PTE0 SPI1_MISOUART1_TXRTC_ CLKOUT CMP0_OUTI2C1_SDALCD_P48 E3 2 B1 2 PTE1 DISABLEDLCD_P49PTE1 SPI1_MOSIUART1_RX SPI1_MISOI2C1_SCLLCD_P49 E2 3 — — PTE2 DISABLEDLCD_P50PTE2 SPI1_SCK LCD_P50 F4 4 — — PTE3 DISABLEDLCD_P51PTE3 SPI1_MISO SPI1_MOSI LCD_P51 H7 5 — — PTE4 DISABLEDLCD_P52PTE4 SPI1_PCS0 LCD_P52 G4 6 — — PTE5 DISABLEDLCD_P53PTE5 LCD_P53 F3 7 — — PTE6 DISABLEDLCD_P54PTE6 I2S0_MCLKaudioUSB_ SOF_OUT LCD_P54 E6 8 — 3 VDD VDD VDD G7 9 C4 4 VSS VSS VSS L6 — — — VSS VSS VSS H1 14 E1 5 PTE16 ADC0_DP1/ ADC0_SE1 LCD_P55/ ADC0_DP1/ ADC0_SE1 PTE16 SPI0_PCS0UART2_TXTPM_ CLKIN0 LCD_P55 H2 15 D1 6 PTE17 ADC0_DM1/ ADC0_SE5a LCD_P56/ ADC0_DM1/ ADC0_SE5a PTE17 SPI0_SCKUART2_RXTPM_ CLKIN1 LPTMR0_ ALT3 LCD_P56 J1 16 E2 7 PTE18 ADC0_DP2/ ADC0_SE2 LCD_P57/ ADC0_DP2/ ADC0_SE2 PTE18 SPI0_MOSI I2C0_SDASPI0_MISO LCD_P57 Pinout Kinetis KL36 Sub-Family, Rev5 08/2014. 49 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 J2 17 D2 8 PTE19 ADC0_DM2/ ADC0_SE6a LCD_P58/ ADC0_DM2/ ADC0_SE6a PTE19 SPI0_MISO I2C0_SCLSPI0_MOSI LCD_P58 K1 18 G1 9 PTE20 ADC0_DP0/ ADC0_SE0 LCD_P59/ ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0UART0_TX LCD_P59 K2 19 F1 10 PTE21 ADC0_DM0/ ADC0_SE4a LCD_P60/ ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1UART0_RX LCD_P60 L1 20 G2 11 PTE22 ADC0_DP3/ ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0UART2_TX L2 21 F2 12 PTE23 ADC0_DM3/ ADC0_SE7a ADC0_DM3/ ADC0_SE7a PTE23 TPM2_CH1UART2_RX F5 22 F4 13 VDDA VDDA VDDA G5 23 G4 14 VREFH VREFH VREFH G6 24 G3 15 VREFL VREFL VREFL F6 25 F3 16 VSSA VSSA VSSA L3 26 H1 17 PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_ CLKIN0 K5 27 H2 18 PTE30 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_ CLKIN1 L4 28 H3 19 PTE31 DISABLED PTE31 TPM0_CH4 L5 29 — — VSS VSS VSS K6 30 — — VDD VDD VDD H5 31 H4 20 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL J5 32 H5 21 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA H6 33 — — PTE26 DISABLED PTE26 TPM0_CH5 RTC_ CLKOUT J6 34 D3 22 PTA0 SWD_CLKTSI0_CH1PTA0 TPM0_CH5 SWD_CLK H8 35 D4 23 PTA1 DISABLEDTSI0_CH2PTA1 UART0_RXTPM2_CH0 J7 36 E5 24 PTA2 DISABLEDTSI0_CH3PTA2 UART0_TXTPM2_CH1 H9 37 D5 25 PTA3 SWD_DIOTSI0_CH4PTA3 I2C1_SCLTPM0_CH0 SWD_DIO J8 38 G5 26 PTA4 NMI_b TSI0_CH5PTA4 I2C1_SDATPM0_CH1 NMI_b K7 39 F5 27 PTA5 DISABLED PTA5 TPM0_CH2 I2S0_TX_ BCLK E5 — — — VDD VDD VDD G3 — — — VSS VSS VSS K3 40 — — PTA6 DISABLED PTA6 TPM0_CH3 H4 41 — — PTA7 DISABLED PTA7 TPM0_CH4 K8 42 H6 28 PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0 L8 43 G6 29 PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_FS K9 44 — — PTA14 DISABLED PTA14 SPI0_PCS0UART0_TX I2S0_RX_ BCLK I2S0_TXD0 Pinout 50 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 L9 45 — — PTA15 DISABLED PTA15 SPI0_SCKUART0_RX I2S0_RXD0 J10 46 — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISOI2S0_RX_FSI2S0_RXD0 H10 47 — — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSII2S0_MCLK L10 48 G7 30 VDD VDD VDD K10 49 H7 31 VSS VSS VSS L11 50 H8 32 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RXTPM_ CLKIN0 K11 51 G8 33 PTA19 XTAL0 XTAL0 PTA19 UART1_TXTPM_ CLKIN1 LPTMR0_ ALT1 J11 52 F8 34 PTA20 RESET_b PTA20 RESET_b G11 53 F7 35 PTB0/ LLWU_P5 LCD_P0/ ADC0_SE8/ TSI0_CH0 LCD_P0/ ADC0_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCLTPM1_CH0 LCD_P0 G10 54 F6 36 PTB1 LCD_P1/ ADC0_SE9/ TSI0_CH6 LCD_P1/ ADC0_SE9/ TSI0_CH6 PTB1 I2C0_SDATPM1_CH1 LCD_P1 G9 55 E7 37 PTB2 LCD_P2/ ADC0_SE12/ TSI0_CH7 LCD_P2/ ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCLTPM2_CH0 LCD_P2 G8 56 E8 38 PTB3 LCD_P3/ ADC0_SE13/ TSI0_CH8 LCD_P3/ ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDATPM2_CH1 LCD_P3 E11 57 — — PTB7 LCD_P7 LCD_P7 PTB7 LCD_P7 D11 58 — — PTB8 LCD_P8 LCD_P8 PTB8 SPI1_PCS0EXTRG_IN LCD_P8 E10 59 — — PTB9 LCD_P9 LCD_P9 PTB9 SPI1_SCK LCD_P9 D10 60 — — PTB10 LCD_P10LCD_P10PTB10 SPI1_PCS0 LCD_P10 C10 61 — — PTB11 LCD_P11LCD_P11PTB11 SPI1_SCK LCD_P11 B10 62 E6 39 PTB16 LCD_P12/ TSI0_CH9 LCD_P12/ TSI0_CH9 PTB16 SPI1_MOSIUART0_RXTPM_ CLKIN0 SPI1_MISO LCD_P12 E9 63 D7 40 PTB17 LCD_P13/ TSI0_CH10 LCD_P13/ TSI0_CH10 PTB17 SPI1_MISOUART0_TXTPM_ CLKIN1 SPI1_MOSI LCD_P13 D9 64 D6 41 PTB18 LCD_P14/ TSI0_CH11 LCD_P14/ TSI0_CH11 PTB18 TPM2_CH0I2S0_TX_ BCLK LCD_P14 C9 65 C7 42 PTB19 LCD_P15/ TSI0_CH12 LCD_P15/ TSI0_CH12 PTB19 TPM2_CH1I2S0_TX_FS LCD_P15 F10 66 — — PTB20 LCD_P16LCD_P16PTB20 CMP0_OUTLCD_P16 F9 67 — — PTB21 LCD_P17LCD_P17PTB21 LCD_P17 F8 68 — — PTB22 LCD_P18LCD_P18PTB22 LCD_P18 E8 69 — — PTB23 LCD_P19LCD_P19PTB23 LCD_P19 B9 70 D8 43 PTC0 LCD_P20/ ADC0_SE14/ TSI0_CH13 LCD_P20/ ADC0_SE14/ TSI0_CH13 PTC0 EXTRG_INaudioUSB_ SOF_OUT CMP0_OUTI2S0_TXD0LCD_P20 D8 71 C6 44 PTC1/ LLWU_P6/ RTC_CLKIN LCD_P21/ ADC0_SE15/ TSI0_CH14 LCD_P21/ ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 I2S0_TXD0LCD_P21 Pinout Kinetis KL36 Sub-Family, Rev5 08/2014. 51 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 C8 72 B7 45 PTC2 LCD_P22/ ADC0_SE11/ TSI0_CH15 LCD_P22/ ADC0_SE11/ TSI0_CH15 PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FSLCD_P22 B8 73 C8 46 PTC3/ LLWU_P7 LCD_P23LCD_P23PTC3/ LLWU_P7 UART1_RXTPM0_CH2CLKOUT I2S0_TX_ BCLK LCD_P23 F7 74 E3 47 VSS VSS VSS E7 — E4 — VDD VDD VDD A11 75 C5 48 VLL3 VLL3 VLL3 A10 76 A6 49 VLL2 VLL2 VLL2/ LCD_P4 PTC20 LCD_P4 A9 77 B5 50 VLL1 VLL1 VLL1/ LCD_P5 PTC21 LCD_P5 B11 78 B4 51 VCAP2 VCAP2 VCAP2/ LCD_P6 PTC22 LCD_P6 C11 79 A5 52 VCAP1 VCAP1 VCAP1/ LCD_P39 PTC23 LCD_P39 A8 80 B8 53 PTC4/ LLWU_P8 LCD_P24LCD_P24PTC4/ LLWU_P8 SPI0_PCS0UART1_TXTPM0_CH3I2S0_MCLK LCD_P24 D7 81 A8 54 PTC5/ LLWU_P9 LCD_P25LCD_P25PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0 CMP0_OUTLCD_P25 C7 82 A7 55 PTC6/ LLWU_P10 LCD_P26/ CMP0_IN0 LCD_P26/ CMP0_IN0 PTC6/ LLWU_P10 SPI0_MOSIEXTRG_INI2S0_RX_ BCLK SPI0_MISOI2S0_MCLKLCD_P26 B7 83 B6 56 PTC7 LCD_P27/ CMP0_IN1 LCD_P27/ CMP0_IN1 PTC7 SPI0_MISOaudioUSB_ SOF_OUT I2S0_RX_FSSPI0_MOSI LCD_P27 A7 84 — — PTC8 LCD_P28/ CMP0_IN2 LCD_P28/ CMP0_IN2 PTC8 I2C0_SCLTPM0_CH4I2S0_MCLK LCD_P28 D6 85 — — PTC9 LCD_P29/ CMP0_IN3 LCD_P29/ CMP0_IN3 PTC9 I2C0_SDATPM0_CH5I2S0_RX_ BCLK LCD_P29 C6 86 — — PTC10 LCD_P30LCD_P30PTC10 I2C1_SCL I2S0_RX_FS LCD_P30 C5 87 — — PTC11 LCD_P31LCD_P31PTC11 I2C1_SDA I2S0_RXD0 LCD_P31 B6 88 — — PTC12 LCD_P32LCD_P32PTC12 TPM_ CLKIN0 LCD_P32 A6 89 — — PTC13 LCD_P33LCD_P33PTC13 TPM_ CLKIN1 LCD_P33 D5 90 — — PTC16 LCD_P36LCD_P36PTC16 LCD_P36 C4 91 — — PTC17 LCD_P37LCD_P37PTC17 LCD_P37 B4 92 — — PTC18 LCD_P38LCD_P38PTC18 LCD_P38 D4 93 C3 57 PTD0 LCD_P40LCD_P40PTD0 SPI0_PCS0 TPM0_CH0 LCD_P40 D3 94 A4 58 PTD1 LCD_P41/ ADC0_SE5b LCD_P41/ ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 LCD_P41 C3 95 C2 59 PTD2 LCD_P42LCD_P42PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISO LCD_P42 B3 96 B3 60 PTD3 LCD_P43LCD_P43PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSI LCD_P43 A3 97 A3 61 PTD4/ LLWU_P14 LCD_P44LCD_P44PTD4/ LLWU_P14 SPI1_PCS0UART2_RXTPM0_CH4 LCD_P44 Pinout 52 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 A2 98 C1 62 PTD5 LCD_P45/ ADC0_SE6b LCD_P45/ ADC0_SE6b PTD5 SPI1_SCKUART2_TXTPM0_CH5 LCD_P45 B2 99 B2 63 PTD6/ LLWU_P15 LCD_P46/ ADC0_SE7b LCD_P46/ ADC0_SE7b PTD6/ LLWU_P15 SPI1_MOSIUART0_RX SPI1_MISO LCD_P46 A1 100 A2 64 PTD7 LCD_P47LCD_P47PTD7 SPI1_MISOUART0_TX SPI1_MOSI LCD_P47 F1 10 — — NC NC NC F2 11 — — NC NC NC G1 12 — — NC NC NC G2 13 — — NC NC NC J3 — — — NC NC NC H3 — — — NC NC NC K4 — — — NC NC NC L7 — — — NC NC NC J9 — — — NC NC NC J4 — — — NC NC NC H11 — — — NC NC NC F11 — — — NC NC NC A5 — — — NC NC NC B5 — — — NC NC NC A4 — — — NC NC NC B1 — — — NC NC NC C2 — — — NC NC NC C1 — — — NC NC NC D2 — — — NC NC NC D1 — — — NC NC NC E1 — — — NC NC NC

5.2 KL36 pinouts

The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, ssee KL36 Signal Multiplexing and Pin Assignments. Pinout Kinetis KL36 Sub-Family, Rev5 08/2014. 53 Freescale Semiconductor, Inc.

Figure 23. KL36 121-pin BGA pinout diagram 54 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

98 PTD5

97 PTD4/LLWU_P14

96 PTD3

95 PTD2

94 PTD1

93 PTD0

92 PTC18

91 PTC17

90 PTC16

89 PTC13

88 PTC12

80 PTC4/LLWU_P8

83 PTC7

84 PTC8

85 PTC9

86 PTC10

87 PTC11

100 PTD7

Figure 24. KL36 100-pin LQFP pinout diagram Freescale Semiconductor, Inc.

Figure 25. KL36 64-pin BGA pinout diagram 56 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Figure 26. KL36 64-pin LQFP pinout diagram

6 Ordering parts

6.1 Determining valid orderable parts

Freescale Semiconductor, Inc.

7 Part identification

7.1 Description

values of these fields to determine the specific part you have received.

7.2 Format

7.3 Fields

Table 41. Part number fields descriptions

• P = Prequalification KL## Kinetis family • KL36 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB R Silicon revision • (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105
• MP = 64 MAPBGA (5 mm x 5 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel Part identification 58 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

7.4 Example

This is an example part number: MKL36Z256VMC4

8 Terminology and guidelines

8.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

8.1.1 Example

This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

8.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

8.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. Terminology and guidelines Kinetis KL36 Sub-Family, Rev5 08/2014. 59 Freescale Semiconductor, Inc.

8.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF

8.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.

8.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

8.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines 60 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

8.6 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

8.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

8.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines Kinetis KL36 Sub-Family, Rev5 08/2014. 61 Freescale Semiconductor, Inc.

8.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

8.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

8.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Terminology and guidelines 62 Kinetis KL36 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.

Table 42. Typical value conditions

9 Revision history

The following table provides a revision history for this document. Table 43. Revision history

• Updated Voltage and current operating behaviors
• Updated EMC radiated emissions operating behaviors
• Updated Power mode transition operating behaviors
• Updated Capacitance attributes
• Updated footnote in the Device clock specifications
• Added thermal attributes of 64-pin MAPBGA in the Thermal attributes
• Added V REFH and VREFL in the 16-bit ADC electrical characteristics
• Updated footnote to the V DACR in the 12-bit DAC operating requirements
• Added Inter-Integrated Circuit Interface (I2C) timing 4 5/2014 • Updated Power consumption operating behaviors
• Updated Definition: Operating behavior 5 08/2014 • Updated related source in the front page
• Updated Power consumption operating behaviors

Revision history

Kinetis KL36 Sub-Family, Rev5 08/2014. 63 Freescale Semiconductor, Inc.

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