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Technical content
Kinetis KL33 Microcontroller
48 MHz ARM® Cortex®-M0+ and 128/256 KB Flash
The KL33 series is optimized for cost-sensitive and battery- powered applications requiring low-power segment LCD. The product offers:
- Low power segment LCD up to 28x8 or 32x4 Embedded ROM with boot loader for flexible program upgrade
- High accuracy internal voltage and clock reference
- FlexIO to support any standard and customized serial peripheral emulation
- Down to 54uA/MHz in very low power run mode and 1.96uA in deep sleep mode (RAM + RTC retained) Core Processor
- ARM ® Cortex®-M0+ core up to 48 MHz Memories 128/256 KB program flash memory
- 16/32 KB SRAM
- 16 KB ROM with build-in bootloader
- 32-byte backup register System
- 4-channel asynchronous DMA controller
- Watchdog
- Low-leakage wakeup unit
- Two-pin Serial Wire Debug (SWD) programming and debug interface
- Micro Trace Buffer
- Bit manipulation engine
- Interrupt controller Clocks
- 48MHz high accuracy (up to 0.5%) internal reference clock
- 8MHz/2MHz high accuracy (up to 3%) internal reference clock
- 1KHz reference clock active under all low-power modes (except VLLS0)
- 32–40KHz and 3–32MHz crystal oscillator Peripherals
- Segment LCD supporting up to 28x8 or 32x4 segments One UART module supporting ISO7816, operating up to 1.5 Mbit/s
- Two low-power UART modules supporting asynchronous operation in low-power modes
- Two I2C modules and I2C0 supporting up to 1 Mbit/s
- Two 16-bit SPI modules supporting up to 24 Mbit/s
- One FlexIO module supporting emulation of additional UART, IrDA, SPI, I2C, I2S, PWM and other serial modules, etc.
- One serial audio interface I2S
- One 16-bit 818 ksps ADC module with high accuracy internal voltage reference (Vref) and up to 16 channels
- High-speed analog comparator containing a 6-bit DAC for programmable reference input
- One 12-bit DAC
- 1.2 V internal voltage reference Timers
- One 6-channel Timer/PWM module
- Two 2-channel Timer/PWM modules
- One low-power timer
- Periodic interrupt timer
- Real time clock MKL33Z256Vxx4(R) MKL33Z128Vxx4(R)
64 LQFP
10x10 mm P 0.5 mm
64 BGA
5x5 mm P 0.5 mm Freescale Semiconductor, Inc. KL33P64M48SF6 Data Sheet: Technical Data Rev. 5, 08/2015 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2015 Freescale Semiconductor, Inc. All rights reserved.
- Voltage range: 1.71 to 3.6 V Flash write voltage range: 1.71 to 3.6 V
- Temperature range: –40 to 105 °C Packages
- 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm thickness
- 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm thickness Security and Integrity
- 80-bit unique identification number per chip Advanced flash security I/O
- Up to 54 general-purpose input/output pins (GPIO) and 6 high-drive pad Low Power
- Down to 54uA/MHz in very low power run mode
- Down to 1.96uA in VLLS3 mode (RAM + RTC retained)
- Six flexible static modes
Ordering Information
Product Memory Package IO and ADC channel Part number Marking (Line1/ Line2) Flash (KB) SRAM (KB) Pin count Package GPIOs GPIOs (INT/HD)1 ADC channels (SE/DP) MKL33Z128VLH4 MKL33Z128V//LH4 128 16 64 LQFP 54 31/6 20/4 MKL33Z256VLH4 MKL33Z256V//LH4 256 32 64 LQFP 54 31/6 20/4 MKL33Z128VMP4 M33P7V 128 16 64 MAPBGA 54 31/6 20/4 MKL33Z256VMP4 M33P8V 256 32 64 MAPBGA 54 31/6 20/4 1. INT: interrupt pin numbers; HD: high drive pin numbers Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. KLX3PB1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL33P64M48SF6RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_L_1N71K1 Package drawing Package dimensions are provided in package drawings. 64-LQFP: 98ASS23234W1 64 MAPBGA: 98ASA00420D1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
8.4 Relationship between ratings and operating
Kinetis KL33 Microcontroller, Rev.5, 08/2015. 3 Freescale Semiconductor, Inc.
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
- Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
- Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
- Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
- Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
4 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
2 General
2.1 AC electrical characteristics
Figure 1. Input signal measurement reference output pins have the following characteristics.
- CL=30 pF loads Slew rate disabled
- Normal drive strength
2.2 Nonswitching electrical specifications
Freescale Semiconductor, Inc.
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V 1.7 V ≤ VDD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V 1.7 V ≤ VDD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
- V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
- Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V 1. All I/O pins are internally clamped to V SS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to V DD.
2.2.2 LVD and POR operating requirements
Table 6. V DD supply LVD and POR operating requirements Table continues on the next page... 6 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 6. V DD supply LVD and POR operating requirements (continued)
- Level 1 falling (LVWV = 00)
- Level 2 falling (LVWV = 01) Level 3 falling (LVWV = 10)
- Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
- Level 1 falling (LVWV = 00) Level 2 falling (LVWV = 01)
- Level 3 falling (LVWV = 10)
- Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA VDD – 0.5 VDD – 0.5 V V VOH Output high voltage — high drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = –18 mA 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — normal drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA 0.5 0.5 V V VOL Output low voltage — high drive pad 0.5 V Table continues on the next page... General Kinetis KL33 Microcontroller, Rev.5, 08/2015. 7 Freescale Semiconductor, Inc.
Table 7. Voltage and current operating behaviors (continued)
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 18 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 6 mA — 0.5 V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 2 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2 IIN Input leakage current (total all pins) for full temperature range — 64 μA 2 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 3 1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at V DD = 3.6 V 3. Measured at V DD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
- CPU and system clocks = 48 MHz Bus and flash clock = 24 MHz
- HIRC clock mode
Table 8. Power mode transition operating behaviors
- VLLS0 → RUN 152 166 μs
- VLLS1 → RUN 152 166 μs
- VLLS3 → RUN 104 μs
- LLS → RUN 7.5 μs Table continues on the next page... General 8 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 8. Power mode transition operating behaviors (continued)
- VLPS → RUN 7.5 μs
- STOP → RUN 7.5 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11)
2.2.5 Power consumption operating behaviors
equivalent to the mean plus three times the standard deviation (mean + 3 sigma). The while (1) test is executed with flash cache enabled. Table 9. Power consumption operating behaviors
- at 25 °C at 105 °C 5.76 6.04 6.40 6.68 mA IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 3.21 3.49 3.85 4.13 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 6.45 6.75 7.09 7.39 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 3.95 4.23 4.59 4.87 mA Table continues on the next page... General Kinetis KL33 Microcontroller, Rev.5, 08/2015. 9 Freescale Semiconductor, Inc.
Table 9. Power consumption operating behaviors (continued)
- at 25 °C at 105 °C 2.68 2.96 3.32 3.60 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 8.08 8.39 8.72 9.03 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in flash all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 3.90 4.21 4.54 4.85 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 2.66 2.94 3.30 3.58 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 2.03 2.31 2.67 2.95 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 5.52 5.83 6.16 6.47 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 5.29 5.56 5.93 6.20 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in SRAM all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
- at 25 °C at 105 °C 6.91 7.19 7.55 7.91 mA Table continues on the next page... General 10 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
- at 25 °C 826 907 μA IDD_VLPRC O Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V
- at 25 °C 405 486 μA IDD_VLPRC O Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
- at 25 °C 154 235 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
- at 25 °C 108 189 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
- at 25 °C 120 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
- at 25 °C 249 330 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
- at 25 °C 337 418 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
- at 25 °C 416 497 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
- at 25 °C 494 575 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
- at 25 °C 166 247 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
- at 25 °C 131 μA Table continues on the next page... General Kinetis KL33 Microcontroller, Rev.5, 08/2015. 11 Freescale Semiconductor, Inc.
- at 25 °C 208 289 μA IDD_WAIT Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V 1.81 1.89 mA IDD_WAIT Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V 1.22 1.39 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 172 182 μA IDD_VLPW Very-low-power wait mode current, core disabled, 2 MHz system/ 0.5 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 69 76 μA IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V — 36 40 μA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V 1.81 2.06 mA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V 1.00 1.25 mA IDD_STOP Stop mode current at 3.0 V
- at 25 °C and below at 50 °C
- at 85 °C
- at 105 °C 161.93 181.45 236.29 390.33 171.82 191.96 271.17 465.58 μA IDD_VLPS Very-low-power stop mode current at 3.0 V
- at 25 °C and below at 50 °C
- at 85 °C
- at 105 °C 3.31 10.43 34.14 104.38 5.14 17.68 61.06 164.44 μA IDD_VLPS Very-low-power stop mode current at 1.8 V
- at 25 °C and below at 50 °C 3.21 10.26 33.49 5.22 17.62 60.19 μA Table continues on the next page... General 12 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
- at 85 °C
- at 105 °C — 102.92 162.20 IDD_LLS Low-leakage stop mode current, all peripheral disable, at 3.0 V
- at 25 °C and below at 50 °C
- at 70 °C
- at 85 °C
- at 105 °C 2.06 4.72 8.13 13.34 41.08 3.33 6.85 13.30 24.70 52.43 μA IDD_LLS Low-leakage stop mode current with RTC current, at 3.0 V
- at 25 °C and below at 50 °C
- at 70 °C
- at 85 °C
- at 105 °C 2.46 5.12 8.53 13.74 41.48 3.73 7.25 11.78 18.91 52.83 μA IDD_LLS Low-leakage stop mode current with RTC current, at 1.8 V
- at 25 °C and below at 50 °C
- at 70 °C
- at 85 °C
- at 105 °C 2.35 4.91 8.32 13.44 40.47 2.70 6.75 11.78 18.21 51.85 μA IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V
- at 25 °C and below at 50 °C
- at 70 °C
- at 85 °C
- at 105 °C 1.45 3.37 5.76 9.72 30.41 1.85 4.39 8.48 14.30 37.50 μA IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V
- at 25 °C and below at 50 °C
- at 70 °C
- at 85 °C
- at 105 °C 2.05 3.97 6.36 10.32 31.01 2.45 4.99 9.08 14.73 38.10 μA Table continues on the next page... General Kinetis KL33 Microcontroller, Rev.5, 08/2015. 13 Freescale Semiconductor, Inc.
- at 25 °C and below at 50 °C
- at 70 °C
- at 85 °C
- at 105 °C 1.96 3.86 6.23 10.21 30.25 2.36 5.67 8.53 13.37 37.02 μA IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V
- at 25 °C and below at 50°C
- at 70°C
- at 85°C
- at 105 °C 0.66 1.78 2.55 4.83 16.42 0.80 3.87 4.26 6.64 20.49 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V
- at 25 °C and below at 50°C
- at 70°C
- at 85°C
- at 105 °C 1.26 2.38 3.15 5.43 17.02 1.40 4.47 4.86 7.24 21.09 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V
- at 25 °C and below at 50°C
- at 70°C
- at 85°C
- at 105 °C 1.16 1.96 2.78 4.85 15.78 1.30 2.28 3.37 6.88 18.81 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V
- at 25 °C and below at 50 °C
- at 70 °C
- at 85 °C
- at 105 °C 0.35 1.25 2.53 4.40 16.09 0.47 1.44 3.24 5.24 19.29 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V General 14 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
- at 25 °C and below
- at 50 °C at 70 °C
- at 85 °C
- at 105 °C 0.18 1.09 2.25 4.25 15.95 0.28 1.31 2.94 5.10 19.10 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high, optimized for balanced. 3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
Table 10. Low power mode peripheral adders — typical value IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled. all modes with the crystal enabled.
- VLLS1 VLLS3
- LLS
- VLPS
- STOP 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 nA ILPTMR LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. 100 200 Table continues on the next page... General Kinetis KL33 Microcontroller, Rev.5, 08/2015. 15 Freescale Semiconductor, Inc.
Table 10. Low power mode peripheral adders — typical value (continued) single external input for compare. Includes 6-bit DAC power consumption.
- IRC8M (8 MHz internal reference clock) IRC2M (2 MHz internal reference clock) 114 114 114 114 114 114 µA ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents.
- IRC8M (8 MHz internal reference clock) IRC2M (2 MHz internal reference clock) 147 147 147 147 147 147 µA IBG Bandgap adder when BGEN bit is set and device is placed in VLPx or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 330 330 330 330 330 330 µA ILCD LCD peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the OSC0_CR[EREFSTEN, EREFSTEN] bits. VIREG disabled, resistor bias network enabled, 1/8 duty cycle, 8 x 36 configuration for driving 288 Segments, 32 Hz frame rate, no LCD glass connected. Includes ERCLK32K (32 kHz external crystal) power consumption. General 16 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG-Lite in HIRC for run mode, and LIRC for VLPR mode No GPIOs toggled
- Code execution from flash
- For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 2. Run mode supply current vs. core frequency Freescale Semiconductor, Inc.
18 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
Freescale Semiconductor, Inc.
whole number, from among the measured orientations in each frequency range.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
2.2.7 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications Table continues on the next page... 20 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 13. Device clock specifications (continued)
- The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48MHz is used as the clock source.
- The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
- The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
Table 14. General switching specifications
- The synchronous and asynchronous timing must be met.
- This is the shortest pulse that is guaranteed to be recognized.
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements Freescale Semiconductor, Inc.
- Maximum T A can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
2.4.2 Thermal attributes
Table 16. Thermal attributes
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Environmental Conditions—Forced Convection (Moving Air).
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
- Thermal characterization parameter indicating the temperature difference between package bottom center and the
parameter is written as Psi-JB.
3 Peripheral operating requirements and behaviors
3.1 Core modules
22 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
- Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
- Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)
Figure 4. Serial wire clock input timing Freescale Semiconductor, Inc.
Figure 5. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 18. IRC48M specification Table continues on the next page... 24 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 18. IRC48M specification (continued)
- The maximum value represents characterized results equivalent to mean plus or minus three times the standard
Table 19. IRC8M/2M specification Freescale Semiconductor, Inc.
Figure 6. IRC8M Frequency Drift vs Temperature curve
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 20. Oscillator DC electrical specifications
- 32 kHz
4 MHz
- 8 MHz (RANGE=01)
- 16 MHz 500 200 300 950 1.2 nA μA μA μA mA Table continues on the next page... Peripheral operating requirements and behaviors 26 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 20. Oscillator DC electrical specifications (continued)
- 24 MHz
- 32 MHz — 1.5 — mA IDDOSC Supply current — high gain mode (HGO=1)
- 32 kHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. V DD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation Peripheral operating requirements and behaviors Kinetis KL33 Microcontroller, Rev.5, 08/2015. 27 Freescale Semiconductor, Inc.
- C x,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
- When low power mode is selected, R F is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
3.3.2.2 Oscillator frequency specifications
Table 21. Oscillator frequency specifications
- Other frequency limits may apply when external clock is being used as a reference for the FLL
- When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module. 28 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
3.4.1.1 Flash timing specifications — program and erase
are active and do not include command overhead. Table 22. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 23. Flash command timing specifications
- 128 KB program flash 1.7 ms trd1sec1k Read 1s Section execution time (flash sector) — — 60 μs 1 tpgmchk Program Check execution time — — 45 μs 1 trdrsrc Read Resource execution time — — 30 μs 1 tpgm4 Program Longword execution time — 65 145 μs — tersblk128k Erase Flash Block execution time
- 128 KB program flash 600 ms tersscr Erase Flash Sector execution time — 14 114 ms 2 trd1all Read 1s All Blocks execution time — — 1.8 ms 1 trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs — tersall Erase All Blocks execution time — 175 1300 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 175 1300 ms 2 1. Assumes 25 MHz flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. Peripheral operating requirements and behaviors Kinetis KL33 Microcontroller, Rev.5, 08/2015. 29 Freescale Semiconductor, Inc.
3.4.1.3 Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
3.4.1.4 Reliability specifications
Table 25. NVM reliability specifications
- Typical data retention values are based on measured response accelerated at high temperature and derated to a
- Cycling endurance represents number of program/erase cycles at –40 °C ≤ T j ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
30 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 26. 16-bit ADC operating conditions
1.13 VDDA VDDA V 3
- All other modes VREFL VREFL 31/32 × VREFH VREFH V — CADIN Input capacitance
- 16-bit mode
- 8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 24 MHz 5 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 5 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 1200 ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 1. Typical values assume V DDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. VREFH can act as VREF_OUT when VREFV1 module is enabled. 4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Peripheral operating requirements and behaviors Kinetis KL33 Microcontroller, Rev.5, 08/2015. 31 Freescale Semiconductor, Inc.
Figure 7. ADC input impedance equivalency diagram Table 27. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC = 1, ADHSC = 0
- ADLPC = 1, ADHSC = 1 ADLPC = 0, ADHSC = 0
- ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12-bit modes
- <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
- 12-bit modes
- <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
- 12-bit modes
- <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors 32 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 27. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
- 16-bit modes
- ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
- Avg = 32 Avg = 4 16-bit single-ended mode
- Avg = 32
- Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
- Avg = 32 16-bit single-ended mode Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
- Avg = 32 16-bit single-ended mode Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with V REFH = VDDA Peripheral operating requirements and behaviors Kinetis KL33 Microcontroller, Rev.5, 08/2015. 33 Freescale Semiconductor, Inc.
3.6.2 Voltage reference electrical specifications
Table 28. VREF full-range operating requirements
- C L must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
- The load capacitance should not exceed +/-25% of the nominal specified C L value over the operating temperature
VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1. Table 29. VREF full-range operating behaviors
- current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs — Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms — Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Peripheral operating requirements and behaviors Kinetis KL33 Microcontroller, Rev.5, 08/2015. 35 Freescale Semiconductor, Inc.
Table 30. VREF limited-range operating requirements Table 31. VREF limited-range operating behaviors
3.6.3 CMP and 6-bit DAC electrical specifications
Table 32. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00 CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to V DD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = V reference/64 Peripheral operating requirements and behaviors 36 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Freescale Semiconductor, Inc.
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 33. 12-bit DAC operating requirements
- The DAC reference can be selected to be V DDA or VREFH.
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
38 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 34. 12-bit DAC operating behaviors
- High power (SP HP) Low power (SPLP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
- High power (SP HP) Low power (SPLP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to V DACR −100 mV 3. The DNL is measured for 0 + 100 mV to V DACR −100 mV 4. The DNL is measured for 0 + 100 mV to V DACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from V SS + 100 mV to VDACR − 100 mV 6. V DDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors Kinetis KL33 Microcontroller, Rev.5, 08/2015. 39 Freescale Semiconductor, Inc.
Figure 12. Typical INL error vs. digital code 40 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Figure 13. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Freescale Semiconductor, Inc.
3.8.1 SPI switching specifications
for communicating with slower peripheral devices. well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 35. SPI master mode timing on slew rate disabled pads
- For SPI0 f periph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
Table 36. SPI master mode timing on slew rate enabled pads Table continues on the next page... 42 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 36. SPI master mode timing on slew rate enabled pads (continued)
- For SPI0 f periph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- If configured as an output.
Figure 14. SPI master mode timing (CPHA = 0) Freescale Semiconductor, Inc.
Figure 15. SPI master mode timing (CPHA = 1) Table 37. SPI slave mode timing on slew rate disabled pads
- For SPI0 f periph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- Time to data active from high-impedance state
- Hold time to high-impedance state
44 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 38. SPI slave mode timing on slew rate enabled pads
- For SPI0 f periph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- Time to data active from high-impedance state
- Hold time to high-impedance state
Figure 16. SPI slave mode timing (CPHA = 0) Freescale Semiconductor, Inc.
Figure 17. SPI slave mode timing (CPHA = 1)
3.8.2 I 2C
3.8.2.1 Inter-Integrated Circuit Interface (I2C) timing
Table 39. I2C timing Hold time (repeated) START condition. 46 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
- The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the
high drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
- The master mode I 2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
- The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
- Input signal Slew = 10 ns and Output Load = 50 pF
- Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
- A Fast mode I 2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
- C b = total capacitance of the one bus line in pF.
- To counter the effects of clock stretching, the I2C baud Rate select bits can be configured for faster than desired baud rate. Use high drive pad and DSE bit should be set in PORTx_PCRn register.
- Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the SCL line to avoid clock stretching.
- Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 40. I 2C 1Mbit/s timing period, the first clock pulse is generated.
- The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins
across the full voltage range.
- C b = total capacitance of the one bus line in pF.
Freescale Semiconductor, Inc.
Figure 18. Timing definition for devices on the I2C bus
3.8.3 UART
See General switching specifications.
3.8.4 I2S/SAI switching specifications
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
3.8.4.1 Normal Run, Wait and Stop mode performance over the full
device in Normal Run, Wait and Stop modes. Table 41. I2S/SAI master mode timing Table continues on the next page... 48 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 41. I2S/SAI master mode timing (continued) Figure 19. I2S/SAI timing — master modes Table 42. I2S/SAI slave mode timing Table continues on the next page... Freescale Semiconductor, Inc.
Table 42. I2S/SAI slave mode timing (continued)
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 20. I2S/SAI timing — slave modes
3.8.4.2 VLPR, VLPW, and VLPS mode performance over the full
device in VLPR, VLPW, and VLPS modes. Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes Table continues on the next page... 50 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Figure 21. I2S/SAI timing — master modes Table 44. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full Freescale Semiconductor, Inc.
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 22. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 LCD electrical characteristics
Table 45. LCD electricals
- GCR[FFR]=0 GCR[FFR]=1 23.3 46.6 73.1 146.2 Hz Hz CLCD LCD charge pump capacitance — nominal value — 100 — nF CBYLCD LCD bypass capacitance — nominal value — 100 — nF 1 CGlass LCD glass capacitance — 2000 8000 pF 2 VIREG VIREG
- RVTRIM=0000 RVTRIM=1000
- RVTRIM=0100
- RVTRIM=1100
- RVTRIM=0010
- RVTRIM=1010
- RVTRIM=0110 0.91 0.92 0.93 0.94 0.96 0.97 0.98 0.99 V 3 Table continues on the next page... Peripheral operating requirements and behaviors 52 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Table 45. LCD electricals (continued)
- RVTRIM=1110
- RVTRIM=0001 RVTRIM=1001
- RVTRIM=0101
- RVTRIM=1101
- RVTRIM=0011
- RVTRIM=1011
- RVTRIM=0111
- RVTRIM=1111 1.01 1.02 1.03 1.05 1.06 1.07 1.08 1.09 ΔRTRIM VIREG TRIM resolution — — 3.0 % VIREG IVIREG VIREG current adder — RVEN = 1 — 1 — µA IRBIAS RBIAS current adder
- LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF) LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) µA µA RRBIAS RBIAS resistor values
- LADJ = 10 or 11 — High load (LCD glass capacitance ≤ 8000 pF) LADJ = 00 or 01 — Low load (LCD glass capacitance ≤ 2000 pF) 0.28 2.98 MΩ MΩ VLL1 VLL1 voltage — — VIREG V 4 VLL2 VLL2 voltage — — 2 x VIREG V 4 VLL3 VLL3 voltage — — 3 x VIREG V 4 VLL1 VLL1 voltage — — VDDA / 3 V 5 VLL2 VLL2 voltage — — VDDA / 1.5 V 5 VLL3 VLL3 voltage — — VDDA V 5 1. The actual value used could vary with tolerance. 2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter within the device's reference manual. 3. V IREG maximum should never be externally driven to any level other than VDD - 0.15 V 4. VLL1, VLL2 and VLL3 are a function of V IREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump is enabled (GCR[CPSEL]=1). 5. VLL1, VLL2 and VLL3 are a function of V DDA only under either of the following conditions:
- The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = V DDA through the internal power switch (GCR[VSUPPLY]=0). The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is connected to VDDA externally (GCR[VSUPPLY]=1). Peripheral operating requirements and behaviors Kinetis KL33 Microcontroller, Rev.5, 08/2015. 53 Freescale Semiconductor, Inc.
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 64-pin LQFP 98ASS23234W 64-pin MAPBGA 98ASA00420D Pinouts and Packaging
5.1 KL33 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE VREFH can act as VREF_OUT when VREFV1 module is enabled. LQFP MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — E4 VDD VDD VDD
1 A1 PTE0 DISABLED LCD_P48 PTE0/
SPI1_MISO LPUART1_TX RTC_CLKOUT CMP0_OUT I2C1_SDA LCD_P48
2 B1 PTE1 DISABLED LCD_P49 PTE1 SPI1_MOSI LPUART1_RX SPI1_MISO I2C1_SCL LCD_P49
3 — VDD VDD VDD
4 C4 VSS VSS VSS
5 E1 PTE16 ADC0_DP1/
ADC0_SE1 LCD_P55/ ADC0_DP1/ ADC0_SE1 PTE16 SPI0_SS UART2_TX TPM_CLKIN0 FXI00_D0 LCD_P55 Dimensions 54 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
6 D1 PTE17 ADC0_DM1/
ADC0_SE5a LCD_P56/ ADC0_DM1/ ADC0_SE5a PTE17 SPI0_SCK UART2_RX TPM_CLKIN1 LPTMR0_ ALT3 FXIO0_D1 LCD_P56
7 E2 PTE18 ADC0_DP2/
ADC0_SE2 LCD_P57/ ADC0_DP2/ ADC0_SE2 PTE18 SPI0_MOSI I2C0_SDA SPI0_MISO FXIO0_D2 LCD_P57
8 D2 PTE19 ADC0_DM2/
ADC0_SE6a LCD_P58/ ADC0_DM2/ ADC0_SE6a PTE19 SPI0_MISO I2C0_SCL SPI0_MOSI FXIO0_D3 LCD_P58
9 G1 PTE20 ADC0_DP0/
ADC0_SE0 LCD_P59/ ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0 LPUART0_TX FXI00_D4 LCD_P59
10 F1 PTE21 ADC0_DM0/
ADC0_SE4a LCD_P60/ ADC0_DM0/ ADC0_SE4a PTE21 TPM1_CH1 LPUART0_RX FXIO0_D5 LCD_P60
11 G2 PTE22 ADC0_DP3/
ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0 UART2_TX FXIO0_D6
12 F2 PTE23 ADC0_DM3/
ADC0_SE7a ADC0_DM3/ ADC0_SE7a PTE23 TPM2_CH1 UART2_RX FXIO0_D7
13 F4 VDDA VDDA VDDA
14 G4 VREFH VREFH VREFH
15 G3 VREFL VREFL VREFL
16 F3 VSSA VSSA VSSA
17 H1 PTE29 CMP0_IN5/
ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2 TPM_CLKIN0
18 H2 PTE30 DAC0_OUT/
ADC0_SE23/ CMP0_IN4 DAC0_OUT/ ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3 TPM_CLKIN1 LPUART1_TX LPTMR0_ ALT1
19 H3 PTE31 DISABLED PTE31 TPM0_CH4
20 H4 PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL
21 H5 PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA
22 D3 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK
23 D4 PTA1 DISABLED PTA1 LPUART0_RX TPM2_CH0
24 E5 PTA2 DISABLED PTA2 LPUART0_TX TPM2_CH1
25 D5 PTA3 SWD_DIO PTA3 I2C1_SCL TPM0_CH0 SWD_DIO
26 G5 PTA4 NMI_b PTA4 I2C1_SDA TPM0_CH1 NMI_b
27 F5 PTA5 DISABLED PTA5 TPM0_CH2 I2S0_TX_
28 H6 PTA12 DISABLED PTA12 TPM1_CH0 I2S0_TXD0
29 G6 PTA13 DISABLED PTA13 TPM1_CH1 I2S0_TX_FS
30 G7 VDD VDD VDD
31 H7 VSS VSS VSS
32 H8 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_RX TPM_CLKIN0
Kinetis KL33 Microcontroller, Rev.5, 08/2015. 55 Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
33 G8 PTA19 XTAL0 XTAL0 PTA19 LPUART1_TX TPM_CLKIN1 LPTMR0_
34 F8 PTA20 RESET_b PTA20 RESET_b
35 F7 PTB0/
LLWU_P5 LCD_P0/ ADC0_SE8 LCD_P0/ ADC0_SE8 PTB0/ LLWU_P5 I2C0_SCL TPM1_CH0 LCD_P0
36 F6 PTB1 LCD_P1/
ADC0_SE9 LCD_P1/ ADC0_SE9 PTB1 I2C0_SDA TPM1_CH1 LCD_P1
37 E7 PTB2 LCD_P2/
ADC0_SE12 LCD_P2/ ADC0_SE12 PTB2 I2C0_SCL TPM2_CH0 LCD_P2
38 E8 PTB3 LCD_P3/
ADC0_SE13 LCD_P3/ ADC0_SE13 PTB3 I2C0_SDA TPM2_CH1 LCD_P3
39 E6 PTB16 LCD_P12 LCD_P12 PTB16 SPI1_MOSI LPUART0_RX TPM_CLKIN0 SPI1_MISO LCD_P12
40 D7 PTB17 LCD_P13 LCD_P13 PTB17 SPI1_MISO LPUART0_TX TPM_CLKIN1 SPI1_MOSI LCD_P13
41 D6 PTB18 LCD_P14 LCD_P14 PTB18 TPM2_CH0 I2S0_TX_
LCD_P14
42 C7 PTB19 LCD_P15 LCD_P15 PTB19 TPM2_CH1 I2S0_TX_FS LCD_P15
43 D8 PTC0 LCD_P20/
ADC0_SE14 LCD_P20/ ADC0_SE14 PTC0 EXTRG_IN audioUSB_ SOF_OUT CMP0_OUT I2S0_TXD0 LCD_P20
44 C6 PTC1/
LLWU_P6/ RTC_CLKIN LCD_P21/ ADC0_SE15 LCD_P21/ ADC0_SE15 PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 I2S0_TXD0 LCD_P21
45 B7 PTC2 LCD_P22/
ADC0_SE11 LCD_P22/ ADC0_SE11 PTC2 I2C1_SDA TPM0_CH1 I2S0_TX_FS LCD_P22
46 C8 PTC3/
LLWU_P7 LCD_P23 LCD_P23 PTC3/ LLWU_P7 SPI1_SCK LPUART1_RX TPM0_CH2 CLKOUT I2S0_TX_ BCLK LCD_P23
47 E3 VSS VSS VSS
48 C5 VLL3 VLL3 VLL3
49 A6 VLL2 VLL2 VLL2/
LCD_P4 PTC20 LCD_P4
50 B5 VLL1 VLL1 VLL1/
LCD_P5 PTC21 LCD_P5
51 B4 VCAP2 VCAP2 VCAP2/
LCD_P6 PTC22 LCD_P6
52 A5 VCAP1 VCAP1 VCAP1/
LCD_P39 PTC23 LCD_P39
53 B8 PTC4/
LLWU_P8 LCD_P24 LCD_P24 PTC4/ LLWU_P8 SPI0_SS LPUART1_TX TPM0_CH3 I2S0_MCLK LCD_P24
54 A8 PTC5/
LLWU_P9 LCD_P25 LCD_P25 PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 CMP0_OUT LCD_P25
55 A7 PTC6/
LLWU_P10 LCD_P26/ CMP0_IN0 LCD_P26/ CMP0_IN0 PTC6/ LLWU_P10 SPI0_MOSI EXTRG_IN I2S0_RX_ BCLK SPI0_MISO I2S0_MCLK LCD_P26
56 B6 PTC7 LCD_P27/
CMP0_IN1 LCD_P27/ CMP0_IN1 PTC7 SPI0_MISO audioUSB_ SOF_OUT I2S0_RX_FS SPI0_MOSI LCD_P27
57 C3 PTD0 LCD_P40 LCD_P40 PTD0 SPI0_SS TPM0_CH0 FXI00_D0 LCD_P40
56 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7
58 A4 PTD1 LCD_P41/
ADC0_SE5b LCD_P41/ ADC0_SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 LCD_P41
59 C2 PTD2 LCD_P42 LCD_P42 PTD2 SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2 LCD_P42
60 B3 PTD3 LCD_P43 LCD_P43 PTD3 SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3 LCD_P43
61 A3 PTD4/
LLWU_P14 LCD_P44 LCD_P44 PTD4/ LLWU_P14 SPI1_SS UART2_RX TPM0_CH4 FXI00_D4 LCD_P44
62 C1 PTD5 LCD_P45/
ADC0_SE6b LCD_P45/ ADC0_SE6b PTD5 SPI1_SCK UART2_TX TPM0_CH5 FXIO0_D5 LCD_P45
63 B2 PTD6/
LLWU_P15 LCD_P46/ ADC0_SE7b LCD_P46/ ADC0_SE7b PTD6/ LLWU_P15 SPI1_MOSI LPUART0_RX SPI1_MISO FXIO0_D6 LCD_P46
64 A2 PTD7 LCD_P47 LCD_P47 PTD7 SPI1_MISO LPUART0_TX SPI1_MOSI FXIO0_D7 LCD_P47
5.2 KL33 Family Pinouts
Figure below shows the 64 LQFP pinouts: Pinouts and Packaging Kinetis KL33 Microcontroller, Rev.5, 08/2015. 57 Freescale Semiconductor, Inc.
Figure 23. 64 LQFP Pinout diagram 58 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
Figure 24. 64 MAPBGA Pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts
7 Part identification
Freescale Semiconductor, Inc.
7.1 Description
values of these fields to determine the specific part you have received.
7.2 Format
7.3 Fields
Table 46. Part number fields descriptions
- P = Prequalification KL## Kinetis family • KL33 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size R Silicon revision • (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- MP = 64 MAPBGA (5 mm x 5 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel
7.4 Example
60 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines Kinetis KL33 Microcontroller, Rev.5, 08/2015. 61 Freescale Semiconductor, Inc.
8.2 Examples
Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines 62 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
8.4 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings. During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
9 Revision History
The following table provides a revision history for this document. Table 47. Revision History
- Updated Table 9 - Power consumption operating behaviors. 4 03 March 2015
- Updated the features and completed the ordering information.
- Removed thickness dimension from package diagrams. Table continues on the next page...
Revision History
Kinetis KL33 Microcontroller, Rev.5, 08/2015. 63 Freescale Semiconductor, Inc.
Table 47. Revision History (continued)
- Updated Related Resources table to include Chip Errata resource name and Package Drawing part numbers in the respective rows.
- Updated Table 7. Voltage and current operating behaviors. Specified correct max. value for IIN.
- Updated Table - 9 Power consumption operating behaviors.
- Rows added for IDD for reset pin hold low (I DD_RESET_LOW) at 1.7V and 3V.
- Measurement unit updated for I DD_VLLS1 from nA to μA.
- Footnote 1 was moved in the beginning of the table as text.
- Added Table - 11 EMC radiated emissions operating behaviors for 64-pin LQFP package under section 2.2.6.
- Updated Table - 18 (IRC48M specification) and Table - 19 (IRC8M/2M specification) under section 3.3.1 - 'MCG-Lite specifications'.
- Removed supply voltage (V DD), temperature range (T), untrimmed (fIRC_UT), trim function (ΔfIRC_C, ΔfIRC_F) data from Table - 18 (IRC48M specification).
- Removed supply voltage (V DD), temperature range (T) data from Table - 19 (IRC8M/2M specification).
- Added Figure 6. IRC8M Frequency Drift vs Temperature curve after Table - 19 (IRC8M/2M specification).
- Updated Table 29. VREF full-range operating behaviors.
- Removed A c(Aging coefficient) row.
- Added T chop_osc_stup parameter.
- Updated typical value of the V out parameter.
- Added tables: "I2C timing" and "I2C 1Mbit/s timing" under section - I 2C.
- Added VREF specifications (V REFH and VREFL) to Table 26. 16-bit ADC operating conditions.
- Removed note: “This device does not have the USB_CLKIN signal available.” 5 12 August 2015
- In Table 9. Power consumption operating behaviors:
- Updated Max. values of I DD_WAIT, IDD_VLPW, IDD_STOP, IDD_VLPS, IDD_LLS, IDD_VLLS3, IDD_VLLS1, IDD_VLLS0. Modified unit of IDD_VLLS0 from nA to μA.
- Removed I DD_RESET_LOW information.
- In Table 13. Device clock specifications, added a footnote for normal run mode.
- In Table 15. Thermal operating requirements, modified the footnote for Ambient temperature.
- In Table 18. IRC48M specification, removed f IRC_T data and added Δfirc48m_of_lv and Δfirc48m_of_hv specifications.
- In Table 26. 16-bit ADC operating conditions, updated Max. value of f ADCK and Crate.
64 Kinetis KL33 Microcontroller, Rev.5, 08/2015. Freescale Semiconductor, Inc.
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