KL24P80M48SF0 NXP | Alldatasheet
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Technical content
48 MHz Cortex-M0+ Based Microcontroller with USB
Designed with efficiency in mind. Compatible with all other Kinetis L families as well as Kinetis K2x family. General purpose MCU with USB 2.0, featuring market leading ultra low-power to provide developers an appropriate entry-level 32-bit solution. This product offers:
- Run power consumption down to 47 μA/MHz in very low power run mode
- Static power consumption down to 2 μA with full state retention and 4 μs wakeup
- Ultra-efficient Cortex-M0+ processor running up to 48 MHz with industry leading throughput
- Memory option is up to 128 KB flash and 16 KB RAM
- Energy-saving architecture is optimized for low power with 90 nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance
- 48 MHz ARM ® Cortex®-M0+ core Memories and memory interfaces
- Up to 64 KB program flash memory
- Up to 8 KB SRAM System peripherals
- Nine low-power modes to provide power optimization based on application requirements
- COP Software watchdog
- 4-channel DMA controller, supporting up to 63 request sources
- Low-leakage wakeup unit
- SWD debug interface and Micro Trace Buffer
- Bit Manipulation Engine Clocks
- 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
- Multi-purpose clock source
- 1 kHz LPO clock Operating Characteristics
- Voltage range: 1.71 to 3.6 V Human-machine interface
- Up to 66 general-purpose input/output (GPIO) Communication interfaces
- USB full-/low-speed On-the-Go controller with on- chip transceiver and 5 V to 3.3 V regulator
- Two 8-bit SPI modules
- One low power UART module
- Two UART modules
- Two I2C module Analog Modules
- 12-bit SAR ADC
- Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Timers
- Six channel Timer/PWM (TPM)
- Two 2-channel Timer/PWM modules
- Periodic interrupt timers
- 16-bit low-power timer (LPTMR)
- Real time clock Security and integrity modules
- 80-bit unique identification number per chip MKL24ZxxVFM4 MKL24ZxxVFT4 MKL24ZxxVLH4 MKL24ZxxVLK4 32-pin QFN (FM) 5 x 5 x 1 Pitch 0.5 mm 48-pin QFN (FT) 7 x 7 x 1 Pitch 0.5 mm 64-pin LQFP (LH) 10 x 10 x 1.4 Pitch 0.5 mm 80-pin LQFP (LK) 12 x 12 x 1.4 Pitch 0.5 mm Freescale Semiconductor, Inc. Document Number: KL24P80M48SF0 Data Sheet: Technical Data Rev 5 08/2014 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2014 Freescale Semiconductor, Inc. All rights reserved.
- Flash write voltage range: 1.71 to 3.6 V
- Temperature range (ambient): -40 to 105°C
Ordering Information
Part Number Memory Maximum number of I\\O's Flash (KB) SRAM (KB) MKL24Z32VFM4 32 4 23 MKL24Z64VFM4 64 8 23 MKL24Z32VFT4 32 4 36 MKL24Z64VFT4 64 8 36 MKL24Z32VLH4 32 4 50 MKL24Z64VLH4 64 8 50 MKL24Z32VLK4 32 4 66 MKL24Z64VLK4 64 8 66 Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. KL2 Family Product Brief1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL24P80M48SF0RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. KL24P80M48SF01 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_L_xN97F2 Package drawing Package dimensions are provided in package drawings. QFN 32-pin: 98ASA00473D1 QFN 48-pin: 98ASA00466D1 LQFP 64-pin: 98ASS23234W1 LQFP 80-pin: 98ASS23174W1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x” replaced by the revision of the device you are using. Figure 1 shows the functional modules in the chip. 2 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Figure 1. Functional block diagram Freescale Semiconductor, Inc.
8.6 Relationship between ratings and operating
4 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
- Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
- Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
- Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
- Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Freescale Semiconductor, Inc.
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
2 General
2.1 AC electrical characteristics
Figure 2. Input signal measurement reference pins have the following characteristics.
- C L=30 pF loads
- Slew rate disabled
- Normal drive strength General 6 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V — IICIO IO pin negative DC injection current—single pin
- V IN < VSS–0.3V –3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
- Negative current injection –25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V — 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 6. V DD supply LVD and POR operating requirements Table continues on the next page... Freescale Semiconductor, Inc.
Table 6. V DD supply LVD and POR operating requirements (continued)
- Level 1 falling (LVWV = 00)
- Level 2 falling (LVWV = 01)
- Level 3 falling (LVWV = 10)
- Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
- Level 1 falling (LVWV = 00)
- Level 2 falling (LVWV = 01)
- Level 3 falling (LVWV = 10)
- Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = –1.5 mA VDD – 0.5 VDD – 0.5 V V 1, 2 VOH Output high voltage — High drive pad (except RESET)
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = –18 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = –6 mA VDD – 0.5 VDD – 0.5 V V 1, 2 IOHT Output high current total for all ports — 100 mA — Table continues on the next page... General 8 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Table 7. Voltage and current operating behaviors (continued)
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 1.5 mA 0.5 0.5 V V VOL Output low voltage — High drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 18 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA — IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 65 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA — RPU Internal pullup resistors 20 50 kΩ 4 RPD Internal pulldown resistors 20 50 kΩ 5 1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 5. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
- CPU and system clocks = 48 MHz
- Bus and flash clock = 24 MHz
- FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors Table continues on the next page... Freescale Semiconductor, Inc.
Table 8. Power mode transition operating behaviors (continued)
- VLLS0 → RUN 115 μs
- VLLS1 → RUN 115 μs
- VLLS3 → RUN μs
- LLS → RUN 4.6 μs
- VLPS → RUN 4.4 μs
- STOP → RUN 4.4 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors Table continues on the next page... 10 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Table 9. Power consumption operating behaviors (continued) Table continues on the next page... Freescale Semiconductor, Inc.
- The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
- MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for
- MCG configured for FEI mode.
- Incremental current consumption from peripheral activity is not included.
- MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
- MCG configured for BLPI mode.
12 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Table 10. Low power mode peripheral adders — typical value IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. IEREFSTEN4MHz External 4 MHz crystal clock adder. kHz external crystal) power consumption. Table continues on the next page... Freescale Semiconductor, Inc.
Table 10. Low power mode peripheral adders — typical value (continued) placing the device in STOP or VLPS mode.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FBE for run mode, and BLPE for VLPR mode
- USB regulator disabled
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFA General 14 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Figure 3. Run mode supply current vs. core frequency Freescale Semiconductor, Inc.
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors for 64-pin LQFP
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
16 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. from among the measured orientations in each frequency range.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
2.2.7 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications Table continues on the next page... Freescale Semiconductor, Inc.
Table 13. Device clock specifications (continued)
- The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
- The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
Table 14. General switching specifications
- The greater synchronous and asynchronous timing must be met.
- This is the shortest pulse that is guaranteed to be recognized.
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements 18 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
2.4.2 Thermal attributes
Table 16. Thermal attributes
48 QFN 32 QFN Unit Notes
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Method Environmental Conditions—Forced Convection (Moving Air).
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
between the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
Freescale Semiconductor, Inc.
3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
- Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
- Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns J11 SWD_CLK high to SWD_DIO data valid — 32 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)
Figure 5. Serial wire clock input timing 20 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Figure 6. Serial wire data timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 18. MCG specifications Table continues on the next page... Freescale Semiconductor, Inc.
Table 18. MCG specifications (continued)
- f VCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
- PLL at 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
- PLL at 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
- f vco = 48 MHz
- f vco = 100 MHz 120 ps ps Table continues on the next page... Peripheral operating requirements and behaviors 22 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
- f vco = 48 MHz
- f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz 500 200 300 950 1.2 nA μA μA μA mA Table continues on the next page... Peripheral operating requirements and behaviors Kinetis KL24 Sub-Family, Rev5 08/2014. 23 Freescale Semiconductor, Inc.
Table 19. Oscillator DC electrical specifications (continued)
- 24 MHz
- 32 MHz — 1.5 — mA IDDOSC Supply current — high gain mode (HGO=1)
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low- power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation Peripheral operating requirements and behaviors 24 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
- Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
- When low power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
3.3.2.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
- Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
- When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module. Freescale Semiconductor, Inc.
3.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 21. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 22. Flash command timing specifications
- Assumes 25 MHz flash clock frequency.
- Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors 26 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
3.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
- Typical data retention values are based on measured response accelerated at high temperature and derated to a
- Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications. Table 25. 12-bit ADC operating conditions
1.13 VDDA VDDA V 3
- 8-bit / 10-bit / 12-bit modes — 4 5 pF — RADIN Input series resistance — 2 5 kΩ — Table continues on the next page... Peripheral operating requirements and behaviors Kinetis KL24 Sub-Family, Rev5 08/2014. 27 Freescale Semiconductor, Inc.
Table 25. 12-bit ADC operating conditions (continued)
- Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
- For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
- This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
RAS/CAS time constant should be kept to < 1 ns.
- To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
- For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Figure 7. ADC input impedance equivalency diagram 28 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Table 26. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC = 1, ADHSC =
- ADLPC = 1, ADHSC =
- ADLPC = 0, ADHSC =
- ADLPC = 0, ADHSC = 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12-bit modes
- <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
- 12-bit modes
- <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
- 12-bit modes
- <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
- <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
- 12-bit modes — — ±0.5 LSB4 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 6 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 6 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. Peripheral operating requirements and behaviors Kinetis KL24 Sub-Family, Rev5 08/2014. 29 Freescale Semiconductor, Inc.
- The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
MHz ADC conversion clock speed.
- 1 LSB = (VREFH - VREFL)/2N
- ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
- ADC conversion clock < 3 MHz
Figure 8. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V Table continues on the next page... Peripheral operating requirements and behaviors 30 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Table 27. Comparator and 6-bit DAC electrical specifications (continued)
- Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
- Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Freescale Semiconductor, Inc.
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
3.8.1 USB electrical specifications
specifications for certification. 32 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
3.8.2 USB VREG electrical specifications
Table 28. USB VREG electrical specifications
- VREGIN = 5.0 V and temperature=25 °C
- Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
- Run mode
- Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.8.3 SPI switching specifications
used for communicating with slower peripheral devices. as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Freescale Semiconductor, Inc.
Table 29. SPI master mode timing on slew rate disabled pads
- For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
Table 30. SPI master mode timing on slew rate enabled pads
- For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
34 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Table 31. SPI slave mode timing on slew rate disabled pads (continued)
- For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- Time to data active from high-impedance state
- Hold time to high-impedance state
Table 32. SPI slave mode timing on slew rate enabled pads
- For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- Time to data active from high-impedance state
- Hold time to high-impedance state
36 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
3.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 33. I2C timing Hold time (repeated) START condition.
- The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
- The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
- The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
- Input signal Slew = 10 ns and Output Load = 50 pF
- Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
- A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
- Cb = total capacitance of the one bus line in pF.
Figure 15. Timing definition for fast and standard mode devices on the I2C bus 38 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
3.8.5 UART
See General switching specifications.
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00473D 48-pin QFN 98ASA00466D 64-pin LQFP 98ASS23234W 80-pin LQFP 98ASS23174W
5 Pinout
5.1 KL24 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. LQFP LQFP QFN QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 1 — 1 PTE0 DISABLED PTE0 UART1_TXRTC_ CLKOUT CMP0_OUTI2C1_SDA 2 2 — — PTE1 DISABLED PTE1 SPI1_MOSIUART1_RX SPI1_MISOI2C1_SCL 3 — — — PTE2 DISABLED PTE2 SPI1_SCK 4 — — — PTE3 DISABLED PTE3 SPI1_MISO SPI1_MOSI 5 — — — PTE4 DISABLED PTE4 SPI1_PCS0 Dimensions Kinetis KL24 Sub-Family, Rev5 08/2014. 39 Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 6 — — — PTE5 DISABLED PTE5 7 3 1 — VDD VDD VDD 8 4 2 2 VSS VSS VSS 9 5 3 3 USB0_DPUSB0_DPUSB0_DP 10 6 4 4 USB0_DMUSB0_DMUSB0_DM 11 7 5 5 VOUT33 VOUT33 VOUT33 12 8 6 6 VREGIN VREGIN VREGIN 13 9 7 — PTE20 ADC0_SE0ADC0_SE0PTE20 TPM1_CH0UART0_TX 14 10 8 — PTE21 ADC0_SE4aADC0_SE4aPTE21 TPM1_CH1UART0_RX 15 11 — — PTE22 ADC0_SE3ADC0_SE3PTE22 TPM2_CH0UART2_TX 16 12 — — PTE23 ADC0_SE7aADC0_SE7aPTE23 TPM2_CH1UART2_RX 17 13 9 7 VDDA VDDA VDDA 18 14 10 — VREFH VREFH VREFH 19 15 11 — VREFL VREFL VREFL 20 16 12 8 VSSA VSSA VSSA 21 17 13 — PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_ CLKIN0 22 18 14 9 PTE30 ADC0_SE23/ CMP0_IN4 ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_ CLKIN1 23 19 — — PTE31 DISABLED PTE31 TPM0_CH4 24 20 15 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 25 21 16 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 26 22 17 10 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 27 23 18 11 PTA1 DISABLED PTA1 UART0_RXTPM2_CH0 28 24 19 12 PTA2 DISABLED PTA2 UART0_TXTPM2_CH1 29 25 20 13 PTA3 SWD_DIO PTA3 I2C1_SCLTPM0_CH0 SWD_DIO 30 26 21 14 PTA4 NMI_b PTA4 I2C1_SDATPM0_CH1 NMI_b 31 27 — — PTA5 DISABLED PTA5 USB_CLKINTPM0_CH2 32 28 — — PTA12 DISABLED PTA12 TPM1_CH0 33 29 — — PTA13 DISABLED PTA13 TPM1_CH1 34 — — — PTA14 DISABLED PTA14 SPI0_PCS0UART0_TX 35 — — — PTA15 DISABLED PTA15 SPI0_SCKUART0_RX 36 — — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO 37 — — — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI 38 30 22 15 VDD VDD VDD 39 31 23 16 VSS VSS VSS 40 32 24 17 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RXTPM_ CLKIN0 41 33 25 18 PTA19 XTAL0 XTAL0 PTA19 UART1_TXTPM_ CLKIN1 LPTMR0_ ALT1 42 34 26 19 PTA20 RESET_b PTA20 RESET_b Pinout 40 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 43 35 27 20 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCLTPM1_CH0 44 36 28 21 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDATPM1_CH1 45 37 29 — PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCLTPM2_CH0 46 38 30 — PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDATPM2_CH1 47 — — — PTB8 DISABLED PTB8 EXTRG_IN 48 — — — PTB9 DISABLED PTB9 49 — — — PTB10 DISABLED PTB10 SPI1_PCS0 50 — — — PTB11 DISABLED PTB11 SPI1_SCK 51 39 31 — PTB16 DISABLED PTB16 SPI1_MOSIUART0_RXTPM_ CLKIN0 SPI1_MISO 52 40 32 — PTB17 DISABLED PTB17 SPI1_MISOUART0_TXTPM_ CLKIN1 SPI1_MOSI 53 41 — — PTB18 DISABLED PTB18 TPM2_CH0 54 42 — — PTB19 DISABLED PTB19 TPM2_CH1 55 43 33 — PTC0 ADC0_SE14ADC0_SE14PTC0 EXTRG_IN CMP0_OUT 56 44 34 22 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15ADC0_SE15PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 57 45 35 23 PTC2 ADC0_SE11ADC0_SE11PTC2 I2C1_SDA TPM0_CH1 58 46 36 24 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 UART1_RXTPM0_CH2CLKOUT 59 47 — — VSS VSS VSS 60 48 — — VDD VDD VDD 61 49 37 25 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXTPM0_CH3 62 50 38 26 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 CMP0_OUT 63 51 39 27 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_IN SPI0_MISO 64 52 40 28 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISO SPI0_MOSI 65 53 — — PTC8 CMP0_IN2CMP0_IN2PTC8 I2C0_SCLTPM0_CH4 66 54 — — PTC9 CMP0_IN3CMP0_IN3PTC9 I2C0_SDATPM0_CH5 67 55 — — PTC10 DISABLED PTC10 I2C1_SCL 68 56 — — PTC11 DISABLED PTC11 I2C1_SDA 69 — — — PTC12 DISABLED PTC12 TPM_ CLKIN0 70 — — — PTC13 DISABLED PTC13 TPM_ CLKIN1 71 — — — PTC16 DISABLED PTC16 72 — — — PTC17 DISABLED PTC17 73 57 41 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 74 58 42 — PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK TPM0_CH1 Pinout Kinetis KL24 Sub-Family, Rev5 08/2014. 41 Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 75 59 43 — PTD2 DISABLED PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISO 76 60 44 — PTD3 DISABLED PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSI 77 61 45 29 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0UART2_RXTPM0_CH4 78 62 46 30 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI1_SCKUART2_TXTPM0_CH5 79 63 47 31 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI1_MOSIUART0_RX SPI1_MISO 80 64 48 32 PTD7 DISABLED PTD7 SPI1_MISOUART0_TX SPI1_MOSI
5.2 KL24 pinouts
The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL24 Signal Multiplexing and Pin Assignments. Pinout 42 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Figure 16. KL24 80-pin LQFP pinout diagram Freescale Semiconductor, Inc.
Figure 17. KL24 64-pin LQFP pinout diagram 44 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Figure 18. KL24 48-pin QFN pinout diagram Freescale Semiconductor, Inc.
Figure 19. KL24 32-pin QFN pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts
7 Part identification
46 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
7.1 Description
values of these fields to determine the specific part you have received.
7.2 Format
7.3 Fields
Table 34. Part number fields descriptions
- P = Prequalification KL## Kinetis family • KL24 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 32 = 32 KB
- 64 = 64 KB R Silicon revision • (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- FT = 48 QFN (7 mm x 7 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- LK = 80 LQFP (12 mm x 12 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
7.4 Example
Freescale Semiconductor, Inc.
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
8.2.1 Example
This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA Terminology and guidelines 48 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V Terminology and guidelines Kinetis KL24 Sub-Family, Rev5 08/2014. 49 Freescale Semiconductor, Inc.
8.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
8.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. Terminology and guidelines 50 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: Terminology and guidelines Kinetis KL24 Sub-Family, Rev5 08/2014. 51 Freescale Semiconductor, Inc.
150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Table 35. Typical value conditions
9 Revision history
The following table provides a revision history for this document. Table 36. Revision history 2 9/2012 Completed all the TBDs, initial public release. Table continues on the next page...
Revision history
52 Kinetis KL24 Sub-Family, Rev5 08/2014. Freescale Semiconductor, Inc.
Table 36. Revision history (continued)
- Added a note to the I LAT in the ESD handling ratings
- Updated Voltage and current operating ratings
- Updated Voltage and current operating requirements
- Updated the Voltage and current operating behaviors
- Updated Power mode transition operating behaviors
- Updated Capacitance attributes
- Updated footnote in the Device clock specifications
- Updated t ersall in the Flash timing specifications — commands
- Updated VADIN in the 12-bit ADC operating conditions
- Updated Temp sensor slope and voltage and added a note to them in the 12-bit ADC electrical characteristics
- Removed T A in the 12-bit DAC operating requirements
- Added Inter-Integrated Circuit Interface (I2C) timing 5 08/2014 • Updated related source and added block diagram in the front page
- Updated Power consumption operating behaviors
- Updated the note in USB electrical specifications
- Changed pin name from RESET_b to PTA20 and added RESET_b to ALT7 in KL24 Signal Multiplexing and Pin Assignments; and synchronized this in all the package pinout drawings.
Kinetis KL24 Sub-Family, Rev5 08/2014. 53 Freescale Semiconductor, Inc.
How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Document Number KL24P80M48SF0 Revision 5 08/2014 © 2012-2014 Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.