KL24P80M48SF0 FREESCALE | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 48
Technical content
Features
- Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
- Performance – Up to 48 MHz ARM® Cortex-M0+ core
- Memories and memory interfaces – Up to 64 KB program flash memory – Up to 8 KB RAM
- Clocks – 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator – Multi-purpose clock source
- System peripherals – Nine low-power modes to provide power optimization based on application requirements – 4-channel DMA controller, supporting up to 63 request sources – COP Software watchdog – Low-leakage wakeup unit – SWD interface and Micro Trace buffer – Bit Manipulation Engine (BME)
- Security and integrity modules – 80-bit unique identification (ID) number per chip
- Human-machine interface – General-purpose input/output
- Analog modules – 12-bit SAR ADC – Analog comparator (CMP) containing a 6-bit DAC and programmable reference input
- Timers – Six channel Timer/PWM (TPM) – Two 2-channel Timer/PWM (TPM) – Periodic interrupt timers – 16-bit low-power timer (LPTMR) – Real-time clock
- Communication interfaces – USB full-/low-speed On-the-Go controller with on- chip transceiver and 5 V to 3.3 V regulator – Two 8-bit SPI modules – Two I2C modules – One low power UART module – Two UART modules Freescale Semiconductor Document Number: KL24P80M48SF0 Data Sheet: Technical Data Rev. 3, 9/19/2012 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012 Freescale Semiconductor, Inc.
3.6 Relationship between ratings and operating
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 2 Freescale Semiconductor, Inc.
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PKL24 and MKL24
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q KL## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification KL## Kinetis family • KL24 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 32 = 32 KB
- 64 = 64 KB R Silicon revision • (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105 Table continues on the next page... Ordering parts KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 3
- FT = 48 QFN (7 mm x 7 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- LK = 80 LQFP (12 mm x 12 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
This is an example part number: MKL24Z64VLK4
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. Terminology and guidelines KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 4 Freescale Semiconductor, Inc.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating: Terminology and guidelines KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 5
Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
3.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.
3.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements: Terminology and guidelines KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 6 Freescale Semiconductor, Inc.
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: Terminology and guidelines KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 7
150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V
4 Ratings
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Ratings KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 8 Freescale Semiconductor, Inc.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol Description Min. Max. Unit VDD Digital supply voltage –0.3 3.8 V IDD Digital supply current — 120 mA VDIO Digital pin input voltage (except RESET) –0.3 3.6 V VAIO Analog pins1and RESET pin input voltage –0.3 VDD + 0.3 V ID Instantaneous maximum current single pin limit (applies to all port pins) –25 25 mA VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB_DP USB_DP input voltage –0.3 3.63 V VUSB_DM USB_DM input voltage –0.3 3.63 V VREGIN USB regulator input –0.3 6.0 V 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 9
5.1 AC electrical characteristics
Figure 1. Input signal measurement reference
- have C L=30pF loads,
- are slew rate disabled, and
- are normal drive strength
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V Table continues on the next page... General KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 10 Freescale Semiconductor, Inc.
Table 1. Voltage and current operating requirements (continued)
- V IN < VSS-0.3V -5 — mA IICAIO Analog2 pin DC injection current — single pin
- V IN < VSS-0.3V (Negative current injection)
- V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
- Negative current injection
- Positive current injection -25 +25 mA VRAM VDD voltage required to retain RAM 1.2 — V 1. All digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
5.2.2 LVD and POR operating requirements
Table 2. V DD supply LVD and POR operating requirements
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V Table continues on the next page... General KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 11
Table 2. V DD supply LVD and POR operating requirements (continued)
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage
5.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -5 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -1.5 mA VDD – 0.5 VDD – 0.5 V V VOH Output high voltage — High drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = -18 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOH = -6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — Normal drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 1.5 mA 0.5 0.5 V V VOL Output low voltage — High drive pad
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 18 mA
- 1.71 V ≤ V DD ≤ 2.7 V, IOL = 6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 2 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2 IIN Input leakage current (total all pins) for full temperature range — 65 μA 2 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA Table continues on the next page... General KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 12 Freescale Semiconductor, Inc.
Table 3. Voltage and current operating behaviors (continued)
- PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
- Measured at VDD supply voltage = VDD min and Vinput = VSS
- Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
- CPU and system clocks = 48 MHz
- Bus and flash clock = 24 MHz
- FEI clock mode
Table 4. Power mode transition operating behaviors
- VLLS0 → RUN 115 μs
- VLLS1 → RUN 115 μs
- VLLS3 → RUN μs
- LLS → RUN 4.6 μs
- VLPS → RUN 4.4 μs
- STOP → RUN 4.4 μs General KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 13
5.2.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
- at 3.0 V 6.4 mA IDD_RUNCO Run mode current in compute operation - 48 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash
- at 3.0 V 4.1 5.2 mA IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code of while(1) loop executing from flash
- at 3.0 V 5.1 6.3 mA IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code of while(1) loop executing from flash
- at 3.0 V
- at 25 °C
- at 125 °C 6.4 6.8 7.8 8.3 mA mA 3, 4, IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
- at 3.0 V — 3.7 5.0 mA IDD_WAIT Wait mode current - core disabled / 24 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
- at 3.0 V — 2.9 4.2 mA IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus
- at 3.0 V — 2.5 3.7 mA IDD_VLPRCO Very low power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code of while(1) loop executing from flash
- at 3.0 V — 188 570 μA IDD_VLPR Very low power run mode current - 4 MHz core /
0.8 MHz bus and flash, all peripheral clocks
- at 3.0 V — 224 613 μA Table continues on the next page... General KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 14 Freescale Semiconductor, Inc.
Table 5. Power consumption operating behaviors (continued)
- at 3.0 V — 300 745 μA 5, 4 IDD_VLPW Very low power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
- at 3.0 V — 135 496 μA 5 IDD_STOP Stop mode current at 3.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C 345 357 392 438 551 490 827 869 927 1065 μA IDD_VLPS Very-low-power stop mode current at 3.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C 4.4 112 201 μA IDD_LLS Low leakage stop mode current at 3.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C 1.9 3.6 6.5 3.7 μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V at 25 °C at 50 °C at 70 °C at 85 °C at 105 °C 1.4 2.5 5.1 9.2 3.2 μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0V at 25°C at 50°C at 70°C at 85°C at 105°C 0.7 1.3 2.3 5.1 1.4 μA Table continues on the next page... General KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 15
- The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
- MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for
- MCG configured for FEI mode.
- Incremental current consumption from peripheral activity is not included.
- MCG configured for BLPI mode.
Table 6. Low power mode peripheral adders — typical value VLPS mode with 4 MHz IRC enabled. mode with the 32 kHz IRC enabled. IEREFSTEN4MHz External 4MHz crystal clock adder. mode with the crystal enabled. Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 16 Freescale Semiconductor, Inc.
Table 6. Low power mode peripheral adders — typical value (continued) single external input for compare. Includes 6-bit DAC power consumption. the RTC ALARM set for 1 minute. for RX data at 115200 baud rate. Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FBE for run mode, and BLPE for VLPR mode
- USB regulator disabled
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFA General KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 18 Freescale Semiconductor, Inc.
Figure 2. Run mode supply current vs. core frequency KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Figure 3. VLPR mode current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 64-pin LQFP
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
measured orientations in each frequency range. KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 20 Freescale Semiconductor, Inc.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
5.2.7 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
5.3 Switching specifications
5.3.1 Device clock specifications
Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
- The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
5.3.2 General Switching Specifications
- The greater synchronous and asynchronous timing must be met.
- This is the shortest pulse that is guaranteed to be recognized.
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 9. Thermal operating requirements KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 22 Freescale Semiconductor, Inc.
5.4.2 Thermal attributes
Table 10. Thermal attributes
48 QFN 32 QFN Unit Notes
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
Environmental Conditions—Forced Convection (Moving Air).
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
- Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
the top of the package and the cold plate.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD Electricals
Table 11. SWD full voltage range electricals Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 12. MCG specifications Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Table 12. MCG specifications (continued)
- f VCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current
- PLL at 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) — 1060 — µA 9 Ipll PLL operating current
- PLL at 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) — 600 — µA 9 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter (RMS)
- f vco = 48 MHz
- f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
- f vco = 48 MHz
- f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 26 Freescale Semiconductor, Inc.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 13. Oscillator DC electrical specifications
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ Table continues on the next page... Peripheral operating requirements and behaviors KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 27
Table 13. Oscillator DC electrical specifications (continued)
- VDD=3.3 V, Temperature =25 °C
- See crystal or resonator manufacturer's recommendation
- Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all
other cases external capacitors must be used..
- When low power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
6.3.2.2 Oscillator frequency specifications
Table 14. Oscillator frequency specifications Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 28 Freescale Semiconductor, Inc.
Table 14. Oscillator frequency specifications (continued)
- Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
- When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 15. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
6.4.1.2 Flash timing specifications — commands
Table 16. Flash command timing specifications
- Assumes 25MHz flash clock frequency.
- Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash high voltage current behaviors
Table 17. Flash high voltage current behaviors
6.4.1.4 Reliability specifications
Table 18. NVM reliability specifications
- Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
- Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 30 Freescale Semiconductor, Inc.
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications. Table 19. 12-bit ADC operating conditions
1.13 VDDA VDDA V 3
- Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
- This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best
time constant should be kept to < 1ns.
- To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
- For guidelines and examples of conversion rate calculation, download the ADC calculator tool
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Figure 6. ADC input impedance equivalency diagram Table 20. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC = 1, ADHSC = 0
- ADLPC = 1, ADHSC = 1
- ADLPC = 0, ADHSC = 0
- ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12-bit modes
- <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
- 12-bit modes
- <12-bit modes ±0.7 ±0.2 -1.1 to +1.9 -0.3 to 0.5 LSB4 5 INL Integral non- linearity
- 12-bit modes
- <12-bit modes ±1.0 ±0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
- <12-bit modes -1.4 -5.4 -1.8 LSB4 VADIN = VDDA Table continues on the next page... Peripheral operating requirements and behaviors KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 32 Freescale Semiconductor, Inc.
Table 20. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- 12-bit modes — — ±0.5 LSB4 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device — 1.715 — mV/°C VTEMP25 Temp sensor voltage 25 °C — 719 — mV 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6.6.2 CMP and 6-bit DAC electrical specifications
Table 21. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V Table continues on the next page... Peripheral operating requirements and behaviors KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 33
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
6.8.1 USB electrical specifications
standards, visit http://www.usb.org.
6.8.2 USB VREG electrical specifications
Table 22. USB VREG electrical specifications
- VREGIN = 5.0 V and temperature=25C
- Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
- Run mode
- Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. Peripheral operating requirements and behaviors KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 35
6.8.3 SPI switching specifications
communicating with slower peripheral devices. well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 23. SPI master mode timing on slew rate disabled pads
- For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
Table 24. SPI master mode timing on slew rate enabled pads Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 36 Freescale Semiconductor, Inc.
Table 24. SPI master mode timing on slew rate enabled pads (continued)
- For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- If configured as an output.
Figure 9. SPI master mode timing (CPHA = 0) KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Figure 10. SPI master mode timing (CPHA = 1) Table 25. SPI slave mode timing on slew rate disabled pads
- For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- Time to data active from high-impedance state
- Hold time to high-impedance state
Table 26. SPI slave mode timing on slew rate enabled pads Table continues on the next page... KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 38 Freescale Semiconductor, Inc.
Table 26. SPI slave mode timing on slew rate enabled pads (continued)
- For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
- Time to data active from high-impedance state
- Hold time to high-impedance state
Figure 11. SPI slave mode timing (CPHA = 0) KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Figure 12. SPI slave mode timing (CPHA = 1)
6.8.4 I2C
See General switching specifications.
6.8.5 UART
See General switching specifications.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 40 Freescale Semiconductor, Inc.
8 Pinout
8.1 KL24 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. LQFP LQFP QFN QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 1 — 1 PTE0 DISABLED PTE0 UART1_TXRTC_CLKOUTCMP0_OUTI2C1_SDA 2 2 — — PTE1 DISABLED PTE1 SPI1_MOSIUART1_RX SPI1_MISOI2C1_SCL 3 — — — PTE2 DISABLED PTE2 SPI1_SCK 4 — — — PTE3 DISABLED PTE3 SPI1_MISO SPI1_MOSI 5 — — — PTE4 DISABLED PTE4 SPI1_PCS0 6 — — — PTE5 DISABLED PTE5 7 3 1 — VDD VDD VDD 8 4 2 2 VSS VSS VSS 9 5 3 3 USB0_DPUSB0_DPUSB0_DP 10 6 4 4 USB0_DMUSB0_DMUSB0_DM 11 7 5 5 VOUT33 VOUT33 VOUT33 12 8 6 6 VREGIN VREGIN VREGIN 13 9 7 — PTE20 ADC0_SE0ADC0_SE0PTE20 TPM1_CH0UART0_TX 14 10 8 — PTE21 ADC0_SE4aADC0_SE4aPTE21 TPM1_CH1UART0_RX 15 11 — — PTE22 ADC0_SE3ADC0_SE3PTE22 TPM2_CH0UART2_TX 16 12 — — PTE23 ADC0_SE7aADC0_SE7aPTE23 TPM2_CH1UART2_RX 17 13 9 7 VDDA VDDA VDDA 18 14 10 — VREFH VREFH VREFH 19 15 11 — VREFL VREFL VREFL 20 16 12 8 VSSA VSSA VSSA 21 17 13 — PTE29 CMP0_IN5/ ADC0_SE4b CMP0_IN5/ ADC0_SE4b PTE29 TPM0_CH2TPM_CLKIN0 22 18 14 9 PTE30 ADC0_SE23/ CMP0_IN4 ADC0_SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_CLKIN1 23 19 — — PTE31 DISABLED PTE31 TPM0_CH4 24 20 15 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 25 21 16 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 26 22 17 10 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 27 23 18 11 PTA1 DISABLED PTA1 UART0_RXTPM2_CH0 28 24 19 12 PTA2 DISABLED PTA2 UART0_TXTPM2_CH1 Pinout KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 41
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 29 25 20 13 PTA3 SWD_DIO PTA3 I2C1_SCLTPM0_CH0 SWD_DIO 30 26 21 14 PTA4 NMI_b PTA4 I2C1_SDATPM0_CH1 NMI_b 31 27 — — PTA5 DISABLED PTA5 USB_CLKINTPM0_CH2 32 28 — — PTA12 DISABLED PTA12 TPM1_CH0 33 29 — — PTA13 DISABLED PTA13 TPM1_CH1 34 — — — PTA14 DISABLED PTA14 SPI0_PCS0UART0_TX 35 — — — PTA15 DISABLED PTA15 SPI0_SCKUART0_RX 36 — — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO 37 — — — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI 38 30 22 15 VDD VDD VDD 39 31 23 16 VSS VSS VSS 40 32 24 17 PTA18 EXTAL0 EXTAL0 PTA18 UART1_RXTPM_CLKIN0 41 33 25 18 PTA19 XTAL0 XTAL0 PTA19 UART1_TXTPM_CLKIN1 LPTMR0_ ALT1 42 34 26 19 RESET_b RESET_b PTA20 43 35 27 20 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCLTPM1_CH0 44 36 28 21 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDATPM1_CH1 45 37 29 — PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCLTPM2_CH0 46 38 30 — PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDATPM2_CH1 47 — — — PTB8 DISABLED PTB8 EXTRG_IN 48 — — — PTB9 DISABLED PTB9 49 — — — PTB10 DISABLED PTB10 SPI1_PCS0 50 — — — PTB11 DISABLED PTB11 SPI1_SCK 51 39 31 — PTB16 DISABLED PTB16 SPI1_MOSIUART0_RXTPM_CLKIN0SPI1_MISO 52 40 32 — PTB17 DISABLED PTB17 SPI1_MISOUART0_TXTPM_CLKIN1SPI1_MOSI 53 41 — — PTB18 DISABLED PTB18 TPM2_CH0 54 42 — — PTB19 DISABLED PTB19 TPM2_CH1 55 43 33 — PTC0 ADC0_SE14ADC0_SE14PTC0 EXTRG_IN CMP0_OUT 56 44 34 22 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_SE15ADC0_SE15PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 57 45 35 23 PTC2 ADC0_SE11ADC0_SE11PTC2 I2C1_SDA TPM0_CH1 58 46 36 24 PTC3/ LLWU_P7 DISABLED PTC3/ LLWU_P7 UART1_RXTPM0_CH2CLKOUT 59 47 — — VSS VSS VSS 60 48 — — VDD VDD VDD 61 49 37 25 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXTPM0_CH3 62 50 38 26 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 CMP0_OUT 63 51 39 27 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_IN SPI0_MISO Pinout KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 42 Freescale Semiconductor, Inc.
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 64 52 40 28 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISO SPI0_MOSI 65 53 — — PTC8 CMP0_IN2CMP0_IN2PTC8 I2C0_SCLTPM0_CH4 66 54 — — PTC9 CMP0_IN3CMP0_IN3PTC9 I2C0_SDATPM0_CH5 67 55 — — PTC10 DISABLED PTC10 I2C1_SCL 68 56 — — PTC11 DISABLED PTC11 I2C1_SDA 69 — — — PTC12 DISABLED PTC12 TPM_CLKIN0 70 — — — PTC13 DISABLED PTC13 TPM_CLKIN1 71 — — — PTC16 DISABLED PTC16 72 — — — PTC17 DISABLED PTC17 73 57 41 — PTD0 DISABLED PTD0 SPI0_PCS0 TPM0_CH0 74 58 42 — PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCK TPM0_CH1 75 59 43 — PTD2 DISABLED PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISO 76 60 44 — PTD3 DISABLED PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSI 77 61 45 29 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI1_PCS0UART2_RXTPM0_CH4 78 62 46 30 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI1_SCKUART2_TXTPM0_CH5 79 63 47 31 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI1_MOSIUART0_RX SPI1_MISO 80 64 48 32 PTD7 DISABLED PTD7 SPI1_MISOUART0_TX SPI1_MOSI
8.2 KL24 Pinouts
The below figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 43
Figure 13. KL24 80-pin LQFP pinout diagram KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 44 Freescale Semiconductor, Inc.
Figure 14. KL24 64-pin LQFP pinout diagram KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012.
Figure 15. KL24 48-pin QFN pinout diagram KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 46 Freescale Semiconductor, Inc.
PTD6/LLWU_P15 PTD5 PTD4/LLWU_P14 PTC7 PTC6/LLWU_P10 PTC5/LLWU_P9 PTC4/LLWU_P8 PTA2 PTA1 PTA0 PTE30 VSS VDD PTA4 PTA3 PTB0/LLWU_P5 RESET_b PTA19 PTA18 PTC3/LLWU_P7 PTC2 PTC1/LLWU_P6/RTC_CLKIN PTB1 VSSA VDDA VREGIN VOUT33 USB0_DM USB0_DP VSS PTE0 Figure 16. KL24 32-pin QFN pinout diagram
9 Revision History
The following table provides a revision history for this document. Table 27. Revision History 1 7/2012 Initial NDA release. 2 9/2012 Completed all the TBDs, initial public release.
Revision History
KL24 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. Freescale Semiconductor, Inc. 47
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com Document Number: KL24P80M48SF0 Rev. 3, 9/19/2012 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductors products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-complaint and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.