Microcontroller

MKL13Z32VFM4

NXP Semiconductors

Kinetis KL13 Microcontroller Rev. 2, 03/2015

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Technical content

Kinetis KL13 Microcontroller

48 MHz ARM® Cortex®-M0+ and 64 KB Flash

The KL13 series is optimized for cost-sensitive and battery- powered applications requiring low-power general purpose connectivity. The product offers:

Embedded ROM with boot loader for flexible program upgrade
High accuracy internal voltage and clock reference
FlexIO to support any standard and customized serial peripheral emulation
Hardware CRC module
Down to 60uA/MHz in very low power run mode and 1.83uA in deep sleep mode (RAM + RTC retained) Core Processor
ARM ® Cortex®-M0+ core up to 48 MHz Memories
32/64 KB program flash memory
4/8 KB SRAM
8 KB ROM with build-in bootloader
32-byte backup register System
4-channel asynchronous DMA controller
Watchdog
Low-leakage wakeup unit
Two-pin Serial Wire Debug (SWD) programming and debug interface
Micro Trace Buffer
Bit manipulation engine
Interrupt controller Clocks
48 MHz high accuracy (up to 0.5%) internal reference clock
8MHz/2MHz high accuracy (up to 3%) internal reference clock
1KHz reference clock active under all low-power modes (except VLLS0)
32–40KHz and 3–32MHz crystal oscillator Peripherals
One UART module supporting ISO7816, operating up to 1.5 Mbit/s
Two low-power UART modules supporting asynchronous operation in low-power modes
Two I2C modules and I2C0 supporting up to 1 Mbit/s
Two 16-bit SPI modules supporting up to 24 Mbit/s
One FlexIO module supporting emulation of additional UART, IrDA, SPI, I2C, PWM and other serial modules, etc.
One 16-bit 818 ksps ADC module with high accuracy internal voltage reference (Vref) and up to 20 channels
High-speed analog comparator containing a 6-bit DAC for programmable reference input
One 12-bit DAC
1.2 V internal voltage reference Timers
One 6-channel Timer/PWM module
Two 2-channel Timer/PWM modules
One low-power timer
Periodic interrupt timer
Real time clock MKL13Z32Vxx4 MKL13Z64Vxx4

64 LQFP

10x10 mm P 0.5 mm

80 LQFP

12x12 mm P 0.5 mm

48 QFN

7x7 mm P 0.5 mm

32 QFN

5x5 mm P 0.5 mm Freescale Semiconductor, Inc. KL13P80M48SF3 Data Sheet: Technical Data Rev. 2, 03/2015 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2014–2015 Freescale Semiconductor, Inc. All rights reserved.

Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range: –40 to 105 °C Packages
80 LQFP 12mm x 12mm, 0.5mm pitch, 1.6mm thickness
64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm thickness
64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm thickness (Package Your Way)
48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness (Package Your Way)
32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness (Package Your Way) Security and Integrity
80-bit unique identification number per chip
Advanced flash security
Hardware CRC module I/O
Up to 70 general-purpose input/output pins (GPIO) and 4 high-drive pad Low Power
Down to 60uA/MHz in very low power run mode
Down to 1.83uA in VLLS3 mode (RAM + RTC retained)
Six flexible static modes

Ordering Information

Product Memory Package IO and ADC channel Part number Marking (Line1/ Line2) Flash (KB) SRAM (KB) Pin count Package GPIOs GPIOs (INT/HD)1 ADC channels (SE/DP) MKL13Z32VFM4 TBD 32 4 32 QFN 28 28/4 11/2 MKL13Z64VFM4 TBD 64 8 32 QFN 28 28/4 11/2 MKL13Z32VFT4 TBD 32 4 48 QFN 40 40/4 18/3 MKL13Z64VFT4 TBD 64 8 48 QFN 40 40/4 18/3 MKL13Z32VLH4 MKL13Z32/VLH4 32 4 64 LQFP 54 54/4 20/4 MKL13Z64VLH4 MKL13Z64/VLH4 64 8 64 LQFP 54 54/4 20/4 MKL13Z32VMP4 TBD 32 4 64 MAPBGA 54 54/4 20/4 MKL13Z64VMP4 TBD 64 8 64 MAPBGA 54 54/4 20/4 MKL13Z32VLK4 MKL13Z32VLK4 32 4 80 LQFP 70 70/4 20/4 MKL13Z64VLK4 MKL13Z64VLK4 64 8 80 LQFP 70 70/4 20/4 1. INT: interrupt pin numbers; HD: high drive pin numbers NOTE The 32 QFN, 48 QFN, and 64 MAPBGA packages supporting MKLx3ZxxVFT4, MKLx3ZxxVFM4, and MKLx3ZxxVMP4 part numbers for this product are not yet available. However, these packages are included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. KL1xPB1 Table continues on the next page... 2 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Related Resources (continued) Type Description Resource Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KL13P80M48SF3RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_L_0N01P1 Package drawing Package dimensions are provided in package drawings. • 64-LQFP: 98ASS23234W 1

64 MAPBGA: 98ASA00420D1
48 QFN: 98ASA00616D 1
80 LQFP: 98ASS23174W 1
32 QFN: 98ASA00615D 1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. Kinetis KL13 Microcontroller, Rev.2, 03/2015. 3 Freescale Semiconductor, Inc.

5.2.1 Inter-Integrated Circuit Interface (I2C) timing.. 45

11.6 Relationship between ratings and operating

4 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

1 Ratings

1.1 Thermal handling ratings

Table 1. Thermal handling ratings

Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 2. Moisture handling ratings

Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Table 3. ESD handling ratings

Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

Freescale Semiconductor, Inc.

1.4 Voltage and current operating ratings

Table 4. Voltage and current operating ratings

2 General

2.1 AC electrical characteristics

Figure 1. Input signal measurement reference output pins have the following characteristics.

C L=30 pF loads
Slew rate disabled
Normal drive strength

2.2 Nonswitching electrical specifications

6 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

2.2.1 Voltage and current operating requirements

Table 5. Voltage and current operating requirements

2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO IO pin negative DC injection current — single pin
V IN < VSS-0.3V -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VSRAM VDD voltage required to retain SRAM 1.2 — V 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 6. V DD supply LVD and POR operating requirements Table continues on the next page... Freescale Semiconductor, Inc.

Table 6. V DD supply LVD and POR operating requirements (continued)

Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 7. Voltage and current operating behaviors

2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = –1.5 mA VDD – 0.5 VDD – 0.5 V V VOH Output high voltage — high drive pad
2.7 V ≤ V DD ≤ 3.6 V, IOH = –18 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = –6 mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOL Output low voltage — normal drive pad
2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 1.5 mA 0.5 0.5 V V VOL Output low voltage — high drive pad 1 Table continues on the next page... General 8 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Table 7. Voltage and current operating behaviors (continued)

2.7 V ≤ V DD ≤ 3.6 V, IOL = 18 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 2 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 2 IIN Input leakage current (total all pins) for full temperature range — 80 μA 2 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 3 1. PTB0, PTB1, PTC3, and PTD7 I/O have both high drive and normal drive capability selected by the associated PORTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. Measured at VDD = 3.6 V 3. Measured at VDD supply voltage = VDD min and Vinput = VSS

2.2.4 Power mode transition operating behaviors

CPU and system clocks = 48 MHz
Bus and flash clock = 24 MHz
HIRC clock mode

Table 8. Power mode transition operating behaviors

VLLS0 → RUN 152 166 μs
VLLS1 → RUN 152 166 μs
VLLS3 → RUN 104 μs
LLS → RUN 7.5 μs Table continues on the next page... General Kinetis KL13 Microcontroller, Rev.2, 03/2015. 9 Freescale Semiconductor, Inc.

Table 8. Power mode transition operating behaviors (continued)

VLPS → RUN 7.5 μs
STOP → RUN 7.5 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11)

2.2.5 Power consumption operating behaviors

equivalent to the mean plus three times the standard deviation (mean + 3 sigma). The while (1) test is executed with flash cache enabled. Table 9. Power consumption operating behaviors

at 25 °C
at 105 °C 4.74 4.9 4.93 5.10 mA IDD_RUNCO Running While(1) loop in flash in compute operation mode—48M HIRC mode, 48 MHz core / 24 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 3.27 3.42 3.43 3.59 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock disable 48 MHz core/24 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 5.63 5.79 5.86 6.02 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 3.47 3.63 3.61 3.78 mA Table continues on the next page... General 10 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Table 9. Power consumption operating behaviors (continued)

at 25 °C
at 105 °C 2.37 2.53 2.56 2.73 mA IDD_RUN Run mode current—48M HIRC mode, running CoreMark in Flash all peripheral clock enable 48 MHz core/24 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 6.91 7.07 7.19 7.35 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in flash all peripheral clock disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 4.14 4.3 4.31 4.47 mA IDD_RUN Run mode current—48M HIRC mode, running While(1) loop in Flash all peripheral clock disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 2.7 2.86 2.92 3.09 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 1.99 2.14 2.15 2.31 mA IDD_RUN Run mode current—48M HIRC mode, Running While(1) loop in Flash all peripheral clock enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
at 25 °C
at 105 °C 5.39 5.56 5.61 5.78 mA IDD_VLPRCO Very Low Power Run Core Mark in Flash in Compute Operation mode: Core@4MHz, Flash @1MHz, VDD = 3.0 V
at 25 °C 739 827.68 μA IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in compute operation mode— 8 MHz LIRC mode, 4 MHz core / 1 MHz flash, VDD = 3.0 V
at 25 °C 339 406.8 μA IDD_VLPRCO Very-low-power run While(1) loop in SRAM in compute operation mode:—2 MHz LIRC mode, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
at 25 °C 152 197.6 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral Table continues on the next page... General Kinetis KL13 Microcontroller, Rev.2, 03/2015. 11 Freescale Semiconductor, Inc.

at 25 °C 119 178.5 μA IDD_VLPR Very-low-power run mode current— 2 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
at 25 °C 89.39 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
at 25 °C 277 360.1 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in flash all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
at 25 °C 343 425.32 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM in all peripheral clock disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
at 25 °C 375 450 μA IDD_VLPR Very-low-power run mode current— 8 MHz LIRC mode, While(1) loop in SRAM all peripheral clock enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
at 25 °C 441 529.2 μA IDD_VLPR Very-low-power run mode current—2 MHz LIRC mode, While(1) loop in SRAM all peripheral clock disable, 125 kHz core / 31.25 kHz flash, VDD = 3.0 V
at 25 °C 103.5 μA IDD_WAIT Wait mode current—core disabled, 48 MHz system/24 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V
at 25 °C 2.14 2.50 mA IDD_WAIT Wait mode current—core disabled, 24 MHz system/12 MHz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, MCG_Lite under HIRC mode, VDD = 3.0 V
at 25 °C 1.41 1.62 mA IDD_VLPW Very-low-power wait mode current, core disabled, 4 MHz system/ 1 MHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V
at 25 °C 193 239.023 μA Table continues on the next page... General 12 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

at 25 °C 124.8 μA IDD_VLPW Very-low-power wait mode current, core disabled, 125 kHz system/ 31.25 kHz bus and flash, all peripheral clocks disabled, VDD = 3.0 V
at 25 °C μA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12 MHz bus and flash, VDD = 3.0 V
at 25 °C 1.72 2.06 mA IDD_PSTOP2 Partial Stop 2, core and system clock disabled, flash doze enabled, 12 MHz bus, VDD = 3.0 V
at 25 °C 1.1 1.32 mA IDD_STOP Stop mode current at 3.0 V
at 25 °C and below
at 50 °C
at 85 °C
at 105 °C 161 171.9 206.8 255.9 178.2 181.17 229.72 302.01 μA IDD_VLPS Very-low-power stop mode current at 3.0 V
at 25 °C and below
at 50 °C
at 85 °C
at 105 °C 2.20 4.57 18.02 39.60 3.80 8.03 31.98 65.80 μA IDD_VLPS Very-low-power stop mode current at 1.8 V
at 25 °C and below
at 50 °C
at 85 °C
at 105 °C 2.13 4.42 17.53 38.55 3.80 7.94 31.58 65.18 μA IDD_LLS Low-leakage stop mode current, all peripheral disable, at 3.0 V
at 25 °C and below
at 50 °C
at 70 °C
at 85 °C
at 105 °C 1.63 2.42 4.22 7.16 15.34 2.25 3.55 7.08 10.22 22.69 μA IDD_LLS Low-leakage stop mode current with RTC current, at 3.0 V
at 25 °C and below 2.3 2.99 μA Table continues on the next page... General Kinetis KL13 Microcontroller, Rev.2, 03/2015. 13 Freescale Semiconductor, Inc.

at 50 °C
at 70 °C
at 85 °C
at 105 °C 3.12 4.96 7.93 16.02 4.50 7.71 10.75 22.99 IDD_LLS Low-leakage stop mode current with RTC current, at 1.8 V
at 25 °C and below
at 50 °C
at 70 °C
at 85 °C
at 105 °C 2.03 2.81 4.53 7.31 14.93 2.55 3.95 7.30 10.25 22.72 μA IDD_VLLS3 Very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 V
at 25 °C and below
at 50 °C
at 70 °C
at 85 °C
at 105 °C 1.16 1.72 3.04 5.21 11.33 1.65 2.65 5.70 7.79 17.63 μA IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 3.0 V
at 25 °C and below
at 50 °C
at 70 °C
at 85 °C
at 105 °C 1.83 2.43 3.78 5.98 12.02 2.35 3.39 5.95 8.14 17.89 μA IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC current, at 1.8 V
at 25 °C and below
at 50 °C
at 70 °C
at 85 °C
at 105 °C 1.58 2.13 3.37 5.4 10.99 1.98 3.17 5.80 7.83 16.86 μA IDD_VLLS1 Very-low-leakage stop mode 1 current all peripheral disabled at 3.0 V
at 25 °C and below
at 50°C
at 70°C 0.62 0.99 1.88 3.41 1.06 1.43 2.65 4.53 μA Table continues on the next page... General 14 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

at 85°C
at 105 °C — 7.89 9.99 IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 3.0 V
at 25 °C and below
at 50°C
at 70°C
at 85°C
at 105 °C 1.31 1.7 2.6 4.14 8.51 1.52 2.04 3.20 4.69 10.46 μA IDD_VLLS1 Very-low-leakage stop mode 1 current RTC enabled at 1.8 V
at 25 °C and below
at 50°C
at 70°C
at 85°C
at 105 °C 1.06 1.39 2.18 3.54 7.43 1.35 1.73 2.83 4.60 9.97 μA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 0) at 3.0 V
at 25 °C and below
at 50 °C
at 70 °C
at 85 °C
at 105 °C 278 578 1530 3070 7550 385 1013 2015 3617 9900 nA IDD_VLLS0 Very-low-leakage stop mode 0 current all peripheral disabled (SMC_STOPCTRL[PORPO] = 1) at 3 V
at 25 °C and below
at 50 °C
at 70 °C
at 85 °C
at 105 °C 412 1350 2900 7380 218 653 1683 3428 9785 nA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.20 with optimization level high, optimized for balanced. 3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption. General Kinetis KL13 Microcontroller, Rev.2, 03/2015. 15 Freescale Semiconductor, Inc.

Table 10. Low power mode peripheral adders — typical value IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled.

VLLS1
VLLS3
LLS
VLPS
STOP 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 nA ILPTMR LPTMR peripheral adder measured by placing the device in VLLS1 mode with LPTMR enabled using LPO. 100 200 nA ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 16 16 16 16 16 16 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 582 627 638 662 682 760 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Table continues on the next page... General 16 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Table 10. Low power mode peripheral adders — typical value (continued)

IRC8M (8 MHz internal reference clock)
IRC2M (2 MHz internal reference clock) 105 110 110 111 112 114 µA ITPM TPM peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source configured for output compare generating 100 Hz clock signal. No load is placed on the I/O generating the clock signal. Includes selected clock source and I/O switching currents.
IRC8M (8 MHz internal reference clock)
IRC2M (2 MHz internal reference clock) 130 130 130 130 130 130 µA IBG Bandgap adder when BGEN bit is set and device is placed in VLPx or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 320 320 320 320 320 320 µA

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
No GPIOs toggled
Code execution from flash
For the ALLOFF curve, all peripheral clocks are disabled except FTFA General Kinetis KL13 Microcontroller, Rev.2, 03/2015. 17 Freescale Semiconductor, Inc.

Figure 2. Run mode supply current vs. core frequency 18 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Kinetis KL13 Microcontroller, Rev.2, 03/2015. 19 Freescale Semiconductor, Inc.

Figure 3. VLPR mode current vs. core frequency

2.2.6 EMC performance

advice and guidance specifically targeted at optimizing EMC performance.

AN2321: Designing for Board Level Electromagnetic Compatibility
AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications General 20 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems
KL-QRUG (Kinetis L-series Quick Reference).

2.2.7 Capacitance attributes

Table 11. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 12. Device clock specifications

The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

Freescale Semiconductor, Inc.

2.3.2 General switching specifications

Table 13. General switching specifications

The synchronous and asynchronous timing must be met.
This is the shortest pulse that is guaranteed to be recognized.

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 14. Thermal operating requirements

Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

determine TJ is: TJ = TA + θJA × chip power dissipation.

2.4.2 Thermal attributes

included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. 22 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Table 15. Thermal attributes

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Thermal characterization parameter indicating the temperature difference between package top and the junction

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 16. SWD full voltage range electricals Table continues on the next page... Freescale Semiconductor, Inc.

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG-Lite specifications

Table 17. IRC48M specifications Table 18. IRC8M/2M specification

3.3.2 Oscillator electrical specifications

Freescale Semiconductor, Inc.

3.3.2.1 Oscillator DC electrical specifications

Table 19. Oscillator DC electrical specifications

32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Table continues on the next page... Peripheral operating requirements and behaviors 26 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Table 19. Oscillator DC electrical specifications (continued)

VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For

all other cases external capacitors must be used.

When low power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.3.2.2 Oscillator frequency specifications

Table 20. Oscillator frequency specifications

Proper PC board layout procedures must be followed to achieve specifications.
Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

Freescale Semiconductor, Inc.

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 21. NVM program/erase timing specifications

Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 22. Flash command timing specifications

Assumes 25 MHz flash clock frequency.
Maximum times for erase parameters based on expectations at cycling end-of-life.

28 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

3.4.1.3 Flash high voltage current behaviors

Table 23. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 24. NVM reliability specifications

Typical data retention values are based on measured response accelerated at high temperature and derated to a
Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

Freescale Semiconductor, Inc.

Table 25. 16-bit ADC operating conditions

All other modes VREFL VREFL 31/32 * VREFH VREFH V — CADIN Input capacitance
16-bit mode
8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 Ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 Ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Peripheral operating requirements and behaviors 30 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 6. ADC input impedance equivalency diagram Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

ADLPC = 1, ADHSC = 0
ADLPC = 1, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
12-bit modes
<12-bit modes ±2.5 ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
12-bit modes
<12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
12-bit modes — ±0.9 –2.7 to +1.9 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis KL13 Microcontroller, Rev.2, 03/2015. 31 Freescale Semiconductor, Inc.

Table 26. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

<12-bit modes — ±0.4 –0.7 to +0.5 EFS Full-scale error • 12-bit modes
<12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
16-bit modes
≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
Avg = 32
Avg = 4 16-bit single-ended mode
Avg = 32
Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
Avg = 32 16-bit single-ended mode
Avg = 32 –94 –85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
Avg = 32 16-bit single-ended mode
Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA Peripheral operating requirements and behaviors 32 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

3.6.2 Voltage reference electrical specifications

Table 27. VREF full-range operating requirements

CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range

VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1. Table 28. VREF full-range operating behaviors

current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs — Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms — Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load Peripheral operating requirements and behaviors 34 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Table 29. VREF limited-range operating requirements Table 30. VREF limited-range operating behaviors

3.6.3 CMP and 6-bit DAC electrical specifications

Table 31. Comparator and 6-bit DAC electrical specifications

CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors Kinetis KL13 Microcontroller, Rev.2, 03/2015. 35 Freescale Semiconductor, Inc.

Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 36 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 32. 12-bit DAC operating requirements

The DAC reference can be selected to be VDDA or VREFH.
A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Freescale Semiconductor, Inc.

Table 33. 12-bit DAC operating behaviors

High power (SP HP)
Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
High power (SP HP)
Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors 38 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 11. Typical INL error vs. digital code Freescale Semiconductor, Inc.

Figure 12. Offset at half scale vs. temperature

4 Timers

See General switching specifications.

5 Communication interfaces

40 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

5.1 SPI switching specifications

used for communicating with slower peripheral devices. as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 34. SPI master mode timing on slew rate disabled pads

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).

Table 35. SPI master mode timing on slew rate enabled pads Table continues on the next page... Freescale Semiconductor, Inc.

Table 35. SPI master mode timing on slew rate enabled pads (continued)

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
If configured as an output.

Figure 13. SPI master mode timing (CPHA = 0) 42 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 14. SPI master mode timing (CPHA = 1) Table 36. SPI slave mode timing on slew rate disabled pads

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
Time to data active from high-impedance state
Hold time to high-impedance state

Freescale Semiconductor, Inc.

Table 37. SPI slave mode timing on slew rate enabled pads

For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
Time to data active from high-impedance state
Hold time to high-impedance state

Figure 15. SPI slave mode timing (CPHA = 0) 44 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 16. SPI slave mode timing (CPHA = 1)

5.2 I2C

5.2.1 Inter-Integrated Circuit Interface (I2C) timing

Table 38. I2C timing Hold time (repeated) START condition. Freescale Semiconductor, Inc.

The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the

High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.

The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
Input signal Slew = 10 ns and Output Load = 50 pF
Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

Cb = total capacitance of the one bus line in pF.

To counter the effects of clock stretching, the I2C baud Rate select bits can be configured for faster than desired baud rate.
Use high drive pad and DSE bit should be set in PORTx_PCRn register.
Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the SCL line to avoid clock stretching.
Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.

Table 39. I 2C 1Mbit/s timing period, the first clock pulse is generated.

The maximum SCL Clock Frequency of 1Mbit/s can support maximum bus loading when using the High drive pins

across the full voltage range.

Cb = total capacitance of the one bus line in pF.

46 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 17. Timing definition for devices on the I2C bus

5.3 UART

See General switching specifications.

6 Design considerations

6.1 Hardware design considerations

any voltages higher than maximum-rated voltages to this high-impedance circuit.

6.1.1 Printed circuit board recommendations

Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
Drivers and filters for I/O functions should be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground.
Physically isolate analog circuits from digital circuits if possible.
Place input filter capacitors as close to the MCU as possible.
For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages. Design considerations Kinetis KL13 Microcontroller, Rev.2, 03/2015. 47 Freescale Semiconductor, Inc.

6.1.2 Power delivery system

Use a plane for ground.
Use a plane for MCU VDD supply if possible.
Always route ground first, as a plane or continuous surface, and never as sequential segments.
Route power next, as a plane or traces that are parallel to ground traces.
Place bulk capacitance, 10uF or more, at the entrance of the power plane.
Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins.
Take special care to minimize noise levels on the VREFH/VREFL inputs. An option is to use the internal reference voltage (output 1.2V typically) as the ADC reference. NOTE The internal reference voltage output (VREFO) is bonded to the VREFH pin on some packages and to PTE30 on other packages. When the VREFO output is used, a 0.1uF capacitor is required as a filter. Do not connect any other supply voltage to the pin that has VREFO activated.

6.1.3 Analog design

small compared to the sample period. Figure 18. RC circuit for ADC input 48 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 19. High voltage measurement with an ADC input

6.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (max I/O spec is VDD+0.3V).

RESET_b pin The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An external RC circuit is recommended to filter noise as shown in the following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to reject spurious noise. Design considerations Kinetis KL13 Microcontroller, Rev.2, 03/2015. 49 Freescale Semiconductor, Inc.

6.1.5 Crystal oscillator

MCU clock system, refer to the following table and diagrams. external feedback is required when using high gain (HGO=1) mode. frequency above 2MHz does not require any series resistance. Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786kHz) mode. high frequency crystals and resonators. Table 40. External crystal/resonator connections Figure 24. Crystal connection – Diagram 1 52 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 25. Crystal connection – Diagram 25 Figure 26. Crystal connection – Diagram 3 Figure 27. Crystal connection – Diagram 4

6.2 Software considerations

www.freescale.com/kinetis/sw for more information and supporting collateral. Freescale Semiconductor, Inc.

Freescale Freedom Development Platform: http://www.freescale.com/freedom
Tower System Development Platform: http://www.freescale.com/tower IDEs for Kinetis MCUs
Kinetis Design Studio IDE: http://www.freescale.com/kds
Partner IDEs: http://www.freescale.com/kide Development Tools
PEG Graphics Software: http://www.freescale.com/peg
Processor Expert Software and Embedded Components: http://www.freescale.com/ processorexpert ) Run-time Software
Kinetis SDK: http://www.freescale.com/ksdk
Kinetis Bootloader: http://www.freescale.com/kboot
ARM mbed Development Platform: http://www.freescale.com/mbed
MQX RTOS: http://www.freescale.com/mqx For all other partner-developed software and tools, visit http://www.freescale.com/ partners.

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00615D 48-pin QFN 98ASA00616D 64-pin LQFP 98ASS23234W 64-pin MAPBGA 98ASA00420D 80-pin LQFP 98ASS23174W Dimensions 54 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

8.1 KL13 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE The 32 QFN, 48 QFN, and 64 MAPBGA packages for this product are not yet available. However, these packages are included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. LQFP LQFP QFN MAP BGA QFN Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — — — C5 — NC NC NC 1 1 — A1 1 PTE0 DISABLED PTE0/ CLKOUT32 K SPI1_MISOLPUART1_ TX RTC_ CLKOUT CMP0_OUTI2C1_SDA 2 2 — B1 2 PTE1 DISABLED PTE1 SPI1_MOSILPUART1_ RX SPI1_MISOI2C1_SCL 3 — — — — PTE2 DISABLED PTE2 SPI1_SCK 4 — — — — PTE3 DISABLED PTE3 SPI1_MISO SPI1_MOSI 5 — — — — PTE4 DISABLED PTE4 SPI1_PCS0 6 — — — — PTE5 DISABLED PTE5 7 3 1 — — VDD VDD VDD 8 4 2 C4 — VSS VSS VSS 9 5 3 E1 3 PTE16 ADC0_DP1/ ADC0_SE1 ADC0_DP1/ ADC0_SE1 PTE16 SPI0_PCS0UART2_TXTPM_ CLKIN0 FXIO0_D0 10 6 4 D1 4 PTE17 ADC0_ DM1/ ADC0_ SE5a ADC0_ DM1/ ADC0_ SE5a PTE17 SPI0_SCKUART2_RXTPM_ CLKIN1 LPTMR0_ ALT3 FXIO0_D1 11 7 5 E2 5 PTE18 ADC0_DP2/ ADC0_SE2 ADC0_DP2/ ADC0_SE2 PTE18 SPI0_MOSI I2C0_SDASPI0_MISOFXIO0_D2 12 8 6 D2 6 PTE19 ADC0_ DM2/ ADC0_ SE6a ADC0_ DM2/ ADC0_ SE6a PTE19 SPI0_MISO I2C0_SCLSPI0_MOSIFXIO0_D3 13 9 7 G1 — PTE20 ADC0_DP0/ ADC0_SE0 ADC0_DP0/ ADC0_SE0 PTE20 TPM1_CH0LPUART0_ TX FXIO0_D4 Pinouts and Packaging Kinetis KL13 Microcontroller, Rev.2, 03/2015. 55 Freescale Semiconductor, Inc.

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 14 10 8 F1 — PTE21 ADC0_ DM0/ ADC0_ SE4a ADC0_ DM0/ ADC0_ SE4a PTE21 TPM1_CH1LPUART0_ RX FXIO0_D5 15 11 — G2 — PTE22 ADC0_DP3/ ADC0_SE3 ADC0_DP3/ ADC0_SE3 PTE22 TPM2_CH0UART2_TX FXIO0_D6 16 12 — F2 — PTE23 ADC0_ DM3/ ADC0_ SE7a ADC0_ DM3/ ADC0_ SE7a PTE23 TPM2_CH1UART2_RX FXIO0_D7 17 13 9 F4 7 VDDA VDDA VDDA 18 14 10 G4 — VREFH VREFH VREFH 18 14 10 G4 — VREFO VREFO (1,2V reference, bond to VREFH) VREFH 19 15 11 G3 — VREFL VREFL VREFL 20 16 12 F3 8 VSSA VSSA VSSA 21 17 13 H1 — PTE29 CMP0_IN5/ ADC0_ SE4b CMP0_IN5/ ADC0_ SE4b PTE29 TPM0_CH2TPM_ CLKIN0 22 18 14 H2 9 PTE30 DAC0_ OUT/ ADC0_ SE23/ CMP0_IN4 DAC0_ OUT/ ADC0_ SE23/ CMP0_IN4 PTE30 TPM0_CH3TPM_ CLKIN1 LPUART1_ TX LPTMR0_ ALT1 23 19 — H3 — PTE31 DISABLED PTE31 TPM0_CH4 24 20 15 H4 — PTE24 DISABLED PTE24 TPM0_CH0 I2C0_SCL 25 21 16 H5 — PTE25 DISABLED PTE25 TPM0_CH1 I2C0_SDA 26 22 17 D3 10 PTA0 SWD_CLK PTA0 TPM0_CH5 SWD_CLK 27 23 18 D4 11 PTA1 DISABLED PTA1 LPUART0_ RX TPM2_CH0 28 24 19 E5 12 PTA2 DISABLED PTA2 LPUART0_ TX TPM2_CH1 29 25 20 D5 13 PTA3 SWD_DIO PTA3 I2C1_SCLTPM0_CH0 SWD_DIO 30 26 21 G5 14 PTA4 NMI_b PTA4 I2C1_SDATPM0_CH1 NMI_b 31 27 — F5 — PTA5 DISABLED PTA5 TPM0_CH2 32 28 — H6 — PTA12 DISABLED PTA12 TPM1_CH0 33 29 — G6 — PTA13 DISABLED PTA13 TPM1_CH1 34 — — — — PTA14 DISABLED PTA14 SPI0_PCS0LPUART0_ TX 35 — — — — PTA15 DISABLED PTA15 SPI0_SCKLPUART0_ RX 36 — — — — PTA16 DISABLED PTA16 SPI0_MOSI SPI0_MISO Pinouts and Packaging 56 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 37 — — — — PTA17 DISABLED PTA17 SPI0_MISO SPI0_MOSI 38 30 22 G7 15 VDD VDD VDD 39 31 23 H7 16 VSS VSS VSS 40 32 24 H8 17 PTA18 EXTAL0 EXTAL0 PTA18 LPUART1_ RX TPM_ CLKIN0 41 33 25 G8 18 PTA19 XTAL0 XTAL0 PTA19 LPUART1_ TX TPM_ CLKIN1 LPTMR0_ ALT1 42 34 26 F8 19 PTA20 RESET_b PTA20 RESET_b 43 35 27 F7 20 PTB0/ LLWU_P5 ADC0_SE8ADC0_SE8PTB0/ LLWU_P5 I2C0_SCLTPM1_CH0SPI1_MOSISPI1_MISO 44 36 28 F6 21 PTB1 ADC0_SE9ADC0_SE9PTB1 I2C0_SDATPM1_CH1SPI1_MISOSPI1_MOSI 45 37 29 E7 — PTB2 ADC0_ SE12 ADC0_ SE12 PTB2 I2C0_SCLTPM2_CH0 46 38 30 E8 — PTB3 ADC0_ SE13 ADC0_ SE13 PTB3 I2C0_SDATPM2_CH1 47 — — — — PTB8 PTB8 SPI1_PCS0EXTRG_IN 48 — — — — PTB9 PTB9 SPI1_SCK 49 — — — — PTB10 PTB10 SPI1_PCS0 50 — — — — PTB11 PTB11 SPI1_SCK 51 39 31 E6 — PTB16 PTB16 SPI1_MOSILPUART0_ RX TPM_ CLKIN0 SPI1_MISO 52 40 32 D7 — PTB17 PTB17 SPI1_MISOLPUART0_ TX TPM_ CLKIN1 SPI1_MOSI 53 41 — D6 — PTB18 PTB18 TPM2_CH0 54 42 — C7 — PTB19 PTB19 TPM2_CH1 55 43 33 D8 — PTC0 ADC0_ SE14 ADC0_ SE14 PTC0 EXTRG_IN CMP0_OUT 56 44 34 C6 22 PTC1/ LLWU_P6/ RTC_CLKIN ADC0_ SE15 ADC0_ SE15 PTC1/ LLWU_P6/ RTC_CLKIN I2C1_SCL TPM0_CH0 57 45 35 B7 23 PTC2 ADC0_ SE11 ADC0_ SE11 PTC2 I2C1_SDA TPM0_CH1 58 46 36 C8 24 PTC3/ LLWU_P7 PTC3/ LLWU_P7 SPI1_SCKLPUART1_ RX TPM0_CH2CLKOUT 59 47 — E3 — VSS VSS VSS 60 48 — E4 — VDD VDD VDD 61 49 37 B8 25 PTC4/ LLWU_P8 PTC4/ LLWU_P8 SPI0_PCS0LPUART1_ TX TPM0_CH3SPI1_PCS0 62 50 38 A8 26 PTC5/ LLWU_P9 PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 CMP0_OUT 63 51 39 A7 27 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_MOSIEXTRG_IN SPI0_MISO 64 52 40 B6 28 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_MISO SPI0_MOSI Pinouts and Packaging Kinetis KL13 Microcontroller, Rev.2, 03/2015. 57 Freescale Semiconductor, Inc.

Pin NameDefault ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 65 53 — A6 — PTC8 CMP0_IN2CMP0_IN2PTC8 I2C0_SCLTPM0_CH4 66 54 — B5 — PTC9 CMP0_IN3CMP0_IN3PTC9 I2C0_SDATPM0_CH5 67 55 — B4 — PTC10 PTC10 I2C1_SCL 68 56 — A5 — PTC11 PTC11 I2C1_SDA 69 — — — — PTC12 PTC12 TPM_ CLKIN0 70 — — — — PTC13 PTC13 TPM_ CLKIN1 71 — — — — PTC16 PTC16 72 — — — — PTC17 PTC17 73 57 41 C3 — PTD0 PTD0 SPI0_PCS0 TPM0_CH0 FXIO0_D0 74 58 42 A4 — PTD1 ADC0_ SE5b ADC0_ SE5b PTD1 SPI0_SCK TPM0_CH1 FXIO0_D1 75 59 43 C2 — PTD2 PTD2 SPI0_MOSIUART2_RXTPM0_CH2SPI0_MISOFXIO0_D2 76 60 44 B3 — PTD3 PTD3 SPI0_MISOUART2_TXTPM0_CH3SPI0_MOSIFXIO0_D3 77 61 45 A3 29 PTD4/ LLWU_P14 PTD4/ LLWU_P14 SPI1_PCS0UART2_RXTPM0_CH4 FXIO0_D4 78 62 46 C1 30 PTD5 ADC0_ SE6b ADC0_ SE6b PTD5 SPI1_SCKUART2_TXTPM0_CH5 FXIO0_D5 79 63 47 B2 31 PTD6/ LLWU_P15 ADC0_ SE7b ADC0_ SE7b PTD6/ LLWU_P15 SPI1_MOSILPUART0_ RX I2C1_SDASPI1_MISOFXIO0_D6 80 64 48 A2 32 PTD7 PTD7 SPI1_MISOLPUART0_ TX I2C1_SCLSPI1_MOSIFXIO0_D7

8.2 KL13 Family Pinouts

Figure below shows the 64 LQFP pinouts: NOTE The 32 QFN, 48 QFN, and 64 MAPBGA packages for this product are not yet available. However, these packages are included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. Pinouts and Packaging 58 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 28. 64 LQFP Pinout diagram Freescale Semiconductor, Inc.

Figure 29. 80 LQFP Pinout diagram 60 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 30. 64 MAPBGA Pinout diagram Freescale Semiconductor, Inc.

Figure 31. 48 QFN Pinout diagram 62 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

Figure 32. 32 QFN Pinout diagram

9 Ordering parts

9.1 Determining valid orderable parts

10 Part identification

10.1 Description

values of these fields to determine the specific part you have received. Freescale Semiconductor, Inc.

10.2 Format

10.3 Fields

Table 41. Part number fields description

P = Prequalification KL## Kinetis family • KL13 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 32 = 32 KB
64 = 64 KB R Silicon revision • (Blank) = Main
A = Revision after main T Temperature range (°C) • V = –40 to 105
FT = 48 QFN (7 mm x 7 mm) 1,
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm) 1
LK = 80 LQFP (12 mm x 12 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel 1. This package for this product is not yet available. However, it is included in Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details.

10.4 Example

64 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

11 Terminology and guidelines

11.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

11.1.1 Example

This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

11.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

11.2.1 Example

This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA Terminology and guidelines Kinetis KL13 Microcontroller, Rev.2, 03/2015. 65 Freescale Semiconductor, Inc.

11.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

11.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF

11.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered.

11.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V Terminology and guidelines 66 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

11.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.

11.6 Relationship between ratings and operating requirements

No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

11.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. Terminology and guidelines Kinetis KL13 Microcontroller, Rev.2, 03/2015. 67 Freescale Semiconductor, Inc.

11.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

Lies within the range of values specified by the operating behavior
Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed.

11.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

11.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: Terminology and guidelines 68 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

11.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Table 42. Typical value conditions The following table provides a revision history for this document. Table 43. Revision History

Added new topic "Electrical Design Considerations" as Section 6.
Added a note in Table 14 - Thermal operating requirements.
Footnote 1 in Table 9 was moved in the beginning of the table as text. Table continues on the next page...

Revision History

Kinetis KL13 Microcontroller, Rev.2, 03/2015. 69 Freescale Semiconductor, Inc.

Table 43. Revision History (continued)

Updated the features and completed the ordering information.
Removed thickness dimension from package diagrams.
Updated Table 7. Voltage and current operating behaviors.
Specified correct max. value for I IN parameter.
Updated Table 8. Power mode transition operating behaviors with Typ. and Max. values.
Updated Table 9. Power consumption operating behaviors with Typ. and Max. values.
Updated Table 10. Low power mode peripheral adders — typical value.
Updated EMC Performance information in section 2.2.6.
Updated Table 17. IRC48M specification and Table 18. IRC8M/2M specification.
Updated Typ. values of TUE and INL parameters in Table 26. 16-bit ADC characteristics.
Updated Table 28. VREF full-range operating behaviors.
Removed A c(Aging coefficient) row.
Added T chop_osc_stup parameter.
Updated typical value of the V out parameter.
Added tables: "I2C timing" and "I2C 1Mbit/s timing" under section - I2C.
Updated Section 6 - Design Considerations.

70 Kinetis KL13 Microcontroller, Rev.2, 03/2015. Freescale Semiconductor, Inc.

How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis Off. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. ©2014-2015 Freescale Semiconductor, Inc. Document Number KL13P80M48SF3 Revision 2, 03/2015

Product Information

MKL13Z32VFM4 specifications and overview.

Summary

Kinetis KL13 Microcontroller Rev. 2, 03/2015

Description

Kinetis KL13 Microcontroller Rev. 2, 03/2015

Source title MKL13Z32VFM4 Datasheet(PDF) - NXP Semiconductors

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