Memory

MKL05Z16VFK4

NXP Semiconductors

Kinetis KL05 32 KB Flash Rev 4 03/2014

Manufacturer: NXP Semiconductors

Document: 53 Pages / 1,001Kb

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KL05P48M48SF1 NXP | Alldatasheet

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Technical content

48 MHz Cortex-M0+ Based Microcontroller

Designed with efficiency in mind. Features a size efficient, small package, energy efficient ARM Cortex-M0+ 32-bit performance. Shares the comprehensive enablement and scalability of the Kinetis family. This product offers:

Run power consumption down to 45 μA/MHz in very low power run mode
Static power consumption down to 2 μA with full state retention and 4 μs wakeup
Ultra-efficient Cortex-M0+ processor running up to 48MHz with industry leading throughput
Memory option is up to 32 KB Flash and 4 KB RAM
Energy-saving architecture is optimized for low power with 90 nm TFS technology, clock and power gating techniques, and zero wait state flash memory controller Performance
48 MHz ARM ® Cortex®-M0+ core Memories and memory interfaces
Up to 32 KB program flash memory
Up to 4 KB SRAM System peripherals
Nine low-power modes to provide power optimization based on application requirements
COP Software watchdog
4-channel DMA controller, supporting up to 63 request sources
Low-leakage wakeup unit
SWD debug interface and Micro Trace Buffer
Bit Manipulation Engine Clocks
32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
Multi-purpose clock source
1 kHz LPO clock Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): -40 to 105°C Human-machine interface
Low-power hardware touch sensor interface (TSI)
Up to 41 general-purpose input/output (GPIO) Communication interfaces
One 8-bit SPI module
One low power UART module
One I2C module Analog Modules
12-bit SAR ADC
12-bit DAC
Analog comparator (CMP) containing a 6-bit DAC and programmable reference input Timers
Six channel Timer/PWM (TPM)
One 2-channel Timer/PWM module
Periodic interrupt timers
16-bit low-power timer (LPTMR)
Real time clock Security and integrity modules
80-bit unique identification number per chip MKL05ZxxVFK4 MKL05ZxxVLC4 MKL05ZxxVFM4 MKL05ZxxVLF4 24-pin QFN (FK) 4 x 4 x 1 Pitch 0.5 mm 32-pin QFN (FM) 5 x 5 x 1 Pitch 0.5 mm 32-pin LQFP (LC) 7 x 7 x 1.4 Pitch 0.8 mm 48-pin LQFP (LF) 7 x 7 x 1.4 Pitch 0.5 mm Freescale Semiconductor, Inc. KL05P48M48SF1 Data Sheet: Technical Data Rev 4 03/2014 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2014 Freescale Semiconductor, Inc. All rights reserved.

Ordering Information

Part Number Memory Maximum number of I\\O's Flash (KB) SRAM (KB) MKL05Z8VFK4 8 1 22 MKL05Z16VFK4 16 2 22 MKL05Z32VFK4 32 4 22 MKL05Z8VLC4 8 1 28 MKL05Z16VLC4 16 2 28 MKL05Z32VLC4 32 4 28 MKL05Z8VFM4 8 1 28 MKL05Z16VFM4 16 2 28 MKL05Z32VFM4 32 4 28 MKL05Z16VLF4 16 2 41 MKL05Z32VLF4 32 4 41 Related Resources Type Description Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. Data Sheet The Data Sheet includes electrical characteristics and signal connections. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Package drawing Package dimensions are provided in package drawings. 2 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

8.6 Relationship between ratings and operating

Kinetis KL05 32 KB Flash, Rev4 03/2014. 3 Freescale Semiconductor, Inc.

1 Ratings

1.1 Thermal handling ratings

Table 1. Thermal handling ratings

Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Table 2. Moisture handling ratings

Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Table 3. ESD handling ratings

Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

1.4 Voltage and current operating ratings

Table 4. Voltage and current operating ratings

2 General

2.1 AC electrical characteristics

Figure 1. Input signal measurement reference pins have the following characteristics.

C L=30 pF loads
Slew rate disabled
Normal drive strength

2.2 Nonswitching electrical specifications

Freescale Semiconductor, Inc.

2.2.1 Voltage and current operating requirements

Table 5. Voltage and current operating requirements

2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
2.7 V ≤ V DD ≤ 3.6 V
1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V — IICIO IO pin negative DC injection current—single pin
V IN < VSS–0.3V (negative current injection)
V IN < VSS–0.3V (positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection –25 +25 mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V — 1. All IO pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VIO_MIN (=VSS-0.3V) and VIN is less than VIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. The positive injection current limiting resistor is calculated as R=(VIN-VIO_MAX)/|IICIO|. Select the larger of these two calculated resistances. 2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 6. V DD supply LVD and POR operating requirements Table continues on the next page... 6 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 6. V DD supply LVD and POR operating requirements (continued)

Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±60 — mV — VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V — VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
Level 1 falling (LVWV = 00)
Level 2 falling (LVWV = 01)
Level 3 falling (LVWV = 10)
Level 4 falling (LVWV = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±40 — mV — VBG Bandgap voltage reference 0.97 1.00 1.03 V — tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs — 1. Rising thresholds are falling threshold + hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 7. Voltage and current operating behaviors

2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = –1.5 mA VDD – 0.5 VDD – 0.5 V V 1, 2 VOH Output high voltage — High drive pad (except RESET_b)
2.7 V ≤ V DD ≤ 3.6 V, IOH = –18 mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = –6 mA VDD – 0.5 VDD – 0.5 V V 1, 2 IOHT Output high current total for all ports — 100 mA VOL Output low voltage — Normal drive pad
2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 1.5 mA 0.5 0.5 V V Table continues on the next page... General Kinetis KL05 32 KB Flash, Rev4 03/2014. 7 Freescale Semiconductor, Inc.

Table 7. Voltage and current operating behaviors (continued)

2.7 V ≤ V DD ≤ 3.6 V, IOL = 18 mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 6 mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 41 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 kΩ 4 1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS

2.2.4 Power mode transition operating behaviors

CPU and system clocks = 48 MHz
Bus and flash clock = 24 MHz
FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 8. Power mode transition operating behaviors

VLLS0 → RUN 115 μs
VLLS1 → RUN Table continues on the next page... General 8 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 8. Power mode transition operating behaviors (continued)

VLLS3 → RUN μs
LLS → RUN 4.6 μs
VLPS → RUN 4.4 μs
STOP → RUN 4.4 μs 1. Normal boot (FTFA_FOPT[LPBOOT]=11).

2.2.5 Power consumption operating behaviors

equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 9. Power consumption operating behaviors

at 3.0 V — 4.0 4.3 mA IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks disabled, code executing from flash
at 3.0 V — 4.9 5.3 mA IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and flash, all peripheral clocks enabled, code executing from flash
at 3.0 V
at 25 °C
at 125 °C 5.7 6.0 5.8 6.2 mA 3, 4 IDD_WAIT Wait mode current - core disabled / 48 MHz system / 24 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
at 3.0 V — 2.7 2.9 mA Table continues on the next page... General Kinetis KL05 32 KB Flash, Rev4 03/2014. 9 Freescale Semiconductor, Inc.

Table 9. Power consumption operating behaviors (continued)

at 3.0 V — 2.2 2.3 mA IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus / flash disabled (flash doze enabled)
at 3.0 V — 1.5 1.7 mA IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, code executing from flash
at 3.0 V — 182 253 μA IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks disabled, code executing from flash
at 3.0 V — 213 284 μA IDD_VLPR Very low power run mode current - 4 MHz core / 0.8 MHz bus and flash, all peripheral clocks enabled, code executing from flash
at 3.0 V — 243 313 μA 4, 5 IDD_VLPW Very low power wait mode current - core disabled / 4 MHz system / 0.8 MHz bus / flash disabled (flash doze enabled), all peripheral clocks disabled
at 3.0 V — 111 170 μA IDD_STOP Stop mode current
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C 257 265 278 295 353 277 285 303 326 412 μA IDD_VLPS Very-low-power stop mode current
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C 2.25 4.08 8.10 14.18 37.07 5.76 8.27 14.52 23.78 58.58 μA IDD_LLS Low-leakage stop mode current
at 3.0 V Table continues on the next page... General 10 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C 1.72 2.52 4.32 7.18 18.67 2.01 3.18 5.94 10.00 25.65 μA IDD_VLLS3 Very-low-leakage stop mode 3 current
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C 1.16 1.78 3.23 5.57 14.80 1.36 2.27 4.38 7.53 19.74 μA IDD_VLLS1 Very-low-leakage stop mode 1 current
at 3.0 V
at 25°C
at 50°C
at 70°C
at 85°C
at 105°C 0.64 1.14 2.35 4.37 12.40 0.81 1.50 3.20 5.80 16.13 μA IDD_VLLS0 Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 0)
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C 0.38 0.88 2.10 4.14 12.00 0.54 1.23 2.95 5.59 15.73 μA IDD_VLLS0 Very-low-leakage stop mode 0 current (SMC_STOPCTRL[PORPO] = 1)
at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C 0.30 0.79 2.01 4.05 11.96 0.45 1.12 2.82 5.45 15.63 μA 1. Data based on characterization results. General Kinetis KL05 32 KB Flash, Rev4 03/2014. 11 Freescale Semiconductor, Inc.

The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

MCG configured for FEI mode.
Incremental current consumption from peripheral activity is not included.
MCG configured for BLPI mode.

Table 10. Low power mode peripheral adders — typical value VLPS mode with 4 MHz IRC enabled. mode with the 32 kHz IRC enabled. IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled.

VLLS1
VLLS3
LLS
VLPS
STOP 440 440 490 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 580 580 680 680 680 nA ICMP CMP peripheral adder measured by placing the device in VLLS1 mode with CMP enabled using the 6-bit DAC and a single external input for compare. Includes 6-bit DAC power consumption. 22 22 22 22 22 22 µA IRTC RTC peripheral adder measured by placing the device in VLLS1 mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC ALARM set for 1 minute. Includes ERCLK32K (32 kHz external crystal) power consumption. 432 357 388 475 532 810 nA IUART UART peripheral adder measured by placing the device in STOP or VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption.
MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal) 214 237 246 254 260 268 µA Table continues on the next page... General 12 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 10. Low power mode peripheral adders — typical value (continued) source and I/O switching currents.

MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal) 235 256 265 274 280 287 µA IBG Bandgap adder when BGEN bit is set and device is placed in VLPx, LLS, or VLLSx mode. 45 45 45 45 45 45 µA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in STOP or VLPS mode. ADC is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 µA

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

MCG in FBE for run mode, and BLPE for VLPR mode
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA General Kinetis KL05 32 KB Flash, Rev4 03/2014. 13 Freescale Semiconductor, Inc.

Figure 2. Run mode supply current vs. core frequency 14 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Figure 3. VLPR mode current vs. core frequency

2.2.6 EMC performance

advice and guidance specifically targeted at optimizing EMC performance.

AN2321: Designing for Board Level Electromagnetic Compatibility
AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers General Kinetis KL05 32 KB Flash, Rev4 03/2014. 15 Freescale Semiconductor, Inc.

AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems

2.2.7 Capacitance attributes

Table 11. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 12. Device clock specifications

The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

16 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

2.3.2 General switching specifications

Table 13. General switching specifications

The greater synchronous and asynchronous timing must be met.
This is the shortest pulse that is guaranteed to be recognized.

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 14. Thermal operating requirements

2.4.2 Thermal attributes

Table 15. Thermal attributes

32 QFN 24 QFN Unit Notes

Table continues on the next page... Freescale Semiconductor, Inc.

Table 15. Thermal attributes (continued)

Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Environmental Conditions—Forced Convection (Moving Air).

Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

the top of the package and the cold plate.

Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 16. SWD full voltage range electricals

Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width Table continues on the next page... Peripheral operating requirements and behaviors 18 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG specifications

Table 17. MCG specifications Table continues on the next page... 20 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 17. MCG specifications (continued)

f VCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

3.3.2 Oscillator electrical specifications

3.3.2.1 Oscillator DC electrical specifications

Table 18. Oscillator DC electrical specifications

32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz 400 500 2.5 μA μA μA mA mA mA Table continues on the next page... Peripheral operating requirements and behaviors Kinetis KL05 32 KB Flash, Rev4 03/2014. 21 Freescale Semiconductor, Inc.

Table 18. Oscillator DC electrical specifications (continued)

24 MHz
32 MHz Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low- power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, high-gain mode (HGO=1) — VDD — V 1. VDD=3.3 V, Temperature =25 °C 2. See crystal or resonator manufacturer's recommendation 3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all other cases external capacitors must be used. 4. When low power mode is selected, RF is integrated and must not be attached externally. 5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. Peripheral operating requirements and behaviors 22 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

3.3.2.2 Oscillator frequency specifications

Table 19. Oscillator frequency specifications

Other frequency limits may apply when external clock is being used as a reference for the FLL
When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

Proper PC board layout procedures must be followed to achieve specifications.
Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

3.4 Memories and memory interfaces

3.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.4.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Freescale Semiconductor, Inc.

Table 20. NVM program/erase timing specifications

Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 21. Flash command timing specifications

Assumes 25 MHz flash clock frequency.
Maximum times for erase parameters based on expectations at cycling end-of-life.

3.4.1.3 Flash high voltage current behaviors

Table 22. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 23. NVM reliability specifications Table continues on the next page... 24 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 23. NVM reliability specifications (continued)

Typical data retention values are based on measured response accelerated at high temperature and derated to a
Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

All ADC channels meet the 12-bit single-ended accuracy specifications. Table 24. 12-bit ADC operating conditions

1.13 VDDA VDDA V 3

8-bit / 10-bit / 12-bit modes — 4 5 pF RADIN Input series resistance — 2 5 kΩ Table continues on the next page... Peripheral operating requirements and behaviors Kinetis KL05 32 KB Flash, Rev4 03/2014. 25 Freescale Semiconductor, Inc.

Table 24. 12-bit ADC operating conditions (continued)

Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

CAS time constant should be kept to < 1 ns.

To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Figure 6. ADC input impedance equivalency diagram 26 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 25. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

ADLPC = 1, ADHSC =
ADLPC = 1, ADHSC =
ADLPC = 0, ADHSC =
ADLPC = 0, ADHSC = 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
12-bit modes
<12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
12-bit modes
<12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
12-bit modes
<12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
<12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
12-bit modes — — ±0.5 LSB4 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 6 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 6 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. Peripheral operating requirements and behaviors Kinetis KL05 32 KB Flash, Rev4 03/2014. 27 Freescale Semiconductor, Inc.

The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

MHz ADC conversion clock speed.

1 LSB = (VREFH - VREFL)/2N
ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
ADC conversion clock < 3 MHz

Figure 7. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode

3.6.2 CMP and 6-bit DAC electrical specifications

Table 26. Comparator and 6-bit DAC electrical specifications

CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01 mV mV Table continues on the next page... Peripheral operating requirements and behaviors 28 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 26. Comparator and 6-bit DAC electrical specifications (continued)

CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN = 1, PMODE = 1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN = 1, PMODE = 0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 40.00E -03 50.00E -03 60.00E -03 70.00E -03 80.00E -03 90.00E -03C MP Hysteresis (V) C MP Hysteresis vs Vinn HY S TC TR S etting 000.00E +00 10.00E -03 20.00E -03 30.00E -03 C MP Hysteresis (V) Vinn (V)

Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Freescale Semiconductor, Inc.

Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 27. 12-bit DAC operating requirements

The DAC reference can be selected to be VDDA or VREFH.
A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Table 28. 12-bit DAC operating behaviors Table continues on the next page... 30 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 28. 12-bit DAC operating behaviors (continued)

High power (SP HP)
Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
High power (SP HP)
Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors Kinetis KL05 32 KB Flash, Rev4 03/2014. 31 Freescale Semiconductor, Inc.

Figure 10. Typical INL error vs. digital code 32 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Figure 11. Offset at half scale vs. temperature

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

Freescale Semiconductor, Inc.

3.8.1 SPI switching specifications

for communicating with slower peripheral devices. well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins. Table 29. SPI master mode timing on slew rate disabled pads

For SPI0, fperiph is the bus clock (fBUS).

Table 30. SPI master mode timing on slew rate enabled pads Table continues on the next page... 34 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 30. SPI master mode timing on slew rate enabled pads (continued)

For SPI0, fperiph is the bus clock (fBUS).
If configured as an output.

Figure 12. SPI master mode timing (CPHA = 0) Freescale Semiconductor, Inc.

Figure 13. SPI master mode timing (CPHA = 1) Table 31. SPI slave mode timing on slew rate disabled pads

For SPI0, fperiph is the bus clock (fBUS).
Time to data active from high-impedance state
Hold time to high-impedance state

36 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Table 32. SPI slave mode timing on slew rate enabled pads

For SPI0, fperiph is the bus clock (fBUS).
Time to data active from high-impedance state
Hold time to high-impedance state

Figure 14. SPI slave mode timing (CPHA = 0) Freescale Semiconductor, Inc.

Figure 15. SPI slave mode timing (CPHA = 1)

3.8.2 Inter-Integrated Circuit Interface (I2C) timing

Table 33. I2C timing Hold time (repeated) START condition.

The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High

38 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
Input signal Slew = 10 ns and Output Load = 50 pF
Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
Cb = total capacitance of the one bus line in pF.

Figure 16. Timing definition for fast and standard mode devices on the I2C bus

3.8.3 UART

See General switching specifications.

3.9 Human-machine interfaces (HMI)

3.9.1 TSI electrical specifications

Table 34. TSI electrical specifications Freescale Semiconductor, Inc.

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 24-pin QFN 98ASA00474D 32-pin QFN 98ASA00473D 32-pin LQFP 98ASH70029A 48-pin LQFP 98ASH00962A

5 Pinout

5.1 KL05 signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. LQFP QFN LQFP QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 1 1 1 1 PTB6/ IRQ_2/ LPTMR0_ALT3 DISABLED DISABLED PTB6/ IRQ_2/ LPTMR0_ALT3 TPM0_CH3 TPM_CLKIN1 2 2 2 2 PTB7/ IRQ_3 DISABLED DISABLED PTB7/ IRQ_3 TPM0_CH2 3 — — — PTA14 DISABLED DISABLED PTA14 TPM_CLKIN0 4 — — — PTA15 DISABLED DISABLED PTA15 CLKOUT 5 3 3 3 VDD VDD VDD 6 4 4 3 VREFH VREFH VREFH 7 5 5 4 VREFL VREFL VREFL 8 6 6 4 VSS VSS VSS Dimensions 40 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 9 7 7 5 PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C0_SDA 10 8 8 6 PTA4/ LLWU_P0 XTAL0 XTAL0 PTA4/ LLWU_P0 I2C0_SDA I2C0_SCL 11 — — — VSS VSS VSS 12 — — — PTB18 DISABLED DISABLED PTB18 13 — — — PTB19 DISABLED DISABLED PTB19 14 9 9 7 PTA5/ LLWU_P1/ RTC_CLK_IN DISABLED DISABLED PTA5/ LLWU_P1/ RTC_CLK_IN TPM0_CH5 SPI0_SS_b 15 10 10 8 PTA6/ LLWU_P2 DISABLED DISABLED PTA6/ LLWU_P2 TPM0_CH4 SPI0_MISO 16 11 11 — PTB8 ADC0_SE11 ADC0_SE11 PTB8 TPM0_CH3 17 12 12 — PTB9 ADC0_SE10 ADC0_SE10 PTB9 TPM0_CH2 18 — — — PTA16/ IRQ_4 DISABLED DISABLED PTA16/ IRQ_4 19 — — — PTA17/ IRQ_5 DISABLED DISABLED PTA17/ IRQ_5 20 — — — PTA18/ IRQ_6 DISABLED DISABLED PTA18/ IRQ_6 21 13 13 9 PTB10 ADC0_SE9/ TSI0_IN7 ADC0_SE9/ TSI0_IN7 PTB10 TPM0_CH1 22 14 14 10 PTB11 ADC0_SE8/ TSI0_IN6 ADC0_SE8/ TSI0_IN6 PTB11 TPM0_CH0 23 15 15 11 PTA7/ IRQ_7/ LLWU_P3 ADC0_SE7/ TSI0_IN5 ADC0_SE7/ TSI0_IN5 PTA7/ IRQ_7/ LLWU_P3 SPI0_MISO SPI0_MOSI 24 16 16 12 PTB0/ IRQ_8/ LLWU_P4 ADC0_SE6/ TSI0_IN4 ADC0_SE6/ TSI0_IN4 PTB0/ IRQ_8/ LLWU_P4 EXTRG_IN SPI0_SCK 25 17 17 13 PTB1/ IRQ_9 ADC0_SE5/ TSI0_IN3/ DAC0_OUT/ CMP0_IN3 ADC0_SE5/ TSI0_IN3/ DAC0_OUT/ CMP0_IN3 PTB1/ IRQ_9 UART0_TX UART0_RX 26 18 18 14 PTB2/ IRQ_10/ LLWU_P5 ADC0_SE4/ TSI0_IN2 ADC0_SE4/ TSI0_IN2 PTB2/ IRQ_10/ LLWU_P5 UART0_RX UART0_TX 27 19 19 15 PTA8 ADC0_SE3/ TSI0_IN1 ADC0_SE3/ TSI0_IN1 PTA8 28 20 20 16 PTA9 ADC0_SE2/ TSI0_IN0 ADC0_SE2/ TSI0_IN0 PTA9 29 — — — PTB20 DISABLED DISABLED PTB20 30 — — — VSS VSS VSS 31 — — — VDD VDD VDD 32 — — — PTB14/ IRQ_11 DISABLED DISABLED PTB14/ IRQ_11 EXTRG_IN Pinout Kinetis KL05 32 KB Flash, Rev4 03/2014. 41 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 33 21 21 — PTA10/ IRQ_12 DISABLED TSI0_IN11 PTA10/ IRQ_12 34 22 22 — PTA11/ IRQ_13 DISABLED TSI0_IN10 PTA11/ IRQ_13 35 23 23 17 PTB3/ IRQ_14 DISABLED DISABLED PTB3/ IRQ_14 I2C0_SCL UART0_TX 36 24 24 18 PTB4/ IRQ_15/ LLWU_P6 DISABLED DISABLED PTB4/ IRQ_15/ LLWU_P6 I2C0_SDA UART0_RX 37 25 25 19 PTB5/ IRQ_16 NMI_b ADC0_SE1/ CMP0_IN1 PTB5/ IRQ_16 TPM1_CH1 NMI_b 38 26 26 20 PTA12/ IRQ_17/ LPTMR0_ALT2 ADC0_SE0/ CMP0_IN0 ADC0_SE0/ CMP0_IN0 PTA12/ IRQ_17/ LPTMR0_ALT2 TPM1_CH0 TPM_CLKIN0 39 27 27 — PTA13 TSI0_IN9 TSI0_IN9 PTA13 40 28 28 — PTB12 TSI0_IN8 TSI0_IN8 PTB12 41 — — — PTA19 DISABLED DISABLED PTA19 SPI0_SS_b 42 — — — PTB15 DISABLED DISABLED PTB15 SPI0_MOSI SPI0_MISO 43 — — — PTB16 DISABLED DISABLED PTB16 SPI0_MISO SPI0_MOSI 44 — — — PTB17 DISABLED DISABLED PTB17 TPM_CLKIN1 SPI0_SCK 45 29 29 21 PTB13 ADC0_SE13 ADC0_SE13 PTB13 TPM1_CH1 RTC_CLKOUT 46 30 30 22 PTA0/ IRQ_0/ LLWU_P7 SWD_CLK ADC0_SE12/ CMP0_IN2 PTA0/ IRQ_0/ LLWU_P7 TPM1_CH0 SWD_CLK 47 31 31 23 PTA1/ IRQ_1/ LPTMR0_ALT1 RESET_b DISABLED PTA1/ IRQ_1/ LPTMR0_ALT1 TPM_CLKIN0 RESET_b 48 32 32 24 PTA2 SWD_DIO DISABLED PTA2 CMP0_OUT SWD_DIO

5.2 KL05 pinouts

The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see KL05 signal multiplexing and pin assignments. Pinout 42 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Figure 17. KL05 48-pin LQFP pinout diagram Freescale Semiconductor, Inc.

Figure 18. KL05 32-pin LQFP pinout diagram 44 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Figure 19. KL05 32-pin QFN pinout diagram Freescale Semiconductor, Inc.

Figure 20. KL05 24-pin QFN pinout diagram

6 Ordering parts

6.1 Determining valid orderable parts

7 Part identification

46 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

7.1 Description

values of these fields to determine the specific part you have received.

7.2 Format

7.3 Fields

Table 35. Part number fields descriptions

P = Prequalification KL## Kinetis family • KL05 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 8 = 8 KB
16 = 16 KB
32 = 32 KB R Silicon revision • (Blank) = Main
A = Revision after main T Temperature range (°C) • V = –40 to 105
LC = 32 LQFP (7 mm x 7 mm)
FM = 32 QFN (5 mm x 5 mm)
LF = 48 LQFP (7 mm x 7 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel
(Blank) = Trays

7.4 Example

Freescale Semiconductor, Inc.

8 Terminology and guidelines

8.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.

8.1.1 Example

This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

8.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

8.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

8.3.1 Example

This is an example of an attribute: Terminology and guidelines 48 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF

8.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered.

8.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

8.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines Kinetis KL05 32 KB Flash, Rev4 03/2014. 49 Freescale Semiconductor, Inc.

8.6 Relationship between ratings and operating requirements

No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

8.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

Never exceed any of the chip’s ratings.
During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

8.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

Lies within the range of values specified by the operating behavior
Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines 50 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

8.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

8.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

8.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Terminology and guidelines Kinetis KL05 32 KB Flash, Rev4 03/2014. 51 Freescale Semiconductor, Inc.

Table 36. Typical value conditions

9 Revision history

The following table provides a revision history for this document. Table 37. Revision history 2 9/2012 Initial public release. 3 11/2012 Completed all the TBDs.

Added a note to the I LAT in the ESD handling ratings
Updated Voltage and current operating ratings
Added V ODPU in the Voltage and current operating requirements
Updated Voltage and current operating behaviors
Updated Power mode transition operating behaviors
Updated Power consumption operating behaviors
Updated Capacitance attributes
Updated footnote in the Device clock specifications
Add t hversall in the Flash timing specifications — commands
Updated Temp sensor slope and voltage and added a note to them in the 12-bit ADC electrical characteristics
Removed T A in the 12-bit DAC operating requirements
Added Inter-Integrated Circuit Interface (I2C) timing

Revision history

52 Kinetis KL05 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc.

How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, Energy Efficient Solutions logo, and & Tm. Off. All other product or service names are the property of their respective owners. ARM and Cortex-M0+ are the registered trademarks of ARM Limited. © 2012-2014 Freescale Semiconductor, Inc. Document Number KL05P48M48SF1 Revision 4 03/2014

Product Information

MKL05Z16VFK4 specifications and overview.

Summary

Kinetis KL05 32 KB Flash Rev 4 03/2014

Description

Kinetis KL05 32 KB Flash Rev 4 03/2014

Source title MKL05Z16VFK4 Datasheet(PDF) - NXP Semiconductors

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