KE1XZP100M72SF1_V02 NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 87
Technical content
- ARM ® Cortex®-M0+ core, supports up to 72 MHz frequency
- ARM Core based on the ARMv6 Architecture and Thumb®-2 ISA
- Configurable Nested Vectored Interrupt Controller (NVIC)
- 8-channel DMA controller extended up to 63 channels with DMAMUX Memory and memory interfaces
- Up to 256 KB program flash
- Up to 48 KB SRAM
- 128 Bytes flash cache Power management
- Low-power ARM Cortex-M0+ core with excellent energy efficiency
- Power management controller (PMC) with multiple power modes: Run, Wait, Stop, VLPR, VLPW and VLPS
- Supports clock gating for unused modules, and specific peripherals remain working in low power modes
- POR, LVD/LVR Debug functionality
- Serial Wire Debug (SWD) debug interface Mixed-signal analog
- 1× 12-bit analog-to-digital converter (ADC) with up to 16 channel analog inputs per module, up to 1 Msps
- 1× high-speed analog comparators (CMP) with internal 8-bit digital to analog converter (DAC) Timing and control
- 3× Flex Timers (FTM) for PWM generation, offering up to 8 standard channels
- 1× 16-bit Low-Power Timer (LPTMR) with flexible wake up control
- 1× 32-bit Low-power Periodic Interrupt Timer (LPIT) with 4 channels Reliability, safety and security
- Cyclic Redundancy Check (CRC) generator module
- 128-bit unique identification (ID) number
- Internal watchdog (WDOG) with independent clock source
- External watchdog monitor (EWM) module
- ADC self calibration feature
- On-chip clock loss monitoring Human-machine interface (HMI)
- Supports up to 32 interrupt request (IRQ) sources Up to 72 MHz ARM® Cortex®-M0+ Based Microcontroller KE1xZ256 MCUs are the leading parts for the KE1xZ family based on ARM® Cortex®-M0+ core. Providing up to 256 KB flash, up to 48 KB RAM, and the complete set of analog/digital features, KE1xZ extends Kinetis E family to higher performance and broader scalability. Robust and enhanced TSIs provide high- level stability and accuracy to customer's HMI system. 1 Msps ADC and FlexTimer help build a perfect solution for BLDC motor control systems. MKE1xZ256VLL7 MKE1xZ256V/CLH7 MKE1xZ256VLF7 MKE1xZ128VLL7 MKE1xZ128VLH7 MKE1xZ128VLF7
100 LQFP (LL)
14x14x1.4 mm P 0.5
64 LQFP (LH)
10x10x1.4 mm P 0.5
48 LQFP (LF)
7x7x1.4 mm P 0.5 KE1xZP100M72SF1 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash Rev. 2.2 — December 2025 Product data sheet
- Debug Watchpoint and Trace (DWT)
- Micro Trace Buffer (MTB) Clock interfaces
- OSC: high range 4 - 40 MHz (with low power or high- gain mode) and low range 32 - 40 kHz (with high-gain mode only)
- 48 MHz high-accuracy (up to ±1%) fast internal reference clock (FIRC) for normal Run
- 8 MHz / 2 MHz high-accuracy (up to ±3%) slow internal reference clock (SIRC) for low-speed Run
- 128 kHz low power oscillator (LPO)
- Low-power FLL (LPFLL)
- Up to 60 MHz DC external square wave input clock
- System clock generator (SCG)
- Up to 89 GPIO pins with interrupt functionality
- 2 x 25ch Touch sensing input (TSI) module, each TSI has 12 mutual channels (up to 6 × 6ch matrix) and 3 shield channels Connectivity and communications interfaces
- 3× low-power universal asynchronous receiver/ transmitter (LPUART) modules with DMA support and low power availability
- 1× low-power serial peripheral interface (LPSPI) modules with DMA support and low power availability
- 1× low-power inter-integrated circuit (LPI2C) modules with DMA support and low power availability
- FlexIO module for flexible and high performance serial interfaces Operating Characteristics
- Voltage range: 2.7 to 5.5 V
- Ambient temperature range: –40 to 105 °C or –40 to 85 °C Related Resources Type Description Resource Fact Sheet The Fact Sheet gives overview of the product key features and its uses. KE1xZ Family Fact Sheet KE1xZMCUFAMFS 1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KE1xZP100M72SF1RM 1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document: KE1xZP100M72SF1 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Kinetis_E_P35D 1 Package drawing Package dimensions are provided in package drawings. 100-LQFP: 98ASS23308W 64-LQFP: 98ASS23234W 48-LQFP: 98ASH00962A 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Figure 1. Functional block diagram
5.1.4 Relationship between ratings and operating
5.1.5 Guidelines for ratings and operating
4 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
1 Ordering information
The following chips are available for ordering. Table 1. Ordering information
- INT: interrupt pin numbers; HD: high drive pin numbers
2 Overview
The following figure shows the system diagram of this device.
Ordering information
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 5 NXP Semiconductors
Figure 2. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure.
2.1 System features
The following sections describe the high-level system features.
2.1.1 ARM Cortex-M0+ core
2.1.2 NVIC
also differs in number of interrupt sources and supports 32 interrupt vectors.
2.1.3 AWIC
wake MCU core from Partial Stop, Stop and VLPS modes. Table 2. AWIC Stop and VLPS Wake-up Sources Table continues on the next page...
Table 2. AWIC Stop and VLPS Wake-up Sources (continued)
2.1.4 Memory
- Upto 256 KB of embedded program flash memory.
- Upto 48 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device. Table 3. Reset source Table continues on the next page...
Table 3. Reset source (continued)
- Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
- Except SMC_PMPROT, SMC_PMCTRL_RUM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT
- Except RCM_RPC, RCM_MR, RCM_FM, RCM_SRIE, RCM_SRS, RCM_SSRS
- Except SCG_CSR and SCG_FIRCSTAT
- internal flash
2.1.6 Clock options
allow granular shutoff of modules.
48 MHz
Figure 3. Clocking block diagram
2.1.7 Security
2.1.8 Power management
application can be selected. Interrupt Controller (AWIC) are used to wake up the MCU from low power states. AWIC is used to wake up the MCU core from STOP and VLPS modes. NVIC, AWIC, please refer to the Reference Manual. Table 5. Peripherals states in different operational modes Run mode Run In Run mode, all device modules are operational. except the Low Voltage Detect (LVD) monitor, which is disabled. Table continues on the next page...
Table 5. Peripherals states in different operational modes (continued) frequency except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU core is placed into Sleep mode. to wake up from an interrupt.
2.1.9 Debug controller
capabilities. The standard ARM debug port supports SWD interface.
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip. can be routed from up to 63 DMA request sources through DMA MUX module.
- All data movement via dual-address transfers: read from source, write to destination
- 8-channel implementation that performs complex data transfers with minimal intervention from a host processor
- Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations Overview 12 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
- Channel activation via one of three methods
- Fixed-priority and round-robin channel arbitration
- Channel completion reported via programmable interrupt requests
- Programmable support for scatter/gather DMA processing
- Support for complex data structures
2.2.2 FTM
This device contains three FlexTimer modules. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. Several key enhancements of this module are made:
- Signed up counter
- Deadtime insertion hardware
- Fault control inputs
- Enhanced triggering functionality
- Initialization and polarity control
2.2.3 ADC
This device contains one 12-bit SAR ADC module. The ADC module supports hardware triggers from FTM, LPTMR, PIT, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features:
- Linear successive approximation algorithm with up to 12-bit resolution
- Up to single-ended external analog inputs
- Support 12-bit, 10-bit, and 8-bit single-ended output modes
- Single or continuous conversion
- Configurable sample time and conversion speed/power
- Input clock selectable from up to four sources
- Operation in low-power modes for lower noise
- Selectable hardware conversion trigger Overview Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 13 NXP Semiconductors
- Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
- Temperature sensor
- Hardware average function
- Selectable Voltage reference: from external or alternate
- Self-Calibration mode
2.2.3.1 Temperature sensor
This device contains one temperature sensor internally connected to the input channel of AD26, see ADC electrical characteristics for details of the linearity factor. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed application information of the temperature sensor.
2.2.4 CMP
There isone analog comparator on this device.
- Each CMP has its own independent 8-bit DAC.
- Each CMP supports up to 6 analog inputs from external pins.
- Each CMP is able to convert an internal reference from the bandgap.
- Each CMP supports the round-robin sampling scheme. In summary, this allow the CMP to operate independently in VLPS and Stop modes, whilst being triggered periodically to sample up to 8 inputs. Only if an input changes state is a full wakeup generated. The CMP has the following features:
- Inputs may range from rail to rail
- Programmable hysteresis control
- Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges of the comparator output
- Selectable inversion on comparator output
- Capability to produce a wide range of outputs such as sampled, windowed, or digitally filtered
- External hysteresis can be used at the same time that the output filter is used for internal functions
- Two software selectable performance levels: Shorter propagation delay at the expense of higher power, and Low power with longer propagation delay
- DMA transfer support
- Functional in all power modes available on this MCU Overview 14 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
- The window and filter functions are not available in STOP mode
- Integrated 8-bit DAC with selectable supply reference source and can be power down to conserve power
2.2.5 LPIT
The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module generating independent pre-trigger and trigger outputs. These timer channels can operate individually or can be chained together. The LPIT can operate in low power modes if configured to do so. The pre-trigger and trigger outputs can be used to trigger other modules on the device.
2.2.6 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features:
- 16-bit time counter or pulse counter with compare
- Optional interrupt can generate asynchronous wakeup from any low-power mode
- Hardware trigger output
- Counter supports free-running mode or reset on compare
- Configurable clock source for prescaler/glitch filter
- Configurable input source for pulse counter
2.2.7 CRC
This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The CRC module has the following features:
- Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register Overview Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 15 NXP Semiconductors
- Programmable initial seed value and polynomial
- Option to transpose input data or output data (the CRC result) bitwise or bytewise.
- Option for inversion of final CRC result
- 32-bit CPU register programming interface
2.2.8 LPUART
This product contains three Low-Power UART modules, and can work in Stop and VLPS modes. The module also supports 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features:
- Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32×
- Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode
- Interrupt, DMA or polled operation
- Hardware parity generation and checking
- Programmable 8-bit, 9-bit or 10-bit character length
- Programmable 1-bit or 2-bit stop bits
- Three receiver wakeup methods
- Idle line wakeup
- Address mark wakeup
- Receive data match
- Automatic address matching to reduce ISR overhead:
- Address mark matching
- Idle line address matching
- Address match start, address match end
- Optional 13-bit break character generation / 11-bit break character detection
- Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters
- Selectable transmitter output and receiver input polarity Overview 16 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
2.2.9 LPSPI
This device contains one LPSPI module. The LPSPI is a low power Serial Peripheral Interface (SPI) module that supports an efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPSPI module has the following features:
- Command/transmit FIFO of 4 words
- Receive FIFO of 4 words
- Host request input can be used to control the start time of an SPI bus transfer
2.2.10 LPI2C
This device contains one LPI2C module. The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master and/or a slave. The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C implements logic support for standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The LPI2C module also complies with the System Management Bus (SMBus) Specification, version 2. The LPI2C modules have the following features:
- Standard, Fast, Fast+ and Ultra Fast modes are supported
- HS-mode supported in slave mode
- Multi-master support including synchronization and arbitration
- Clock stretching
- General call, 7-bit and 10-bit addressing
- Software reset, START byte and Device ID require software support
- For master mode:
- command/transmit FIFO of 4 words
- receive FIFO of 4 words
- For slave mode:
- separate I2C slave registers to minimize software overhead due to master/ slave switching
- support for 7-bit or 10-bit addressing, address range, SMBus alert and general call address
- transmit/receive data register supporting interrupt or DMA requests Overview Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 17 NXP Semiconductors
2.2.11 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features:
- Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled
- Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer
- The timing of the shifter's shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter
- Two or more shifters can be concatenated to support large data transfer sizes
- Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity
- Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode
- Supports interrupt, DMA or polled transmit/receive operation
2.2.12 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The following figure shows the basic I/O pad structure. Pseudo open-drain pins have the p-channel output driver disabled when configured for open-drain operation. None of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above VDD. Overview 18 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Figure 4. I/O simplified block diagram
- all PIN support interrupt enable
- Configurable edge (rising, falling, or both) or level sensitive interrupt type
- Support DMA request
- Asynchronous wake-up in low-power modes
- Configurable pullup, pulldown, and pull-disable on select pins
- Configurable high and low drive strength on selected pins
- Configurable passive filter on selected pins
- Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions
- Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features:
- Port Data Input register visible in all digital pin-multiplexing modes
- Port Data Output register with corresponding set/clear/toggle registers
- Port Data Direction register
- GPIO support single-cycle access via fast GPIO. Overview Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 19 NXP Semiconductors
3 Memory map
This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. For more details of the system memory and peripheral locations, see the Memory Map chapter in the Reference Manual.
4 Pinouts
4.1 KE1xZ Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE TSI shield pin on CH4, CH12 and CH21. 100 LQFP LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 10 10 VREFL/ VSS VREFL/ VSS VREFL/ VSS 1 — — PTE16 TSI0_CH13TSI0_CH13PTE16 FXIO_D3 TRGMUX_ OUT7 2 — — PTE15 TSI0_CH14TSI0_CH14PTE15 FXIO_D2 TRGMUX_ OUT6 3 1 1 PTD1 TSI0_CH11TSI0_CH11PTD1 FTM0_CH3 FTM2_CH1 FXIO_D1 TRGMUX_ OUT2 4 2 2 PTD0 TSI0_CH12TSI0_CH12PTD0 FTM0_CH2 FTM2_CH0 FXIO_D0 TRGMUX_ OUT1 5 3 3 PTE11 TSI0_CH9TSI0_CH9PTE11 PWT_IN1 LPTMR0_ ALT1 FXIO_D5 TRGMUX_ OUT5 6 4 4 PTE10 TSI0_CH10TSI0_CH10PTE10 CLKOUT FXIO_D4 TRGMUX_ OUT4 7 — — PTE13 TSI0_CH15TSI0_CH15PTE13 TRGMUX_ OUT5 8 5 5 PTE5 TSI0_CH16TSI0_CH16PTE5 TCLK2 FTM2_CH3 FXIO_D7 EWM_IN 9 6 6 PTE4 TSI0_CH17TSI0_CH17PTE4 BUSOUT FTM2_CH2 FXIO_D6 EWM_OUT_b 10 7 7 VDD VDD VDD 11 8 8 VDDA VDDA VDDA Memory map 20 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 12 9 9 VREFH VREFH VREFH 13 — — VREFL VREFL VREFL 14 — — VSS VSS VSS 15 11 11 PTB7 EXTAL EXTAL PTB7 LPI2C0_SCLLPUART0_TX 16 12 12 PTB6 XTAL XTAL PTB6 LPI2C0_SDALPUART0_RX 17 — — PTE14 DISABLED PTE14 FTM0_FLT1 TRGMUX_ OUT4 18 13 13 PTE3 ADC0_SE6/ TSI0_CH18 ADC0_SE6/ TSI0_CH18 PTE3 FTM0_FLT0LPUART2_ RTS TRGMUX_IN6 19 — — PTE12 DISABLED PTE12 FTM0_FLT3LPUART2_TX TRGMUX_ OUT3 20 — — PTD17 DISABLED PTD17 FTM0_FLT2LPUART2_RX TRGMUX_ OUT2 21 14 — PTD16 ADC0_SE4/ TSI0_CH19 ADC0_SE4/ TSI0_CH19 PTD16 FTM0_CH1 22 15 — PTD15 ADC0_SE2/ TSI0_CH20 ADC0_SE2/ TSI0_CH20 PTD15 FTM0_CH0 23 16 — PTE9 ADC0_SE0/ TSI0_CH21 ADC0_SE0/ TSI0_CH21 PTE9 FTM0_CH7LPUART2_ CTS 24 — — PTD14 DISABLED PTD14 LPUART1_TX CLKOUT 25 — — PTD13 DISABLED PTD13 LPUART1_RX 26 17 14 PTE8 ACMP0_IN3/ ADC0_SE1/ TSI0_CH22 ACMP0_IN3/ ADC0_SE1/ TSI0_CH22 PTE8 FTM0_CH6 27 18 15 PTB5 ADC0_SE3/ TSI0_CH23 ADC0_SE3/ TSI0_CH23 PTB5 FTM0_CH5LPSPI0_ PCS1 TRGMUX_IN0 28 19 16 PTB4 ADC0_SE5/ TSI0_CH24 ADC0_SE5/ TSI0_CH24 PTB4 FTM0_CH4LPSPI0_ SOUT TRGMUX_IN1 29 20 17 PTC3 ADC0_SE7/ ACMP0_IN4 ADC0_SE7/ ACMP0_IN4 PTC3 FTM0_CH3 FXIO_D7 30 21 18 PTC2 ADC0_SE15/ ACMP0_IN5 ADC0_SE15/ ACMP0_IN5 PTC2 FTM0_CH2 FXIO_D6 31 22 19 PTD7 ADC0_SE13ADC0_SE13PTD7 LPUART2_TX 32 23 20 PTD6 ADC0_SE11ADC0_SE11PTD6 LPUART2_RX 33 24 21 PTD5 ADC0_SE9ADC0_SE9PTD5 FTM2_CH3LPTMR0_ ALT2 FXIO_D3 PWT_IN2 TRGMUX_IN7LPUART2_ CTS 34 — — PTD12 DISABLED PTD12 FTM2_CH2 LPUART2_ RTS 35 — — PTD11 DISABLED PTD11 FTM2_CH1 LPUART2_ CTS 36 — — PTD10 DISABLED PTD10 FTM2_CH0 37 — — VSS VSS VSS 38 — — VDD VDD VDD 39 25 22 PTC1 ADC0_SE8/ TSI1_CH24 ADC0_SE8/ TSI1_CH24 PTC1 FTM0_CH1 Pinouts Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 21 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 40 26 23 PTC0 ADC0_SE10/ TSI1_CH23 ADC0_SE10/ TSI1_CH23 PTC0 FTM0_CH0 41 — — PTD9 DISABLED PTD9 FXIO_D2 42 — — PTD8 DISABLED PTD8 FTM0_CH7 LPSPI0_ PCS1 43 27 — PTC17 ADC0_SE12/ TSI1_CH22 ADC0_SE12/ TSI1_CH22 PTC17 44 28 — PTC16 ADC0_SE14/ TSI1_CH21 ADC0_SE14/ TSI1_CH21 PTC16 45 29 — PTC15 TSI1_CH20TSI1_CH20PTC15 FTM1_CH3 46 30 — PTC14 TSI1_CH19TSI1_CH19PTC14 FTM1_CH2 47 31 24 PTB3 TSI1_CH18TSI1_CH18PTB3 FTM1_CH1LPSPI0_SIN TRGMUX_IN2 48 32 25 PTB2 TSI1_CH17TSI1_CH17PTB2 FTM1_CH0LPSPI0_SCK TRGMUX_IN3 49 — — PTC13 DISABLED PTC13 LPSPI0_ PCS0 50 — — PTC12 DISABLED PTC12 LPSPI0_ SOUT 51 — — PTC11 DISABLED PTC11 LPSPI0_SIN 52 — — PTC10 DISABLED PTC10 LPSPI0_SCK 53 33 26 PTB1 TSI1_CH16TSI1_CH16PTB1 LPUART0_TXLPSPI0_ SOUT TCLK0 54 34 27 PTB0 TSI1_CH15TSI1_CH15PTB0 LPUART0_RXLPSPI0_ PCS0 LPTMR0_ ALT3 PWT_IN3 55 35 — PTC9 TSI1_CH14TSI1_CH14PTC9 LPUART1_TX LPUART0_ RTS 56 36 — PTC8 TSI1_CH13TSI1_CH13PTC8 LPUART1_RX LPUART0_ CTS 57 37 28 PTA7 TSI1_CH12TSI1_CH12PTA7 FTM0_FLT2LPSPI0_ PCS3 LPUART1_ RTS 58 38 29 PTA6 TSI1_CH11TSI1_CH11PTA6 FTM0_FLT1 LPUART1_ CTS 59 39 — PTE7 TSI1_CH10TSI1_CH10PTE7 FTM0_CH7 60 40 30 VSS VSS VSS 61 41 31 VDD VDD VDD 62 — — PTA17 DISABLED PTA17 FTM0_CH6 EWM_OUT_b 63 — — PTB17 DISABLED PTB17 FTM0_CH5 64 — — PTB16 DISABLED PTB16 FTM0_CH4 65 — — PTB15 DISABLED PTB15 FTM0_CH3 66 — — PTB14 DISABLED PTB14 FTM0_CH2 67 42 — PTB13 TSI1_CH9TSI1_CH9PTB13 FTM0_CH1 68 43 — PTB12 TSI1_CH8TSI1_CH8PTB12 FTM0_CH0 69 44 32 PTD4 TSI1_CH7TSI1_CH7PTD4 FTM0_FLT3 70 45 33 PTD3 NMI_b PTD3 FXIO_D5 LPI2C0_SCLTRGMUX_IN4NMI_b Pinouts 22 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 71 46 34 PTD2 TSI1_CH6TSI1_CH6PTD2 FXIO_D4 LPI2C0_SDATRGMUX_IN5 72 47 35 PTA3 TSI1_CH5TSI1_CH5PTA3 LPI2C0_SCLEWM_IN LPUART0_TX 73 48 36 PTA2 TSI1_CH4TSI1_CH4PTA2 LPI2C0_SDAEWM_OUT_b LPUART0_RX 74 — — PTB11 DISABLED PTB11 FTM0_CH1LPI2C0_ HREQ FXIO_D1 75 — — PTB10 DISABLED PTB10 FTM0_CH0LPI2C0_ SDAS FXIO_D0 76 — — PTB9 DISABLED PTB9 LPI2C0_ SCLS FXIO_D5 77 — — PTB8 DISABLED PTB8 LPI2C0_SCL FXIO_D4 78 49 37 PTA1 ACMP0_IN1/ TSI1_CH3 ACMP0_IN1/ TSI1_CH3 PTA1 FTM1_CH1LPI2C0_ SDAS FXIO_D3 LPUART0_ RTS TRGMUX_ OUT0 79 50 38 PTA0 ACMP0_IN0/ TSI1_CH2 ACMP0_IN0/ TSI1_CH2 PTA0 FTM2_CH1LPI2C0_ SCLS FXIO_D2 LPUART0_ CTS TRGMUX_ OUT3 80 51 39 PTC7 TSI1_CH1TSI1_CH1PTC7 LPUART1_TX 81 52 40 PTC6 TSI1_CH0TSI1_CH0PTC6 LPUART1_RX 82 — — PTA16 DISABLED PTA16 FTM1_CH3 LPI2C0_SDA 83 — — PTA15 DISABLED PTA15 FTM1_CH2LPSPI0_ PCS3 84 53 41 PTE6 TSI0_CH0TSI0_CH0PTE6 LPSPI0_ PCS2 LPUART1_ RTS 85 54 42 PTE2 TSI0_CH1TSI0_CH1PTE2 LPSPI0_ SOUT LPTMR0_ ALT3 PWT_IN3 LPUART1_ CTS 86 — — VSS VSS VSS 87 — — VDD VDD VDD 88 — — PTA14 DISABLED PTA14 FTM0_FLT0 EWM_IN BUSOUT 89 55 — PTA13 TSI0_CH2TSI0_CH2PTA13 LPUART0_RX 90 56 — PTA12 TSI0_CH3TSI0_CH3PTA12 LPUART0_TX 91 57 — PTA11 TSI0_CH4TSI0_CH4PTA11 LPUART0_RXFXIO_D1 92 58 — PTA10 TSI0_CH5TSI0_CH5PTA10 LPUART0_TXFXIO_D0 93 59 43 PTE1 TSI0_CH6TSI0_CH6PTE1 LPSPI0_SINLPI2C0_ HREQ 94 60 44 PTE0 TSI0_CH7TSI0_CH7PTE0 LPSPI0_SCKTCLK1 95 61 45 PTC5 TSI0_CH8TSI0_CH8PTC5 FTM2_CH0 96 62 46 PTC4 SWD_CLKACMP0_IN2PTC4 FTM1_CH0LPUART1_RX EWM_IN SWD_CLK 97 63 47 PTA5 RESET_b PTA5 TCLK1 RESET_b 98 64 48 PTA4 SWD_DIO PTA4 LPUART1_TXACMP0_OUTEWM_OUT_b SWD_DIO 99 — — PTA9 DISABLED PTA9 FXIO_D7 TRGMUX_ OUT1 100 — — PTA8 DISABLED PTA8 FXIO_D6 TRGMUX_ OUT0 Pinouts Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 23 NXP Semiconductors
4.2 Port control and interrupt summary
Table 6. Ports summary
4.3 Module Signal Description Tables
the module's chapter. They also briefly describe the signal function and direction.
4.3.1 Core Modules
Table 7. SWD Signal Descriptions
4.3.2 System Modules
Table 8. System Signal Descriptions Table 9. EWM Signal Descriptions EWM_CTRL[ASSIN] bit. The default polarity is active-low.
4.3.3 Clock Modules
Table 10. OSC (in SCG) Signal Descriptions
4.3.4 Analog
Table 11. ADC 0 Signal Descriptions Table 12. ACMP 0 Signal Descriptions
4.3.5 Timer Modules
Table 13. LPTMR0 Signal Descriptions Table 14. FTM 0 Signal Descriptions Table 15. FTM 1 Signal Descriptions
Table 16. FTM 2 Signal Descriptions
4.3.6 Communication Interfaces
Table 17. LPSPI n Signal Descriptions Table 18. LPI2C n Signal Descriptions Table 19. LPUART n Signal Descriptions
Table 20. FlexIO Signal Descriptions
4.3.7 Human-Machine Interfaces (HMI)
Table 21. GPIO Signal Descriptions Table 22. TSI n Signal Descriptions
4.4 Pinout diagram
signals can be used on which pin, see the previous table of Pin Assignments.
98 PTA4
97 PTA5
96 PTC4
95 PTC5
94 PTE0
93 PTE1
92 PTA10
91 PTA11
90 PTA12
89 PTA13
88 PTA14
80 PTC7
83 PTA15
84 PTE6
85 PTE2
86 VSS
87 VDD
100 PTA8
Figure 5. 100 LQFP Pinout Diagram
Figure 6. 64 LQFP Pinout Diagram
Figure 7. 48 LQFP Pinout Diagram
4.5 Package dimensions
Figure 8. 100-pin LQFP package dimensions 1
Figure 9. 100-pin LQFP package dimensions 2
Figure 10. 64-pin LQFP package dimensions 1
Figure 11. 64-pin LQFP package dimensions 2
Figure 12. 48-pin LQFP package dimension
5 Electrical characteristics
5.1 Terminology and guidelines
5.1.1 Definitions
Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
Electrical characteristics
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 37 NXP Semiconductors
5.1.2 Examples
Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE
5.1.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 5.0 V 38 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
5.1.4 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
5.1.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
5.2 Ratings
5.2.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 39 NXP Semiconductors
5.2.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
5.2.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model − 6000 6000 V 1 VCDM Electrostatic discharge voltage, charged-device model All pins except the corner pins − 500 500 V Corner pins only − 750 750 V ILAT Latch-up current at ambient temperature upper limit − 100 100 mA 3 1. Determined according to JEDEC Standard JS001, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JS002, Field-Induced Charged-Device Model Test Method for Electrostatic- Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.2.4 Voltage and current operating ratings
Functional operating conditions appear in the "DC electrical specifications". Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 23. Voltage and current operating ratings Table continues on the next page... 40 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 23. Voltage and current operating ratings (continued)
- 60s lifetime - No restrictions, i.e. the part can switch.
10 hours lifetime - Device in reset, i.e. the part cannot switch.
5.3 General
5.3.1 Nonswitching electrical specifications
5.3.1.1 Voltage and current operating requirements
Table 24. Voltage and current operating requirements
- All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater
IICIO|. The actual resistor values should be an order of magnitude higher to tolerate transient voltages.
- Open drain outputs must be pulled to VDD.
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 41 NXP Semiconductors
Table 25. DC electrical specifications Table continues on the next page... 42 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 25. DC electrical specifications (continued)
- Max power supply ramp rate is 500 V/ms.
- The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value
- The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz.
- The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value
- Refers to the current that leaks into the core when the pad is in Hi-Z (Off state).
- Maximum pin leakage current at the ambient temperature upper limit.
- PTD0, PTD1, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability selected by the
associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
- Refers to the pin leakage on the GPIOs when they are OFF.
- Measured at VDD supply voltage = VDD min and input V = VSS
- Measured at VDD supply voltage = VDD min and input V = VDD
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 43 NXP Semiconductors
5.3.1.3 Voltage regulator electrical characteristics
100 LQFP
64 LQFP /
48 LQFP
Figure 13. Pinout decoupling Table 26. Voltage regulator electrical characteristics
- For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel.
- The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding VDD/VSS pins.
- The requirement and value of of CDEC will be decided by the device application requirement.
5.3.1.4 LVR, LVD and POR operating requirements
Table 27. V DD supply LVR, LVD and POR operating requirements 44 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
- Rising threshold is the sum of falling threshold and hysteresis voltage.
5.3.1.5 Power mode transition operating behaviors
Table 28. Power mode transition operating behaviors
- Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V.
- Max value is mean+6×sigma of tested values at the worst case of ambient temperature range and VDD 2.7 V to 5.5 V.
- After a POR event, the amount of time from the point VDD reaches the reference voltage 2.7 V to execution of the first
instruction, across the operating temperature range of the chip.
5.3.1.6 Power consumption
the standard deviation (mean + 3 sigma). Table 29. Power consumption operating behaviors Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 45 NXP Semiconductors
Table 29. Power consumption operating behaviors (continued) Flash in Compute Operation mode. Flash all peripheral clock disabled. Flash all peripheral clock enabled. Table continues on the next page... 46 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Flash all peripheral clock disabled. Flash all peripheral clock enabled. Flash all peripheral clock disabled. Flash all peripheral clock enabled. Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 47 NXP Semiconductors
- These values are based on characterization but not covered by test limits in production.
- PMC_REGSC[BIASEN] is the control bit to enable or disable bias under STOP/VLPS mode.
- PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.
optimization level high, optimized for balanced.
5.3.1.6.1 Low power mode peripheral current adder — typical value
with LPTMR enabled using LPO. Includes LPO power consumption. compare. 8-bit DAC enabled with half VDDA voltage, low speed mode. Includes 8-bit DAC power consumption. for RX data. Includes the DMA power consumption. Table continues on the next page... 48 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Symbol Description Typical ILPIT LPIT peripheral adder measured by placing the device in VLPS mode with internal SIRC 8 MHz enabled in Stop mode. Includes selected clock source power consumption. 18 μA ILPSPI LPSPI peripheral adder measured by placing the device in VLPS mode with selected clock source, output data on SOUT pin with SCK 500 kbit/s. Includes the DMA power consumption. 565 μA ITSI TSI self-cap mode: TSI peripheral adder measured by placing the device in RUN mode, continuous TSI self-cap mode scan with 11.6 kHz switching clock. 784 μA TSI mutual-cap mode: TSI peripheral adder measured by placing the device in RUN mode, continuous TSI mutual-cap mode scan with 37.22 kHz switching clock. 899 μA
5.3.1.6.2 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
- SCG in SOSC for both Run and VLPR modes
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 14. Run mode supply current vs. core frequency Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 49 NXP Semiconductors
Figure 15. VLPR mode supply current vs. core frequency
5.3.1.7 EMC performance
and guidance specifically targeted at optimizing EMC performance.
- AN2321: Designing for Board Level Electromagnetic Compatibility
- AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
- AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
- AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
- AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems
5.3.1.7.1 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request. 50 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
5.3.1.7.2 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. Go to http://www.nxp.com. 2. Perform a keyword search for “EMC design”. 3. Select the "Documents" category and find the application notes.
5.3.1.8 Capacitance attributes
Table 30. Capacitance attributes
5.3.2 Switching specifications
5.3.2.1 Device clock specifications
Table 31. Device clock specifications
- The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing
specification for any other module. Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 51 NXP Semiconductors
5.3.2.2 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% VIL Input Signal VIH Fall Time HighLow Rise Time Midpoint1 The midpoint is VIL + (VIH - VIL) / 2 Figure 16. Input signal measurement reference output pins have the following characteristics.
- C L=30 pF loads
- Normal drive strength
5.3.2.3 General AC specifications
Table 32. General switching specifications
- This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
- The greater of synchronous and asynchronous timing must be met.
- These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
- These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
52 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
5.3.2.4 AC specifications at 3.3 V range Table 33. Functional pad AC specifications
- Max power supply ramp rate is 500 V/ms.
- Propagation delay measured from 50% of core side input to 50% of the output.
- Edges measured using 20% and 80% of the VDD supply.
5.3.2.5 AC specifications at 5 V range
Table 34. Functional pad AC specifications
- Max power supply ramp rate is 500 V/ms.
- As measured from 50% of core side input to 50% of the output.
- Edges measured using 20% and 80% of the VDD supply.
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 53 NXP Semiconductors
All measurements were taken accounting for 150 mV drop across VDD and VSS.
5.3.3 Thermal specifications
5.3.3.1 Thermal operating requirements
Table 35. Thermal operating requirements
- Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
5.3.3.2 Thermal attributes
5.3.3.2.1 Description
The tables in the following sections describe the thermal characteristics of the device.
5.3.3.2.2 Thermal characteristics for the 100-pin LQFP package
Table 36. Thermal characteristics for the 100-pin LQFP package Table continues on the next page... 54 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 36. Thermal characteristics for the 100-pin LQFP package (continued)
- Thermal test board meets JEDEC specification for this package (JESD51-7).
- Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this
environment. It is not meant to predict the performance of a package in an application-specific environment.
5.3.3.2.3 Thermal characteristics for the 64-pin LQFP package
Table 37. Thermal characteristics for the 64-pin LQFP package
- Thermal test board meets JEDEC specification for this package (JESD51-7).
- Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this
environment. It is not meant to predict the performance of a package in an application-specific environment.
- Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold
surface temperature at the package top side dead centre.
5.3.3.2.4 Thermal characteristics for the 48-pin LQFP package
Table 38. Thermal characteristics for the 48-pin LQFP package
- Thermal test board meets JEDEC specification for this package (JESD51-7).
- Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this
environment. It is not meant to predict the performance of a package in an application-specific environment.
- Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold
surface temperature at the package top side dead centre. Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 55 NXP Semiconductors
5.3.3.2.5 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from this equation: TJ = TA + (RθJA × PD) where:
- T A = ambient temperature for the package (°C)
- R θJA = junction to ambient thermal resistance (°C/W)
- P D = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where:
- R θJA = junction to ambient thermal resistance (°C/W)
- R θJC = junction to case thermal resistance (°C/W)
- R θCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (ΨJT × PD)
56 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
where:
- T T = thermocouple temperature on top of the package (°C)
- ΨJT = thermal characterization parameter (°C/W)
- P D = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
5.4 Peripheral operating requirements and behaviors
5.4.1 System modules
There are no specifications necessary for the device's system modules.
5.4.2 Clock interface modules
5.4.2.1 Oscillator electrical specifications
5.4.2.1.1 External Oscillator electrical specifications
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 57 NXP Semiconductors
(EXTAL WAVE) mux ref_clk Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 300 ohms ESD PAD 40 ohms EXTAL pin XTAL pin Series resistor for current limitation Crystal or resonatorC1 C2 1M ohms Feedback Resistor1 NOTE: 1. 1M Feedback resistor is needed only for HG mode. Figure 17. Oscillator connections scheme (OSC) specifications" tables are from simulation. Table 39. External Oscillator electrical specifications (OSC)
4 MHz — 200 — µA
8 MHz — 300 — µA
Table continues on the next page... 58 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 39. External Oscillator electrical specifications (OSC) (continued)
32 MHz — 2 — mA
4 MHz — 1 — mA
24 MHz — 5 — mA
40 MHz — 6 — mA
- Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator,
- C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator
the parasitic capacitance of package and board. Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 59 NXP Semiconductors
- When low power mode is selected, RF is integrated and must not be attached externally. 4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.
5.4.2.1.2 External Oscillator frequency specifications
Table 40. External Oscillator frequency specifications (OSC)
- The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve
5.4.2.2 System Clock Generation (SCG) specifications
5.4.2.2.1 Fast internal RC Oscillator (FIRC) electrical specifications
Table 41. Fast internal RC Oscillator electrical specifications Table continues on the next page... 60 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 41. Fast internal RC Oscillator electrical specifications (continued)
- The limit is respected across process, voltage and full temperature range.
- Startup time is defined as the time between clock enablement and clock availability for system use.
5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications
Table 42. Slow internal RC oscillator (SIRC) electrical specifications
- The limit is respected across process, voltage and full temperature range.
- Startup time is defined as the time between clock enablement and clock availability for system use.
5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications
Table 43. Low Power Oscillator (LPO) electrical specifications
5.4.2.2.4 LPFLL electrical specifications
Table 44. LPFLL electrical specifications Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 61 NXP Semiconductors
Table 44. LPFLL electrical specifications (continued)
- ΔFcl is dependent on reference clock accuracy. For example, if locked to crystal oscillator, ΔFcl is typically limited by
trimming ability of the module itself; if locked to other clock source which has 3% accuracy, then ΔFcl can only be ±3%.
5.4.3 Memories and memory interfaces
5.4.3.1 Flash memory module (FTFA) electrical specifications
5.4.3.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 45. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
5.4.3.1.2 Flash timing specifications — commands
Table 46. Flash command timing specifications Table continues on the next page... 62 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 46. Flash command timing specifications (continued)
- Assumes 25 MHz flash clock frequency.
- Maximum times for erase parameters based on expectations at cycling end-of-life.
5.4.3.1.3 Flash high voltage current behaviors
Table 47. Flash high voltage current behaviors
5.4.3.1.4 Reliability specifications (Industrial)
Table 48. NVM reliability specifications
- Typical data retention values are based on measured response accelerated at high temperature and derated to a
- Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.4.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.4.5 Analog
Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 63 NXP Semiconductors
5.4.5.1 ADC electrical specifications
5.4.5.1.1 12-bit ADC operating conditions Table 49. 12-bit ADC operating conditions
- Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
- For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
- Clock and compare cycle need to be set according to the guidelines in the device Reference Manual.
- ADC conversion will become less reliable above maximum frequency.
- When using ADC hardware averaging, see the device Reference Manual to determine the most appropriate setting for
- Max ADC conversion rate of 1200 Ksps is with 10-bit mode
64 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Figure 18. ADC input impedance equivalency diagram clock as the clocking source for ADC. Table 50. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 65 NXP Semiconductors
Table 50. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
- Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 48 MHz unless otherwise stated.
- These values are based on characterization but not covered by test limits in production.
- The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
MHz ADC conversion clock speed.
- 1 LSB = (VREFH - VREFL)/2N
- ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
- Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz.
- ADC conversion clock < 3 MHz
- The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed
application information of the temperature sensor. 66 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
5.4.5.2 CMP with 8-bit DAC electrical specifications
Table 51. Comparator with 8-bit DAC electrical specifications Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 67 NXP Semiconductors
Table 51. Comparator with 8-bit DAC electrical specifications (continued)
- Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated.
- Difference at input > 200mV
- Applied ± (100 mV + Hyst) around switch point
- Applied ± (30 mV + 2 × Hyst) around switch point
Figure 19. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 68 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Figure 22. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 1)
5.4.6 Communication interfaces
5.4.6.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications.
5.4.6.2 LPSPI electrical specifications
with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins. Table 52. LPSPI master mode timing Table continues on the next page... 70 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 52. LPSPI master mode timing (continued)
- fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
High drive pin should be used for fast bit rate.
- If configured as an output.
Figure 23. LPSPI master mode timing (CPHA = 0) Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 71 NXP Semiconductors
<<CLASSIFICATION>> <<NDA MESSAGE>> 6 7 MSB IN 2 BIT 6 . . . 1 MASTER MSB OUT 2 MASTER LSB OUT 10 11 PORT DATA PORT DATA 3 10 11 4 1.If configured as output (OUTPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS 1 (OUTPUT) (OUTPUT) MOSI (OUTPUT) MISO (INPUT) LSB INBIT 6 . . . 1 Figure 24. LPSPI master mode timing (CPHA = 1) Table 53. LPSPI slave mode timing
- fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
- Time to data active from high-impedance state
- Hold time to high-impedance state
72 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
BIT 6 . . . 1 SLAVE MSB SLAVE LSB OUT 553 SEE NOTE see note (INPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS (INPUT) (INPUT) MOSI (INPUT) MISO (OUTPUT) LSB INBIT 6 . . . 1 Figure 25. LPSPI slave mode timing (CPHA = 0) Figure 26. LPSPI slave mode timing (CPHA = 1)
5.4.6.3 LPI2C
Table 54. LPI 2C specifications Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 73 NXP Semiconductors
- Hs-mode is only supported in slave mode. 2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more information on the required pull-up devices, see I2C Bus Specification. 3. See the section "General switching specifications".
5.4.7 Human-machine interfaces (HMI)
5.4.7.1 Touch sensing input (TSI) electrical specifications
Table 55. TSI electrical specifications
5.4.8 Debug modules
5.4.8.1 SWD electricals
Table 56. SWD full voltage range electricals Table continues on the next page... 74 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 56. SWD full voltage range electricals (continued) Figure 27. Serial wire clock input timing Figure 28. Serial wire data timing
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static voltage or electric fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit.
6.1.1 Printed circuit board recommendations
- Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
- Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground. Consider to add ferrite bead or inductor to some sensitive lines.
- Physically isolate analog circuits from digital circuits if possible.
- Place input filter capacitors as close to the MCU as possible.
- For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages.
6.1.2 Power delivery system
Consider the following items in the power delivery system:
- Use a plane for ground.
- Use a plane for MCU VDD supply if possible.
- Always route ground first, as a plane or continuous surface, and never as sequential segments.
- Always route the power net as star topology, and make each power trace loop as minimum as possible.
- Route power next, as a plane or traces that are parallel to ground traces.
- Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
- Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
- The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins. Design considerations 76 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
6.1.3 Analog design
small compared to the sample period. Figure 29. RC circuit for ADC input here to protect against transient over-voltages. Figure 30. High voltage measurement with an ADC input
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
- NMI pin Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level on this pin will trigger non-maskable interrupt. When this pin is enabled as the NMI function, an external pull-up resistor (10 kΩ) as shown in the following figure is recommended for robustness. If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is required to disable the NMI function by remapping to another function. The NMI function is disabled by programming the FOPT[NMI_DIS] bit to zero. D D C C B B A A EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR MCU ADCx MCU ADCx MCU RESET_b MCU NMI_b MCU RESET_b Supervisor Chip OUT Active high, open drain RESET_b SWD_DIO SWD_CLK Analog input High voltage input RESET_b VDD VDD VDD VDD VDD VDD Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 R 1 2 0.1uF 1 2 Cx 0.1uF RESONATOR 1 3 Cy Cx CRYSTAL HDR_5X2 1 2 3 4 7 8 9 10 Cy 10k 10k CRYSTAL 0.1uF 10k CRYSTAL 1 2 1 2 C RESONATOR 1 3 1 2 10k 10k RF 1 2 RS BAT54SW 1 2 RS RS C RF 1 2 RS 1 2 RF 1 2 CRYSTAL
Figure 33. NMI pin biasing
- Debug interface This MCU uses the standard ARM SWD interface protocol as shown in the following figure. While pull-up or pull-down resistors are not required (SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ pull resistors are recommended for system robustness. The RESET_b pin recommendations mentioned above must also be considered. Design considerations Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 79 NXP Semiconductors
Figure 34. SWD debug interface
- Unused pin Unused GPIO pins must be left floating (no electrical connections) with the MUX field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital input path to the MCU.
6.1.5 Crystal oscillator
MCU clock system, refer to the following table and diagrams. external feedback is required when using high gain (HGO=1) mode. frequency above 2 MHz does not require any series resistance. Table 57. External crystal/resonator connections
Figure 35. Crystal connection – Diagram 2 Figure 36. Crystal connection – Diagram 3 ring to the crystal oscillator circuit.
7 Part identification
7.1 Description
values of these fields to determine the specific part you have received.
7.2 Format
7.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Table 58. Part number fields description
- P = Prequalification KE## Kinetis family • KE17, KE13, KE12 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 128 = 128 KB
- 256 = 256 KB R Silicon revision • (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- C = –40 to 85
- LH = 64 LQFP (10 mm x 10 mm)
- LL = 100 LQFP (14 mm x 14 mm) CC Maximum CPU frequency (MHz) • 7 = 72 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
7.4 Example
8 Revision history
The following table provides a revision history for this document. Table 59. Revision history
Description
72SF1 v.2.2
1 December
- Replaced the 48-pin package drawing with the correct LQFP figure, in the "Package dimensions" section.
- Added new part of MKE13Z256CLH7. Table continues on the next page...
Revision history
82 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Table 59. Revision history (continued) 72SF1 v.2.1
10 February
- Added the new 48LQFP package and related information.
- Updated the "Thermal attributes" section. KE1xZP100M 72SF1 v.2
10 September
Initial public release. Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 83 NXP Semiconductors
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 84 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. HTML publications — An HTML version, if available, of this document is provided as a courtesy. Definitive information is contained in the applicable document in PDF format. If there is a discrepancy between the HTML document and the PDF document, the PDF document has priority. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 85 NXP Semiconductors
NXP — wordmark and logo are trademarks of NXP B.V. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. 86 Kinetis KE17Z/13Z/12Z with up to 256 KB Flash, Rev. 2.2, 12/2025 NXP Semiconductors
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2021-2025 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: December 2025 Document identifier: KE1xZP100M72SF1