KE1XZP48M48SF0 NXP | Alldatasheet

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Technical content

Kinetis KE1xZ with up to 64 KB Flash Up to 48 MHz Arm® Cortex®-M0+ Based Microcontroller Providing up to 64 KB flash, up to 8 KB RAM, and a complete set of analog/digital features, KE1xZ64 offers a robust Touch Sense Interface (TSI) and CAN bus for industrial networking, which provides high-level stability and accuracy in customer's home appliance touch UI and industrial control systems. Core Processor and System

  • Arm ® Cortex®-M0+ core, supports up to 48 MHz frequency
  • Arm Core based on the ARMv6 Architecture and Thumb®-2 ISA
  • Configurable Nested Vectored Interrupt Controller (NVIC)
  • Memory-Mapped Divide and Square Root module (MMDVSQ) Reliability, safety and security
  • Cyclic Redundancy Check (CRC) generator module
  • 128-bit unique identification (ID) number
  • Internal watchdog (WDOG) with independent clock source
  • External watchdog monitor (EWM) module
  • ADC self calibration feature
  • On-chip clock loss monitoring Power management
  • Low-power Arm Cortex-M0+ core with excellent energy efficiency
  • Power management controller (PMC) with multiple power modes: Run, Wait, Stop, VLPR, VLPW and VLPS Memory and memory interfaces
  • Up to 64 KB program flash
  • Up to 8 KB SRAM
  • 64 Bytes flash cache Mixed-signal analog
  • 1× 12-bit analog-to-digital converter (ADC) with up to 16 channel analog inputs per module, up to 1 Msps
  • 1× high-speed analog comparators (CMP) with internal 8-bit digital to analog converter (DAC) Timing and control
  • 2× Flex Timers (FTM) for PWM generation, offering 6ch+2ch
  • 1× 16-bit Low-Power Timer (LPTMR) with flexible wake up control
  • 1× Programmable Delay Block (PDB) with flexible trigger system
  • 1× 32-bit Low-power Periodic Interrupt Timer (LPIT) with 2 independent channels
  • Real timer clock (RTC) Debug functionality
  • Serial Wire Debug (SWD) debug interface
  • Debug Watchpoint and Trace (DWT)
  • Micro Trace Buffer (MTB) MKE1xZ64VLF4 MKE1xZ64VLD4 MKE1xZ64VFP4 MKE1xZ32VLF4 MKE1xZ32VLD4 MKE1xZ32VFP4

48 LQFP (LF)

7x7x1.4 mm P 0.5

44 LQFP (LD)

10x10x1.4 mm P 0.8

40 QFN (FP)

5x5x0.85 mm P 0.4 NXP Semiconductors KE1xZP48M48SF0 Data Sheet: Technical Data Rev. 3, 06/2020 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

  • Supports clock gating for unused modules, and specific peripherals remain working in low power modes
  • POR, LVD/LVR Clock interfaces
  • OSC: high range 4 - 40 MHz (with low power or high- gain mode) and low range 32 - 40 kHz (with high-gain mode only)
  • 48 MHz high-accuracy (up to ±1%) fast internal reference clock (FIRC) for normal Run
  • 8 MHz / 2 MHz high-accuracy (up to ±3%) slow internal reference clock (SIRC) for low-speed Run
  • 128 kHz low power oscillator (LPO)
  • Low-power FLL (LPFLL)
  • Up to 50 MHz DC external square wave input clock
  • System clock generator (SCG)
  • Real time counter (RTC) Human-machine interface (HMI)
  • Supports up to 32 interrupt request (IRQ) sources
  • Up to 42 GPIO pins with interrupt functionality
  • Touch sensing input (TSI) module Connectivity and communications interfaces
  • 3× low-power universal asynchronous receiver/ transmitter (LPUART) modules with FIFO support and low power availability
  • 1× low-power serial peripheral interface (LPSPI) modules with FIFO support and low power availability
  • 1× low-power inter-integrated circuit (LPI2C) modules with FIFO support and low power availability
  • 1× CAN module (MSCAN), with 5 Rx buffers and 3 Tx buffers Operating Characteristics
  • Voltage range: 2.7 to 5.5 V
  • Ambient temperature range: –40 to 105 °C Related Resources Type Description Resource Fact Sheet The Fact Sheet gives overview of the product key features and its uses. KE1xZ Family Fact Sheet Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. KE1xZ64PB1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KE1xZP48M48SF0RM 1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document: KE1xZP48M48SF0 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Kinetis_E_0N16X 1 Package drawing Package dimensions are provided in package drawings. 48-LQFP: 98ASH00962A 44-LQFP: 98ASS23225W 40-QFN: 98ASA01371D 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Figure 1. Functional block diagram

2.2.12 Modular/Scalable Controller Area Network

5.1.4 Relationship between ratings and operating

5.1.5 Guidelines for ratings and operating

4 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

1 Ordering information

The following chips are available for ordering. Table 1. Ordering information

  1. INT: interrupt pin numbers; HD: high drive pin numbers

2 Overview

The following figure shows the system diagram of this device.

Ordering information

Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 5 NXP Semiconductors

Figure 2. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure.

2.1 System features

The following sections describe the high-level system features.

2.1.1 ARM Cortex-M0+ core

2.1.2 NVIC

also differs in number of interrupt sources and supports 32 interrupt vectors.

2.1.3 AWIC

wake MCU core from Partial Stop, Stop and VLPS modes. Table 2. AWIC Stop and VLPS Wake-up Sources Table continues on the next page...

Table 2. AWIC Stop and VLPS Wake-up Sources (continued)

2.1.4 Memory

  • Upto 64 KB of embedded program flash memory.
  • Upto 8 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.
  • The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 1 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. The security circuitry prevents unauthorized access to RAM or flash contents from debug port.

2.1.5 Reset and boot

The following table lists all the reset sources supported by this device.

Table 3. Reset source

  1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
  2. Except SMC_PMPROT, SMC_PMCTRL_RUM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT
  3. Except RCM_RPC, RCM_MR, RCM_FM, RCM_SRIE, RCM_SRS, RCM_SSRS
  4. Except SCG_CSR and SCG_FIRCSTAT
  • internal flash

2.1.6 Clock options

allow granular shutoff of modules.

Figure 3. Clocking block diagram

2.1.7 Security

2.1.8 Power management

application can be selected. Interrupt Controller (AWIC) are used to wake up the MCU from low power states. AWIC is used to wake up the MCU core from STOP and VLPS modes. NVIC, AWIC, please refer to the Reference Manual. Table 5. Peripherals states in different operational modes Table continues on the next page...

Table 5. Peripherals states in different operational modes (continued) Run In Run mode, all device modules are operational. except the Low Voltage Detect (LVD) monitor, which is disabled. frequency except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU core is placed into Sleep mode. be used to wake up from an interrupt. including flash programming/erasing.

2.1.9 Debug controller

capabilities. The standard ARM debug port supports SWD interface.

2.2 Peripheral features

The following sections describe the features of each peripherals of the chip.

2.2.1 FTM

This device contains two FlexTimer modules.

The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. Several key enhancements of this module are made:

  • Signed up counter
  • Deadtime insertion hardware
  • Fault control inputs
  • Enhanced triggering functionality
  • Initialization and polarity control

2.2.2 ADC

This device contains one 12-bit SAR ADC modules. The ADC module supports hardware triggers from FTM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features:

  • Linear successive approximation algorithm with up to 12-bit resolution
  • Up to 12 single-ended external analog inputs
  • Support 12-bit, 10-bit, and 8-bit single-ended output modes
  • Single or continuous conversion
  • Configurable sample time and conversion speed/power
  • Input clock selectable from up to four sources
  • Operation in low-power modes for lower noise
  • Selectable hardware conversion trigger
  • Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
  • Temperature sensor
  • Hardware average function
  • Selectable Voltage reference: from external or alternate
  • Self-Calibration mode

2.2.2.1 Temperature sensor

This device contains one temperature sensor internally connected to the input channel of AD26, see ADC electrical characteristics for details of the linearity factor. Overview Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 13 NXP Semiconductors

The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed application information of the temperature sensor.

2.2.3 CMP

There are one analog comparators on this device.

  • Each CMP has its own independent 8-bit DAC.
  • Each CMP supports up to 6 analog inputs from external pins.
  • Each CMP is able to convert an internal reference from the bandgap.
  • Each CMP supports the round-robin sampling scheme. In summary, this allow the CMP to operate independently in VLPS and Stop modes, whilst being triggered periodically to sample up to 8 inputs. Only if an input changes state is a full wakeup generated. The CMP has the following features:
  • Inputs may range from rail to rail
  • Programmable hysteresis control
  • Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges of the comparator output
  • Selectable inversion on comparator output
  • Capability to produce a wide range of outputs such as sampled, windowed, or digitally filtered
  • External hysteresis can be used at the same time that the output filter is used for internal functions
  • Two software selectable performance levels: Shorter propagation delay at the expense of higher power, and Low power with longer propagation delay
  • Functional in all power modes available on this MCU
  • The window and filter functions are not available in STOP mode
  • Integrated 8-bit DAC with selectable supply reference source and can be power down to conserve power

2.2.4 RTC

The RTC is an always powered-on block that remains active in all low power modes. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. The RTC module has the following features

  • 32-bit seconds counter with roll-over protection and 32-bit alarm Overview 14 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors
  • 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm
  • Register write protection with register lock mechanism
  • 1 Hz square wave or second pulse output with optional interrupt

2.2.5 LPIT

The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module generating independent pre-trigger and trigger outputs. These timer channels can operate individually or can be chained together. The LPIT can operate in low power modes if configured to do so. The pre-trigger and trigger outputs can be used to trigger other modules on the device.

2.2.6 PDB

The Programmable Delay Block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved. The PDB can optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in the CMP block. The PDB module has the following capabilities:

  • trigger input sources and one software trigger source
  • 1 DAC refresh trigger output, for this device
  • configurable PDB channels for ADC hardware trigger
  • 1 pulse output, for this device

2.2.7 LPTMR

The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features:

  • 16-bit time counter or pulse counter with compare Overview Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 15 NXP Semiconductors
  • Optional interrupt can generate asynchronous wakeup from any low-power mode
  • Hardware trigger output
  • Counter supports free-running mode or reset on compare
  • Configurable clock source for prescaler/glitch filter
  • Configurable input source for pulse counter

2.2.8 CRC

This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The CRC module has the following features:

  • Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register
  • Programmable initial seed value and polynomial
  • Option to transpose input data or output data (the CRC result) bitwise or bytewise.
  • Option for inversion of final CRC result
  • 32-bit CPU register programming interface

2.2.9 LPUART

This product contains three Low-Power UART modules, and can work in Stop and VLPS modes. The module also supports 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features:

  • Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32×
  • Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode
  • Interrupt, or polled operation
  • Hardware parity generation and checking
  • Programmable 8-bit, 9-bit or 10-bit character length
  • Programmable 1-bit or 2-bit stop bits
  • Three receiver wakeup methods Overview 16 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors
  • Idle line wakeup
  • Address mark wakeup
  • Receive data match
  • Automatic address matching to reduce ISR overhead:
  • Address mark matching
  • Idle line address matching
  • Address match start, address match end
  • Optional 13-bit break character generation / 11-bit break character detection
  • Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters
  • Selectable transmitter output and receiver input polarity

2.2.10 LPSPI

This device contains one LPSPI modules. The LPSPI is a low power Serial Peripheral Interface (SPI) module that supports an efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPSPI modules have the following features:

  • Command/transmit FIFO of 4 words
  • Receive FIFO of 4 words
  • Host request input can be used to control the start time of an SPI bus transfer

2.2.11 LPI2C

This device contains one LPI2C modules. The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master and/or a slave. The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C implements logic support for standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The LPI2C module also complies with the System Management Bus (SMBus) Specification, version 2. The LPI2C modules have the following features:

  • Standard, Fast, Fast+ and Ultra Fast modes are supported
  • HS-mode supported in slave mode Overview Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 17 NXP Semiconductors
  • Multi-master support including synchronization and arbitration
  • Clock stretching
  • General call, 7-bit and 10-bit addressing
  • Software reset, START byte and Device ID require software support
  • For master mode:
  • command/transmit FIFO of 4 words
  • receive FIFO of 4 words
  • For slave mode:
  • separate I2C slave registers to minimize software overhead due to master/slave switching
  • support for 7-bit or 10-bit addressing, address range, SMBus alert and general call address
  • transmit/receive data register supporting interrupt requests

2.2.12 Modular/Scalable Controller Area Network (MSCAN)

This device contains one CAN module. It uses the MSCAN mudule which is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. Its 5 Rx buffers and 3 Tx buffers are adaptable to target CAN applications. The MSCAN module has the following features :

  • Implementation of the CAN protocol Version 2.0 A/B
  • Standard and extended data frames
  • 0-to-8 bytes data length
  • Programmable bit rate up to 1 Mbit/s
  • Support for remote frames
  • Individual Rx Mask Registers per Message Buffer
  • Internal timer for time-stamping of received and transmitted messages
  • Listen-only mode capability
  • Programmable loopback mode supporting self-test operation
  • Programmable transmission priority scheme: lowest ID, lowest buffer number, or highest priority
  • Low power modes, with programmable wakeup on bus activity Overview 18 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

2.2.13 Port control and GPIO

corresponding Port Control and Interrupt module for that pin is enabled. Figure 4. I/O simplified block diagram

  • all PIN support interrupt enable
  • Configurable edge (rising, falling, or both) or level sensitive interrupt type
  • Support DMA request Overview Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 19 NXP Semiconductors
  • Asynchronous wake-up in low-power modes
  • Configurable pullup, pulldown, and pull-disable on select pins
  • Configurable high and low drive strength on selected pins
  • Configurable passive filter on selected pins
  • Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions
  • Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features:
  • Port Data Input register visible in all digital pin-multiplexing modes
  • Port Data Output register with corresponding set/clear/toggle registers
  • Port Data Direction register
  • GPIO support single-cycle access via fast GPIO.

3 Memory map

This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. For more details of the system memory and peripheral locations, see the Memory Map chapter in the Reference Manual.

4 Pinouts

4.1 KE1xZ64 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. LQFP LQFP QFN Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — — 5 PTE5 TSI0_CH0TSI0_CH0PTE5 TCLK2 EWM_IN — — 6 PTE4 TSI0_CH1TSI0_CH1PTE4 BUSOUT EWM_OUT_b — — 32 PTC7 TSI0_CH16TSI0_CH16PTC7 LPUART1_TX — — 33 PTC6 TSI0_CH15TSI0_CH15PTC6 LPUART1_RX 1 1 1 PTD1 TSI0_CH5TSI0_CH5PTD1 FTM0_CH3 TRGMUX_ OUT2 2 2 2 PTD0 TSI0_CH4TSI0_CH4PTD0 FTM0_CH2 TRGMUX_ OUT1 Memory map 20 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 3 — 3 PTE11 TSI0_CH3TSI0_CH3PTE11 PWT_IN1 LPTMR0_ ALT1 4 — 4 PTE10 TSI0_CH2TSI0_CH2PTE10 CLKOUT 5 3 — PTE5 TSI0_CH0TSI0_CH0PTE5 TCLK2 CAN0_TX EWM_IN 6 4 — PTE4 TSI0_CH1TSI0_CH1PTE4 BUSOUT CAN0_RX EWM_OUT_b 7 5 7 VDD VDD VDD 8 6 7 VDDA VDDA VDDA 9 7 7 VREFH VREFH VREFH 10 8 — VSS/ VREFL VSS/ VREFL VSS/ VREFL 11 9 8 PTB7 EXTAL EXTAL PTB7 LPI2C0_SCL 12 10 9 PTB6 XTAL XTAL PTB6 LPI2C0_SDA 13 11 — PTE3 TSI0_CH24TSI0_CH24PTE3 FTM0_FLT0LPUART2_ RTS 14 — 10 PTE8 ACMP0_IN3/ TSI0_CH11 ACMP0_IN3/ TSI0_CH11 PTE8 15 12 11 PTB5 TSI0_CH9TSI0_CH9PTB5 FTM0_CH5LPSPI0_ PCS1 TRGMUX_IN0 16 13 12 PTB4 TSI0_CH8TSI0_CH8PTB4 FTM0_CH4LPSPI0_ SOUT TRGMUX_IN1 17 14 13 PTC3 ADC0_SE11/ ACMP0_IN4 ADC0_SE11/ ACMP0_IN4 PTC3 FTM0_CH3 18 15 14 PTC2 ADC0_SE10/ ACMP0_IN5 ADC0_SE10/ ACMP0_IN5 PTC2 FTM0_CH2 19 16 15 PTD7 TSI0_CH10TSI0_CH10PTD7 LPUART2_TX 20 17 16 PTD6 TSI0_CH7TSI0_CH7PTD6 LPUART2_RX 21 18 17 PTD5 TSI0_CH6TSI0_CH6PTD5 LPTMR0_ ALT2 PWT_IN2 LPUART2_ CTS 22 19 18 PTC1 ADC0_SE9/ TSI0_CH23 ADC0_SE9/ TSI0_CH23 PTC1 FTM0_CH1 23 20 19 PTC0 ADC0_SE8/ TSI0_CH22 ADC0_SE8/ TSI0_CH22 PTC0 FTM0_CH0 24 21 20 PTB3 ADC0_SE7/ TSI0_CH21 ADC0_SE7/ TSI0_CH21 PTB3 FTM1_CH1LPSPI0_SINFTM1_QD_ PHA TRGMUX_IN2 25 22 22 PTB2 ADC0_SE6/ TSI0_CH20 ADC0_SE6/ TSI0_CH20 PTB2 FTM1_CH0LPSPI0_SCKFTM1_QD_ PHB TRGMUX_IN3 26 23 23 PTB1 ADC0_SE5ADC0_SE5PTB1 LPUART0_TXLPSPI0_ SOUT TCLK0 27 24 24 PTB0 ADC0_SE4ADC0_SE4PTB0 LPUART0_RXLPSPI0_ PCS0 LPTMR0_ ALT3 PWT_IN3 28 25 25 PTA7 ADC0_SE3ADC0_SE3PTA7 FTM0_FLT2LPSPI0_ PCS3 RTC_CLKIN LPUART1_ RTS 29 26 — PTA6 ADC0_SE2ADC0_SE2PTA6 FTM0_FLT1 LPUART1_ CTS Pinouts Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 21 NXP Semiconductors

4.2 Port control and interrupt summary

Table 6. Ports summary Table continues on the next page...

Table 6. Ports summary (continued)

4.3 Module Signal Description Tables

in the module's chapter. They also briefly describe the signal function and direction.

4.3.1 Core Modules

Table 7. SWD Signal Descriptions

4.3.2 System Modules

Table 8. System Signal Descriptions Table 9. EWM Signal Descriptions of EWM_IN is programmable using the EWM_CTRL[ASSIN] bit. The default polarity is active-low.

4.3.3 Clock Modules

Table 10. OSC (in SCG) Signal Descriptions

4.3.4 Analog

Table 11. ADC 0 Signal Descriptions Table continues on the next page...

Table 11. ADC 0 Signal Descriptions (continued) Table 12. ACMP 0 Signal Descriptions

4.3.5 Timer Modules

Table 13. LPTMR0 Signal Descriptions Table 14. RTC Signal Descriptions Table 15. FTM 0 Signal Descriptions Table 16. FTM 1 Signal Descriptions Table continues on the next page...

Table 16. FTM 1 Signal Descriptions (continued)

4.3.6 Communication Interfaces

Table 17. CAN n Signal Descriptions Table 18. LPSPI n Signal Descriptions Table 19. LPI2C n Signal Descriptions Table 20. LPUART n Signal Descriptions

4.3.7 Human-Machine Interfaces (HMI)

Table 21. GPIO Signal Descriptions Table 22. TSI0 Signal Descriptions

4.4 Pinout diagram

signals can be used on which pin, see the previous table of Pin Assignments.

Figure 5. 48 LQFP Pinout Diagram

33 PTA2

Figure 6. 44 LQFP Pinout Diagram

Figure 7. 40 QFN Pinout Diagram

4.5 Package dimensions

options for the devices supported by this document.

  • 48-LQFP: 98ASH00962A
  • 44-LQFP: 98ASS23225W
  • 40-QFN: 98ASA01371D Pinouts 30 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

5 Electrical characteristics

5.1 Terminology and guidelines

5.1.1 Definitions

Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

  • Operating ratings apply during operation of the chip.
  • Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
  • Lies within the range of values specified by the operating behavior
  • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

Electrical characteristics

Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 31 NXP Semiconductors

5.1.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE

5.1.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 5.0 V 32 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

5.1.4 Relationship between ratings and operating requirements

  • No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

5.1.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

  • Never exceed any of the chip’s ratings.
  • During normal operation, don’t exceed any of the chip’s operating requirements.
  • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

5.2 Ratings

5.2.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 33 NXP Semiconductors

5.2.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

5.2.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model − 6000 6000 V 1 VCDM Electrostatic discharge voltage, charged-device model All pins except the corner pins − 500 500 V Corner pins only − 750 750 V ILAT Latch-up current at ambient temperature upper limit − 100 100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

5.2.4 Voltage and current operating ratings

Functional operating conditions appear in the "DC electrical specifications". Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 23. Voltage and current operating ratings Table continues on the next page... 34 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Table 23. Voltage and current operating ratings (continued)

  1. 60s lifetime - No restrictions, i.e. the part can switch.

10 hours lifetime - Device in reset, i.e. the part cannot switch.

5.3 General

5.3.1 Nonswitching electrical specifications

5.3.1.1 Voltage and current operating requirements

Table 24. Voltage and current operating requirements

  1. All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater

IICIO|. The actual resistor values should be an order of magnitude higher to tolerate transient voltages.

  1. Open drain outputs must be pulled to VDD.

Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 35 NXP Semiconductors

Table 25. DC electrical specifications Table continues on the next page... 36 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Table 25. DC electrical specifications (continued)

  1. Max power supply ramp rate is 500 V/ms.
  2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value
  3. The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz.
  4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value
  5. Refers to the current that leaks into the core when the pad is in Hi-Z (Off state).
  6. Maximum pin leakage current at the ambient temperature upper limit.
  7. PTD0, PTD1, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability selected by the

associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

  1. Refers to the pin leakage on the GPIOs when they are OFF.
  2. Measured at VDD supply voltage = VDD min and input V = VSS
  3. Measured at VDD supply voltage = VDD min and input V = VDD

Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 37 NXP Semiconductors

5.3.1.3 Voltage regulator electrical characteristics

48 LQFP /

44 LQFP

Figure 8. Pinout decoupling Table 26. Voltage regulator electrical characteristics

  1. For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel.
  2. The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding VDD/VSS pins.
  3. The requirement and value of of CDEC will be decided by the device application requirement.

5.3.1.4 LVR, LVD and POR operating requirements

Table 27. V DD supply LVR, LVD and POR operating requirements

  1. Rising threshold is the sum of falling threshold and hysteresis voltage.

38 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

5.3.1.5 Power mode transition operating behaviors

Table 28. Power mode transition operating behaviors

  1. Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V.
  2. Max value is mean+6×sigma of tested values at the worst case of ambient temperature range and VDD 2.7 V to 5.5 V.
  3. After a POR event, the amount of time from the point VDD reaches the reference voltage 2.7 V to execution of the first

instruction, across the operating temperature range of the chip.

5.3.1.6 Power consumption

the standard deviation (mean + 3 sigma). Table 29. Power consumption operating behaviors (48 LQFP and 44 LQFP) Table continues on the next page... Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 39 NXP Semiconductors

Table 29. Power consumption operating behaviors (48 LQFP and 44 LQFP) (continued) Flash in Compute Operation mode. Flash all peripheral clock disabled. Flash all peripheral clock enabled. Table continues on the next page... 40 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Flash all peripheral clock disabled. Flash all peripheral clock enabled. Flash all peripheral clock disabled. Flash all peripheral clock enabled. Table continues on the next page... Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 41 NXP Semiconductors

  1. These values are based on characterization but not covered by test limits in production.
  2. PMC_REGSC[BIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.
  3. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable clockbias under STOP/VLPS mode.

Table 30. Power consumption operating behaviors (40 QFN) Table continues on the next page... 42 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Table 30. Power consumption operating behaviors (40 QFN) (continued) all peripheral clock disabled. all peripheral clock enabled. Flash all peripheral clock disabled. Flash all peripheral clock enabled. Flash all peripheral clock disabled. Flash all peripheral clock enabled. Table continues on the next page... Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 43 NXP Semiconductors

  1. These values are based on characterization but not covered by test limits in production.
  2. PMC_REGSC[BIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.
  3. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable clockbias under STOP/VLPS mode.

44 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

CoreMark benchmark compiled using IAR 8.30 with optimization level high, optimized for balanced.

5.3.1.6.1 Low power mode peripheral current adder — typical value

Symbol Description Typical ILPTMR LPTMR peripheral adder measured by placing the device in VLPS mode with LPTMR enabled using LPO. Includes LPO power consumption. 366 nA ICMP CMP peripheral adder measured by placing the device in VLPS mode with CMP enabled using the 8-bit DAC and a single external input for compare. 8-bit DAC enabled with half VDDA voltage, low speed mode. Includes 8-bit DAC power consumption. 16 μA IRTC RTC peripheral adder measured by placing the device in VLPS mode with external 32 kHz crystal enabled by means of the RTC_CR[OSCE] bit and the RTC counter enabled. Includes EXTAL32 (32 kHz external crystal) power consumption. 312 nA ILPUART LPUART peripheral adder measured by placing the device in VLPS mode with selected clock source waiting for RX data at 115200 baud rate. Includes selected clock source power consumption. (SIRC 8 MHz) 79 μA IFTM FTM peripheral adder measured by placing the device in VLPW mode with selected clock source, outputting the edge aligned PWM of 100 Hz frequency. 45 μA IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in VLPS mode. ADC is configured for low power mode using SIRC clock source, 8-bit resolution and continuous conversions. 484 μA ILPI2C LPI2C peripheral adder measured by placing the device in VLPS mode with selected clock source sending START and Slave address, waiting for RX data. Includes the DMA power consumption. 179 μA ILPIT LPIT peripheral adder measured by placing the device in VLPS mode with internal SIRC 8 MHz enabled in Stop mode. Includes selected clock source power consumption. 18 μA ILPSPI LPSPI peripheral adder measured by placing the device in VLPS mode with selected clock source, output data on SOUT pin with SCK 500 kbit/s. Includes the DMA power consumption. 565 μA IMSCAN MSCAN peripheral adder measured by placing the device in RUN mode, CAN baud rate = 125 kbps, loopback mode: MSCAN receives the frame sent by itself continuously. 2354 μA ITSI TSI self-cap mode: TSI peripheral adder measured by placing the device in RUN mode, continuous TSI self-cap mode scan with 11.6 kHz switching clock. 784 μA TSI mutual-cap mode: TSI peripheral adder measured by placing the device in RUN mode, continuous TSI mutual-cap mode scan with 37.22 kHz switching clock. 899 μA Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 45 NXP Semiconductors

5.3.1.6.2 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

  • SCG in SOSC for both Run and VLPR modes
  • No GPIOs toggled
  • Code execution from flash with cache enabled
  • For the ALLOFF curve, all peripheral clocks are disabled except FTFA

Figure 9. Run mode supply current vs. core frequency 46 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Figure 10. VLPR mode supply current vs. core frequency

5.3.1.7 EMC performance

and guidance specifically targeted at optimizing EMC performance.

  • AN2321: Designing for Board Level Electromagnetic Compatibility
  • AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
  • AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
  • AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
  • AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems

5.3.1.7.1 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request. Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 47 NXP Semiconductors

5.3.1.7.2 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. Go to http://www.nxp.com. 2. Perform a keyword search for “EMC design”. 3. Select the "Documents" category and find the application notes.

5.3.1.8 Capacitance attributes

Table 31. Capacitance attributes

5.3.2 Switching specifications

5.3.2.1 Device clock specifications

Table 32. Device clock specifications

  1. The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing

specification for any other module. 48 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

5.3.2.2 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% VIL Input Signal VIH Fall Time HighLow Rise Time Midpoint1 The midpoint is VIL + (VIH - VIL) / 2 Figure 11. Input signal measurement reference output pins have the following characteristics.

  • C L=30 pF loads
  • Normal drive strength

5.3.2.3 General AC specifications

Table 33. General switching specifications

  1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
  2. The greater of synchronous and asynchronous timing must be met.
  3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
  4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be

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5.3.2.4 AC specifications at 3.3 V range Table 34. Functional pad AC specifications

  1. Max power supply ramp rate is 500 V/ms.
  2. Propagation delay measured from 50% of core side input to 50% of the output.
  3. Edges measured using 20% and 80% of the VDD supply.

5.3.2.5 AC specifications at 5 V range

Table 35. Functional pad AC specifications

  1. Max power supply ramp rate is 500 V/ms.
  2. As measured from 50% of core side input to 50% of the output.
  3. Edges measured using 20% and 80% of the VDD supply.

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All measurements were taken accounting for 150 mV drop across VDD and VSS.

5.3.3 Thermal specifications

5.3.3.1 Thermal operating requirements

Table 36. Thermal operating requirements

  1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

determine TJ is: TJ = TA + RΘJA × chip power dissipation.

5.3.3.2 Thermal attributes

5.3.3.2.1 Description

The tables in the following sections describe the thermal characteristics of the device.

5.3.3.2.2 Thermal characteristics for the 44-pin LQFP package

Table 37. Thermal characteristics for the 44-pin LQFP package Table continues on the next page... Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 51 NXP Semiconductors

Table 37. Thermal characteristics for the 44-pin LQFP package (continued)

  1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
  2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

  1. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s

or 2s2p board, respectively.

  1. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

  1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
  2. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

5.3.3.2.3 Thermal characteristics for the 48-pin LQFP package

Table 38. Thermal characteristics for the 48-pin LQFP package

  1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
  2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

  1. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s

or 2s2p board, respectively.

  1. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

  1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

52 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

  1. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

5.3.3.2.4 Thermal characteristics for the 40-pin QFN package

Table 39. Thermal characteristics for the 40-pin QFN package

  1. Thermal test board meets JEDEC specification for this package (JESD51-9).
  2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this

environment. It is not meant to predict the performance of a package in an application-specific environment.

  1. Junction-to-Case thermal resistance determined using an isothermal cold plate. Case is defined as the bottom of the

5.3.3.2.5 General notes for specifications at maximum junction temperature

  • T A = ambient temperature for the package (°C)
  • R θJA = junction to ambient thermal resistance (°C/W)
  • P D = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated.

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When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where:

  • R θJA = junction to ambient thermal resistance (°C/W)
  • R θJC = junction to case thermal resistance (°C/W)
  • R θCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (ΨJT × PD) where:
  • T T = thermocouple temperature on top of the package (°C)
  • ΨJT = thermal characterization parameter (°C/W)
  • P D = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

5.4 Peripheral operating requirements and behaviors

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5.4.1 System modules

There are no specifications necessary for the device's system modules.

5.4.2 Clock interface modules

5.4.2.1 Oscillator electrical specifications

5.4.2.1.1 External Oscillator electrical specifications

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(EXTAL WAVE) mux ref_clk Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 300 ohms ESD PAD 40 ohms EXTAL pin XTAL pin Series resistor for current limitation Crystal or resonatorC1 C2 1M ohms Feedback Resistor1 NOTE: 1. 1M Feedback resistor is needed only for HG mode. Figure 12. Oscillator connections scheme (OSC) specifications" tables are from simulation. Table 40. External Oscillator electrical specifications (OSC)

4 MHz — 200 — µA

8 MHz — 300 — µA

Table continues on the next page... 56 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

32 MHz — 2 — mA

4 MHz — 1 — mA

24 MHz — 5 — mA

40 MHz — 6 — mA

  1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator,

Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 57 NXP Semiconductors

  1. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider the parasitic capacitance of package and board. 3. When low power mode is selected, RF is integrated and must not be attached externally. 4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices.

5.4.2.1.2 External Oscillator frequency specifications

Table 41. External Oscillator frequency specifications (OSC)

  1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve

5.4.2.2 System Clock Generation (SCG) specifications

5.4.2.2.1 Fast internal RC Oscillator (FIRC) electrical specifications

Table 42. Fast internal RC Oscillator electrical specifications Table continues on the next page... 58 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

  1. The limit is respected across process, voltage and full temperature range.
  2. Startup time is defined as the time between clock enablement and clock availability for system use.

5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications

Table 43. Slow internal RC oscillator (SIRC) electrical specifications

  1. The limit is respected across process, voltage and full temperature range.
  2. Startup time is defined as the time between clock enablement and clock availability for system use.

5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications

Table 44. Low Power Oscillator (LPO) electrical specifications Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 59 NXP Semiconductors

5.4.2.2.4 LPFLL electrical specifications

Table 45. LPFLL electrical specifications

  1. ΔFcl is dependent on reference clock accuracy. For example, if locked to crystal oscillator, ΔFcl is typically limited by

trimming ability of the module itself; if locked to other clock source which has 3% accuracy, then ΔFcl can only be ±3%.

5.4.3 Memories and memory interfaces

5.4.3.1 Flash memory module (FTFA) electrical specifications

5.4.3.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 46. NVM program/erase timing specifications

  1. Maximum time based on expectations at cycling end-of-life.

5.4.3.1.2 Flash timing specifications — commands

Table 47. Flash command timing specifications Table continues on the next page... 60 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Table 47. Flash command timing specifications (continued)

  1. Assumes 25 MHz flash clock frequency.
  2. Maximum times for erase parameters based on expectations at cycling end-of-life.

5.4.3.1.3 Flash high voltage current behaviors

Table 48. Flash high voltage current behaviors

5.4.3.1.4 Reliability specifications

Table 49. NVM reliability specifications

  1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
  2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.

5.4.4 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules. Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 61 NXP Semiconductors

5.4.5 Analog

5.4.5.1 ADC electrical specifications

5.4.5.1.1 12-bit ADC operating conditions Table 50. 12-bit ADC operating conditions

  1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

  1. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
  2. Clock and compare cycle need to be set according the guidelines in the block guide.
  3. ADC conversion will become less reliable above maximum frequency.
  4. When using ADC hardware averaging, refer to the device Reference Manual to determine the most appropriate setting
  5. Max ADC conversion rate of 1200 Ksps is with 10-bit mode

62 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Figure 13. ADC input impedance equivalency diagram clock as the clocking source for ADC. Table 51. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page... Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 63 NXP Semiconductors

Table 51. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

  1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
  2. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 48 MHz unless otherwise stated.
  3. These values are based on characterization but not covered by test limits in production.
  4. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

MHz ADC conversion clock speed.

  1. 1 LSB = (VREFH - VREFL)/2N
  2. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
  3. Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz.
  4. ADC conversion clock < 3 MHz
  5. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed

application information of the temperature sensor. 64 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

5.4.5.2 CMP with 8-bit DAC electrical specifications

Table 52. Comparator with 8-bit DAC electrical specifications Table continues on the next page... Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 65 NXP Semiconductors

Table 52. Comparator with 8-bit DAC electrical specifications (continued)

  1. Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated.
  2. Difference at input > 200mV
  3. Applied ± (100 mV + Hyst) around switch point
  4. Applied ± (30 mV + 2 × Hyst) around switch point

Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 66 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Figure 17. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 1)

5.4.6 Communication interfaces

5.4.6.1 LPUART electrical specifications

Refer to General AC specifications for LPUART specifications.

5.4.6.2 LPSPI electrical specifications

with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins. Table 53. LPSPI master mode timing Table continues on the next page... 68 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Table 53. LPSPI master mode timing (continued)

  1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.

High drive pin should be used for fast bit rate.

  1. If configured as an output.

Figure 18. LPSPI master mode timing (CPHA = 0) Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 69 NXP Semiconductors

<<CLASSIFICATION>> <<NDA MESSAGE>> 6 7 MSB IN 2 BIT 6 . . . 1 MASTER MSB OUT 2 MASTER LSB OUT 10 11 PORT DATA PORT DATA 3 10 11 4 1.If configured as output (OUTPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS 1 (OUTPUT) (OUTPUT) MOSI (OUTPUT) MISO (INPUT) LSB INBIT 6 . . . 1 Figure 19. LPSPI master mode timing (CPHA = 1) Table 54. LPSPI slave mode timing

  1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
  2. Time to data active from high-impedance state
  3. Hold time to high-impedance state

70 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

BIT 6 . . . 1 SLAVE MSB SLAVE LSB OUT 553 SEE NOTE see note (INPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS (INPUT) (INPUT) MOSI (INPUT) MISO (OUTPUT) LSB INBIT 6 . . . 1 Figure 20. LPSPI slave mode timing (CPHA = 0) Figure 21. LPSPI slave mode timing (CPHA = 1)

5.4.6.3 LPI2C

Table 55. LPI 2C specifications Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 71 NXP Semiconductors

  1. Hs-mode is only supported in slave mode. 2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more information on the required pull-up devices, see I2C Bus Specification. 3. See the section "General switching specifications".

5.4.6.4 Modular/Scalable Controller Area Network (MSCAN)

Table 56. MSCAN Timing Parameters Figure 22. Bus Wake-up Detection

5.4.7 Human-machine interfaces (HMI)

5.4.7.1 Touch sensing input (TSI) electrical specifications

Table 57. TSI electrical specifications Table continues on the next page... 72 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

Table 57. TSI electrical specifications (continued)

5.4.8 Debug modules

5.4.8.1 SWD electricals

Table 58. SWD full voltage range electricals Figure 23. Serial wire clock input timing Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 73 NXP Semiconductors

Figure 24. Serial wire data timing

6 Design considerations

6.1 Hardware design considerations

voltages higher than maximum-rated voltages to this high-impedance circuit.

6.1.1 Printed circuit board recommendations

  • Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
  • Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground. Consider to add ferrite bead or inductor to some sensitive lines.
  • Physically isolate analog circuits from digital circuits if possible. Design considerations 74 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors
  • Place input filter capacitors as close to the MCU as possible.
  • For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages.

6.1.2 Power delivery system

  • Use a plane for ground.
  • Use a plane for MCU VDD supply if possible.
  • Always route ground first, as a plane or continuous surface, and never as sequential segments.
  • Always route the power net as star topology, and make each power trace loop as minimum as possible.
  • Route power next, as a plane or traces that are parallel to ground traces.
  • Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
  • Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
  • The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins.

6.1.3 Analog design

small compared to the sample period. Figure 25. RC circuit for ADC input

against transient over-voltages. Figure 26. High voltage measurement with an ADC input

6.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).

  • RESET_b pin The RESET_b pin is a pseudo open-drain I/O pin that has an internal pullup resistor. An external RC circuit is recommended to filter noise as shown in the following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to reject spurious noise. Design considerations 76 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

6.1.5 Crystal oscillator

MCU clock system, refer to the following table and diagrams. The feedback resistor, RF, is incorporated internally with the low power oscillators. An external feedback is required when using high gain (HGO=1) mode. frequency above 2 MHz does not require any series resistance. Table 59. External crystal/resonator connections Figure 31. Crystal connection – Diagram 2 Figure 32. Crystal connection – Diagram 3 ring to the crystal oscillator circuit.

6.2 Software considerations

All Kinetis MCUs are supported by comprehensive NXP and third-party hardware and software enablement solutions, which can reduce development costs and time to market. Featured software and tools are listed below. Visit http://www.nxp.com/kinetis/sw for more information and supporting collateral. Evaluation and Prototyping Hardware

  • Freedom Development Platform: http://www.nxp.com/freedom IDEs for Kinetis MCUs
  • MCUXpresso IDE: https://www.nxp.com/support/developer-resources/software- development-tools/mcuxpresso-software-and-tools/mcuxpresso-integrated- development-environment-ide:MCUXpresso-IDE
  • Partner IDEs: http://www.nxp.com/kide Run-time Software
  • MCUXpresso Software Development Kit (SDK): https://www.nxp.com/support/ developer-resources/software-development-tools/mcuxpresso-software-and-tools/ mcuxpresso-software-development-kit-sdk:MCUXpresso-SDK For all other partner-developed software and tools, visit http://www.nxp.com/partners.

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format: Q KE## A FFF R T PP CC N Part identification 80 Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 NXP Semiconductors

7.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Table 60. Part number fields description

  • P = Prequalification KE## Kinetis family • KE16, KE15, KE14 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 32 = 32 KB
  • 64 = 64 KB R Silicon revision • (Blank) = Main
  • A = Revision after main T Temperature range (°C) • V = –40 to 105
  • LF = 48 LQFP (7 mm x 7 mm)
  • FP = 40 QFN (5 mm x 5 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel
  • (Blank) = Trays

7.4 Example

8 Revision history

The following table provides a revision history for this document. Table 61. Revision history 2 01/2019 Initial public release. Power consumption, Thermal characteristics, etc.) are updated.

Revision history

Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020 81 NXP Semiconductors

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