MKE15Z128VLH7

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Kinetis KE1xZ with up to 256 KB Flash Up to 72 MHz ARM® Cortex®-M0+ Based Microcontroller Kinetis KE1xZ256 MCUs are the leading parts for the KE1xZ familiy based on ARM® Cortex®-M0+ core. Providing up to 256 KB flash, up to 32 KB RAM, and the complete set of analog/ digital features, KE1xZ extends Kinetis E family to higher performance and broader scalability. Robust TSI provides high- level stability and accuracy to customer's HMI system. 1 Msps ADC and FlexTimer help build a perfect solution for BLDC motor control systems. Core Processor and System

• ARM ® Cortex®-M0+ core, supports up to 72 MHz frequency
• ARM Core based on the ARMv6 Architecture and Thumb®-2 ISA
• Configurable Nested Vectored Interrupt Controller (NVIC)
• Memory-Mapped Divide and Square Root module (MMDVSQ)
• 8-channel DMA controller extended up to 63 channels with DMAMUX Reliability, safety and security
• Flash Access Control (FAC)
• Cyclic Redundancy Check (CRC) generator module
• 128-bit unique identification (ID) number
• Internal watchdog (WDOG) with independent clock source
• External watchdog monitor (EWM) module
• ADC self calibration feature
• On-chip clock loss monitoring Human-machine interface (HMI)
• Supports up to 32 interrupt request (IRQ) sources
• Up to 89 GPIO pins with interrupt functionality
• Touch sensing input (TSI) module Memory and memory interfaces
• Up to 256 KB program flash
• Up to 32 KB SRAM
• 32 KB FlexNVM for data flash and with EEPROM emulation
• 2 KB FlexRAM for EEPROM emulation
• 128 Bytes flash cache
• Boot ROM with built in bootloader Mixed-signal analog
• 2× 12-bit analog-to-digital converter (ADC) with up to 16 channel analog inputs per module, up to 1 Msps
• 2× high-speed analog comparators (CMP) with internal 8-bit digital to analog converter (DAC); the 8-bit DAC of CMP0 supports an output option to pad with a buffer Timing and control
• 3× Flex Timers (FTM) for PWM generation, offering up to 8 standard channels
• 1× 16-bit Low-Power Timer (LPTMR) with flexible wake up control
• 1× Programmable Delay Block (PDB) with flexible trigger system
• 1× 32-bit Low-power Periodic Interrupt Timer (LPIT) with 4 channels
• Real timer clock (RTC) MKE1xZ256VLL7 MKE1xZ256VLH7 MKE1xZ128VLL7 MKE1xZ128VLH7

100 LQFP (LL)

14x14x1.4 mm P 0.5

64 LQFP (LH)

10x10x1.4 mm P 0.5 NXP Semiconductors KE1xZP100M72SF0 Data Sheet: Technical Data Rev. 4.2, 03/2021 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• 4 - 40 MHz fast external oscillator (OSC)
• 32 kHz slow external oscillator (OSC32)
• 48 - 60 MHz high-accuracy (up to ±1%) fast internal reference clock (FIRC) for normal Run
• 8 MHz / 2 MHz high-accuracy (up to ±3%) slow internal reference clock (SIRC) for low-speed Run
• 128 kHz low power oscillator (LPO)
• Low-power FLL (LPFLL)
• Up to 60 MHz DC external square wave input clock
• System clock generator (SCG)
• Real time counter (RTC) Power management
• Low-power ARM Cortex-M0+ core with excellent energy efficiency
• Power management controller (PMC) with multiple power modes: Run, Wait, Stop, VLPR, VLPW and VLPS
• Supports clock gating for unused modules, and specific peripherals remain working in low power modes
• POR, LVD/LVR Connectivity and communications interfaces
• 3× low-power universal asynchronous receiver/ transmitter (LPUART) modules with DMA support and low power availability
• 2× low-power serial peripheral interface (LPSPI) modules with DMA support and low power availability
• 2× low-power inter-integrated circuit (LPI2C) modules with DMA support and low power availability
• FlexIO module for flexible and high performance serial interfaces Debug functionality
• Serial Wire Debug (SWD) debug interface
• Debug Watchpoint and Trace (DWT)
• Micro Trace Buffer (MTB) Operating Characteristics
• Voltage range: 2.7 to 5.5 V
• Ambient temperature range: –40 to 105 °C Related Resources Type Description Resource Selector Guide The Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. KE1xZ256PB 1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. KE1xZP100M72SF0RM 1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document: KE1xZP100M72SF0 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Kinetis_E_1N36S 1 Kinetis_E_2N36S 1 Package drawing Package dimensions are provided in package drawings. 100-LQFP: 98ASS23308W 64-LQFP: 98ASS23234W 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Figure 1. Functional block diagram

5.1.4 Relationship between ratings and operating

5.1.5 Guidelines for ratings and operating

4 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

1 Ordering information

The following chips are available for ordering. Table 1. Ordering information

1. INT: interrupt pin numbers; HD: high drive pin numbers

2 Overview

The following figure shows the system diagram of this device.

Ordering information

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 5 NXP Semiconductors

8 KB ROM

Figure 2. System diagram The crossbar switch connects bus masters and slaves using a crossbar switch structure.

2.1 System features

The following sections describe the high-level system features.

2.1.1 ARM Cortex-M0+ core

2.1.2 NVIC

also differs in number of interrupt sources and supports 32 interrupt vectors.

2.1.3 AWIC

wake MCU core from Partial Stop, Stop and VLPS modes. Table 2. AWIC Stop and VLPS Wake-up Sources Table continues on the next page...

Table 2. AWIC Stop and VLPS Wake-up Sources (continued)

2.1.4 Memory

• Upto 256 KB of embedded program flash memory.
• Upto 32 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.
• The non-volatile memory is divided into several arrays:
• 32 KB of embedded data flash memory
• 2 KB of Emulated EEPROM
• 8 KB ROM (built-in bootloader to support UART, I2C, and SPI interfaces) The program flash memory contains a 16-byte flash configuration field that stores default protection settings and security information. The page size of program flash is 1 KB. The protection setting can protect 32 regions of the program flash memory from unintended erase or program operations. The security circuitry prevents unauthorized access to RAM or flash contents from debug port.

2.1.5 Reset and boot

The following table lists all the reset sources supported by this device.

Table 3. Reset source

1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
2. Except SMC_PMPROT, SMC_PMCTRL_RUM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT
3. Except RCM_RPC, RCM_MR, RCM_FM, RCM_SRIE, RCM_SRS, RCM_SSRS
4. Except SCG_CSR and SCG_FIRCSTAT

• internal flash
• boot ROM Overview Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 9 NXP Semiconductors

Figure 3. Boot flow chart address, otherwise, it remaps to flash address.

2.1.6 Clock options

including the clocks for the system bus masters, system bus slaves, and flash memory . granular shutoff of modules.

48 MHz

Figure 4. Clocking block diagram

2.1.7 Security

2.1.7.1 Flash Access Control (FAC)

rights for each transaction routed to the on-chip flash memory. Configurability allows an increasing number of protected segments while supporting two levels of vendors adding their proprietary software to a device.

2.1.8 Power management

The Power Management Controller (PMC) expands upon ARM’s operational modes of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can be used to optimize current consumption for a wide range of applications. The WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current configuration. For more information on ARM’s operational modes, See the ARM® Cortex® User Guide. The PMC provides Normal Run (RUN), and Very Low Power Run (VLPR) configurations in ARM’s Run operation mode. In these modes, the MCU core is active and can access all peripherals. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The configuration that matches the power versus performance requirements of the application can be selected. The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive, all of the peripherals can be enabled and operate as programmed. The difference between the modes is the maximum clock frequency of the system and therefore the power consumption. The PMC provides Stop (Stop), Very Low Power Stop (VLPS) configurations in ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the peripherals are disabled. Depending on the requirements of the application, different portions of the analog, logic, and memory can be retained or disabled to conserve power. The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up Interrupt Controller (AWIC) are used to wake up the MCU from low power states. The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU core from STOP and VLPS modes. For additional information regarding operational modes, power management, the NVIC, AWIC, please refer to the Reference Manual. The following table provides information about the state of the peripherals in the various operational modes and the modules that can wake MCU from low power modes. Overview 12 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 5. Peripherals states in different operational modes Run mode Run In Run mode, all device modules are operational. except the Low Voltage Detect (LVD) monitor, which is disabled. frequency except the Low Voltage Detect (LVD) monitor, which is disabled. The MCU core is placed into Sleep mode. be used to wake up from an interrupt. command including flash programming/erasing.

2.1.9 Debug controller

capabilities. The standard ARM debug port supports SWD interface.

2.2 Peripheral features

The following sections describe the features of each peripherals of the chip.

transferred data itself. The DMA controller in this device implements 8 channels which can be routed from up to 63 DMA request sources through DMA MUX module. Main features of eDMA are listed below:

• All data movement via dual-address transfers: read from source, write to destination
• 8-channel implementation that performs complex data transfers with minimal intervention from a host processor
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
• Channel activation via one of three methods
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via programmable interrupt requests
• Programmable support for scatter/gather DMA processing
• Support for complex data structures

2.2.2 FTM

This device contains three FlexTimer modules. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. Several key enhancements of this module are made:

• Signed up counter
• Deadtime insertion hardware
• Fault control inputs
• Enhanced triggering functionality
• Initialization and polarity control

2.2.3 ADC

This device contains two 12-bit SAR ADC modules. The ADC module supports hardware triggers from FTM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features: Overview 14 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

• Linear successive approximation algorithm with up to 12-bit resolution
• Up to 16 single-ended external analog inputs
• Support 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Input clock selectable from up to four sources
• Operation in low-power modes for lower noise
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function
• Selectable Voltage reference: from external or alternate
• Self-Calibration mode

2.2.3.1 Temperature sensor

This device contains one temperature sensor internally connected to the input channel of AD26, see ADC electrical characteristics for details of the linearity factor. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed application information of the temperature sensor.

2.2.4 CMP

There aretwo analog comparators on this device.

• Each CMP has its own independent 8-bit DAC.
• Each CMP supports up to 6 analog inputs from external pins.
• Each CMP is able to convert an internal reference from the bandgap.
• Each CMP supports the round-robin sampling scheme. In summary, this allow the CMP to operate independently in VLPS and Stop modes, whilst being triggered periodically to sample up to 8 inputs. Only if an input changes state is a full wakeup generated. The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges of the comparator output
• Selectable inversion on comparator output Overview Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 15 NXP Semiconductors

• Capability to produce a wide range of outputs such as sampled, windowed, or digitally filtered
• External hysteresis can be used at the same time that the output filter is used for internal functions
• Two software selectable performance levels: Shorter propagation delay at the expense of higher power, and Low power with longer propagation delay
• DMA transfer support
• Functional in all power modes available on this MCU
• The window and filter functions are not available in STOP mode
• Integrated 8-bit DAC with selectable supply reference source and can be power down to conserve power

2.2.5 RTC

The RTC is an always powered-on block that remains active in all low power modes. The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator, or clock directly from RTC_CLKIN pin. RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all RTC registers. The RTC module has the following features

• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt

2.2.6 LPIT

The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module generating independent pre-trigger and trigger outputs. These timer channels can operate individually or can be chained together. The LPIT can operate in low power modes if configured to do so. The pre-trigger and trigger outputs can be used to trigger other modules on the device. This device contains one LPIT module with four channels. The LPIT generates periodic trigger events to the DMAMUX. Overview 16 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

2.2.7 PDB

The Programmable Delay Block (PDB) provides controllable delays from either an internal or an external trigger, or a programmable interval tick, to the hardware trigger inputs of ADCs and/or generates the interval triggers to DACs, so that the precise timing between ADC conversions and/or DAC updates can be achieved. The PDB can optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in the CMP block. The PDB module has the following capabilities:

• trigger input sources and one software trigger source
• 1 DAC refresh trigger output, for this device
• configurable PDB channels for ADC hardware trigger
• 1 pulse output, for this device

2.2.8 LPTMR

The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features:

• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter

2.2.9 CRC

This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. Overview Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 17 NXP Semiconductors

The CRC module has the following features:

• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface

2.2.10 LPUART

This product contains three Low-Power UART modules, and can work in Stop and VLPS modes. The module also supports 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features:

• Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32×
• Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters
• Selectable transmitter output and receiver input polarity Overview 18 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

2.2.11 LPSPI

This device contains two LPSPI modules. The LPSPI is a low power Serial Peripheral Interface (SPI) module that supports an efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPSPI module has the following features:

• Command/transmit FIFO of 4 words
• Receive FIFO of 4 words
• Host request input can be used to control the start time of an SPI bus transfer

2.2.12 LPI2C

This device contains two LPI2C modules. The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master and/or a slave. The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C implements logic support for standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The LPI2C module also complies with the System Management Bus (SMBus) Specification, version 2. The LPI2C modules have the following features:

• Standard, Fast, Fast+ and Ultra Fast modes are supported
• HS-mode supported in slave mode
• Multi-master support including synchronization and arbitration
• Clock stretching
• General call, 7-bit and 10-bit addressing
• Software reset, START byte and Device ID require software support
• For master mode:
• command/transmit FIFO of 4 words
• receive FIFO of 4 words
• For slave mode:
• separate I2C slave registers to minimize software overhead due to master/ slave switching
• support for 7-bit or 10-bit addressing, address range, SMBus alert and general call address
• transmit/receive data register supporting interrupt or DMA requests Overview Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 19 NXP Semiconductors

2.2.13 FlexIO

The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features:

• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer
• The timing of the shifter's shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter
• Two or more shifters can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity
• Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation

2.2.14 Port control and GPIO

The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The following figure shows the basic I/O pad structure. Pseudo open-drain pins have the p-channel output driver disabled when configured for open-drain operation. None of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above VDD. NOTE The RESET_b pin is also a normal I/O pad with pseudo open- drain. Overview 20 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Figure 5. I/O simplified block diagram

• all PIN support interrupt enable
• Configurable edge (rising, falling, or both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
• Port Data Direction register
• GPIO support single-cycle access via fast GPIO. Overview Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 21 NXP Semiconductors

3 Memory map

This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. For more details of the system memory and peripheral locations, see the Memory Map chapter in the Reference Manual. Memory map 22 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

devices with different part numbers. See "Ordering information" in DataSheet for details. Figure 6. Memory map

4 Pinouts

4.1 KE1xZ Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE On this device, there are several special ADC channels which support hardware interleave between multiple ADCs. Taking ADC0_SE4 and ADC1_SE14 channels as an example, these two channels can work independently, but they can also be hardware interleaved. In the hardware interleaved mode, a signal on the pin PTB0 can be sampled by both ADC0 and ADC1. The interleaved mode is enabled by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits. For more information, see "ADC Hardware Interleaved Channels" in the ADC chapter of Reference Manual. 100 LQFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 — 10 VREFL/ VSS VREFL/ VSS VREFL/ VSS 1 — PTE16 DISABLED PTE16 FXIO_D3 TRGMUX_ OUT7 2 — PTE15 DISABLED PTE15 FXIO_D2 TRGMUX_ OUT6 3 1 PTD1 TSI0_CH5 TSI0_CH5 PTD1 FTM0_CH3LPSPI1_SINFTM2_CH1 FXIO_D1 TRGMUX_ OUT2 4 2 PTD0 TSI0_CH4 TSI0_CH4 PTD0 FTM0_CH2LPSPI1_SCKFTM2_CH0 FXIO_D0 TRGMUX_ OUT1 5 3 PTE11 TSI0_CH3 TSI0_CH3 PTE11 PWT_IN1 LPTMR0_ ALT1 FXIO_D5 TRGMUX_ OUT5 6 4 PTE10 TSI0_CH2 TSI0_CH2 PTE10 CLKOUT FXIO_D4 TRGMUX_ OUT4 7 — PTE13 DISABLED PTE13 8 5 PTE5 TSI0_CH0 TSI0_CH0 PTE5 TCLK2 FTM2_QD_ PHA FTM2_CH3 FXIO_D7 EWM_IN 9 6 PTE4 TSI0_CH1 TSI0_CH1 PTE4 BUSOUT FTM2_QD_ PHB FTM2_CH2 FXIO_D6 EWM_OUT_b Pinouts 24 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 10 7 VDD VDD VDD 11 8 VDDA VDDA VDDA 12 9 VREFH VREFH VREFH 13 — VREFL VREFL VREFL 14 — VSS VSS VSS 15 11 PTB7 EXTAL EXTAL PTB7 LPI2C0_SCL 16 12 PTB6 XTAL XTAL PTB6 LPI2C0_SDA 17 — PTE14 DISABLED PTE14 FTM0_FLT1 18 13 PTE3 TSI0_CH24TSI0_CH24PTE3 FTM0_FLT0LPUART2_ RTS TRGMUX_IN6 19 — PTE12 DISABLED PTE12 FTM0_FLT3LPUART2_TX 20 — PTD17 DISABLED PTD17 FTM0_FLT2LPUART2_RX 21 14 PTD16 DISABLED PTD16 FTM0_CH1 22 15 PTD15 DISABLED PTD15 FTM0_CH0 23 16 PTE9 DAC0_OUTDAC0_OUTPTE9 FTM0_CH7LPUART2_ CTS 24 — PTD14 DISABLED PTD14 CLKOUT 25 — PTD13 DISABLED PTD13 RTC_CLKOUT 26 17 PTE8 ACMP0_IN3/ TSI0_CH11 ACMP0_IN3/ TSI0_CH11 PTE8 FTM0_CH6 27 18 PTB5 TSI0_CH9 TSI0_CH9 PTB5 FTM0_CH5LPSPI0_PCS1 TRGMUX_IN0ACMP1_OUT 28 19 PTB4 ACMP1_IN2/ TSI0_CH8 ACMP1_IN2/ TSI0_CH8 PTB4 FTM0_CH4LPSPI0_SOUT TRGMUX_IN1 29 20 PTC3 ADC0_SE11/ ACMP0_IN4/ EXTAL32 ADC0_SE11/ ACMP0_IN4/ EXTAL32 PTC3 FTM0_CH3 30 21 PTC2 ADC0_SE10/ ACMP0_IN5/ XTAL32 ADC0_SE10/ ACMP0_IN5/ XTAL32 PTC2 FTM0_CH2 31 22 PTD7 TSI0_CH10TSI0_CH10PTD7 LPUART2_TX FTM2_FLT3 32 23 PTD6 TSI0_CH7 TSI0_CH7 PTD6 LPUART2_RX FTM2_FLT2 33 24 PTD5 TSI0_CH6 TSI0_CH6 PTD5 FTM2_CH3LPTMR0_ ALT2 PWT_IN2 TRGMUX_IN7 34 — PTD12 DISABLED PTD12 FTM2_CH2LPI2C1_HREQ LPUART2_ RTS 35 — PTD11 DISABLED PTD11 FTM2_CH1FTM2_QD_ PHA LPUART2_ CTS 36 — PTD10 DISABLED PTD10 FTM2_CH0FTM2_QD_ PHB 37 — VSS VSS VSS 38 — VDD VDD VDD 39 25 PTC1 ADC0_SE9/ ACMP1_IN3/ TSI0_CH23 ADC0_SE9/ ACMP1_IN3/ TSI0_CH23 PTC1 FTM0_CH1 Pinouts Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 25 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 40 26 PTC0 ADC0_SE8/ ACMP1_IN4/ TSI0_CH22 ADC0_SE8/ ACMP1_IN4/ TSI0_CH22 PTC0 FTM0_CH0 41 — PTD9 ACMP1_IN5ACMP1_IN5PTD9 LPI2C1_SCL FTM2_FLT3 42 — PTD8 DISABLED PTD8 LPI2C1_SDA FTM2_FLT2 43 27 PTC17 ADC0_SE15ADC0_SE15PTC17 FTM1_FLT3 LPI2C1_SCLS 44 28 PTC16 ADC0_SE14ADC0_SE14PTC16 FTM1_FLT2 LPI2C1_SDAS 45 29 PTC15 ADC0_SE13ADC0_SE13PTC15 FTM1_CH3 46 30 PTC14 ADC0_SE12ADC0_SE12PTC14 FTM1_CH2 47 31 PTB3 ADC0_SE7/ TSI0_CH21 ADC0_SE7/ TSI0_CH21 PTB3 FTM1_CH1LPSPI0_SINFTM1_QD_ PHA TRGMUX_IN2 48 32 PTB2 ADC0_SE6/ TSI0_CH20 ADC0_SE6/ TSI0_CH20 PTB2 FTM1_CH0LPSPI0_SCKFTM1_QD_ PHB TRGMUX_IN3 49 — PTC13 DISABLED PTC13 50 — PTC12 DISABLED PTC12 51 — PTC11 DISABLED PTC11 52 — PTC10 DISABLED PTC10 53 33 PTB1 ADC0_SE5ADC0_SE5PTB1 LPUART0_TXLPSPI0_SOUTTCLK0 54 34 PTB0 ADC0_SE4ADC0_SE4PTB0 LPUART0_RXLPSPI0_PCS0LPTMR0_ ALT3 PWT_IN3 55 35 PTC9 DISABLED PTC9 LPUART1_TX LPUART0_ RTS 56 36 PTC8 DISABLED PTC8 LPUART1_RX LPUART0_ CTS 57 37 PTA7 ADC0_SE3/ ACMP1_IN1 ADC0_SE3/ ACMP1_IN1 PTA7 FTM0_FLT2 RTC_CLKIN LPUART1_ RTS 58 38 PTA6 ADC0_SE2/ ACMP1_IN0 ADC0_SE2/ ACMP1_IN0 PTA6 FTM0_FLT1LPSPI1_PCS1 LPUART1_ CTS 59 39 PTE7 DISABLED PTE7 FTM0_CH7 60 40 VSS VSS VSS 61 41 VDD VDD VDD 62 — PTA17 DISABLED PTA17 FTM0_CH6 EWM_OUT_b 63 — PTB17 DISABLED PTB17 FTM0_CH5LPSPI1_PCS3 64 — PTB16 DISABLED PTB16 FTM0_CH4LPSPI1_SOUT 65 — PTB15 DISABLED PTB15 FTM0_CH3LPSPI1_SIN 66 — PTB14 ADC1_SE9ADC1_SE9PTB14 FTM0_CH2LPSPI1_SCK 67 42 PTB13 ADC1_SE8ADC1_SE8PTB13 FTM0_CH1 68 43 PTB12 ADC1_SE7ADC1_SE7PTB12 FTM0_CH0 69 44 PTD4 ADC1_SE6ADC1_SE6PTD4 FTM0_FLT3 70 45 PTD3 NMI_b ADC1_SE3PTD3 LPSPI1_PCS0FXIO_D5 TRGMUX_IN4NMI_b 71 46 PTD2 ADC1_SE2ADC1_SE2PTD2 LPSPI1_SOUTFXIO_D4 TRGMUX_IN5 72 47 PTA3 ADC1_SE1ADC1_SE1PTA3 LPI2C0_SCLEWM_IN LPUART0_TX Pinouts 26 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 73 48 PTA2 ADC1_SE0ADC1_SE0PTA2 LPI2C0_SDAEWM_OUT_b LPUART0_RX 74 — PTB11 DISABLED PTB11 LPI2C0_HREQ 75 — PTB10 DISABLED PTB10 LPI2C0_SDAS 76 — PTB9 DISABLED PTB9 LPI2C0_SCLS 77 — PTB8 DISABLED PTB8 78 49 PTA1 ADC0_SE1/ ACMP0_IN1/ TSI0_CH18 ADC0_SE1/ ACMP0_IN1/ TSI0_CH18 PTA1 FTM1_CH1LPI2C0_SDASFXIO_D3 FTM1_QD_ PHA LPUART0_ RTS TRGMUX_ OUT0 79 50 PTA0 ADC0_SE0/ ACMP0_IN0/ TSI0_CH17 ADC0_SE0/ ACMP0_IN0/ TSI0_CH17 PTA0 FTM2_CH1LPI2C0_SCLSFXIO_D2 FTM2_QD_ PHA LPUART0_ CTS TRGMUX_ OUT3 80 51 PTC7 ADC1_SE5/ TSI0_CH16 ADC1_SE5/ TSI0_CH16 PTC7 LPUART1_TX 81 52 PTC6 ADC1_SE4/ TSI0_CH15 ADC1_SE4/ TSI0_CH15 PTC6 LPUART1_RX 82 — PTA16 DISABLED PTA16 FTM1_CH3LPSPI1_PCS2 83 — PTA15 DISABLED PTA15 FTM1_CH2LPSPI0_PCS3 84 53 PTE6 ADC1_SE11ADC1_SE11PTE6 LPSPI0_PCS2 LPUART1_ RTS 85 54 PTE2 ADC1_SE10/ TSI0_CH19 ADC1_SE10/ TSI0_CH19 PTE2 LPSPI0_SOUTLPTMR0_ ALT3 PWT_IN3 LPUART1_ CTS 86 — VSS VSS VSS 87 — VDD VDD VDD 88 — PTA14 DISABLED PTA14 FTM0_FLT0 EWM_IN BUSOUT 89 55 PTA13 DISABLED PTA13 LPI2C1_SCLS 90 56 PTA12 DISABLED PTA12 LPI2C1_SDAS 91 57 PTA11 DISABLED PTA11 LPUART0_RXFXIO_D1 92 58 PTA10 DISABLED PTA10 LPUART0_TXFXIO_D0 93 59 PTE1 TSI0_CH14TSI0_CH14PTE1 LPSPI0_SINLPI2C0_HREQLPI2C1_SCL 94 60 PTE0 TSI0_CH13TSI0_CH13PTE0 LPSPI0_SCKTCLK1 LPI2C1_SDA FTM1_FLT2 95 61 PTC5 TSI0_CH12TSI0_CH12PTC5 FTM2_CH0RTC_CLKOUTLPI2C1_HREQ FTM2_QD_ PHB 96 62 PTC4 SWD_CLK ACMP0_IN2PTC4 FTM1_CH0RTC_CLKOUT EWM_IN FTM1_QD_ PHB SWD_CLK 97 63 PTA5 RESET_b PTA5 TCLK1 RESET_b 98 64 PTA4 SWD_DIO PTA4 ACMP0_OUTEWM_OUT_b SWD_DIO 99 — PTA9 DISABLED PTA9 FXIO_D7 FTM1_FLT3 100 — PTA8 DISABLED PTA8 FXIO_D6 Pinouts Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 27 NXP Semiconductors

4.2 Port control and interrupt summary

Table 6. Ports summary

4.3 Module Signal Description Tables

the module's chapter. They also briefly describe the signal function and direction.

4.3.1 Core Modules

Table 7. SWD Signal Descriptions

4.3.2 System Modules

Table 8. System Signal Descriptions Table 9. EWM Signal Descriptions EWM_CTRL[ASSIN] bit. The default polarity is active-low.

4.3.3 Clock Modules

Table 10. OSC (in SCG) Signal Descriptions

Table 11. RTC Oscillator (OSC32) Signal Descriptions

4.3.4 Analog

Table 12. ADC 0 Signal Descriptions Table 13. ADC 1 Signal Descriptions Table 14. ACMP 0 Signal Descriptions Table 15. ACMP 1 Signal Descriptions

4.3.5 Timer Modules

Table 16. LPTMR0 Signal Descriptions Table 17. RTC Signal Descriptions Table 18. FTM 0 Signal Descriptions Table 19. FTM 1 Signal Descriptions Table 20. FTM 2 Signal Descriptions

4.3.6 Communication Interfaces

Table 21. LPSPI n Signal Descriptions Table 22. LPI2C n Signal Descriptions Table 23. LPUART n Signal Descriptions Table 24. FlexIO Signal Descriptions

4.3.7 Human-Machine Interfaces (HMI)

Table 25. GPIO Signal Descriptions Table 26. TSI0 Signal Descriptions

4.4 Pinout diagram

signals can be used on which pin, see the previous table of Pin Assignments.

98 PTA4

97 PTA5

96 PTC4

95 PTC5

94 PTE0

93 PTE1

92 PTA10

91 PTA11

90 PTA12

89 PTA13

88 PTA14

80 PTC7

83 PTA15

84 PTE6

85 PTE2

86 VSS

87 VDD

100 PTA8

Figure 7. 100 LQFP Pinout Diagram

Figure 8. 64 LQFP Pinout Diagram

4.5 Package dimensions

Figure 9. 100-pin LQFP package dimensions 1

Figure 10. 100-pin LQFP package dimensions 2

Figure 11. 64-pin LQFP package dimensions 1

Figure 12. 64-pin LQFP package dimensions 2

5 Electrical characteristics

5.1 Terminology and guidelines

5.1.1 Definitions

Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

Electrical characteristics

40 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

5.1.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE

5.1.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 5.0 V Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 41 NXP Semiconductors

5.1.4 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

5.1.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

5.2 Ratings

5.2.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 42 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

5.2.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

5.2.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model − 6000 6000 V 1 VCDM Electrostatic discharge voltage, charged-device model All pins except the corner pins − 500 500 V Corner pins only − 750 750 V ILAT Latch-up current at ambient temperature upper limit − 100 100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

5.2.4 Voltage and current operating ratings

Functional operating conditions appear in the "DC electrical specifications". Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 27. Voltage and current operating ratings Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 43 NXP Semiconductors

Table 27. Voltage and current operating ratings (continued)

1. 60s lifetime - No restrictions, i.e. the part can switch.

10 hours lifetime - Device in reset, i.e. the part cannot switch.

5.3 General

5.3.1 Nonswitching electrical specifications

5.3.1.1 Voltage and current operating requirements

Table 28. Voltage and current operating requirements

1. All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater

R=(VSS – 0.3V–VIN)/|IICIO|. The positive injection current limiting resistor is calculated as R=[VIN–(VDD + 0.3V)]/|IICIO|. The actual resistor values should be an order of magnitude higher to tolerate transient voltages.

1. Open drain outputs must be pulled to VDD.

44 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 29. DC electrical specifications Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 45 NXP Semiconductors

Table 29. DC electrical specifications (continued)

1. Max power supply ramp rate is 500 V/ms.
2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value
3. The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz.
4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value given
5. Refers to the current that leaks into the core when the pad is in Hi-Z (Off state).
6. Maximum pin leakage current at the ambient temperature upper limit.
7. PTD0, PTD1, PTD15, PTD16, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability

selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

1. Refers to the pin leakage on the GPIOs when they are OFF.
2. Measured at VDD supply voltage = VDD min and input V = VSS
3. Measured at VDD supply voltage = VDD min and input V = VDD

46 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

5.3.1.3 Voltage regulator electrical characteristics

100 LQFP

64 LQFP

Figure 13. Pinout decoupling Table 30. Voltage regulator electrical characteristics

1. For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel.
2. The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding VDD/VSS pins.
3. The requirement and value of of CDEC will be decided by the device application requirement.

5.3.1.4 LVR, LVD and POR operating requirements

Table 31. V DD supply LVR, LVD and POR operating requirements Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 47 NXP Semiconductors

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

5.3.1.5 Power mode transition operating behaviors

Table 32. Power mode transition operating behaviors

1. Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V.
2. Max value is mean+6×sigma of tested values at the worst case of ambient temperature range and VDD 2.7 V to 5.5 V.
3. After a POR event, the amount of time from the point VDD reaches the reference voltage 2.7 V to execution of the first

instruction, across the operating temperature range of the chip.

5.3.1.6 Power consumption

the standard deviation (mean + 3 sigma). Table 33. Power consumption operating behaviors Table continues on the next page... 48 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 33. Power consumption operating behaviors (continued) all peripheral clock disabled. all peripheral clock enabled. Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 49 NXP Semiconductors

Flash all peripheral clock disabled. Flash all peripheral clock enabled. Flash all peripheral clock disabled. Flash all peripheral clock enabled. Table continues on the next page... 50 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

1. These values are based on characterization but not covered by test limits in production.
2. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.

optimization level high, optimized for balanced.

5.3.1.6.1 Low power mode peripheral current adder — typical value

compare. 8-bit DAC enabled with half VDDA voltage, low speed mode. Includes 8-bit DAC power consumption. Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 51 NXP Semiconductors

Symbol Description Typical IADC ADC peripheral adder combining the measured values at VDD and VDDA by placing the device in VLPS mode. ADC is configured for low power mode using SIRC clock source, 8-bit resolution and continuous conversions. 484 μA ILPI2C LPI2C peripheral adder measured by placing the device in VLPS mode with selected clock source sending START and Slave address, waiting for RX data. Includes the DMA power consumption. 179 μA ILPIT LPIT peripheral adder measured by placing the device in VLPS mode with internal SIRC 8 MHz enabled in Stop mode. Includes selected clock source power consumption. 18 μA ILPSPI LPSPI peripheral adder measured by placing the device in VLPS mode with selected clock source, output data on SOUT pin with SCK 500 kbit/s. Includes the DMA power consumption. 565 μA

5.3.1.6.2 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• SCG in SOSC for both Run and VLPR modes
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE 000.00E +00 2.00E -03 4.00E -03 6.00E -03 8.00E -03 10.00E -03 12.00E -03 1 2 4 6 12 24 48 72 1-1 1-2 1-3 C urrent C onsumption(A) R un mode C urrent vs C ore F req ALLOF F ALLON Temperature = 25, VDD= 5V C lockG ates C ore F req C ore : F lash

Figure 14. Run mode supply current vs. core frequency 52 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

000.00E +00 100.00E -06 200.00E -06 300.00E -06 400.00E -06 500.00E -06 600.00E -06 700.00E -06 800.00E -06 900.00E -06 1 2 4 1-1 1-2 1-4 C urrent C onsumption (A) VL P R C urrent V s C ore F req ALLOF F ALLON Temperature = 25, VDD= 5V C lockG ates C ore F req C ore : F lash Figure 15. VLPR mode supply current vs. core frequency

5.3.1.7 EMC performance

and guidance specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems

5.3.1.7.1 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 53 NXP Semiconductors

5.3.1.7.2 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. Go to http://www.nxp.com. 2. Perform a keyword search for “EMC design”. 3. Select the "Documents" category and find the application notes.

5.3.1.8 Capacitance attributes

Table 34. Capacitance attributes

5.3.2 Switching specifications

5.3.2.1 Device clock specifications

Table 35. Device clock specifications

1. The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing

specification for any other module. 54 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

5.3.2.2 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% VIL Input Signal VIH Fall Time HighLow Rise Time Midpoint1 The midpoint is VIL + (VIH - VIL) / 2 Figure 16. Input signal measurement reference output pins have the following characteristics.

• C L=30 pF loads
• Normal drive strength

5.3.2.3 General AC specifications

Table 36. General switching specifications

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 55 NXP Semiconductors

5.3.2.4 AC specifications at 3.3 V range Table 37. Functional pad AC specifications

1. Max power supply ramp rate is 500 V/ms.
2. Propagation delay measured from 50% of core side input to 50% of the output.
3. Edges measured using 20% and 80% of the VDD supply.

5.3.2.5 AC specifications at 5 V range

Table 38. Functional pad AC specifications

1. Max power supply ramp rate is 500 V/ms.
2. As measured from 50% of core side input to 50% of the output.
3. Edges measured using 20% and 80% of the VDD supply.

56 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

All measurements were taken accounting for 150 mV drop across VDD and VSS.

5.3.3 Thermal specifications

5.3.3.1 Thermal operating requirements

Table 39. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

determine TJ is: TJ = TA + RΘJA × chip power dissipation.

5.3.3.2 Thermal attributes

5.3.3.2.1 Description

The tables in the following sections describe the thermal characteristics of the device.

5.3.3.2.2 Thermal characteristics for the 64-pin LQFP package

Table 40. Thermal characteristics for the 64-pin LQFP package Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 57 NXP Semiconductors

Table 40. Thermal characteristics for the 64-pin LQFP package (continued)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

1. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s

or 2s2p board, respectively.

1. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
2. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

5.3.3.2.3 Thermal characteristics for the 100-pin LQFP package

Table 41. Thermal characteristics for the 100-pin LQFP package

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

1. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s

or 2s2p board, respectively.

1. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

58 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

1. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

5.3.3.2.4 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from this equation: TJ = TA + (RθJA × PD) where:

• T A = ambient temperature for the package (°C)
• R θJA = junction to ambient thermal resistance (°C/W)
• P D = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where:
• R θJA = junction to ambient thermal resistance (°C/W)
• R θJC = junction to case thermal resistance (°C/W)
• R θCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device.

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 59 NXP Semiconductors

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (ΨJT × PD) where:

• T T = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• P D = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

5.4 Peripheral operating requirements and behaviors

5.4.1 System modules

There are no specifications necessary for the device's system modules.

5.4.2 Clock interface modules

5.4.2.1 Oscillator electrical specifications

5.4.2.1.1 External Oscillator electrical specifications

60 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

(EXTAL32 WAVE) mux ref_clk Differential input comparator (VLP mode) Peak detector LP mode Driver (VLP mode) Pull down resistor (OFF) ESD PAD 300 ohms ESD PAD 300 ohms EXTAL32 pin XTAL32 pin Series resistor for current limitation Crystal or resonatorC1 C2 Figure 17. Oscillator connections scheme (OSC32) Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 61 NXP Semiconductors

(EXTAL WAVE) mux ref_clk Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 300 ohms ESD PAD 40 ohms EXTAL pin XTAL pin Series resistor for current limitation Crystal or resonatorC1 C2 1M ohms Feedback Resistor1 NOTE: 1. 1M Feedback resistor is needed only for HG mode. Figure 18. Oscillator connections scheme (OSC) specifications" tables are from simulation. Table 42. External Oscillator electrical specifications (OSC32) Table continues on the next page... 62 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 42. External Oscillator electrical specifications (OSC32) (continued)

1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator,
2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator

the parasitic capacitance of package and board.

1. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be

connected to any other devices. Table 43. External Oscillator electrical specifications (OSC)

4 MHz — 200 — µA

8 MHz — 300 — µA

32 MHz — 2 — mA

4 MHz — 1 — mA

24 MHz — 5 — mA

40 MHz — 6 — mA

Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 63 NXP Semiconductors

1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator, loading
2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator

the parasitic capacitance of package and board.

1. When low power mode is selected, RF is integrated and must not be attached externally.
2. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

5.4.2.1.2 External Oscillator frequency specifications

Table 44. External Oscillator frequency specifications (OSC32) Table continues on the next page... 64 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 44. External Oscillator frequency specifications (OSC32) (continued)

1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve

Table 45. External Oscillator frequency specifications (OSC)

1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve

5.4.2.2 System Clock Generation (SCG) specifications

5.4.2.2.1 Fast internal RC Oscillator (FIRC) electrical specifications

Table 46. Fast internal RC Oscillator electrical specifications Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 65 NXP Semiconductors

1. The limit is respected across process, voltage and full temperature range.
2. Startup time is defined as the time between clock enablement and clock availability for system use.

5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications

Table 47. Slow internal RC oscillator (SIRC) electrical specifications

1. The limit is respected across process, voltage and full temperature range.
2. Startup time is defined as the time between clock enablement and clock availability for system use.

5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications

Table 48. Low Power Oscillator (LPO) electrical specifications

5.4.2.2.4 LPFLL electrical specifications

66 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 49. LPFLL electrical specifications

1. ΔFcl is dependent on reference clock accuracy. For example, if locked to crystal oscillator, ΔFcl is typically limited by

5.4.3 Memories and memory interfaces

5.4.3.1 Flash memory module (FTFE) electrical specifications

5.4.3.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 50. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

5.4.3.1.2 Flash timing specifications — commands

Table 51. Flash command timing specifications

• 32 KB data flash
• 256 KB program flash 0.3 1.8 ms ms Table continues on the next page...

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 67 NXP Semiconductors

Table 51. Flash command timing specifications (continued)

• 32 KB data flash
• 256 KB program flash 220 240 1850 ms ms tersscr Erase Flash Sector execution time — 15 115 ms 2 tpgmsec512 Program Section execution time (512B flash) — 2.5 — ms trd1all Read 1s All Blocks execution time — — 2.2 ms trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 250 2100 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 250 2100 ms 2 tpgmpart24k tpgmpart32k Program Partition for EEPROM execution time
• 24 KB EEPROM backup
• 32 KB EEPROM backup ms ms tsetramff tsetram24k tsetram32k Set FlexRAM Function execution time:
• Control Code 0xFF
• 24 KB EEPROM backup
• 32 KB EEPROM backup 0.6 0.8 1.1 1.2 μs ms ms teewr8b24k teewr8b32k Byte-write to FlexRAM execution time:
• 24 KB EEPROM backup
• 32 KB EEPROM backup 370 385 1625 1700 μs μs teewr16b24k teewr16b32k 16-bit write to FlexRAM execution time:
• 24 KB EEPROM backup
• 32 KB EEPROM backup 370 385 1625 1700 μs μs teewr32bers 32-bit write to erased FlexRAM location execution time — 360 1500 μs teewr32b24k teewr32b32k 32-bit write to FlexRAM execution time:
• 24 KB EEPROM backup
• 32 KB EEPROM backup 600 630 1950 2000 μs μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.

68 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

5.4.3.1.3 Flash high voltage current behaviors

Table 52. Flash high voltage current behaviors

5.4.3.1.4 Reliability specifications

Table 53. NVM reliability specifications

• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 1,024 140 K 1.26 M 5 M 10 M 400 K 3.2 M 12.8 M 25 M writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C. 3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ 125 °C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 69 NXP Semiconductors

5.4.4 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

5.4.5 Analog

5.4.5.1 ADC electrical specifications

5.4.5.1.1 12-bit ADC operating conditions Table 54. 12-bit ADC operating conditions

1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

1. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
2. Clock and compare cycle need to be set according the guidelines in the block guide.

70 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

1. ADC conversion will become less reliable above maximum frequency. 6. When using ADC hardware averaging, refer to the device Reference Manual to determine the most appropriate setting for AVGS. 7. Max ADC conversion rate of 1200 Ksps is with 10-bit mode

Figure 19. ADC input impedance equivalency diagram clock as the clocking source for ADC. Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 71 NXP Semiconductors

Table 55. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 48 MHz unless otherwise stated.
3. These values are based on characterization but not covered by test limits in production.
4. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

MHz ADC conversion clock speed.

1. 1 LSB = (VREFH - VREFL)/2N
2. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
3. Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz.
4. ADC conversion clock < 3 MHz
5. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed

application information of the temperature sensor. 72 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

5.4.5.2 CMP with 8-bit DAC electrical specifications

Table 56. Comparator with 8-bit DAC electrical specifications Table continues on the next page... Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 73 NXP Semiconductors

Table 56. Comparator with 8-bit DAC electrical specifications (continued)

1. Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated.
2. Difference at input > 200mV
3. Applied ± (100 mV + Hyst) around switch point
4. Applied ± (30 mV + 2 × Hyst) around switch point

Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) 74 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Figure 23. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 1)

5.4.6 Communication interfaces

5.4.6.1 LPUART electrical specifications

Refer to General AC specifications for LPUART specifications.

5.4.6.2 LPSPI electrical specifications

with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins. Table 57. LPSPI master mode timing Table continues on the next page... 76 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 57. LPSPI master mode timing (continued)

1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.

High drive pin should be used for fast bit rate.

1. If configured as an output.

Figure 24. LPSPI master mode timing (CPHA = 0) Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 77 NXP Semiconductors

<<CLASSIFICATION>> <<NDA MESSAGE>> 6 7 MSB IN 2 BIT 6 . . . 1 MASTER MSB OUT 2 MASTER LSB OUT 10 11 PORT DATA PORT DATA 3 10 11 4 1.If configured as output (OUTPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS 1 (OUTPUT) (OUTPUT) MOSI (OUTPUT) MISO (INPUT) LSB INBIT 6 . . . 1 Figure 25. LPSPI master mode timing (CPHA = 1) Table 58. LPSPI slave mode timing

1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
2. Time to data active from high-impedance state
3. Hold time to high-impedance state

78 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

BIT 6 . . . 1 SLAVE MSB SLAVE LSB OUT 553 SEE NOTE see note (INPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS (INPUT) (INPUT) MOSI (INPUT) MISO (OUTPUT) LSB INBIT 6 . . . 1 Figure 26. LPSPI slave mode timing (CPHA = 0) Figure 27. LPSPI slave mode timing (CPHA = 1)

5.4.6.3 LPI2C

Table 59. LPI 2C specifications Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 79 NXP Semiconductors

1. Hs-mode is only supported in slave mode. 2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more information on the required pull-up devices, see I2C Bus Specification. 3. See the section "General switching specifications".

5.4.7 Human-machine interfaces (HMI)

5.4.7.1 Touch sensing input (TSI) electrical specifications

Table 60. TSI electrical specifications

5.4.8 Debug modules

5.4.8.1 SWD electricals

Table 61. SWD full voltage range electricals Table continues on the next page... 80 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 61. SWD full voltage range electricals (continued) Figure 28. Serial wire clock input timing Figure 29. Serial wire data timing

6 Design considerations

6.1 Hardware design considerations

This device contains protective circuitry to guard against damage due to high static voltage or electric fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit.

6.1.1 Printed circuit board recommendations

• Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground. Consider to add ferrite bead or inductor to some sensitive lines.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages.

6.1.2 Power delivery system

Consider the following items in the power delivery system:

• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential segments.
• Always route the power net as star topology, and make each power trace loop as minimum as possible.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins. Design considerations 82 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

6.1.3 Analog design

small compared to the sample period. Figure 30. RC circuit for ADC input here to protect against transient over-voltages. Figure 31. High voltage measurement with an ADC input

6.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).

• NMI pin Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level on this pin will trigger non-maskable interrupt. When this pin is enabled as the NMI function, an external pull-up resistor (10 kΩ) as shown in the following figure is recommended for robustness. If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is required to disable the NMI function by remapping to another function. The NMI function is disabled by programming the FOPT[NMI_DIS] bit to zero. D D C C B B A A EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR MCU ADCx MCU ADCx MCU RESET_b MCU NMI_b MCU RESET_b Supervisor Chip OUT Active high, open drain RESET_b SWD_DIO SWD_CLK Analog input High voltage input RESET_b VDD VDD VDD VDD VDD VDD Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 R 1 2 0.1uF 1 2 Cx 0.1uF RESONATOR 1 3 Cy Cx CRYSTAL HDR_5X2 1 2 3 4 7 8 9 10 Cy 10k 10k CRYSTAL 0.1uF 10k CRYSTAL 1 2 1 2 C RESONATOR 1 3 1 2 10k 10k RF 1 2 RS BAT54SW 1 2 RS RS C RF 1 2 RS 1 2 RF 1 2 CRYSTAL

Figure 34. NMI pin biasing

• Debug interface This MCU uses the standard ARM SWD interface protocol as shown in the following figure. While pull-up or pull-down resistors are not required (SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ pull resistors are recommended for system robustness. The RESET_b pin recommendations mentioned above must also be considered. Design considerations Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 85 NXP Semiconductors

Figure 35. SWD debug interface

• Unused pin Unused GPIO pins must be left floating (no electrical connections) with the MUX field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital input path to the MCU.

6.1.5 Crystal oscillator

MCU clock system, refer to the following table and diagrams. external feedback is required when using high gain (HGO=1) mode. frequency above 2 MHz does not require any series resistance. Figure 36. RTC Oscillator (OSC32) module connection – Diagram 1

Table 62. External crystal/resonator connections Figure 37. Crystal connection – Diagram 2 Figure 38. Crystal connection – Diagram 3 ring to the crystal oscillator circuit.

6.2 Software considerations

kinetis/sw for more information and supporting collateral.

• Freedom Development Platform: http://www.nxp.com/freedom Design considerations Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 87 NXP Semiconductors

• Kinetis Design Studio IDE: http://www.nxp.com/kds
• Partner IDEs: http://www.nxp.com/kide Run-time Software
• Kinetis SDK: http://www.nxp.com/ksdk
• Kinetis Bootloader: http://www.nxp.com/kboot
• ARM mbed Development Platform: http://www.nxp.com/mbed For all other partner-developed software and tools, visit http://www.nxp.com/partners.

7 Part identification

7.1 Description

values of these fields to determine the specific part you have received.

7.2 Format

7.3 Fields

Table 63. Part number fields description

• P = Prequalification KE## Kinetis family • KE15, KE14 A Key attribute • Z = Cortex-M0+ Table continues on the next page... Part identification 88 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Table 63. Part number fields description (continued)

• 256 = 256 KB R Silicon revision • (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105
• LL = 100 LQFP (14 mm x 14 mm) CC Maximum CPU frequency (MHz) • 7 = 72 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

7.4 Example

8 Revision history

The following table provides a revision history for this document. Table 64. Revision history 09/2016 Initial public release.

• Minor correction: V DDE symbol should be VDD, in the "DC electrical specifications" table.
• Minor update in the "Clocking block diagram" figure.
• Minor update in the "Analog design" section. 2.2 (internal version) 06/2017 • Updated the "Voltage and current operating ratings" section.
• Minor update in the "Pinout decoupling" figure.
• Fixed the "Description" collumn of STOP and VLPS mode rows, in the "Power consumption operating behaviors" table. 2.3 (internal version) 08/2017 • Minor update in the "Clock interfaces" section of the feature list, on the front matter cover pages. Table continues on the next page...

Revision history

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 89 NXP Semiconductors

Table 64. Revision history (continued)

• Some updates in the "External Oscillator electrical specifications (OSC32)" and "External Oscillator electrical specifications (OSC)" tables.
• Some updates in the "External Oscillator frequency specifications (OSC32)" and "External Oscillator frequency specifications (OSC)" tables. (public release) 07/2018 • Updated the figure "Memory map".
• Minor updates in the figures "Oscillator connections scheme (OSC32)" and "Oscillator connections scheme (OSC)".
• Some updates of V IH and VIL in the "External Oscillator electrical specifications (OSC32)" and "External Oscillator electrical specifications (OSC)" tables, and minor editorial fix.
• Updated the table "Fast internal RC Oscillator electrical specifications": FIRC is trimmed to 48 MHz only, in this device.
• Updated the figure "ADC input impedance equivalency diagram".
• Corrected the unit as uA, in the I DDA_ADC row of the table "12-bit ADC characteristics".
• Footnote updated in the tables "LPSPI master mode timing" and "LPSPI slave mode timing".
• Corrected the minimum and the maximum values of V LVRX in the "VDD supply LVR, LVD and POR operating requirements" table.
• Updated the "Voltage and current operating requirements" table. (public release) 06/2019 • Corrected the "Clock interfaces" section in the cover page: FIRC is trimmed to 48 MHz only in this device. Up to 50 MHz DC external square wave input clock.
• Minor fix in Figure 4.
• Note added after Table 5.
• Statement restored in the section RTC : The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an external crystal using the oscillator, or clock directly from RTC_CLKIN pin.
• Minor fix in Table 23.
• Some major updates in Table 54.
• Some minor updates in tables "LPSPI master mode timing" and "LPSPI slave mode timing", including the footnotes, in the section LPSPI electrical specifications. 4.1 (internal version) 07/2020 • Minor correction in the FTM channel numbers of the "Module Signal Description Tables" section.
• Minor correction in the "Functional block diagram" figure after the cover page: GPIO and TSI blocks.
• Minor correction in the "Ordering information" table: ADC channels collumn. 4.2 (public release) 03/2021 • Added errata for Mask 2N36S, in the "Related Resources" table of cover page.

90 Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021 NXP Semiconductors

Home Page: nxp.com Web Support: nxp.com/support Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,EMBRACE, GREENCHIP, HITAG, ICODE, JCOP, LIFE, VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET, TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, CodeWarrior, ColdFire, ColdFire+, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV, mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, SafeAssure, the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet, Flexis, MXC, Platform in a Package, QUICC Engine, Tower, TurboLink, EdgeScale, EdgeLock, eIQ, and Immersive3D are trademarks of NXP B.V. All other product or service names are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Table continues on the next page...

Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. M, M Mobileye and other Mobileye trademarks or logos appearing herein are trademarks of Mobileye Vision Technologies Ltd. in the United States, the EU and/or other jurisdictions. © NXP B.V. 2015-2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 03/ 2021 Document identifier: KE1xZP100M72SF0