KE1XZP100M96SF0 NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 86
Technical content
Datasheet sections
- 1 Kinetis KE17Z/13Z/12Z introduction
- 1.1 Ordering information
- 1.2 Part identification
- 1.2.1 Description
- 1.2.2 Format
- 1.2.3 Fields
- 1.2.4 Example
- 2 Overview
- 2.1 System features
- 2.1.1 ARM Cortex-M0+ core
- 2.1.2 NVIC
- 2.1.3 AWIC
- 2.1.4 Memory
- 2.1.5 Reset and boot
- 2.1.6 Clock options
- 2.1.7 Security
- 2.1.8 Power management
- 2.1.9 Debug controller
- 2.2 Peripheral features
- 2.2.2 FTM
- 2.2.3 ADC
- 2.2.4 CMP
- 2.2.5 LPIT
- 2.2.6 LPTMR
- 2.2.7 CRC
- 2.2.8 LPUART
- 2.2.9 SCI
- 2.2.10 LPSPI
- 2.2.11 LPI2C
- 2.2.12 FlexIO
- 2.2.13 Port control and GPIO
- 2.2.14 TSI
- 3 Memory map
- 4 Pinouts
- 4.1 KE1xZ Signal Multiplexing and Pin
- 4.2 Port control and interrupt summary
- 4.3 Module Signal Description Tables
- 4.3.1 SWD signal module
- 4.3.2 System modules
- 4.3.3 Clock modules
- 4.3.4 Analog modules
- 4.3.5 Timer modules
- 4.3.6 Communication interfaces
- 4.3.7 Human-Machine interfaces
- 4.4 Pinout diagram
- 4.5 Package dimensions
- 5 Electrical characteristics
- 5.1 Terminology and guidelines
- 5.1.1 Definitions
- 5.1.2 Examples
- 5.1.3 Typical-value conditions
- 5.1.4 Relationship between ratings and operating
- 5.1.5 Guidelines for ratings and operating
- 5.2 Ratings
- 5.2.1 Thermal handling ratings
- 5.2.2 Moisture handling ratings
- 5.2.3 ESD handling ratings
- 5.2.4 Voltage and current operating ratings
- 5.3 General
- 5.3.1 Non-switching electrical specifications
- 5.3.2 Switching specifications
- 5.3.3 Thermal specifications
- 5.4 Peripheral operating requirements and
- 5.4.1 System modules
- 5.4.2 Clock interface modules
- 5.4.3 Memories and memory interfaces
- 5.4.4 Security and integrity modules
- 5.4.5 Analog
- 5.4.6 Communication interfaces
- 5.4.7 Human-machine interfaces (HMI)
- 5.4.8 Debug modules
- 6 Design considerations
- 6.1 Hardware design considerations
- 6.1.1 Printed circuit board recommendations
- 6.1.2 Power delivery system
- 6.1.3 Analog design
- 6.1.4 Digital design
- 6.1.5 Crystal oscillator
- 7 Revision history
- This document provides electrical specifications for Kinetis KE17Z/13Z/12Z with up to 512 KB Flash Data Sheet
- For functional characteristics and the programming model, see Kinetis KE17Z/13Z/12Z with up to 512 KB Flash Reference Manual. KE1xZP100M96SF0 Kinetis KE17Z/13Z/12Z with up to 512 KB Flash Rev. 2 — 04/2024 Data Sheet: Technical Data NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. General Business Information
1 Kinetis KE17Z/13Z/12Z introduction
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash Up to 96 MHz ARM Cortex -M0+ Based Microcontroller KE1xZ512 MCUs are the leading parts for the KE1xZ family based on ARM® Cortex®-M0+ core. Providing up to 512 KB flash, up to 96 KB RAM, and the enhanced dual Touch Sensing Interface (TSI) module extends Kinetis E family to 50 touch channels. Enhanced robust TSI provides high level stability and accuracy to help customer develop HMI system easily and quickly. 1 Msps ADC and FlexTimer help build a perfect solution for BLDC motor control systems. Core Processor and System
- ARM® Cortex®-M0+ core, supports up to 96 MHz frequency
- ARM Core based on the ARMv6 Architecture and Thumb -2 ISA
- Configurable Nested Vectored Interrupt Controller (NVIC)
- 8-channel DMA controller extended up to 63 channels with DMAMUX Reliability, safety, and security
- Cyclic Redundancy Check (CRC) generator module
- 128-bit unique identification (ID) number
- Internal watchdog (WDOG) with independent clock source
- External watchdog monitor (EWM) module
- ADC self-calibration feature
- On-chip clock loss monitoring Human-machine interface (HMI)
- Supports up to 32 interrupt request (IRQ) sources
- Up to 89 GPIO pins with interrupt functionality
- 2x Touch sensing input (TSI) modules, each TSI has up to 25 channels Memory and memory interfaces
- Up to 512 KB program flash, dual-bank flash supporting flash SWAP feature
- Up to 96 KB SRAM
- 256 Bytes flash cache Mixed-signal analog
- 1× 12-bit analog-to-digital converter (ADC) with up to 24 channel analog inputs per module, up to 1 Msps
- 1× high-speed analog comparator (CMP) with internal 8-bit digital to analog converter (DAC) Timing and control
- 3× Flex Timers (FTM) for PWM generation, offering up to 16 standard channels
- 1× 16-bit Low-Power Timer (LPTMR) with flexible wake up control
- 1× 32-bit Low-power Periodic Interrupt Timer (LPIT) with 4 channels
- 1x Real Time Clock (RTC) Clock interfaces
- OSC: high range 4 - 40 MHz (with high-gain mode) and low range 32 - 40 kHz (with low-gain mode)
- 48 - 60 MHz high-accuracy (up to ±1%) fast internal reference clock (FIRC) for normal Run NXP Semiconductors Kinetis KE17Z/13Z/12Z introduction Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 3 / 86
- 8 MHz / 2 MHz high-accuracy (up to ±3%) slow internal reference clock (SIRC) for low-speed Run
- 128 kHz low power oscillator (LPO)
- Low-power FLL (LPFLL)
- Up to 60 MHz DC external square wave input clock
- System clock generator (SCG) Power management
- Low-power ARM Cortex-M0+ core with excellent energy efficiency
- Power management controller (PMC) with multiple power modes: HSRUN, Run, Wait, Stop, VLPR, VLPW, and VLPS
- Supports clock gating for unused modules, and specific peripherals remain working in low power modes
- POR, LVD, and LVR Connectivity and communications interfaces
- 3× low-power universal asynchronous receiver / transmitter (LPUART) modules with DMA support and low power availability
- 2x Serial Communications Interface (SCI) modules with DMA support and LIN slave operation
- 2× low-power serial peripheral interface (LPSPI) modules with DMA support and low power availability
- 2× low-power inter-integrated circuit (LPI2C) modules with DMA support and low power availability
- FlexIO module for flexible and high performance serial interfaces Debug functionality
- Serial Wire Debug (SWD) debug interface
- Debug Watchpoint and Trace (DWT)
- Micro Trace Buffer (MTB) Operating Characteristics
- Voltage range: 2.7 to 5.5 V
- Ambient temperature range: –40 to 105 °C
Table 1. Related Resources structure and function (operation) of a device.
- To find the associated resource, go to http://www.nxp.com and perform a search using this term.
4 M-40 MHz OSC
1 MSPS , 24ch
Figure 1. Functional block diagram
1.1 Ordering information
The following chips are available for ordering. Table 2. Ordering information Table continues on the next page...
Table 2. Ordering information (continued)
- INT: interrupt pin numbers; HD: high drive pin numbers
1.2 Part identification
1.2.1 Description
1.2.2 Format
1.2.3 Fields
Table 3. Part number fields description
- P = Prequalification KE## Kinetis family • KE17, KE13, KE12 A Key attribute • Z = Cortex-M0+ FFF Program flash memory size • 128 = 128 KB
- 256 = 256 KB
- 512 = 512 KB R Silicon revision • (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- LL = 100 LQFP (14 mm x 14 mm) Table continues on the next page... NXP Semiconductors Kinetis KE17Z/13Z/12Z introduction Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 6 / 86
Table 3. Part number fields description (continued)
- (Blank) = Trays
1.2.4 Example
2 Overview
The following figure shows the system diagram of this device. Figure 2. System diagram
2.1 System features
The following sections describe the high-level system features.
2.1.1 ARM Cortex-M0+ core
very cost sensitive, low power applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. instructions. It is upward compatible with other Cortex-M profile processors.
2.1.2 NVIC
in the IPR registers contains 2 bits. It also differs in number of interrupt sources and supports 32 interrupt vectors. be used to wake the MCU core from Wait and VLPW modes.
2.1.3 AWIC
normal interrupt or event processing. The AWIC can be used to wake MCU core from Partial Stop, Stop and VLPS modes. Table 4. AWIC Stop and VLPS Wake-up Sources
2.1.4 Memory
- Up to 512 KB of embedded program flash memory, dual-bank flash supporting flash SWAP feature.
- Up to 96 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait states.
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device. Table 5. Reset source
- Except SMC_PMPROT, SMC_PMCTRL_RUNM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT
- Except RCM_RPC, RCM_SRIE, RCM_SRS, RCM_SSRS
- Except SCG_CSR and SCG_FIRCSTAT
2.1.6 Clock options
memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. see the Clocking chapter in the Reference Manual.
48 MHz
Figure 3. Clocking block diagram
2.1.7 Security
access the memory resources of the MCU. Table 6. Security state erase (Erase All Blocks) command.
2.1.8 Power management
versus performance requirements of the application can be selected. the modes is the maximum clock frequency of the system and therefore the power consumption. portions of the analog, logic, and memory can be retained or disabled to conserve power. to wake up the MCU core from STOP and VLPS modes. For additional information regarding operational modes, power management, the NVIC, AWIC, please see the Reference Manual. can wake MCU from low power modes. Table 7. Peripherals states in different operational modes Run In Run mode, all device modules are operational. the Low Voltage Detect (LVD) monitor, which is disabled. Deep sleep Stop In Stop mode, most peripheral clocks are disabled and placed in a static state. ADC, OSC, LPTMR, LPIT, FlexIO, LPUART, LPI2C, LPSPI, and RTC.
2.1.9 Debug controller
This device has extensive debug capabilities including run control and tracing capabilities. The standard ARM debug port supports SWD interface.
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip. 2.2.1 eDMA and DMAMUX The eDMA is a highly programmable data-transfer engine optimized to minimize any required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the transferred data itself. The DMA controller in this device implements 8 channels which can be routed from up to 63 DMA request sources through DMAMUX module. Main features of eDMA are listed below:
- All data movement via dual-address transfers: read from source, write to destination
- 8-channel implementation that performs complex data transfers with minimal intervention from a host processor
- Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations — Channel activation via one of three methods — Fixed-priority and round-robin channel arbitration — Channel completion reported via programmable interrupt requests — Programmable support for scatter/gather DMA processing — Support for complex data structures
2.2.2 FTM
This device contains three FlexTimer modules. The FlexTimer module (FTM) is a two-to-eight channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. Several key enhancements of this module are made:
- Signed up counter
- Deadtime insertion hardware
- Fault control inputs
- Enhanced triggering functionality
- Initialization and polarity control
2.2.3 ADC
This device contains one 12-bit SAR ADC module. The ADC module supports hardware triggers from FTM, LPTMR, LPIT, external trigger pin, RTC, and CMP output. It supports wakeup of MCU in low power mode when using internal clock source or external crystal clock. ADC module has the following features:
- Linear successive approximation algorithm with up to 12-bit resolution
- Up to single-ended external analog inputs NXP Semiconductors Overview Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 12 / 86
- Support 12-bit, 10-bit, and 8-bit single-ended output modes
- Single or continuous conversion
- Configurable sample time and conversion speed/power
- Input clock selectable from up to four sources
- Operation in low-power modes for lower noise
- Selectable hardware conversion trigger
- Automatic compare with interrupt for less-than, greater-than or equal-to, within range, or out-of-range, programmable value
- Temperature sensor
- Hardware average function
- Selectable Voltage reference: from external or alternate
- Self-Calibration mode
2.2.3.1 Temperature sensor
This device contains one temperature sensor internally connected to the input channel of AD26, see ADC electrical specifications for details of the linearity factor. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed application information of the temperature sensor.
2.2.4 CMP
There is one analog comparator on this device.
- Each CMP has its own independent 8-bit DAC.
- Each CMP supports up to 6 analog inputs from external pins.
- Each CMP is able to convert an internal reference from the bandgap.
- Each CMP supports the round-robin sampling scheme. In summary, this allow the CMP to operate independently in VLPS and Stop modes, whilst being triggered periodically to sample up to 6 inputs. Only if an input changes state is a full wakeup generated. The CMP has the following features:
- Inputs may range from rail to rail
- Programmable hysteresis control
- Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges of the comparator output
- Selectable inversion on comparator output
- Capability to produce a wide range of outputs such as sampled, windowed, or digitally filtered
- External hysteresis can be used at the same time that the output filter is used for internal functions
- Two software selectable performance levels: Shorter propagation delay at the expense of higher power, and Low power with longer propagation delay
- DMA transfer support
- Functional in all power modes available on this MCU
- The window and filter functions are not available in STOP mode
- Integrated 8-bit DAC with selectable supply reference source and can be power down to conserve power NXP Semiconductors Overview Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 13 / 86
2.2.5 LPIT
The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module generating independent pre-trigger and trigger outputs. These timer channels can operate individually or can be chained together. The LPIT can operate in low power modes if configured to do so. The pre-trigger and trigger outputs can be used to trigger other modules on the device.
2.2.6 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes. It can also continue operating through most system reset events, allowing it to be used as a time of day counter. The LPTMR module has the following features:
- 16-bit time counter or pulse counter with compare — Optional interrupt can generate asynchronous wakeup from any low-power mode — Hardware trigger output — Counter supports free-running mode or reset on compare
- Configurable clock source for prescaler/glitch filter
- Configurable input source for pulse counter
2.2.7 CRC
This device contains one cyclic redundancy check (CRC) module which can generate 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The CRC module has the following features:
- Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift register
- Programmable initial seed value and polynomial
- Option to transpose input data or output data (the CRC result) bitwise or bytewise.
- Option for inversion of final CRC result
- 32-bit CPU register programming interface
2.2.8 LPUART
This product contains three Low-Power UART modules, and can work in Stop and VLPS modes. The module also supports 4× to 32× data oversampling rate to meet different applications. The LPUART module has the following features:
- Programmable baud rates (13-bit modulo divider) with configurable oversampling ratio from 4× to 32×
- Transmit and receive baud rate can operate asynchronous to the bus clock and can be configured independently of the bus clock frequency, support operation in Stop mode
- Interrupt, DMA or polled operation
- Hardware parity generation and checking
- Programmable 8-bit, 9-bit or 10-bit character length
- Programmable 1-bit or 2-bit stop bits
- Three receiver wakeup methods — Idle line wakeup NXP Semiconductors Overview Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 14 / 86
— Address mark wakeup — Receive data match
- Automatic address matching to reduce ISR overhead: — Address mark matching — Idle line address matching — Address match start, address match end
- Optional 13-bit break character generation / 11-bit break character detection
- Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle characters
- Selectable transmitter output and receiver input polarity
2.2.9 SCI
This device contains two SCI modules to provide more UART ports with minimum die size increase. The SCI modules have the following features:
- Support standard UART features
- Two SCI modules support both LIN operation
- Support DMA
2.2.10 LPSPI
This device contains one LPSPI module. The LPSPI is a low power Serial Peripheral Interface (SPI) module that supports an efficient interface to an SPI bus as a master and/or a slave. The LPSPI can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPSPI module has the following features:
- Command/transmit FIFO of 4 words
- Receive FIFO of 4 words
- Host request input can be used to control the start time of an SPI bus transfer
2.2.11 LPI2C
This device contains one LPI2C module. The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master and/or a slave. The LPI2C can continue operating in stop modes provided an appropriate clock is available and is designed for low CPU overhead with DMA offloading of FIFO register accesses. The LPI2C implements logic support for standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The LPI2C module also complies with the System Management Bus (SMBus) Specification, version 2. The LPI2C modules have the following features:
- Standard, Fast, Fast+ and Ultra Fast modes are supported
- HS-mode supported in slave mode
- Multi-master support including synchronization and arbitration
- Clock stretching
- General call, 7-bit and 10-bit addressing
- Software reset, START byte and Device ID require software support
- For master mode: — command/transmit FIFO of 4 words NXP Semiconductors Overview Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 15 / 86
— receive FIFO of 4 words
- For slave mode: — separate I2C slave registers to minimize software overhead due to master/ slave switching — support for 7-bit or 10-bit addressing, address range, SMBus alert and general call address — transmit/receive data register supporting interrupt or DMA requests
2.2.12 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform generation. The module supports programmable baud rates independent of bus clock frequency, with automatic start/stop bit generation. The FlexIO module has the following features:
- Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using remains enabled
- Four 32-bit double buffered shift registers with transmit, receive, and data match modes, and continuous data transfer
- The timing of the shifter's shift, load and store events are controlled by the highly flexible 16-bit timer assigned to the shifter
- Two or more shifters can be concatenated to support large data transfer sizes
- Each 16-bit timers operates independently, supports for reset, enable and disable on a variety of internal or external trigger conditions with programmable trigger polarity
- Flexible pin configuration supporting output disabled, open drain, bidirectional output data and output mode
- Supports interrupt, DMA or polled transmit/receive operation
2.2.13 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. The GPIO data direction and output data registers control the direction and output data of each pin when the pin is configured for the GPIO function. The GPIO input data register displays the logic value on each pin when the pin is configured for any digital function, provided the corresponding Port Control and Interrupt module for that pin is enabled. The following figure shows the basic I/O pad structure. Pseudo open-drain pins have the p-channel output driver disabled when configured for open-drain operation. None of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above VDD. NXP Semiconductors Overview Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 16 / 86
Figure 4. I/O simplified block diagram
- All PIN support interrupt enable
- Configurable edge (rising, falling, or both) or level sensitive interrupt type
- Support DMA request
- Asynchronous wake-up in low-power modes
- Configurable pullup, pulldown, and pull-disable on select pins
- Configurable high and low drive strength on selected pins
- Configurable passive filter on selected pins
- Individual mux control field supporting analog or pin disabled, GPIO, and up to chip-specific digital functions
- Pad configuration fields are functional in all digital pin muxing modes. The GPIO module has the following features:
- Port Data Input register visible in all digital pin-multiplexing modes
- Port Data Output register with corresponding set/clear/toggle registers
- Port Data Direction register
- GPIO support single-cycle access via fast GPIO. NXP Semiconductors Overview Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 17 / 86
2.2.14 TSI
- Advanced EMC robustness
- Supports both self-cap sensor and mutual-cap sensor
- One pin per electrode – no external components
- Adjustable touch sensing resolution and sensitivity for sensing a variety of overlay materials and thicknesses
- Low power consumption
- Capability to wake up MCU from low power modes for low power application
- Supports DMA data transfer
- Fully supports NXP touch library, see NXP touch library for details.
- Each TSI channel configurable to function as the scan channel or shield channel
3 Memory map
4 Pinouts
4.1 KE1xZ Signal Multiplexing and Pin Assignments
document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. Table 8. Pin assignments Table continues on the next page...
Table 8. Pin assignments (continued) Table continues on the next page...
Table continues on the next page...
Table continues on the next page...
Table continues on the next page...
Table continues on the next page...
Each TSI channel can be configured as TSI shield channel.
4.2 Port control and interrupt summary
The following table provides more information regarding the Port Control and Interrupt configurations. Table 9. Ports summary Table continues on the next page...
Table 9. Ports summary (continued)
4.3 Module Signal Description Tables
describe the signal function and direction.
4.3.1 SWD signal module
Table 10. SWD signal descriptions
4.3.2 System modules
Table 11. System signal description Table 12. EWM signal descriptions default polarity is active-low.
4.3.3 Clock modules
Table 13. OSC (in SCG) signal descriptions
4.3.4 Analog modules
Table 14. ADC0 signal descriptions
Table 15. CMP0 signal descriptions
4.3.5 Timer modules
Table 16. LPTMR0 signal descriptions Table 17. FTM0 signal descriptions Table 18. FTM1 signal descriptions Table 19. FTM2 signal descriptions
4.3.6 Communication interfaces
Table 20. LPSPIn signal descriptions Table 21. SCIn signal descriptions Table 22. LPI2Cn signal descriptions Table 23. LPUARTn signal descriptions Table 24. FlexIO signal descriptions
4.3.7 Human-Machine interfaces
Table 25. GPIO signal descriptions Table 26. TSIn signal descriptions
4.4 Pinout diagram
a single pin. To determine what signals can be used on which pin, see the previous table of Pin Assignments.
98 PTA4
97 PTA5
96 PTC4
95 PTC5
94 PTE0
93 PTE1
92 PTA10
91 PTA11
90 PTA12
89 PTA13
88 PTA14
80 PTC7
83 PTA15
84 PTE6
85 PTE2
86 VSS
87 VDD
100 PTA8
Figure 5. 100 LQFP pinout diagram
Figure 6. 64 LQFP pinout diagram
4.5 Package dimensions
The following figures show the dimensions of the package options for the devices supported by this document.
Figure 7. 100-pin LQFP package dimensions 1
Figure 8. 100-pin LQFP package dimensions 2
Figure 9. 64-pin LQFP package dimensions 1
Figure 10. 64-pin LQFP package dimensions 2
5 Electrical characteristics
5.1 Terminology and guidelines
Electrical characteristics
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 35 / 86
5.1.1 Definitions
Key terms are defined in the following table: Table 27. Definition
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered. The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. NOTE Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Is representative of that characteristic during operation when you meet the Typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. NOTE NXP Semiconductors
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 36 / 86
5.1.2 Examples
Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE Figure 11. Examples
5.1.3 Typical-value conditions
Table 28. Typical-value conditions Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 37 / 86
5.1.4 Relationship between ratings and operating requirements
Expected permanent failure Degraded operating range - No permanent failure - Possible decreased life - Possible incorrect operation Normaloperatingrange -Nopermanentfailure - Correct operation Degraded operating range - No permanent failure - Possible decreased life - Possible incorrect operation Fatal range Expected permanent failure – ∞ ∞ Operating (power on) Fatal range Expected permanent failure Handling range No permanent failure Fatal range Expected permanent failure – ∞ ∞ Handling (power off) Normal operating range - No permanent failure
5.1.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
5.2 Ratings
5.2.1 Thermal handling ratings
Table 29. Thermal handling ratings
- Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices. Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 38 / 86
5.2.2 Moisture handling ratings
Table 30. Moisture handling ratings
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.2.3 ESD handling ratings
Table 31. ESD handling ratings
- Determined according to JEDEC Standard JS001, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
- Determined according to JEDEC Standard JS002, Field-Induced Charged-Device Model Test Method for Electrostatic-
Discharge-Withstand Thresholds of Microelectronic Components.
- Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.2.4 Voltage and current operating ratings
values may affect device reliability or cause permanent damage to the device. Table 32. Voltage and current operating ratings
- 60s lifetime - No restrictions, i.e. the part can switch.
10 hours lifetime - Device in reset, i.e. the part cannot switch. Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 39 / 86
5.3 General
5.3.1 Non-switching electrical specifications
5.3.1.1 Voltage and current operating requirements
Table 33. Voltage and current operating requirements
- All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater
actual resistor values should be an order of magnitude higher to tolerate transient voltages.
- Open drain outputs must be pulled to VDD.
Table 34. DC electrical specifications Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 40 / 86
Table 34. DC electrical specifications (continued) Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 41 / 86
- Max power supply ramp rate is 500 V/ms.
- The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value given
- The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz.
- The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value given
- Refers to the current that leaks into the core when the pad is in Hi-Z (Off state).
- Maximum pin leakage current at the ambient temperature upper limit.
- PTD0, PTD1, PTD15, PTD16, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability selected
by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
- Refers to the pin leakage on the GPIOs when they are OFF.
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 42 / 86
- Measured at VDD supply voltage = VDD min and input V = VSS 10. Measured at VDD supply voltage = VDD min and input V = VDD
5.3.1.3 Voltage regulator electrical characteristics
Figure 12. Pinout decoupling
100 LQFP
64 LQFP
Table 35. Voltage regulator electrical characteristics
- For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel.
- The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding VDD/VSS pins.
- The requirement and value of CDEC will be decided by the device application requirement.
5.3.1.4 LVR, LVD and POR operating requirements
Table 36. VDD supply LVR, LVD and POR operating requirements Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 43 / 86
Table 36. VDD supply LVR, LVD and POR operating requirements (continued)
- Rising threshold is the sum of falling threshold and hysteresis voltage.
5.3.1.5 Power mode transition operating behaviors
Table 37. Power mode transition operating behaviors
- Typical value is the average of values tested at Temperature = 25 ℃ and VDD = 3.3 V.
- Max value is mean + 6 × sigma of tested values at the worst case of ambient temperature range and VDD 2.7 V to 5.5 V.
- After a POR event, the amount of time from the point VDD reaches the reference voltage 2.7 V to execution of the first
instruction, across the operating temperature range of the chip.
5.3.1.6 Power consumption
Table 38 shows the power consumption targets for the device in various modes of operations. Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 44 / 86
The maximum values stated in the table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). NOTE Specifications below only inculde power rails of the MCU (VDD, VDDA, and VREFH). Table 38. Power consumption operating behaviors
24 MHz, flash at 24 MHz, VDD = 5 V
Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 45 / 86
Table 38. Power consumption operating behaviors (continued)
24 MHz, VDD = 5 V
all peripheral clock disabled. all peripheral clock enabled. Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 46 / 86
Flash all peripheral clock disabled. Flash all peripheral clock enabled. Flash all peripheral clock disabled. Flash all peripheral clock enabled.
1 MHz, all peripheral clocks disabled, VDD
Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 47 / 86
- These values are based on characterization of typical samples, but not covered by test limits in production.
- PMC_REGSC[BIASEN] is the control bit to enable or disable bias under low power mode.
- PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable clock bias under STOP / VLPS mode.
CoreMark benchmark compiled using IAR 9.40 with optimization level high, optimized for balanced.
5.3.1.6.1 Low power mode peripheral current adder — typical value
Table 39. Low power mode peripheral current adder — typical value with LPTMR enabled using LPO. Includes LPO power consumption. CMP enabled using the 8-bit DAC and a single external input for compare. selected clock source power consumption (SIRC 8 MHz). Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 48 / 86
Table 39. Low power mode peripheral current adder — typical value (continued) using SIRC clock source, 8-bit resolution and continuous conversions. data. Includes the DMA power consumption. with selected clock source, output data on SOUT pin with SCK 500 kbit/s. Includes the DMA power consumption. self-cap mode scans continuously with a 1 ms time period. mutual-cap mode scans continuously with a 1 ms time period. clock waiting for RX data at 115200 baud rate. counter enabled. It includes LPO power consumption.
5.3.1.6.2 Diagram: Typical IDD_HSRUN, IDD_RUN, IDD_VLPR operating behavior
- SCG in SOSC for HSRun, Run, and VLPR modes
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALL Disable curve, all peripheral clocks are disabled except FTFE
- Running while (1) loop in Flash NXP Semiconductors
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 49 / 86
Current Consumption (A) Core Freq (MHz)Core: Flash VLPR mode current vs Core FreqTemperature = 25, VDD = 5 V ALL Disable ALL Enable Figure 15. VLPR mode supply current vs. core frequency
5.3.1.7 EMC performance
http://www.nxp.com for advice and guidance specifically targeted at optimizing EMC performance.
- AN2321: Designing for Board Level Electromagnetic Compatibility
- AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
- AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
- AN2764: Improving the Transient Immunity Performance of Microcontroller- Based Applications
- AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems
5.3.1.7.1 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request.
5.3.1.7.2 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize interference from radiated emissions.
- Go to http://www.nxp.com.
- Perform a keyword search for “EMC design”.
- Select the "Documents" category and find the application notes.
5.3.1.8 Capacitance attributes
Table 40. Capacitance attributes Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 51 / 86
Table 40. Capacitance attributes (continued) Please see External Oscillator electrical specifications for EXTAL/XTAL pins.
5.3.2 Switching specifications
5.3.2.1 Device clock specifications
Table 41. Device clock specifications
- The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing specification
5.3.2.2 AC electrical characteristics
at the 20% and 80% points, as shown in the following figure. Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 52 / 86
The midpoint is V IL + (V IH - V IL ) / 2 Low High Midpoint 1 80% 50% 20% Fall Time VIL Rise Time VIH Figure 16. Input signal measurement reference All digital I/O switching characteristics, unless otherwise specified, assume that the output pins have the following characteristics.
- CL = 30 pF loads
- Normal drive strength
5.3.2.3 General AC specifications
These general purpose specifications apply to all signals configured for GPIO, LPUART, SCI, and timers. Table 42. General switching specifications
- This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
- The greater of synchronous and asynchronous timing must be met.
- These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
- These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized.
Table 43. Supply voltage range
- Max power supply ramp rate is 500 V/ms.
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 53 / 86
Table 44. Functional pad AC specifications
- Propagation delay measured from 50% of core side input to 50% of the output.
- Edges measured using 20% and 80% of the VDD supply.
All measurements were taken accounting for 150 mV drop across VDD and VSS.
5.3.2.5 AC specifications at 5 V range
Table 45. I/O supply voltage range
- Max power supply ramp rate is 500 V/ms
Table 46. Functional pad AC specifications
- As measured from 50% of core side input to 50% of the output.
- Edges measured using 20% and 80% of the VDD supply.
All measurements were taken accounting for 150 mV drop across VDD and VSS. Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 54 / 86
5.3.3 Thermal specifications
5.3.3.1 Thermal operating requirements
Table 47. Thermal operating requirements
- Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
5.3.3.2 Thermal attributes
5.3.3.2.1 Description
The tables in the following sections describe the thermal characteristics of the device.
5.3.3.2.2 Thermal characteristics for the 100-pin LQFP package
Table 48. Thermal characteristics for the 100-pin LQFP package
- Thermal test board meets JEDEC specification for this package (JESD51-7).
- Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
meant to predict the performance of a package in an application-specific environment.
5.3.3.2.3 Thermal characteristics for the 64-pin LQFP package
Table 49. Thermal characteristics for the 64-pin LQFP package Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 55 / 86
Table 49. Thermal characteristics for the 64-pin LQFP package (continued)
- Thermal test board meets JEDEC specification for this package (JESD51-7).
- Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
meant to predict the performance of a package in an application-specific environment.
- Junction-to-Case thermal resistance determined using an isothermal cold plate. Case temperature refers to the mold
surface temperature at the package top side dead centre.
5.3.3.2.4 General notes for specifications at maximum junction temperature
- TA = ambient temperature for the package (°C)
- RθJA = junction to ambient thermal resistance (°C/W)
- PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: RθJA = RθJC + RθCA where:
- RθJA = junction to ambient thermal resistance (°C/W)
- RθJC = junction to case thermal resistance (°C/W)
- RθCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: TJ = TT + (ΨJT × PD) where:
- TT = thermocouple temperature on top of the package (°C)
- ΨJT = thermal characterization parameter (°C/W) NXP Semiconductors
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 56 / 86
- PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
5.4 Peripheral operating requirements and behaviors
5.4.1 System modules
There are no specifications necessary for the device's system modules.
5.4.2 Clock interface modules
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 57 / 86
5.4.2.1 Oscillator electrical specifications
5.4.2.1.1 External Oscillator electrical specifications
(EXTAL WAVE) mux ref_clk Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 300 ohms ESD PAD 40 ohms EXTAL pin XTAL pin Series resistor for current limitation Crystal or resonatorC1 C2 1M ohms Feedback Resistor1 NOTE: 1. 1M Feedback resistor is needed only for HG mode. Figure 17. Oscillator connections scheme (OSC) Data values in the following "External Oscillator electrical specifications" tables are from simulation. Table 50. External Oscillator electrical specifications (OSC)
4 MHz — 200 — µA
Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 58 / 86
Table 50. External Oscillator electrical specifications (OSC) (continued)
8 MHz — 300 — µA
32 MHz — 2 — mA
4 MHz — 1 — mA
24 MHz — 5 — mA
40 MHz — 6 — mA
Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 59 / 86
- Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator, loading
- C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator
parasitic capacitance of package and board.
- When low power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
5.4.2.1.2 External Oscillator electrical specifications
Table 51. External Oscillator frequency specifications (OSC) Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 60 / 86
Table 51. External Oscillator frequency specifications (OSC) (continued)
- The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve specifications.
5.4.2.2 System Clock Generation (SCG) specifications
5.4.2.2.1 Fast internal RC Oscillator (FIRC) electrical specifications
Table 52. Fast internal RC Oscillator (FIRC) electrical specifications
- The limit is respected across process, voltage and full temperature range.
- Startup time is defined as the time between clock enablement and clock availability for system use.
5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications
Table 53. Slow internal RC oscillator (SIRC) electrical specifications Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 61 / 86
Table 53. Slow internal RC oscillator (SIRC) electrical specifications (continued)
- The limit is respected across process, voltage and full temperature range.
- Startup time is defined as the time between clock enablement and clock availability for system use.
5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications
Table 54. Low Power Oscillator (LPO) electrical specifications
5.4.2.2.4 LPFLL electrical specifications
Table 55. LPFLL electrical specifications
- ΔFcl is dependent on reference clock accuracy. For example, if locked to crystal oscillator, ΔFcl is typically limited by
trimming ability of the module itself; if locked to other clock source which has 3% accuracy, then ΔFcl can only be ±3%.
5.4.3 Memories and memory interfaces
5.4.3.1 Flash memory module (FTFE) electrical specifications
This section describes the electrical characteristics of the flash memory module (FTFE). Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 62 / 86
5.4.3.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 56. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
5.4.3.1.2 Flash timing specifications — command
Table 57. Flash command timing specifications
- 512 KB program flash — — 1.8 ms — trd1sec2k Read 1s Section execution time (2 KB flash) — — 75 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs — tersblk512k Erase Flash Block execution time
- 512 KB program flash — 435 3700 ms tersscr Erase Flash Sector execution time — 15 115 ms 2 tpgmsec1k Program Section execution time (1 KB flash) — 5 — ms — trd1allx Read 1s All Blocks execution time — — 2.2 ms — trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 90 — μs — tersall Erase All Blocks execution time — 500 4200 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tersallu Erase All Blocks Unsecure execution time — 500 4200 ms 2 1. Assumes 25 MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. NXP Semiconductors
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 63 / 86
5.4.3.1.3 Flash high voltage current behaviors
Table 58. Flash high voltage current behaviors
5.4.3.1.4 Reliability specifications
Table 59. NVM reliability specifications
- Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
- Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.4.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.4.5 Analog
5.4.5.1 ADC electrical specifications
Table 60. 12-bit ADC operating conditions Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 64 / 86
Table 60. 12-bit ADC operating conditions (continued)
- Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
- For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
- Clock and compare cycle need to be set according to the guidelines in the device Reference Manual
- ADC conversion will become less reliable above maximum frequency.
- When using ADC hardware averaging, see the device Reference Manual to determine the most appropriate setting for
- Max ADC conversion rate of 1200 Ksps is with 10-bit mode
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 65 / 86
Figure 18. ADC input impedance equivalency diagram All the parameters in the table are given assuming system clock as the clocking source for ADC. monitor the internal analogue parameters, please assume minor degradation. Table 61. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 66 / 86
Table 61. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
- All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
- Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 48 MHz unless otherwise stated.
- These values are based on characterization but not covered by test limits in production.
- The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
MHz ADC conversion clock speed.
- 1 LSB = (VREFH - VREFL)/2N
- ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
- Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz.
- ADC conversion clock < 3 MHz
- The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed
application information of the temperature sensor. Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 67 / 86
5.4.5.2 CMP with 8-bit DAC electrical specifications
Table 62. Comparator with 8-bit DAC electrical specifications Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 68 / 86
Table 62. Comparator with 8-bit DAC electrical specifications (continued)
- Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated.
- Difference at input > 200mV
- Applied ± (100 mV + Hyst) around switch point
- Applied ± (30 mV + 2 × Hyst) around switch point
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 69 / 86
5.4.6 Communication interfaces
5.4.6.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications.
5.4.6.2 LPSPI electrical specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input signal transitions of 3 ns and a 25 pF maximum load on all LPSPI pins. Table 63. LPSPI master mode timing
- fperiph is LPSPI peripheral functional clock. The maximum frequency of fSPSCK cannot be exceed 25 MHz.
High drive pin should be used for fast bit rate. Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 72 / 86
When LPSPI transmitting data with using pins in Table 64, the maximum frequency of fSPSCK can reach 48 MHz in HSRUN mode. NOTE Table 64. Specifical pins can reach 48 MHz frequency
- If configured as an output.
Figure 23. LPSPI master mode timing (CPHA = 0) Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 73 / 86
<<CLASSIFICATION>> <<NDA MESSAGE>> 6 7 MSB IN 2 BIT 6 . . . 1 MASTER MSB OUT 2 MASTER LSB OUT 10 11 PORT DATA PORT DATA 3 10 11 4 1.If configured as output (OUTPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS 1 (OUTPUT) (OUTPUT) MOSI (OUTPUT) MISO (INPUT) LSB INBIT 6 . . . 1 Figure 24. LPSPI master mode timing (CPHA = 1) Table 65. LPSPI slave mode timing on slew rate enabled pads
- fperiph = LPSPI peripheral functional clock. The maximum frequency of fSPSCk cannot be exceed 25 MHz.
- Time to data active from high-impedance state
- Hold time to high-impedance state
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 74 / 86
BIT 6 . . . 1 SLAVE MSB SLAVE LSB OUT 553 SEE NOTE see note (INPUT) (CPOL=0) SPSCK SPSCK (CPOL=1) SS (INPUT) (INPUT) MOSI (INPUT) MISO (OUTPUT) LSB INBIT 6 . . . 1 Figure 25. LPSPI slave mode timing (CPHA = 0) Figure 26. LPSPI slave mode timing (CPHA = 1)
5.4.6.3 LPI2C
Table 66. LPI2C specifications Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 75 / 86
- Hs-mode is only supported in slave mode. 2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more information on the required pull-up devices, see I2C Bus Specification. 3. See the section "General switching specifications".
5.4.7 Human-machine interfaces (HMI)
5.4.7.1 Touch sensing input (TSI) electrical specifications
Table 67. TSI electrical specifications
5.4.8 Debug modules
5.4.8.1 SWD electricals
Table 68. SWD full voltage range electricals Table continues on the next page... Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 76 / 86
Table 68. SWD full voltage range electricals (continued) Figure 27. Serial wire clock input timing Figure 28. Serial wire data timing
6 Design considerations
6.1 Hardware design considerations
precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit.
6.1.1 Printed circuit board recommendations
- Place connectors or cables on one edge of the board and do not place digital circuits between connectors.
- Drivers and filters for I/O functions must be placed as close to the connectors as possible. Connect TVS devices at the connector to a good ground. Connect filter capacitors at the connector to a good ground. Consider to add ferrite bead or inductor to some sensitive lines.
- Physically isolate analog circuits from digital circuits if possible.
- Place input filter capacitors as close to the MCU as possible.
- For best EMC performance, route signals as transmission lines; use a ground plane directly under LQFP packages; and solder the exposed pad (EP) to ground directly under QFN packages.
6.1.2 Power delivery system
- Use a plane for ground.
- Use a plane for MCU VDD supply if possible.
- Always route ground first, as a plane or continuous surface, and never as sequential segments.
- Always route the power net as star topology, and make each power trace loop as minimum as possible.
- Route power next, as a plane or traces that are parallel to ground traces.
- Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
- Place bypass capacitors for MCU power domain as close as possible to each VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
- The minimum bypass requirement is to place 0.1 μF capacitors positioned as near as possible to the package supply pins.
6.1.3 Analog design
Figure 29. RC circuit for ADC input less than the injection current limit. External clamp diodes can be added here to protect against transient over-voltages.
Figure 30. High voltage measurement with an ADC input
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V). CAUTION: Do not provide power to I/O pins prior to VDD, especially the RESET_b pin.
- RESET_b pin The RESET_b pin is a pseudo open-drain I/O pin that has an internal pullup resistor. An external RC circuit is recommended to filter noise as shown in the following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable digital filter to reject spurious noise. D D C C B B A A EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR EXTAL XTAL OSCILLATOR MCU ADCx MCU ADCx MCU RESET_b MCU NMI_b MCU RESET_b Supervisor Chip OUT Active high, open drain RESET_b SWD_DIO SWD_CLK Analog input High voltage input RESET_b VDD VDD VDD VDD VDD VDD Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 R 1 2 0.1uF 1 2 Cx 0.1uF RESONATOR 1 3 Cy Cx CRYSTAL HDR_5X2 1 2 3 4 7 8 9 10 Cy 10k 10k CRYSTAL 0.1uF 10k CRYSTAL 1 2 1 2 C RESONATOR 1 3 1 2 10k 10k RF 1 2 RS BAT54SW 1 2 RS RS C RF 1 2 RS 1 2 RF 1 2 CRYSTAL
Figure 31. Reset circuit
Figure 34. SWD debug interface
- Unused pin Unused GPIO pins must be left floating (no electrical connections) with the MUX field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital input path to the MCU.
6.1.5 Crystal oscillator
The series resistor, RS, is required in high gain (HGO=1) mode when the crystal or resonator frequency is below 2 MHz. with a frequency above 2 MHz does not require any series resistance. Table 69. External crystal/resonator connections Figure 35. Crystal connection – Diagram 2
RESET_b MCU NMI_b MCU RESET_b Supervisor Chip OUT Active high, open drain RESET_b SWD_DIO SWD_CLK Analog input High voltage input RESET_b VDD VDD VDD VDD VDD VDD Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 Drawing Title: Size Document Number Rev Date: Sheet of Page Title: ICAP Classification: FCP: FIUO: PUBI: SCH-XXXXX PDF: SPF-XXXXX X <Title> C Friday, February 06, 2015 <PageTitle> 1 1 R 1 2 0.1uF 1 2 Cx 0.1uF RESONATOR 1 3 Cy Cx CRYSTAL HDR_5X2 1 2 3 4 7 8 9 10 Cy 10k 10k CRYSTAL 0.1uF 10k CRYSTAL 1 2 1 2 C RESONATOR 1 3 1 2 10k 10k RF 1 2 RS BAT54SW 1 2 RS RS C RF 1 2 RS 1 2 RF 1 2 CRYSTAL Figure 36. Crystal connection – Diagram 3 For PCB layout, the user could consider to add the guard ring to the crystal oscillator circuit.
7 Revision history
Table 70 provides a revision history for this document. Table 70. Revision history
- Updated Ordering information
- Updated Figure 2
- Updated Memory
- Updated Table 7
- Added TSI
- Updated ESD handling ratings
- UPdated descritions of Power consumption
- Updated Low power mode peripheral current adder — typical value Rev. 1 11/2023 • Initial version NXP Semiconductors
Revision history
Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 82 / 86
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. NXP Semiconductors Legal information Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 83 / 86
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at https://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this document expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document, including the legal information in that document, is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. NXP B.V. — NXP B.V. is not an operating company and it does not distribute or sell products. Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. NXP Semiconductors Legal information Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 84 / 86
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, μVision, Versatile — are trademarks and/or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved. EdgeLock — is a trademark of NXP B.V. i.MX — is a trademark of NXP B.V. NXP Semiconductors Legal information Kinetis KE17Z/13Z/12Z with up to 512 KB Flash, Rev. 2, 04/2024 Data Sheet: Technical Data General Business Information 85 / 86
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2024. All rights reserved. For more information, please visit: https://www.nxp.com Date of release: 04/2024 Document identifier: KE1xZP100M96SF0