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Technical content
KE06 Sub-Family Data Sheet Supports the following: MKE06Z64VLD4(R), MKE06Z128VLD4(R), MKE06Z64VQH4(R), MKE06Z128VQH4(R), MKE06Z64VLH4(R), MKE06Z128VLH4(R), MKE06Z64VLK4(R), and MKE06Z128VLK4(R) Key features
- Operating characteristics – Voltage range: 2.7 to 5.5 V – Flash write voltage range: 2.7 to 5.5 V – Temperature range (ambient): -40 to 105°C
- Performance – Up to 48 MHz ARM® Cortex-M0+ core – Single cycle 32-bit x 32-bit multiplier – Single cycle I/O access port
- Memories and memory interfaces – Up to 128 KB flash – Up to 16 KB RAM
- Clocks – Oscillator (OSC) - supports 32.768 kHz crystal or 4 MHz to 24 MHz crystal or ceramic resonator; choice of low power or high gain oscillators – Internal clock source (ICS) - internal FLL with internal or external reference, 37.5 kHz pre-trimmed internal reference for 48 MHz system clock – Internal 1 kHz low-power oscillator (LPO)
- System peripherals – Power management module (PMC) with three power modes: Run, Wait, Stop – Low-voltage detection (LVD) with reset or interrupt, selectable trip points – Watchdog with independent clock source (WDOG) – Programmable cyclic redundancy check module (CRC) – Serial wire debug interface (SWD) – Aliased SRAM bitband region (BIT-BAND) – Bit manipulation engine (BME)
- Security and integrity modules – 80-bit unique identification (ID) number per chip
- Human-machine interface – Up to 71 general-purpose input/output (GPIO) – Two 32-bit keyboard interrupt modules (KBI) – External interrupt (IRQ)
- Analog modules – One up to 16-channel 12-bit SAR ADC, operation in Stop mode, optional hardware trigger (ADC) – Two analog comparators containing a 6-bit DAC and programmable reference input (ACMP)
- Timers – One 6-channel FlexTimer/PWM (FTM) – Two 2-channel FlexTimer/PWM (FTM) – One 2-channel periodic interrupt timer (PIT) – One pulse width timer (PWT) – One real-time clock (RTC)
- Communication interfaces – Two SPI modules (SPI) – Up to three UART modules (UART) – Two I2C modules (I2C) – One MSCAN module (MSCAN)
- Package options – 80-pin LQFP – 64-pin QFP/LQFP – 44-pin LQFP NXP Semiconductors Document Number MKE06P80M48SF0 Data Sheet: Technical Data Rev. 4, 07/2016 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
KE06 Sub-Family Data Sheet, Rev. 4, 07/2016
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KE06 Sub-Family Data Sheet, Rev. 4, 07/2016 NXP Semiconductors 3
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: KE06Z. Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q KE## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification KE## Kinetis family • KE06 A Key attribute • Z = M0+ core FFF Program flash memory size • 128 = 128 KB R Silicon revision • (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105 Table continues on the next page... Ordering parts KE06 Sub-Family Data Sheet, Rev. 4, 07/2016
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- QH = 64 QFP (14 mm x 14 mm)
- LH = 64 LQFP (10 mm x 10 mm)
- LK = 80 LQFP (14 mm x 14 mm) CC Maximum CPU frequency (MHz) • 4 = 48 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
3 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. Table 1. Parameter classifications P Those parameters are guaranteed during production testing on each individual device. typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. parameter tables where appropriate.
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model –6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 +500 V 2 ILAT Latch-up current at ambient temperature of 125°C –100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test.
- Test was performed at 125 °C case temperature (Class II).
- I/O pins pass ±100 mA I-test with I DD current limit at 400 mA.
- I/O pins pass +50/-100 mA I-test with I DD current limit at 1000 mA.
- Supply groups pass 1.5 V ccmax.
- RESET pin was only tested with negative I-test due to product conditioning requirement. Ratings KE06 Sub-Family Data Sheet, Rev. 4, 07/2016
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4.4 Voltage and current operating ratings
operating conditions, refer to the remaining tables in this document. associated with the pin is enabled. Table 2. Voltage and current operating ratings
- Maximum rating of VDD also applies to VIN.
5.1.1 DC characteristics
Table 3. DC characteristics Table continues on the next page...
Table 3. DC characteristics (continued)
3 V — — –60
3 V — — 60
- Typical values are measured at 25 °C. Characterized, not tested.
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- Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0 (64-pin and 80-pin packages only), and PTH1 (64-pin and 80-pin
packages only) support high current output.
- The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
- All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 are true
open drain I/O pins that are internally clamped to VSS.
- Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger value.
- Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
is very low (which would reduce overall power consumption). Table 4. LVD and POR specification
- Maximum is highest voltage that POR is guaranteed.
- Rising thresholds are falling threshold + hysteresis.
- voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C
Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V) Figure 2. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 3 V)
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Figure 5. Typical VOL Vs. IOL (standard drive strength) (VDD = 5 V) Figure 6. Typical VOL Vs. IOL (standard drive strength) (VDD = 3 V)
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5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes. Table 5. Supply current characteristics Table continues on the next page...
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Table 5. Supply current characteristics (continued)
- Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
- The Max current is observed at high temperature of 105 °C.
- RTC adder cause <1 µA IDD increase typically, RTC clock source is 1 kHz LPO clock.
- LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
specifically targeted at optimizing EMC performance.
- AN2321: Designing for Board Level Electromagnetic Compatibility
- AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
- AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers Nonswitching electrical specifications KE06 Sub-Family Data Sheet, Rev. 4, 07/2016 NXP Semiconductors 15
- AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
- AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems
5.1.3.1 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors for 80-pin LQFP package
- Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
measured orientations in each frequency range.
- IEC/SAE Level Maximums: N≤12 dBµV, M≤18 dBµV, K≤30 dBµV, I ≤36 dBµV, H≤42 dBµV.
- Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
5.2.1 Control timing
Table 7. Control timing
1 D System and core clock fSys DC — 48 MHz
2 P Bus frequency (tcyc = 1/fBus) fBus DC — 24 MHz
5 D Reset low drive trstdrv 34 × tcyc — — ns
6 D IRQ pulse width Asynchronous
Table continues on the next page...
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Table 7. Control timing (continued)
7 D Keyboard interrupt pulse
8 C Port rise and fall time -
- Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
- This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
- This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
- Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
Figure 9. Reset timing Figure 10. KBIPx timing
5.2.2 FTM module timing
synchronizers operate from the current bus rate clock. Table 8. FTM input timing Table continues on the next page...
Table 8. FTM input timing (continued) Figure 11. Timer external clock Figure 12. Timer input capture pulse
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
- Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
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5.3.2 Thermal characteristics
Table 10. Thermal attributes
64 QFP 44
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
- Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
- Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
- Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
- Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.
be obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
Table 11. SWD full voltage range electricals
- Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
- Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 3 — ns Table continues on the next page... Peripheral operating requirements and behaviors KE06 Sub-Family Data Sheet, Rev. 4, 07/2016
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Table 11. SWD full voltage range electricals (continued) Figure 13. Serial wire clock input timing Figure 14. Serial wire data timing
6.2 External oscillator (OSC) and ICS characteristics
Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
1 C Crystal or
Table continues on the next page...
2 D Load capacitors C1, C2 See Note2
3 D Feedback
4 D Series resistor -
5 D Series resistor -
4 MHz — 0 — kΩ
6 C Crystal start-up
7 T Internal reference start-up time tIRST — 20 50 µs
8 P Internal reference clock (IRC) frequency trim
9 P Internal
10 P DCO output
11 P Factory trimmed
12 C Deviation of IRC
13 C Frequency
Table continues on the next page...
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14 C FLL acquisition time4,6 tAcquire — — 2 ms
15 C Long term jitter of DCO output clock
- Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
- See crystal or resonator manufacturer's recommendation.
- Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
- This parameter is characterized and not tested on each device.
- Proper PC board layout procedures must be followed to achieve specifications.
- This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
the reference, this specification assumes it is already running.
- Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Figure 15. Typical crystal or resonator circuit
6.3 NVM specifications
Table 13. Flash characteristics Table continues on the next page...
Table 13. Flash characteristics (continued)
- Minimum times are based on maximum fNVMOP and maximum fNVMBUS
- Typical times are based on typical fNVMOP and maximum fNVMBUS
- Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
the Flash Memory Module section in the reference manual.
6.4 Analog
6.4.1 ADC characteristics
Table 14. 5 V 12-bit ADC operating conditions
- Low
- High VREFL VREFH VSSA VDDA/2 VDDA/2 VDDA V — Table continues on the next page... Peripheral operating requirements and behaviors KE06 Sub-Family Data Sheet, Rev. 4, 07/2016
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Table 14. 5 V 12-bit ADC operating conditions (continued)
- f ADCK > 4 MHz
- f ADCK < 4 MHz RAS — kΩ External to MCU 10-bit mode
- f ADCK > 4 MHz
- f ADCK < 4 MHz 8-bit mode (all valid fADCK) — — 10 ADC conversion clock frequency High speed (ADLPC=0) fADCK 0.4 — 8.0 MHz — Low power (ADLPC=1) 0.4 — 4.0 1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. ADC SAR ENGINE SIMPLIFIED CHANNEL SELECT CIRCUIT SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS R AS C AS v ADIN v AS z ADIN R ADIN R ADIN R ADIN R ADIN INPUT PIN INPUT PIN INPUT PIN C ADIN
Figure 16. ADC input impedance equivalency diagram
Table 15. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page...
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Table 15. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- 1 LSB = (VREFH - VREFL)/2N
- IIn = leakage current (refer to DC characteristics)
6.4.2 Analog comparator (ACMP) electricals
Table 16. Comparator electrical specifications
6.5 Communication interfaces
6.5.1 SPI switching specifications
rate control is disabled and high-drive strength is enabled for SPI output pins. Table 17. SPI master mode timing 1 . If configured as an output. Figure 17. SPI master mode timing (CPHA=0)
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Figure 18. SPI master mode timing (CPHA=1) Table 18. SPI slave mode timing
Figure 19. SPI slave mode timing (CPHA = 0) Figure 20. SPI slave mode timing (CPHA=1)
6.5.2 MSCAN
Table 19. MSCAN wake-up pulse characteristics
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7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 32-pin QFN 98ASA00473D 44-pin LQFP 98ASS23225W 64-pin QFP 98ASB42844B 64-pin LQFP 98ASS23234W 80-pin LQFP 98ASS23237W Pinout
8.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE VSS and VSSA are internally connected. VREFH and VDDA are internally connected in 64-pin packages. PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 are high-current drive pins when operated as output. PTA2 and PTA3 are true open-drain pins when operated as output. Dimensions KE06 Sub-Family Data Sheet, Rev. 4, 07/2016 NXP Semiconductors 31
/QFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 1 1 1 PTD1 DISABLEDPTD1 KBI0_P25 FTM2_CH3SPI1_MOSI 2 2 2 PTD0 DISABLEDPTD0 KBI0_P24 FTM2_CH2SPI1_SCK 3 3 — PTH7 DISABLEDPTH7 KBI1_P31 PWT_IN1 4 4 — PTH6 DISABLEDPTH6 KBI1_P30 5 — — PTH5 DISABLEDPTH5 KBI1_P29 6 5 3 PTE7 DISABLEDPTE7 KBI1_P7 TCLK2 FTM1_CH1CAN0_TX 7 6 4 PTH2 DISABLEDPTH2 KBI1_P26 BUSOUT FTM1_CH0CAN0_RX 8 7 5 VDD VDD VDD 9 8 6 VDDA VDDA VREFH VDDA 10 — — VREFH VREFH VREFH 11 9 7 VREFL VREFL VREFL 12 10 8 VSS/ VSSA VSS/ VSSA VSSA VSS 13 11 9 PTB7 EXTAL PTB7 KBI0_P15 I2C0_SCL EXTAL 14 12 10 PTB6 XTAL PTB6 KBI0_P14 I2C0_SDA XTAL 15 13 11 PTI4 DISABLEDPTI4 IRQ 16 — — PTI1 DISABLEDPTI1 IRQ UART2_TX 17 — — PTI0 DISABLEDPTI0 IRQ UART2_RX 18 14 — PTH1 DISABLEDPTH1 KBI1_P25 FTM2_CH1 19 15 — PTH0 DISABLEDPTH0 KBI1_P24 FTM2_CH0 20 16 — PTE6 DISABLEDPTE6 KBI1_P6 21 17 — PTE5 DISABLEDPTE5 KBI1_P5 22 18 12 PTB5 DISABLEDPTB5 KBI0_P13 FTM2_CH5SPI0_PCSACMP1_OUT 23 19 13 PTB4 NMI_b PTB4 KBI0_P12 FTM2_CH4SPI0_MISOACMP1_IN2NMI_b 24 20 14 PTC3 ADC0_SE11PTC3 KBI0_P19 FTM2_CH3 ADC0_SE11 25 21 15 PTC2 ADC0_SE10PTC2 KBI0_P18 FTM2_CH2 ADC0_SE10 26 22 16 PTD7 DISABLEDPTD7 KBI0_P31 UART2_TX 27 23 17 PTD6 DISABLEDPTD6 KBI0_P30 UART2_RX 28 24 18 PTD5 DISABLEDPTD5 KBI0_P29 PWT_IN0 29 — — PTI6 DISABLEDPTI6 IRQ 30 — — PTI5 DISABLEDPTI5 IRQ 31 25 19 PTC1 ADC0_SE9PTC1 KBI0_P17 FTM2_CH1 ADC0_SE9 32 26 20 PTC0 ADC0_SE8PTC0 KBI0_P16 FTM2_CH0 ADC0_SE8 33 — — PTH4 DISABLEDPTH4 KBI1_P28 I2C1_SCL 34 — — PTH3 DISABLEDPTH3 KBI1_P27 I2C1_SDA 35 27 — PTF7 ADC0_SE15PTF7 KBI1_P15 ADC0_SE15 36 28 — PTF6 ADC0_SE14PTF6 KBI1_P14 ADC0_SE14 37 29 — PTF5 ADC0_SE13PTF5 KBI1_P13 ADC0_SE13 38 30 — PTF4 ADC0_SE12PTF4 KBI1_P12 ADC0_SE12 39 31 21 PTB3 ADC0_SE7PTB3 KBI0_P11 SPI0_MOSIFTM0_CH1ADC0_SE7 40 32 22 PTB2 ADC0_SE6PTB2 KBI0_P10 SPI0_SCKFTM0_CH0ADC0_SE6 Pinout KE06 Sub-Family Data Sheet, Rev. 4, 07/2016
32 NXP Semiconductors
/QFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 41 33 23 PTB1 ADC0_SE5PTB1 KBI0_P9 UART0_TX ADC0_SE5 42 34 24 PTB0 ADC0_SE4PTB0 KBI0_P8 UART0_RXPWT_IN1 ADC0_SE4 43 35 — PTF3 DISABLEDPTF3 KBI1_P11 UART1_TX 44 36 — PTF2 DISABLEDPTF2 KBI1_P10 UART1_RX 45 37 25 PTA7 ADC0_SE3PTA7 KBI0_P7 FTM2_FLT2ACMP1_IN1ADC0_SE3 46 38 26 PTA6 ADC0_SE2PTA6 KBI0_P6 FTM2_FLT1ACMP1_IN0ADC0_SE2 47 39 — PTE4 DISABLEDPTE4 KBI1_P4 48 40 27 VSS VSS VSS 49 41 28 VDD VDD VDD 50 — — PTG7 DISABLEDPTG7 KBI1_P23 FTM2_CH5SPI1_PCS 51 — — PTG6 DISABLEDPTG6 KBI1_P22 FTM2_CH4SPI1_MISO 52 — — PTG5 DISABLEDPTG5 KBI1_P21 FTM2_CH3SPI1_MOSI 53 — — PTG4 DISABLEDPTG4 KBI1_P20 FTM2_CH2SPI1_SCK 54 42 — PTF1 DISABLEDPTF1 KBI1_P9 FTM2_CH1 55 43 — PTF0 DISABLEDPTF0 KBI1_P8 FTM2_CH0 56 44 29 PTD4 DISABLEDPTD4 KBI0_P28 57 45 30 PTD3 DISABLEDPTD3 KBI0_P27 SPI1_PCS 58 46 31 PTD2 DISABLEDPTD2 KBI0_P26 SPI1_MISO 59 47 32 PTA3 DISABLEDPTA3 KBI0_P3 UART0_TXI2C0_SCL 60 48 33 PTA2 DISABLEDPTA2 KBI0_P2 UART0_RXI2C0_SDA 61 49 34 PTA1 ADC0_SE1PTA1 KBI0_P1 FTM0_CH1I2C0_ 4WSDAOUT ACMP0_IN1ADC0_SE1 62 50 35 PTA0 ADC0_SE0PTA0 KBI0_P0 FTM0_CH0I2C0_ 4WSCLOUT ACMP0_IN0ADC0_SE0 63 51 36 PTC7 DISABLEDPTC7 KBI0_P23 UART1_TX CAN0_TX 64 52 37 PTC6 DISABLEDPTC6 KBI0_P22 UART1_RX CAN0_RX 65 — — PTI3 DISABLEDPTI3 IRQ 66 — — PTI2 DISABLEDPTI2 IRQ 67 53 — PTE3 DISABLEDPTE3 KBI1_P3 SPI0_PCS 68 54 38 PTE2 DISABLEDPTE2 KBI1_P2 SPI0_MISOPWT_IN0 69 — — VSS VSS VSS 70 — — VDD VDD VDD 71 55 — PTG3 DISABLEDPTG3 KBI1_P19 72 56 — PTG2 DISABLEDPTG2 KBI1_P18 73 57 — PTG1 DISABLEDPTG1 KBI1_P17 74 58 — PTG0 DISABLEDPTG0 KBI1_P16 75 59 39 PTE1 DISABLEDPTE1 KBI1_P1 SPI0_MOSI I2C1_SCL 76 60 40 PTE0 DISABLEDPTE0 KBI1_P0 SPI0_SCKTCLK1 I2C1_SDA 77 61 41 PTC5 DISABLEDPTC5 KBI0_P21 FTM1_CH1 RTC_ CLKOUT Pinout KE06 Sub-Family Data Sheet, Rev. 4, 07/2016 NXP Semiconductors 33
/QFP LQFP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 78 62 42 PTC4 SWD_CLKPTC4 KBI0_P20 RTC_ CLKOUT FTM1_CH0ACMP0_IN2SWD_CLK 79 63 43 PTA5 RESET_b PTA5 KBI0_P5 IRQ TCLK0 RESET_b 80 64 44 PTA4 SWD_DIO PTA4 KBI0_P4 ACMP0_OUTSWD_DIO
8.2 Device pin assignment
KE06 Sub-Family Data Sheet, Rev. 4, 07/2016
34 NXP Semiconductors
Figure 21. 80-pin LQFP package
Figure 22. 64-pin QFP/LQFP packages
36 NXP Semiconductors
33 PTA2
Figure 23. 44-pin LQFP package
9 Revision history
The following table provides a revision history for this document. Table 20. Revision history 1 12/2013 Initial NDA release. 2 3/2014 Initial public release. 3 5/2014 • Updated the Max. of SI DD.
- Updated footnote to the V OH.
- Corrected Unit in the FTM input timing table. 4 07/2016 • Added a new section of Thermal operating requirements.
- Corrected pinout diagram for 44-pin LQFP in the Device pin assignment.
Revision history
KE06 Sub-Family Data Sheet, Rev. 4, 07/2016 NXP Semiconductors 37
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