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Document overview
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Technical content
Supports the following: MKE02Z16VLC2(R), MKE02Z32VLC2(R), MKE02Z64VLC2(R), MKE02Z16VLD2(R), MKE02Z32VLD2(R), MKE02Z64VLD2(R), MKE02Z32VLH2(R), MKE02Z64VLH2(R), MKE02Z32VQH2(R), and MKE02Z64VQH2(R) Key features Operating characteristics – Voltage range: 2.7 to 5.5 V – Flash write voltage range: 2.7 to 5.5 V – Temperature range (ambient): -40 to 105°C
- Performance – Up to 20 MHz ARM® Cortex-M0+ core – Single cycle 32-bit x 32-bit multiplier – Single cycle I/O access port
- Memories and memory interfaces – Up to 64 KB flash – Up to 256 B EEPROM – Up to 4 KB RAM
- Clocks – Oscillator (OSC) - loop-controlled Pierce oscillator, crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz – Internal clock source (ICS) - internal FLL with internal or external reference, precision trimming of internal reference allowing 1% deviation across temperature range of 0 °C to 70 °C and 1.5% deviation across temperature range of -40 °C to 105 °C, up to 20 MHz – Internal 1 kHz low-power oscillator (LPO)
- System peripherals Power management module (PMC) with three power modes: Run, Wait, Stop – Low-voltage detection (LVD) with reset or interrupt, selectable trip points – Watchdog with independent clock source (WDOG) – Programmable cyclic redundancy check module (CRC) – Serial wire debug interface (SWD) – Bit manipulation engine (BME)
- Security and integrity modules – 64-bit unique identification (ID) number per chip
- Human-machine interface – Up to 57 general-purpose input/output (GPIO) – Two 8-bit keyboard interrupt modules (KBI) – Interrupt (IRQ)
- Analog modules – One 16-channel 12-bit SAR ADC, operation in Stop mode, optional hardware trigger (ADC) – Two analog comparators containing a 6-bit DAC and programmable reference input (ACMP)
- Timers – One 6-channel FlexTimer/PWM (FTM) – Two 2-channel FlexTimer/PWM (FTM) – One 2-channel periodic interrupt timer (PIT) – One real-time clock (RTC) Freescale Semiconductor Document Number MKE02P64M20SF0 Data Sheet: Technical Data Rev 3, 07/2013 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2013 Freescale Semiconductor, Inc.
- Communication interfaces – Two SPI modules (SPI) – Three UART modules (UART) – One I2C module (I2C)
- Package options – 64-pin QFP/LQFP – 44-pin LQFP – 32-pin LQFP KE02 Sub-Family Data Sheet, Rev3, 07/2013. 2 Freescale Semiconductor, Inc.
KE02 Sub-Family Data Sheet, Rev3, 07/2013. Freescale Semiconductor, Inc. 3
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: KE02Z. Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format: Q KE## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow
- P = Prequalification KE## Kinetis family • KE02 A Key attribute • Z = M0+ core FFF Program flash memory size • 16 = 16 KB
- 32 = 32 KB
- 64 = 64 KB R Silicon revision • (Blank) = Main
- A = Revision after main Table continues on the next page... Ordering parts KE02 Sub-Family Data Sheet, Rev3, 07/2013. 4 Freescale Semiconductor, Inc.
- LD = 44 LQFP (10 mm x 10 mm)
- QH = 64 QFP (14 mm x 14 mm)
- LH = 64 LQFP (10 mm x 10 mm) CC Maximum CPU frequency (MHz) • 2 = 20 MHz N Packaging type • R = Tape and reel
- (Blank) = Trays
2.4 Example
3 Parameter classification
The electrical parameters shown in this supplement are guaranteed by various methods. Table 1. Parameter classifications P Those parameters are guaranteed during production testing on each individual device. typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. parameter tables where appropriate. KE02 Sub-Family Data Sheet, Rev3, 07/2013.
4.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model –6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 +500 V ILAT Latch-up current at ambient temperature of 105°C –100 +100 mA 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM).
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. Ratings KE02 Sub-Family Data Sheet, Rev3, 07/2013. 6 Freescale Semiconductor, Inc.
associated with the pin is enabled. Table 2. Voltage and current operating ratings
- Analog pins are defined as pins that do not have an associated general-purpose I/O port function.
5.1.1 DC characteristics
Table 3. DC characteristics
5 V, Iload = –
Table continues on the next page... KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Table 3. DC characteristics (continued)
5 V — — –100 mA
3 V — — –60
5 V, Iload = 5
5 V, Iload
5 V — — 100 mA
3 V — — 60
- Typical values are measured at 25 °C. Characterized, not tested.
- Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support ultra high current output.
- All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD.
- Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the large value.
- Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
very low (which would reduce overall power consumption). KE02 Sub-Family Data Sheet, Rev3, 07/2013. 8 Freescale Semiconductor, Inc.
Table 4. LVD and POR specification
- Maximum is highest voltage that POR is guaranteed.
- Rising thresholds are falling threshold + hysteresis.
- voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C
KE02 Sub-Family Data Sheet, Rev3, 07/2013.
5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes. Table 5. Supply current characteristics Table continues on the next page... KE02 Sub-Family Data Sheet, Rev3, 07/2013. 14 Freescale Semiconductor, Inc.
Table 5. Supply current characteristics (continued)
- Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
- RTC adder causes IDD to increase typically by less than 1 µA; RTC clock source is 1 kHz LPO clock.
- ACMP adder causes IDD to increase typically by less than 1 µA.
- LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
guidance specifically targeted at optimizing EMC performance.
- AN2321: Designing for Board Level Electromagnetic Compatibility
- AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
- AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
- AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
- AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems Nonswitching electrical specifications KE02 Sub-Family Data Sheet, Rev3, 07/2013. Freescale Semiconductor, Inc. 15
5.2.1 Control timing
Table 6. Control timing
1 P Bus frequency (tcyc = 1/fBus) fBus DC — 20 MHz
4 D Reset low drive trstdrv 34 × tcyc — — ns
5 D IRQ pulse width Asynchronous
6 D Keyboard interrupt pulse
7 C Port rise and fall time -
- Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
- This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
- Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.
Figure 9. Reset timing Figure 10. KBIPx timing KE02 Sub-Family Data Sheet, Rev3, 07/2013. 16 Freescale Semiconductor, Inc.
5.2.2 FTM module timing
synchronizers operate from the current bus rate clock. Table 7. FTM input timing
1 D External clock
2 D External clock
3 D External clock
4 D External clock
5 D Input capture
Figure 11. Timer external clock Figure 12. Timer input capture pulse KE02 Sub-Family Data Sheet, Rev3, 07/2013.
5.3.1 Thermal characteristics
Table 8. Thermal attributes
64 QFP 44
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
- Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
- Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
- Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
- Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
- Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization. KE02 Sub-Family Data Sheet, Rev3, 07/2013. 18 Freescale Semiconductor, Inc.
be obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD electricals
Table 9. SWD full voltage range electricals
- Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width ns Table continues on the next page... Peripheral operating requirements and behaviors KE02 Sub-Family Data Sheet, Rev3, 07/2013. Freescale Semiconductor, Inc. 19
6.2 External oscillator (OSC) and ICS characteristics
Table 10. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)
1 C Oscillator
2 D Load capacitors C1, C2 See Note3
3 D Feedback
4 D Series resistor -
5 D Series resistor -
4 MHz — 0 — kΩ
6 C Crystal start-up
7 T Internal reference start-up time tIRST — 20 50 µs
8 D Square wave
9 P Average target internal reference frequency -
10 P DCO output frequency range - trimmed fdco_t 16 — 20 MHz
11 P Total deviation
12 C FLL acquisition time5, 7 tAcquire — — 2 ms
Table continues on the next page... KE02 Sub-Family Data Sheet, Rev3, 07/2013.
13 C Long term jitter of DCO output clock
- Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
- When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
- See crystal or resonator manufacturer's recommendation.
- Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
- This parameter is characterized and not tested on each device.
- Proper PC board layout procedures must be followed to achieve specifications.
- This specification applies to any time the FLL reference source or reference divider is changed, trim value changed,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
- Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Figure 15. Typical crystal or resonator circuit
6.3 NVM specifications
the flash and EEPROM memories. Table 11. Flash and EEPROM characteristics Table continues on the next page... KE02 Sub-Family Data Sheet, Rev3, 07/2013. 22 Freescale Semiconductor, Inc.
- Minimum times are based on maximum fNVMOP and maximum fNVMBUS
- Typical times are based on typical fNVMOP and maximum fNVMBUS
- Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
the Flash Memory Module section in the reference manual. KE02 Sub-Family Data Sheet, Rev3, 07/2013.
6.4 Analog
6.4.1 ADC characteristics
Table 12. 5 V 12-bit ADC operating conditions
- f ADCK > 4 MHz
- f ADCK < 4 MHz RAS — kΩ External to MCU 10-bit mode
- f ADCK > 4 MHz
- f ADCK < 4 MHz 8-bit mode (all valid fADCK) — — 10 ADC conversion clock frequency High speed (ADLPC=0) fADCK 0.4 — 8.0 MHz — Low power (ADLPC=1) 0.4 — 4.0 1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 1. DC potential difference. Peripheral operating requirements and behaviors KE02 Sub-Family Data Sheet, Rev3, 07/2013. 24 Freescale Semiconductor, Inc.
Figure 16. ADC input impedance equivalency diagram Table 13. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page... KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Table 13. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
- 1 LSB = (VREFH - VREFL)/2N
- Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
- IIn = leakage current (refer to DC characteristics)
KE02 Sub-Family Data Sheet, Rev3, 07/2013. 26 Freescale Semiconductor, Inc.
6.4.2 Analog comparator (ACMP) electricals
Table 14. Comparator electrical specifications
6.5 Communication interfaces
6.5.1 SPI switching specifications
slew rate control is disabled and high-drive strength is enabled for SPI output pins. Table 15. SPI master mode timing Table continues on the next page... KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Table 16. SPI slave mode timing Figure 19. SPI slave mode timing (CPHA = 0) KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Figure 20. SPI slave mode timing (CPHA=1)
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings. KE02 Sub-Family Data Sheet, Rev3, 07/2013. 30 Freescale Semiconductor, Inc.
8.1 Signal multiplexing and pin assignments
for selecting which ALT functionality is available on each pin. Table 17. Pin availability by package pin-count Table continues on the next page... KE02 Sub-Family Data Sheet, Rev3, 07/2013.
Table 17. Pin availability by package pin-count (continued)
- This is a high-current drive pin when operated as output.
KE02 Sub-Family Data Sheet, Rev3, 07/2013. 32 Freescale Semiconductor, Inc.
- VREFH and VDDA are internally connected.
- VSSA and VSS are internally connected.
- This is a true open-drain pin when operated as output.
8.2 Device pin assignment
- High source/sink current pins
Pins in bold are no t available on less pi n -count packages. Figure 21. 64-pin QFP/LQFP packages KE02 Sub-Family Data Sheet, Rev3, 07/2013.
- True open drain pins PTB0 PTB3 PTA7 PTA6 VSS VDD PTD4 PTD3 PTD2 PTA22 PTA1 PTA0 PTC7 PTC6 PTE2 PTE11 PTE01 PTC5 PTC4 PTA5 PTA4 PTD11 PTD01 PTE7 PTH2 VDD VDDA/VREFH VREFL VSS VSSA/VSS PTB7 PTB6 PTB51 PTB41 PTC2 PTD7 PTD6 PTD5 PTC1 PTC0 1. High source/sink current pins Pins in bold are no t available on less pi n -count packages. 3433 PTA32
Figure 22. 44-pin LQFP package
- High source/sink current pins
Figure 23. 32-pin LQFP package
9 Revision history
The following table provides a revision history for this document.
Revision history
KE02 Sub-Family Data Sheet, Rev3, 07/2013. 34 Freescale Semiconductor, Inc.
Table 18. Revision history 3 07/2013 Initial public release. KE02 Sub-Family Data Sheet, Rev3, 07/2013. Freescale Semiconductor, Inc. 35
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