MKE02Z32VQH2

MKE02P64M20SF0 NXP | Alldatasheet

Document overview

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Technical content

KE02 Sub-Family Data Sheet Supports the following: MKE02Z16VLC2(R), MKE02Z32VLC2(R), MKE02Z64VLC2(R), MKE02Z16VLD2(R), MKE02Z32VLD2(R), MKE02Z64VLD2(R), MKE02Z32VLH2(R), MKE02Z64VLH2(R), MKE02Z32VQH2(R), and MKE02Z64VQH2(R) Key features

• Operating characteristics – Voltage range: 2.7 to 5.5 V – Flash write voltage range: 2.7 to 5.5 V – Temperature range (ambient): -40 to 105°C
• Performance – Up to 20 MHz Arm® Cortex-M0+ core – Single cycle 32-bit x 32-bit multiplier – Single cycle I/O access port
• Memories and memory interfaces – Up to 64 KB flash – Up to 256 B EEPROM – Up to 4 KB RAM
• Clocks – Oscillator (OSC) - supports 32.768 kHz crystal or 4 MHz to 20 MHz crystal or ceramic resonator; choice of low power or high gain oscillators – Internal clock source (ICS) - internal FLL with internal or external reference, 31.25 kHz pre- trimmed internal reference for 16 MHz system clock (able to be trimmed for up to 20 MHz system clock) – Internal 1 kHz low-power oscillator (LPO)
• System peripherals – Power management module (PMC) with three power modes: Run, Wait, Stop – Low-voltage detection (LVD) with reset or interrupt, selectable trip points – Watchdog with independent clock source (WDOG) – Programmable cyclic redundancy check module (CRC) – Serial wire debug interface (SWD) – Bit manipulation engine (BME)
• Security and integrity modules – 64-bit unique identification (ID) number per chip
• Human-machine interface – Up to 57 general-purpose input/output (GPIO) – Two up to 8-bit keyboard interrupt modules (KBI) – External interrupt (IRQ)
• Analog modules – One up to 16-channel 12-bit SAR ADC, operation in Stop mode, optional hardware trigger (ADC) – Two analog comparators containing a 6-bit DAC and programmable reference input (ACMP)
• Timers – One 6-channel FlexTimer/PWM (FTM) – Two 2-channel FlexTimer/PWM (FTM) – One 2-channel periodic interrupt timer (PIT) – One real-time clock (RTC) NXP Semiconductors Document Number MKE02P64M20SF0 Data Sheet: Technical Data Rev. 7, 12/2019 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Communication interfaces – Two SPI modules (SPI) – Up to three UART modules (UART) – One I2C module (I2C)
• Package options – 64-pin QFP/LQFP – 44-pin LQFP – 32-pin LQFP KE02 Sub-Family Data Sheet, Rev. 7, 12/2019

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KE02 Sub-Family Data Sheet, Rev. 7, 12/2019 NXP Semiconductors 3

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: KE02Z. Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q KE## A FFF R T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification KE## Kinetis family • KE02 A Key attribute • Z = M0+ core FFF Program flash memory size • 16 = 16 KB
• 32 = 32 KB
• 64 = 64 KB R Silicon revision • (Blank) = Main
• A = Revision after main Table continues on the next page... Ordering parts KE02 Sub-Family Data Sheet, Rev. 7, 12/2019

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• LD = 44 LQFP (10 mm x 10 mm)
• QH = 64 QFP (14 mm x 14 mm)
• LH = 64 LQFP (10 mm x 10 mm) CC Maximum CPU frequency (MHz) • 2 = 20 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

2.4 Example

3 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. Table 1. Parameter classifications P Those parameters are guaranteed during production testing on each individual device. typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. parameter tables where appropriate.

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model –6000 +6000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 +500 V 2 ILAT Latch-up current at ambient temperature of 125°C –100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test.

• Test was performed at 125 °C case temperature (Class II).
• I/O pins pass ±100 mA I-test with I DD current limit at 800 mA.
• I/O pins pass +60/-100 mA I-test with I DD current limit at 1000 mA.
• Supply groups pass 1.5 V ccmax.
• RESET pin was only tested with negative I-test due to product conditioning requirement. Ratings KE02 Sub-Family Data Sheet, Rev. 7, 12/2019

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4.4 Voltage and current operating ratings

operating conditions, refer to the remaining tables in this document. associated with the pin is enabled. Table 2. Voltage and current operating ratings

1. Maximum rating of VDD also applies to VIN.

5.1.1 DC characteristics

Table 3. DC characteristics Table continues on the next page...

Table 3. DC characteristics (continued)

3 V — — –60

3 V — — 60

1. Typical values are measured at 25 °C. Characterized, not tested.
2. Maximum power supply VDD ramp-up rate is 70V/ms, characterized on samples of different lots.

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1. Only PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, and PTH1 support high current output.
2. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
3. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 are true

open drain I/O pins that are internally clamped to VSS.

1. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,

calculate resistance values for positive and negative clamp voltages, then use the larger value.

1. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current

is very low (which would reduce overall power consumption). Table 4. LVD and POR specification

1. Maximum is highest voltage that POR is guaranteed.
2. Rising thresholds are falling threshold + hysteresis.
3. voltage Factory trimmed at VDD = 5.0 V, Temp = 25 °C

Figure 1. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 5 V) Figure 2. Typical VDD-VOH Vs. IOH (standard drive strength) (VDD = 3 V)

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Figure 5. Typical VOL Vs. IOL (standard drive strength) (VDD = 5 V) Figure 6. Typical VOL Vs. IOL (standard drive strength) (VDD = 3 V)

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5.1.2 Supply current characteristics

This section includes information about power supply current in various operating modes. Table 5. Supply current characteristics Table continues on the next page...

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Table 5. Supply current characteristics (continued)

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. The Max current is observed at high temperature of 105 °C.
3. RTC adder causes IDD to increase typically by less than 1 µA; RTC clock source is 1 kHz LPO clock.
4. LVD is periodically woken up from Stop by 5% duty cycle. The period is equal to or less than 2 ms.

5.1.3 EMC performance

specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based

Applications

• AN1259: System Design and Layout Techniques for Noise Reduction in MCU- Based Systems Nonswitching electrical specifications KE02 Sub-Family Data Sheet, Rev. 7, 12/2019 NXP Semiconductors 15

5.1.3.1 EMC radiated emissions operating behaviors

Table 6. EMC radiated emissions operating behaviors for 64-pin QFP package

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

measured orientations in each frequency range.

1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

5.2.1 Control timing

Table 7. Control timing

1 D System and core clock fSys DC — 20 MHz

2 P Bus frequency (tcyc = 1/fBus) fBus DC — 20 MHz

5 D Reset low drive trstdrv 34 × tcyc — — ns

6 D IRQ pulse width Asynchronous

7 D Keyboard interrupt pulse

8 C Port rise and fall time -

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1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a RESET pin request.
3. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

1. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C.

Figure 9. Reset timing Figure 10. KBIPx timing

5.2.2 FTM module timing

synchronizers operate from the current bus rate clock. Table 8. FTM input timing Figure 11. Timer external clock

Figure 12. Timer input capture pulse

5.3.1 Thermal operating requirements

Table 9. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

5.3.2 Thermal characteristics

Table 10. Thermal attributes

64 QFP 44

Table continues on the next page...

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Table 10. Thermal attributes (continued)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
2. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

1. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
2. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization.

be obtained by solving the above equations iteratively for any value of TA.

6 Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 SWD electricals

Table 11. SWD full voltage range electricals

• Serial wire debug MHz J2 SWD_CLK cycle period 1/J1 — ns J3 SWD_CLK clock pulse width
• Serial wire debug ns J4 SWD_CLK rise and fall times — 3 ns J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns J10 SWD_DIO input data hold time after SWD_CLK rise 3 — ns J11 SWD_CLK high to SWD_DIO data valid — 35 ns J12 SWD_CLK high to SWD_DIO high-Z 5 — ns J3 J3 J4 J4 SWD_CLK (input)

Figure 13. Serial wire clock input timing

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Figure 14. Serial wire data timing

6.2 External oscillator (OSC) and ICS characteristics

Table 12. OSC and ICS specifications (temperature range = -40 to 105 °C ambient)

1 C Crystal or

2 D Load capacitors C1, C2 See Note2

3 D Feedback

4 D Series resistor -

5 D Series resistor -

Table continues on the next page...

4 MHz — 0 — kΩ

6 C Crystal start-up

7 T Internal reference start-up time tIRST — 20 50 µs

8 P Internal reference clock (IRC) frequency trim

9 P Internal

10 P DCO output

11 P Factory trimmed

12 C Deviation of IRC

13 C Frequency

14 C FLL acquisition time4,7 tAcquire — — 2 ms

15 C Long term jitter of DCO output clock

1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. See crystal or resonator manufacturer's recommendation.
3. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
4. This parameter is characterized and not tested on each device.
5. Proper PC board layout procedures must be followed to achieve specifications.
6. The accuracy is for factory trimmed deviation when performing trim process in NXP, however, the reflow process may

cause an extra 0.5% drift at the room temperature.

1. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or

the reference, this specification assumes it is already running.

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1. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.

Figure 15. Typical crystal or resonator circuit

6.3 NVM specifications

the flash and EEPROM memories. Table 13. Flash and EEPROM characteristics Table continues on the next page...

1. Minimum times are based on maximum fNVMOP and maximum fNVMBUS
2. Typical times are based on typical fNVMOP and maximum fNVMBUS
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging

the Flash Memory Module section in the reference manual.

6.4 Analog

6.4.1 ADC characteristics

Table 14. 5 V 12-bit ADC operating conditions

• Low
• High VREFL VREFH VSSA VDDA VSSA VDDA V — Supply voltage Absolute VDDA 2.7 — 5.5 V — Delta to VDD (VDD-VDDA) ΔVDDA -100 0 +100 mV — Ground voltage Delta to VSS (VSS-VSSA) ΔVSSA -100 0 +100 mV — Input voltage VADIN VREFL — VREFH V — Table continues on the next page... Peripheral operating requirements and behaviors KE02 Sub-Family Data Sheet, Rev. 7, 12/2019

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Table 14. 5 V 12-bit ADC operating conditions (continued)

• f ADCK > 4 MHz
• f ADCK < 4 MHz RAS — kΩ External to MCU 10-bit mode
• f ADCK > 4 MHz
• f ADCK < 4 MHz 8-bit mode (all valid fADCK) — — 10 ADC conversion clock frequency High speed (ADLPC=0) fADCK 0.4 — 8.0 MHz — Low power (ADLPC=1) 0.4 — 4.0 1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. ADC SAR ENGINE SIMPLIFIED CHANNEL SELECT CIRCUIT SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS R AS C AS v ADIN v AS z ADIN R ADIN R ADIN R ADIN R ADIN INPUT PIN INPUT PIN INPUT PIN C ADIN

Figure 16. ADC input impedance equivalency diagram Table 15. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page...

Table 15. 12-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued) Table continues on the next page...

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1. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. This parameter is valid for the temperature range of 25 °C to 50 °C.
2. 1 LSB = (VREFH - VREFL)/2N
3. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
4. IIn = leakage current (refer to DC characteristics)

6.4.2 Analog comparator (ACMP) electricals

Table 16. Comparator electrical specifications

6.5 Communication interfaces

6.5.1 SPI switching specifications

high-drive strength is enabled for SPI output pins. Table 17. SPI master mode timing

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Table 18. SPI slave mode timing (continued) Figure 19. SPI slave mode timing (CPHA = 0)

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Figure 20. SPI slave mode timing (CPHA=1)

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

8.1 Signal multiplexing and pin assignments

for selecting which ALT functionality is available on each pin. Table 19. Pin availability by package pin-count Table continues on the next page...

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Table 19. Pin availability by package pin-count (continued)

1. This is a high-current drive pin when operated as output.

1. VREFH and VDDA are internally connected.
2. VSSA and VSS are internally connected.
3. This is a true open-drain pin when operated as output.

8.2 Device pin assignment

Pins in bold are not available on less pin-count packages. Figure 21. 64-pin QFP/LQFP packages

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1. True open drain pins PTB0 PTB3 PTA7 PTA6 PTD3 PTD2 PTA22 PTA1 PTA0 PTC7 PTC6 PTC5 PTC4 PTA5 PTA4 PTD11 PTD01 VDD VDDA/VREFH VREFL VSSA/VSS PTB7 PTB6 PTB51 PTB41 PTC2 PTC1 PTC0 1 . High source/sink current pins 24 25 PTA32

Figure 24. 32-pin QFN package

9 Revision history

The following table provides a revision history for this document. Table 20. Revision history 3 07/2013 Initial public release.

• Updated the features of OSC, ICS, UART, KBI and ADC in the front page
• Updated I LAT and VCDM in the ESD handling ratings
• Added V IN and removed VDIO, VAIO in the Voltage and current operating ratings
• Updated DC characteristics
• Added the item of ACMP adder to Stop and a note to the Max. in Supply current characteristics
• Added EMC radiated emissions operating behaviors
• Added f Sys and a note to tIHIL in the Control timing
• Added a new section of Thermal operating requirements
• Updated J1, J10 and J11 in the SWD electricals
• Updated External oscillator (OSC) and ICS characteristics
• Added reference potential and a note to the E TUE and EZS in ADC characteristics
• Updated SPI switching specifications 5 07/2016 • Updated the Typical value of E TUE in 12-bit mode and added a note to the 12-bit mode of ETUE and INL in the ADC characteristics. 6 01/2019 • Added a footnote of "Max power suppply ramp rate is 500 V/ms." to Operating voltage in the DC characteristics.
• Added a footnote to the Δfint_ft in the External oscillator (OSC) and ICS characteristics Table continues on the next page...

Revision history

KE02 Sub-Family Data Sheet, Rev. 7, 12/2019

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Table 20. Revision history (continued) KE02 Sub-Family Data Sheet, Rev. 7, 12/2019 NXP Semiconductors 37

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