MK74CG117A

MK74CG117A RENESAS | Alldatasheet

Document overview

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Technical content

Features

• 48-pin SSOP (300 mil) package
• On-chip PLL generates output clocks up to 90 MHz from a simple crystal or clock input
• 16 low-skew outputs
• Output skew less than 350 ps on rising edges
• Ability to configure as – 16 cloc ks at full-frequency – 12 at full and 4 at half-frequency – 8 at full and 8 at half-frequency
• Tri-state mode for Output Enable function
• 3.3 V ±5% supply voltage Block Diagram Clock Synthesis and Mode Select Circuitry S2:0 M1:0 REF GND VDD Crystal Ocsillator X1/ICLK The crystal requires external capacitors for accurate tuning of the clock Crystal or clock input Clock 16 Clock 2 Clock 1

16 OUTPUT LOW SKEW CLOCK GENERATOR CLOCK SYNTHESIZER

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR 2 MK74CG117A REV F 082704 Pin Assignment VDD X1/ICLK CLK16 NC VDD VDD S01 48-pin (300 mil) SSOP CLK15 CLK14 GND NC44 CLK13 CLK12 GND40 VDD CLK11 VDD36 CLK9 VDD NC CLK1032 NC GND GND REF GND GND CLK1 CLK2 VDD VDD CLK3 CLK4 GND GND NC CLK5 CLK6 VDD GND CLK8 CLK7 GND28

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR 3 MK74CG117A REV F 082704 Pin Descriptions External Components The MK74CG117A requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.1µF must be connected between each VDD and GND. Connect the capacitor as close to these pins as possible. For optimum device performance, mount the decoupling capacitor on the component side of the PCB. Avoid the use of vias in the decoupling circuit. PCB Layout Recommendations For optimum device performance and lowest output phase noise, observe the following guidelines: 1) Mount the 0.01µF decoupling capacitor on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to the VDD pin and the PCB trace to the ground via should be kept as short as possible. 2) To minimize EMI, place the 33Ω series-termination resistor (if needed) close to the clock output. 3) An optimum layout is one with all components on the same side of the board, thus minimizing vias through other signal layers. Other signal traces should be routed away from the MK74CG117A device. This includes signal traces located underneath the device, or on layers adjacent to the ground plane layer used by the device. Crystal Information The crystal used should be a fundamental mode (do not use third overtone), parallel resonant crystal. The oscillator has internal caps that provide the proper load for a crystal with C L = 18 pF . The value of these capacitors is given by the following equation: Crystal caps (pF) = (CL - 18) x 2 Pin Number Pin Name Pin Type Pin Description 1, 15, 16, 24, 30, 35, 36, 45, 46 VDD Power Connect to VDD. 2 X1/ICLK XI Connect to a crystal input or clock.

3 X2 XO Connect to a crystal or leave unconnected for clock

input. 4, 5, 21, 29, 44 NC — No connect. Nothing is connected to these pins. 6, 7, 11, 12, 19, 20, 27, 28, 40, 41 GND Power Connect to ground. 8, 10, 48 S2, S1, S0 Input Multiplier select pins. See table 2. 9 REF Output Crystal oscillator buff ered reference clock output. 13, 14, 17, 18 CLK1 - 4 Output Clock 1-4. Can be either full or half-speed per Table 1. 22, 23, 25, 26, 31, 32, 33, 37 CLK5 - 12 Output Clock outputs 5-12. At full (1x) speed unless tri-stated per Table 1. 34, 39 M0, M1 Input Mode Select pins. Selects tri-state or speed of outputs per Table 1. 38, 42, 43, 47 CLK13 - 16 Output Clock 13-16. Can be either full or half-speed per Table

cause non-linear transitions on the output clock waveform. resistor should be used at each output as shown in Figure 1. Table 1. Tri-state and Mode Select Table 2. Multiplier Selections (Input and CLK Figure 1. External Termination allowing output frequencies up to 100 MHz. the output frequency cannot exceed 83.3 MHz.

83.3 MHz

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR 5 MK74CG117A REV F 082704 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK74CG117A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device, at these or any other conditions, above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70°C Item Rating Supply Voltage, VDD (referenced to GND) 7 V All Inputs and Outputs (referenced to GND) 0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 °C Storage Temperature -65 to +150 °C Junction Temperature 125 °C Soldering Temperature 260 °C Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 °C Power Supply Voltage (measured in respect to GND) +3.14 3.47 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.14 3.3 3.47 V Supply Current (at 50 MHz) IDD No load 63 mA Input High Voltage, ICLK V IH pin 2 VDD-1 VDD/2 V Input Low Voltage, ICLK VIL pin 2 VDD/2 1 V Output High Voltage V OH IOH = -8 mA VDD-0.4 V Output High Voltage V OH IOH = -12 mA 2.0 V Output Low Voltage, 3.3 V VOL IOL = 12 mA 0.4 V Short Circuit Current Each output ±35 mA Input Capacitance C IN S0, S1, FRSEL pins 7 pF

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR 6 MK74CG117A REV F 082704 Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C, CL = 15 pF Note 1: Based upon characterization data with a 33 Ω series termination resistor and 15 pF capacitor to ground. Note 2: Between any two outputs with equal loading. Note 3: Additional load may be driven with the addition of an external heat sink. Contact ICS for details. Thermal Characteristics for 48-pin SSOP Parameter Symbol Conditions Min. Typ. Max. Units Input Clock Frequency See table 2 Input Crystal Frequency Except when S2=S1=1 8 20 MHz Output Clock Frequency (see tables 1, 2) M1=M0=1 90 MHz Output Clock Duty Cycle At VDD/2 45 50 55 % Output Clock Rising Edge Skew VDD=3.3 V, Note 2 200 350 ps Absolute Clock Period Jitter, except REF VDD=3.3 V ±300 ps Absolute Clock Period Jitter, REF VDD=3.3 V ±500 ps Output Clock Rise Time t R 0.8 to 2.0 V, Note 1 1.5 2 ns Output Clock Fall Time t F 2.0 V to 0.8 V, Note 1 1.5 2 ns Maximum Load per Total of 16 Outputs, with 33 Ω termination, Note 3

100 MHz output clock 240 pF

83.3 MHz output clock 320 pF

Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 80 °C/W θJA 1 m/s air flow 67 °C/W θJA 3 m/s air flow 54 °C/W Thermal Resistance Junction to Case θJC 45 °C/W

IDT™ / ICS™ 16 OUTPUT LOW SKEW CLOCK GENERATOR 7 MK74CG117A REV F 082704 Package Outline and Package Dimensions (48-pin SSOP, 300 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK74CG117AF MK74CG117A Tubes 48-pin SSOP 0 to +70 ° C MK74CG117AFT MK74CG117A Tape and Reel 48-pin SSOP 0 to +70 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b aaa C c L Millimeters Inches Symbol Min Max Min Max A 2 . 4 12 . 8 0. 0 9 5. 1 1 0 A1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0 . 1 30 . 2 5. 0 0 5. 0 1 0 D 15.75 16.00 .620 .630 E 10.03 10.68 .395 .420 E1 7.40 7.60 .291 .299 e 0.635 BASIC 0.025 BASIC h 0 . 3 80 . 6 4. 0 1 5. 0 2 5 L 0 . 5 01 . 0 2. 0 2 0. 0 4 0 α 0° 8° 0° 8°

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