MK66FN2M0VLQ18

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Technical content

180 MHz ARM® Cortex®-M4F Microcontroller. The K66 sub-family members provide greater performance, memory options up to 2 MB total flash and 256 KB of SRAM, as well as higher peripheral integration with features such as Dual USB and a 10/100 Mbit/s Ethernet MAC. These devices maintain hardware and software compatibility with the existing Kinetis family. This product also offers:

• Integration of a High Speed USB Physical Transceiver
• Greater performance flexibility with a High Speed Run mode
• Smarter peripherals with operation in Stop modes Performance
• Up to 180 MHz ARM Cortex-M4 based core with DSP instructions and Single Precision Floating Point unit System and Clocks
• Multiple low-power modes to provide power optimization based on application requirements
• Memory protection unit with multi-master protection
• 3 to 32 MHz main crystal oscillator
• 32 kHz low power crystal oscillator
• 48 MHz internal reference Security
• Hardware random-number generator
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security Timers
• Four Periodic interrupt timers
• 16-bit low-power timer
• Two 16-bit low-power timer PWM modules
• Two 8-channel motor control/general purpose/PWM timers
• Two 2-ch quad decoder/general purpose timers
• Real-time clock Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output Memories and memory expansion
• Up to 2 MB program flash memory on non- FlexMemory devices with 256 KB RAM
• Up to 1 MB program flash memory and 256 KB of FlexNVM on FlexMemory devices
• 4 KB FlexRAM on FlexMemory devices
• FlexBus external bus interface and SDRAM controller Analog modules
• Two 16-bit SAR ADCs and two 12-bit DAC
• Four analog comparators (CMP) containing a 6-bit DAC and programmable reference input
• Voltage reference 1.2V Communication interfaces
• Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
• USB high-/full-/low-speed On-the-Go with on-chip high speed transceiver
• USB full-/low-speed OTG with on-chip transceiver
• Two CAN, three SPI and four I2C modules
• Low Power Universal Asynchronous Receiver/ Transmitter 0 (LPUART0) and five standard UARTs
• Secure Digital Host Controller (SDHC)
• I2S module Operating Characteristics
• Voltage/Flash write voltage range:1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C MK66FN2M0VMD18 MK66FX1M0VMD18 MK66FN2M0VLQ18 MK66FX1M0VLQ18

144 MAPBGA (MD)

144 LQFP (LQ)

0.5 mm NXP Semiconductors K66P144M180SF5V2 Data Sheet: Technical Data Rev. 4, 04/2017 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

Part Number Memory Maximum number of I\\O's Flash SRAM MK66FN2M0VMD18 2 MB 256 KB 100 MK66FX1M0VMD18 1.25 MB 256 KB 100 MK66FN2M0VLQ18 2 MB 256 KB 100 MK66FX1M0VLQ18 1.25 MB 256 KB 100 1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K66P144M180SF5RMV21 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document. Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. Kinetis_K_0N65N 1 Package drawing Package dimensions are provided in package drawings. • MAPBGA 144-pin : 98ASA00222D1

• LQFP 144-pin: 98ASS23177W1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Figure 1. K66 Block Diagram

3.8.2 USB Voltage Regulator Electrical

3.8.3 USB Full Speed Transceiver and High Speed

3.8.6 DSPI switching specifications (limited voltage

3.8.7 DSPI switching specifications (full voltage

5.2 Recommended connection for unused analog and

8.4 Relationship between ratings and operating

4 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Kinetis K66 Sub-Family, Rev. 4, 04/2017 5 NXP Semiconductors

1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general

2 General

2.1 AC electrical characteristics

Figure 2. Input signal measurement reference

• have C L=30pF loads,
• are slew rate disabled, and
• are normal drive strength 2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.71 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.71 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICDIO Digital1 input pin negative DC injection current (except RTC_WAKEUP pins) — single pin
• V IN < VSS-0.3V -5 — mA IICAIO Analog1 input pin DC injection current — single pin
• V IN < VSS-0.3V (Negative current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pin
• Negative current injection -25 — mA VODPU Pseudo Open drain pullup voltage level VDD VDD V 3 VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V General Kinetis K66 Sub-Family, Rev. 4, 04/2017 7 NXP Semiconductors

1. Digital pins have a general purpose I/O port assigned (e.g. PTA0). Analog pins do not have an associated general
2. All digital and analog I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode

should be an order of magnitude higher to tolerate transient voltages.

1. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤V DD ≤ 2.7 V, IOH = -5mA VDD – 0.5 VDD – 0.5 V V Output high voltage — High drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -20mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -10mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — — 100 mA VOH_RTC_WAKEUP Output high voltage— normal drive pad
• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -2.5 mA VBAT – 0.5 VBAT – 0.5 V V IOH_RTC_WAKEUP Output high current total for RTC_WAKEUP pins — — 100 mA VOL Output low voltage — normal drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 5 mA 0.5 0.5 V V Output low voltage — high drive pad
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 10 mA 0.5 0.5 V V IOLT Output low current total for all ports — — 100 mA VOL_RTC_WAKEUP Output low voltage— normal drive pad
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 2.5mA 0.5 0.5 V V IOL_RTC_WAKEUP Output low current total for RTC_WAKEUPpins — — 100 mA IIN Input leakage current, analog and digital pins
• V SS ≤ VIN ≤ VDD — 0.002 0.5 µA 1 IOZ_RTC_WAKEUP Hi-Z (off-state) leakage current (per RTC_WAKEUP pin) — — 0.25 µA RPU Internal pullup resistors 20 — 50 kΩ 2 RPD Internal pulldown resistors 20 — 50 kΩ 3 1. Measured at VDD=3.6V 2. Measured at VDD supply voltage = VDD min and Vinput = VSS General Kinetis K66 Sub-Family, Rev. 4, 04/2017 9 NXP Semiconductors

1. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

• CPU and system clocks = 100MHz
• Bus clock = 50MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode=FEI

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

• VLLS0 –> RUN — 172 µs
• VLLS1 –> RUN — 172 µs
• VLLS2 –> RUN — 94 µs
• VLLS3 –> RUN — 94 µs
• LLS2 –> RUN — 5.8 µs
• LLS3 –> RUN — 5.8 µs
• VLPS –> RUN — 5.4 µs
• STOP –> RUN — 5.4 µs

Table 6. Low power mode peripheral adders — typical value IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. Table continues on the next page...

Table 6. Low power mode peripheral adders — typical value (continued) 32 kHz internal reference clock (IRC) adder. modes with the crystal enabled. external crystal) power consumption. internal clock and continuous conversions.

2.2.5 Power consumption operating behaviors

Table 7. Power consumption operating behaviors

• @ 1.8V
• @ 3.0V 32.3 32.4 71.03 71.81 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 105°C 50.5 50.6 69.7 89.58 55.95 99.85 mA mA mA 3, 4 IDD_RUNC O Run mode current in compute operation - 120 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from flash
• at 3.0 V — 28.5 67.74 mA IDD_HSRUN Run mode current — all peripheral clocks disabled, code executing from flash
• @ 1.8V
• @ 3.0V 47.2 47.3 91.25 91.62 mA mA IDD_HSRUN Run mode current — all peripheral clocks enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 105°C 71.4 71.5 93.3 103.58 79.13 115.08 mA mA mA 7, 4 IDD_HSRUN CO HSRun mode current in compute operation – 168 MHz core/ 28 MHz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0V — 42.9 91.97 mA 5 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 16.9 45.2 mA 8 Table continues on the next page... General 12 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Table 7. Power consumption operating behaviors (continued)

• at 3.0 V — 986 9.47 μA IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled — 0.690 9.25 mA 12 IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks enabled — 1.5 10.00 mA IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.791 3.8 13.2 2.39 6.91 18.91 mA mA mA IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 202 1400 5100 353.77 2464.54 8949.06 μA μA μA IDD_LLS3 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 9.0 76.3 402 16.5 88.63 656.08 μA μA μA IDD_LLS2 Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 5.7 41.3 229 9.7 55.80 276.81 μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 5.5 46.3 249 7.31 58.33 380.77 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 2.7 13.1 76.6 3.24 18.72 84.77 μA μA μA Table continues on the next page... General Kinetis K66 Sub-Family, Rev. 4, 04/2017 13 NXP Semiconductors

• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.847 6.5 46.7 1.48 11.31 81.78 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.551 6.3 49.6 .65 7.12 53.68 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.254 6.3 48.7 0.445 10.99 85.27 μA μA μA IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.19 0.49 2.2 0.22 0.64 3.2 μA μA μA IDD_VBAT Average current when CPU is not accessing RTC registers
• @ 1.8V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.68 1.2 3.6 0.81 1.45 4.3 0.8 1.56 5.3 0.96 1.89 6.33 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. MCG configured for PEE mode. 6. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 7. 168 MHz core and system clock, 56 MHz bus and FlexBus clock, and 28 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. General 14 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

1. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.
2. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks disabled. Code executing from flash.

1. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks enabled but peripherals are not in active operation. Code executing from flash.

1. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high,
2. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
3. Includes 32kHz oscillator current and RTC operation.

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Figure 3. Run mode supply current vs. core frequency

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 8. EMC radiated emissions operating behaviors

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.

from among the measured orientations in each frequency range.

1. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = MHz, fBUS = MHz
2. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

2.2.7 Designing with radiated emissions in mind

interference from radiated emissions.

1. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 9. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 10. Device clock specifications

• 10 Mbps
• 100 Mbps MHz Table continues on the next page... General Kinetis K66 Sub-Family, Rev. 4, 04/2017 17 NXP Semiconductors

Table 10. Device clock specifications (continued)

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

2.3.2 General switching specifications

CAN, CMT, IEEE 1588 timer, timers, and I2C signals. Table 11. General switching specifications

• Slew enabled ns ns Table continues on the next page... General 18 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Table 11. General switching specifications (continued)

• 1.71 ≤ V DD ≤ 2.7V
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V ns ns Port rise and fall time (low drive strength)
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 12. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

determine TJ is: TJ = TA + RθJA x chip power dissipation.

2.4.2 Thermal attributes

Board type Symbol Description 144 LQFP 144 MAPBGA Unit Notes Single-layer (1s) RθJA Thermal resistance, junction to ambient (natural convection) 45 48 °C/W 1 Four-layer (2s2p) RθJA Thermal resistance, junction to ambient (natural convection) 36 29 °C/W 1 Single-layer (1s) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 36 38 °C/W 1 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 30 25 °C/W 1 — RθJB Thermal resistance, junction to board 24 16 °C/W 2 — RθJC Thermal resistance, junction to case 9 9 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 2 2 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air). General 20 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 13. Debug trace operating behaviors Figure 5. TRACE_CLKOUT specifications Figure 6. Trace data specifications

3.1.2 JTAG electricals

Table 14. JTAG limited voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.0 — ns J7 TCLK low to boundary scan output data valid — 28 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 19 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns

Table 15. JTAG full voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug 12.5 ns ns ns Table continues on the next page... Peripheral operating requirements and behaviors 22 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Figure 9. Test Access Port timing Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG specifications

Table 16. MCG specifications Table continues on the next page...

Table 16. MCG specifications (continued)

• f DCO = 48 MHz
• f DCO = 98 MHz 180 150 ps Table continues on the next page... Peripheral operating requirements and behaviors 26 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

• VCO @ 184 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 23) — 2.8 — mA 8 Ipll PLL operating current
• VCO @ 360 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) — 3.6 — mA 8 Jcyc_pll PLL period jitter (RMS)
• f vco = 180 MHz
• f vco = 360 MHz 100 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
• f vco = 180 MHz
• f vco = 360 MHz 600 300 ps ps Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors Kinetis K66 Sub-Family, Rev. 4, 04/2017 27 NXP Semiconductors

3.3.2 IRC48M specifications

Table 17. IRC48M specifications

• Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1 ± 0.4 ± 0.5 ± 1.0 ± 1.5 %firc48m Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over 0—70°C
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1 ± 0.2 ± 0.5 %firc48m Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over full temperature
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1 ± 0.4 ± 1.0 %firc48m Δfirc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature — — ± 0.1 %fhost 2 Jcyc_irc48m Period Jitter (RMS) — 35 150 ps tirc48mst Startup time — 2 3 μs 3 1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard deviation (mean ± 3 sigma) 2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11

3.3.3 Oscillator electrical specifications

3.3.3.1 Oscillator DC electrical specifications

Table 18. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 600 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 7.5 500 650 2.5 3.25 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low- power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K66 Sub-Family, Rev. 4, 04/2017 29 NXP Semiconductors

Table 18. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.3.3.2 Oscillator frequency specifications

Table 19. Oscillator frequency specifications

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.

1. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

and cannot be moved into high power/gain mode. Table 20. 32kHz oscillator DC electrical specifications

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. Table 21. 32 kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the

applied clock must be within the range of VSS to VBAT.

3.4 Memories and memory interfaces

3.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

3.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 22. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 23. Flash command timing specifications

• 256 KB data flash
• 512 KB program flash 1.0 1.8 ms ms trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs tersblk256k tersblk512k Erase Flash Block execution time
• 256 KB data flash
• 512 KB program flash 220 435 1850 3700 ms ms tersscr Erase Flash Sector execution time — 15 115 ms 2 tpgmsec1k Program Section execution time (1 KB flash) — 5 — ms trd1allx trd1alln Read 1s All Blocks execution time
• FlexNVM devices
• Program flash only devices 5.9 6.7 ms ms trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 1750 14,800 ms 2 Table continues on the next page... Peripheral operating requirements and behaviors 32 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Table 23. Flash command timing specifications (continued)

• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08
• control code 0x10 200 150 150 150 μs μs μs μs μs tpgmpart32k tpgmpart256k Program Partition for EEPROM execution time
• 32 KB EEPROM backup
• 256 KB EEPROM backup ms ms tsetramff tsetram32k tsetram64k tsetram128k tsetram256k Set FlexRAM Function execution time:
• Control Code 0xFF
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 0.8 1.3 2.4 4.5 1.2 1.9 3.1 5.5 μs ms ms ms ms teewr8b32k teewr8b64k teewr8b128k teewr8b256k Byte-write to FlexRAM execution time:
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 385 475 650 1000 1700 2000 2350 3250 μs μs μs μs teewr16b32k teewr16b64k teewr16b128k teewr16b256k 16-bit write to FlexRAM execution time:
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 385 475 650 1000 1700 2000 2350 3250 μs μs μs μs teewr32bers 32-bit write to erased FlexRAM location execution time — 360 1500 μs teewr32b32k teewr32b64k teewr32b128k teewr32b256k 32-bit write to FlexRAM execution time:
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 630 810 1200 1900 2000 2250 2650 3500 μs μs μs μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. Peripheral operating requirements and behaviors Kinetis K66 Sub-Family, Rev. 4, 04/2017 33 NXP Semiconductors

3.4.1.3 Flash high voltage current behaviors

Table 24. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 25. NVM reliability specifications

• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
• EEPROM backup to FlexRAM ratio = 8,192 140 K 1.26 M 5 M 20 M 80 M 400 K 3.2 M 12.8 M 50 M 200 M writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16-bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance. Peripheral operating requirements and behaviors 34 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

3.4.1.5 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFE to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = × Write_efficiency × nEEPROM – 2 × EEESPLIT × EEESIZEEEESPLIT × EEESIZEnvmcycee where

• Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• n nvmcycee — EEPROM-backup cycling endurance Peripheral operating requirements and behaviors Kinetis K66 Sub-Family, Rev. 4, 04/2017 35 NXP Semiconductors

Figure 11. EEPROM backup writes to FlexRAM

3.4.2 EzPort switching specifications

Table 26. EzPort full voltage range switching specifications

Figure 12. EzPort Timing Diagram

3.4.3 Flexbus switching specifications

relationships can be derived from these values. Table 27. Flexbus limited voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],

1. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 28. Flexbus full voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Figure 13. FlexBus read timing diagram

Figure 14. FlexBus write timing diagram

3.4.4 SDRAM controller specifications

Following figure shows SDRAM read cycle.

Figure 15. SDRAM read timing diagram Table 29. SDRAM Timing (Full voltage range)

1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz

1. D7 and D8 are for write cycles only.

Table 30. SDRAM Timing (Limited voltage range)

1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 60 MHz
3. D7 and D8 are for write cycles only.

Following figure shows an SDRAM write cycle.

1 DACR[CASL] = 2

Figure 16. SDRAM write timing diagram

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

the differential pins ADCx_DP0, ADCx_DM0.

Table 31. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• All other modes VREFL VREFL 31/32 * VREFH VREFH V — CADIN Input capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz — — 5 kΩ 3 fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 24 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 — 1200 kS/s 5 Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 — 461.467 kS/s 5 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. Peripheral operating requirements and behaviors 44 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

1. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Figure 17. ADC input impedance equivalency diagram Table 32. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K66 Sub-Family, Rev. 4, 04/2017 45 NXP Semiconductors

Table 32. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA Peripheral operating requirements and behaviors 46 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

3.6.2 CMP and 6-bit DAC electrical specifications

Table 33. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors 48 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 34. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Table 35. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV Peripheral operating requirements and behaviors Kinetis K66 Sub-Family, Rev. 4, 04/2017 51 NXP Semiconductors

1. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

Figure 22. Typical INL error vs. digital code

Figure 23. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 36. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature

Table 37. VREF full-range operating behaviors

• current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms — Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 38. VREF limited-range operating requirements Table 39. VREF limited-range operating behaviors

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

3.8.1 Ethernet switching specifications

appropriately to arrive at timing specs/constraints for the physical interface.

3.8.1.1 MII signal switching specifications

Table 40. MII signal switching specifications (limited voltage range) Table 41. MII signal switching specifications (full voltage range) Table continues on the next page...

3.8.1.2 RMII signal switching specifications

range of transceiver devices. Table 42. RMII signal switching specifications (limited voltage range) Table 43. RMII signal switching specifications (full voltage range)

3.8.1.3 MDIO serial management timing specifications

Table 44. MDIO serial management channel signal timing

Figure 26. MDIO serial management channel timing diagram

3.8.2 USB Voltage Regulator Electrical Specifications

Table 45. USB VREG electrical specifications

• VREG_IN*= 5.0 V and temperature=25 °C — 680 920 nA ILOADrun Maximum load current — Run mode — — 150 mA 3 ILOADstby Maximum load current — Standby mode — — 1 mA VDROPOUT Regulator drop-out voltage — Run mode at maximum load current with inrush current limit disabled 300 — — mV VREG_OUT Regulator programmable output target voltage — Selected input supply > programmed output target voltage + VDROPOUT
• Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V Table continues on the next page... Peripheral operating requirements and behaviors 58 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

1. Typical values assume the selected input supply is 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V.
3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on

USB operation and device power dissipation limits.

1. The target voltage for the regulator is programmable, accounting for the range of the max and min values
2. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator.
3. IINRUSH with VREGINx=4.0 V to 5.5 V
4. The minimum value of IINRUSH is stated for operation when only one of VREG_IN0 / VREG_IN1 is powered, or when

IINRUSH may decrease to a lower value.

1. Total current load on startup should be less than IINRUSH min over full input voltage range of the regulator.

3.8.3 USB Full Speed Transceiver and High Speed PHY

low speed signalling as well. Specification with the amendments below.

• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE Peripheral operating requirements and behaviors Kinetis K66 Sub-Family, Rev. 4, 04/2017 59 NXP Semiconductors

• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
• Revision 2.0 version 1.1a July 27, 2012
• Battery Charging Specification (available from USB-IF)
• Revision 1.2 (including errata and ECNs through March 15, 2012), March 15, 2012 USB1_VBUS pin is a detector function which is 5v tolerant and complies with the above specifications without needing any external voltage division components.

3.8.4 USB DCD electrical specifications

Table 46. USB DCD electrical specifications

3.8.5 CAN switching specifications

See General switching specifications.

3.8.6 DSPI switching specifications (limited voltage range)

formats used for communicating with slower peripheral devices. Table 47. Master mode DSPI timing (limited voltage range)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 27. DSPI classic SPI timing — master mode Table 48. Slave mode DSPI timing (limited voltage range) Table continues on the next page...

Table 48. Slave mode DSPI timing (limited voltage range) (continued)

1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

when bus clock is 60MHz, SPI clock should not be greater than 10MHz. Figure 28. DSPI classic SPI timing — slave mode

3.8.7 DSPI switching specifications (full voltage range)

formats used for communicating with slower peripheral devices. Table 49. Master mode DSPI timing (full voltage range) Table continues on the next page...

Table 49. Master mode DSPI timing (full voltage range) (continued)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 29. DSPI classic SPI timing — master mode Table 50. Slave mode DSPI timing (full voltage range)

Figure 30. DSPI classic SPI timing — slave mode

3.8.8 Inter-Integrated Circuit Interface (I2C) timing

Table 51. I 2C timing Hold time (repeated) START condition.

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

1. Cb = total capacitance of the one bus line in pF.

Table 52. I 2C 1 Mbps timing period, the first clock pulse is generated.

1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins

across the full voltage range.

1. Cb = total capacitance of the one bus line in pF.

Figure 31. Timing definition for devices on the I2C bus

3.8.9 UART switching specifications

See General switching specifications.

3.8.10 Low Power UART switching specifications

See General switching specifications.

3.8.11 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 53. SDHC full voltage range switching specifications Table 54. SDHC limited voltage range switching specifications Table continues on the next page...

Table 54. SDHC limited voltage range switching specifications (continued) Figure 32. SDHC timing

3.8.12 I2S switching specifications

the frame sync (I2S_FS) shown in the figures below. Table 55. I2S master mode timing (limited voltage range) Table continues on the next page...

Table 55. I2S master mode timing (limited voltage range) (continued) Figure 33. I2S timing — master mode Table 56. I2S slave mode timing (limited voltage range)

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 34. I2S timing — slave modes

3.8.12.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 57. I2S/SAI master mode timing

Figure 35. I2S/SAI timing — master modes Table 58. I2S/SAI slave mode timing

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 36. I2S/SAI timing — slave modes

3.8.12.2 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 59. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Figure 37. I2S/SAI timing — master modes Table 60. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 38. I2S/SAI timing — slave modes

3.9 Human-machine interfaces (HMI)

3.9.1 TSI electrical specifications

Table 61. TSI electrical specifications

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 144-pin MAPBGA 98ASA00222D

5 Pinout

5.1 K66 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort — L5 RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC

1 D3 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1TRACE_

I2C1_SDARTC_ CLKOUT

2 D2 PTE1/

LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RXSDHC0_D0TRACE_D3I2C1_SCLSPI1_SIN

3 D1 PTE2/

LLWU_P1 ADC1_SE6aADC1_SE6aPTE2/ LLWU_P1 SPI1_SCKUART1_ CTS_b SDHC0_ DCLK TRACE_D2

4 E4 PTE3 ADC1_SE7aADC1_SE7aPTE3 SPI1_SIN UART1_

RTS_b SDHC0_ CMD TRACE_D1 SPI1_SOUT

5 E5 VDD VDD VDD

6 H3 VSS VSS VSS

7 E3 PTE4/

LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TXSDHC0_D3TRACE_D0

8 E2 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2 FTM3_CH0

9 E1 PTE6/

LLWU_P16 DISABLED PTE6/ LLWU_P16 SPI1_PCS3UART3_ CTS_b I2S0_MCLK FTM3_CH1USB0_SOF_ OUT

10 F4 PTE7 DISABLED PTE7 UART3_

RTS_b I2S0_RXD0 FTM3_CH2 Pinout 74 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

11 F3 PTE8 DISABLED PTE8 I2S0_RXD1 I2S0_RX_FSLPUART0_

FTM3_CH3

12 F2 PTE9/

LLWU_P17 DISABLED PTE9/ LLWU_P17 I2S0_TXD1 I2S0_RX_ BCLK LPUART0_ RX FTM3_CH4

13 F1 PTE10/

LLWU_P18 DISABLED PTE10/ LLWU_P18 I2C3_SDA I2S0_TXD0LPUART0_ CTS_b FTM3_CH5USB1_ID

14 G4 PTE11 DISABLED PTE11 I2C3_SCL I2S0_TX_FSLPUART0_

RTS_b FTM3_CH6

15 G3 PTE12 DISABLED PTE12 I2S0_TX_

FTM3_CH7

16 E6 VDD VDD VDD

17 F7 VSS VSS VSS

18 F6 VSS VSS VSS

19 H1 USB0_DPUSB0_DPUSB0_DP

20 H2 USB0_DMUSB0_DMUSB0_DM

21 G1 VREG_OUTVREG_OUTVREG_OUT

22 G2 VREG_IN0VREG_IN0VREG_IN0

23 J2 VREG_IN1DISABLEDVREG_IN1

24 K2 USB1_VSSDISABLEDUSB1_VSS

25 J1 USB1_DPDISABLEDUSB1_DP

26 K1 USB1_DMDISABLEDUSB1_DM

27 L1 USB1_VBUSDISABLEDUSB1_VBUS

28 L2 ADC0_DM0/

ADC1_DM3 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3

29 M1 ADC1_DP0/

ADC0_DP3 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3

30 M2 ADC1_DM0/

ADC0_DM3 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3

31 H5 VDDA VDDA VDDA

32 G5 VREFH VREFH VREFH

33 G6 VREFL VREFL VREFL

34 H6 VSSA VSSA VSSA

35 K3 ADC1_SE16/

CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22

36 J3 ADC0_SE16/

CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21

37 M3 VREF_OUT/

CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 Pinout Kinetis K66 Sub-Family, Rev. 4, 04/2017 75 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

38 L3 DAC0_OUT/

CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23

39 L4 DAC1_OUT/

CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23

40 M7 XTAL32 XTAL32 XTAL32

41 M6 EXTAL32 EXTAL32 EXTAL32

42 L6 VBAT VBAT VBAT

43 — VDD VDD VDD 44 — VSS VSS VSS

45 M4 PTE24 ADC0_SE17ADC0_SE17PTE24 CAN1_TXUART4_TX I2C0_SCLEWM_OUT_

b

46 K5 PTE25/

LLWU_P21 ADC0_SE18ADC0_SE18PTE25/ LLWU_P21 CAN1_RXUART4_RX I2C0_SDAEWM_IN

47 K4 PTE26 DISABLED PTE26 ENET_1588_

UART4_ CTS_b RTC_ CLKOUT USB0_CLKIN

48 J4 PTE27 DISABLED PTE27 UART4_

RTS_b

49 H4 PTE28 DISABLED PTE28

50 J5 PTA0 JTAG_TCLK/

SWD_CLK/ EZP_CLK TSI0_CH1PTA0 UART0_ CTS_b/ UART0_ COL_b FTM0_CH5 LPUART0_ CTS_b JTAG_TCLK/ SWD_CLK EZP_CLK

51 J6 PTA1 JTAG_TDI/

EZP_DI TSI0_CH2PTA1 UART0_RXFTM0_CH6I2C3_SDALPUART0_ RX JTAG_TDIEZP_DI

52 K6 PTA2 JTAG_TDO/

TRACE_ SWO/ EZP_DO TSI0_CH3PTA2 UART0_TXFTM0_CH7I2C3_SCLLPUART0_ TX JTAG_TDO/ TRACE_ SWO EZP_DO

53 K7 PTA3 JTAG_TMS/

SWD_DIO TSI0_CH4PTA3 UART0_ RTS_b FTM0_CH0 LPUART0_ RTS_b JTAG_TMS/ SWD_DIO

54 L7 PTA4/

LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b

55 M8 PTA5 DISABLED PTA5 USB0_CLKINFTM0_CH2RMII0_

MII0_RXER CMP2_OUTI2S0_TX_ BCLK JTAG_ TRST_b

56 E7 VDD VDD VDD

57 G7 VSS VSS VSS

58 J7 PTA6 DISABLED PTA6 FTM0_CH3 CLKOUT TRACE_

59 J8 PTA7 ADC0_SE10ADC0_SE10PTA7 FTM0_CH4 RMII0_MDIO/

MII0_MDIO TRACE_D3 Pinout 76 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

60 K8 PTA8 ADC0_SE11ADC0_SE11PTA8 FTM1_CH0 RMII0_MDC/

MII0_MDC FTM1_QD_ PHA/ TPM1_CH0 TRACE_D2

61 L8 PTA9 DISABLED PTA9 FTM1_CH1MII0_RXD3 FTM1_QD_

TPM1_CH1 TRACE_D1

62 M9 PTA10/

LLWU_P22 DISABLED PTA10/ LLWU_P22 FTM2_CH0MII0_RXD2 FTM2_QD_ PHA/ TPM2_CH0 TRACE_D0

63 L9 PTA11/

LLWU_P23 DISABLED PTA11/ LLWU_P23 FTM2_CH1MII0_RXCLKI2C2_SDAFTM2_QD_ PHB/ TPM2_CH1

64 K9 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TXFTM1_CH0RMII0_

MII0_RXD1 I2C2_SCLI2S0_TXD0FTM1_QD_ PHA/ TPM1_CH0

65 J9 PTA13/

LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RXFTM1_CH1RMII0_ RXD0/ MII0_RXD0 I2C2_SDAI2S0_TX_FSFTM1_QD_ PHB/ TPM1_CH1

66 L10 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TXRMII0_CRS_

MII0_RXDV I2C2_SCLI2S0_RX_ BCLK I2S0_TXD1

67 L11 PTA15 CMP3_IN1CMP3_IN1PTA15 SPI0_SCKUART0_RXRMII0_

MII0_TXEN I2S0_RXD0

68 K10 PTA16 CMP3_IN2CMP3_IN2PTA16 SPI0_SOUTUART0_

CTS_b/ UART0_ COL_b RMII0_TXD0/ MII0_TXD0 I2S0_RX_FSI2S0_RXD1

69 K11 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_

RTS_b RMII0_TXD1/ MII0_TXD1 I2S0_MCLK

70 E8 VDD VDD VDD

71 G8 VSS VSS VSS

72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 TPM_

73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_

TPM_ CLKIN1

74 L12 RESET_bRESET_bRESET_b

75 K12 PTA24 CMP3_IN4CMP3_IN4PTA24 MII0_TXD2 FB_A29

76 J12 PTA25 CMP3_IN5CMP3_IN5PTA25 MII0_TXCLK FB_A28

77 J11 PTA26 DISABLED PTA26 MII0_TXD3 FB_A27

78 J10 PTA27 DISABLED PTA27 MII0_CRS FB_A26

79 H12 PTA28 DISABLED PTA28 MII0_TXER FB_A25

80 H11 PTA29 DISABLED PTA29 MII0_COL FB_A24

81 H10 PTB0/

LLWU_P5 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCLFTM1_CH0RMII0_MDIO/ MII0_MDIO SDRAM_ CAS_b FTM1_QD_ PHA/ TPM1_CH0 Pinout Kinetis K66 Sub-Family, Rev. 4, 04/2017 77 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

82 H9 PTB1 ADC0_SE9/

ADC1_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDAFTM1_CH1RMII0_MDC/ MII0_MDC SDRAM_ RAS_b FTM1_QD_ PHB/ TPM1_CH1

83 G12 PTB2 ADC0_SE12/

TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCLUART0_ RTS_b ENET0_ 1588_TMR0 SDRAM_WEFTM0_FLT3

84 G11 PTB3 ADC0_SE13/

TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDAUART0_ CTS_b/ UART0_ COL_b ENET0_ 1588_TMR1 SDRAM_ CS0_b FTM0_FLT0

85 G10 PTB4 ADC1_SE10ADC1_SE10PTB4 ENET0_

1588_TMR2 SDRAM_ CS1_b FTM1_FLT0

86 G9 PTB5 ADC1_SE11ADC1_SE11PTB5 ENET0_

1588_TMR3 FTM2_FLT0

87 F12 PTB6 ADC1_SE12ADC1_SE12PTB6 FB_AD23/

SDRAM_D23

88 F11 PTB7 ADC1_SE13ADC1_SE13PTB7 FB_AD22/

SDRAM_D22

89 F10 PTB8 DISABLED PTB8 UART3_

RTS_b FB_AD21/ SDRAM_D21

90 F9 PTB9 DISABLED PTB9 SPI1_PCS1UART3_

CTS_b FB_AD20/ SDRAM_D20

91 E12 PTB10 ADC1_SE14ADC1_SE14PTB10 SPI1_PCS0UART3_RX FB_AD19/

SDRAM_D19 FTM0_FLT1

92 E11 PTB11 ADC1_SE15ADC1_SE15PTB11 SPI1_SCKUART3_TX FB_AD18/

SDRAM_D18 FTM0_FLT2

93 H7 VSS VSS VSS

94 F5 VDD VDD VDD

95 E10 PTB16 TSI0_CH9TSI0_CH9PTB16 SPI1_SOUTUART0_RXFTM_CLKIN0FB_AD17/

SDRAM_D17 EWM_IN TPM_ CLKIN0

96 E9 PTB17 TSI0_CH10TSI0_CH10PTB17 SPI1_SIN UART0_TXFTM_CLKIN1FB_AD16/

SDRAM_D16 EWM_OUT_ b TPM_ CLKIN1

97 D12 PTB18 TSI0_CH11TSI0_CH11PTB18 CAN0_TXFTM2_CH0I2S0_TX_

FB_AD15/ SDRAM_A23 FTM2_QD_ PHA/ TPM2_CH0

98 D11 PTB19 TSI0_CH12TSI0_CH12PTB19 CAN0_RXFTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_

TPM2_CH1

99 D10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31/

SDRAM_D31 CMP0_OUT

100 D9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30/

SDRAM_D30 CMP1_OUT

101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29/

SDRAM_D29 CMP2_OUT

102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28/

SDRAM_D28 CMP3_OUT Pinout 78 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

103 B12 PTC0 ADC0_SE14/

TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_ EXTRG USB0_SOF_ OUT FB_AD14/ SDRAM_A22 I2S0_TXD1

104 B11 PTC1/

LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_ RTS_b FTM0_CH0FB_AD13/ SDRAM_A21 I2S0_TXD0

105 A12 PTC2 ADC0_SE4b/

CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_ CTS_b FTM0_CH1FB_AD12/ SDRAM_A20 I2S0_TX_FS

106 A11 PTC3/

LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK

107 H8 VSS VSS VSS

108 — VDD VDD VDD

109 A9 PTC4/

LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11/ SDRAM_A19 CMP1_OUT

110 D8 PTC5/

LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0FB_AD10/ SDRAM_A18 CMP0_OUTFTM0_CH2

111 C8 PTC6/

LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_ EXTRG I2S0_RX_ BCLK FB_AD9/ SDRAM_A17 I2S0_MCLK

112 B8 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB0_SOF_

I2S0_RX_FSFB_AD8/ SDRAM_A16

113 A8 PTC8 ADC1_SE4b/

CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4I2S0_MCLKFB_AD7/ SDRAM_A15

114 D7 PTC9 ADC1_SE5b/

CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5I2S0_RX_ BCLK FB_AD6/ SDRAM_A14 FTM2_FLT0

115 C7 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCLFTM3_CH6I2S0_RX_FSFB_AD5/

SDRAM_A13

116 B7 PTC11/

LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDAFTM3_CH7I2S0_RXD1FB_RW_b

117 A7 PTC12 DISABLED PTC12 UART4_

RTS_b FTM_CLKIN0FB_AD27/ SDRAM_D27 FTM3_FLT0TPM_ CLKIN0

118 D6 PTC13 DISABLED PTC13 UART4_

CTS_b FTM_CLKIN1FB_AD26/ SDRAM_D26 TPM_ CLKIN1

119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25/

SDRAM_D25

120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24/

SDRAM_D24 121 — VSS VSS VSS 122 — VDD VDD VDD

123 A6 PTC16 DISABLED PTC16 CAN1_RXUART3_RXENET0_

1588_TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_ 16_BLS15_ 8_b/ SDRAM_ DQM2

124 D5 PTC17 DISABLED PTC17 CAN1_TXUART3_TXENET0_

1588_TMR1 FB_CS4_b/ FB_TSIZ0/ Pinout Kinetis K66 Sub-Family, Rev. 4, 04/2017 79 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort FB_BE31_ 24_BLS7_0_ SDRAM_ DQM3

125 C5 PTC18 DISABLED PTC18 UART3_

RTS_b ENET0_ 1588_TMR2 FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ BLS23_16_b/ SDRAM_ DQM1

126 B5 PTC19 DISABLED PTC19 UART3_

CTS_b ENET0_ 1588_TMR3 FB_CS3_b/ FB_BE7_0_ BLS31_24_b/ SDRAM_ DQM0 FB_TA_b

127 A5 PTD0/

LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_ RTS_b FTM3_CH0FB_ALE/ FB_CS1_b/ FB_TS_b

128 D4 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_

CTS_b FTM3_CH1FB_CS0_b

129 C4 PTD2/

LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RXFTM3_CH2FB_AD4/ SDRAM_A12 I2C0_SCL

130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TXFTM3_CH3FB_AD3/

SDRAM_A11 I2C0_SDA

131 A4 PTD4/

LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_ RTS_b FTM0_CH4FB_AD2/ SDRAM_A10 EWM_IN SPI1_PCS0

132 A3 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_

CTS_b/ UART0_ COL_b FTM0_CH5FB_AD1/ SDRAM_A9 EWM_OUT_ b SPI1_SCK

133 A2 PTD6/

LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0SPI1_SOUT

134 M10 VSS VSS VSS

135 F8 VDD VDD VDD

136 A1 PTD7 DISABLED PTD7 CMT_IROUART0_TXFTM0_CH7SDRAM_

FTM0_FLT1SPI1_SIN

137 C9 PTD8/

LLWU_P24 DISABLED PTD8/ LLWU_P24 I2C0_SCL LPUART0_ RX FB_A16

138 B9 PTD9 DISABLED PTD9 I2C0_SDA LPUART0_

FB_A17

139 B3 PTD10 DISABLED PTD10 LPUART0_

RTS_b FB_A18

140 B2 PTD11/

LLWU_P25 DISABLED PTD11/ LLWU_P25 SPI2_PCS0 SDHC0_ CLKIN LPUART0_ CTS_b FB_A19

141 B1 PTD12 DISABLED PTD12 SPI2_SCKFTM3_FLT0SDHC0_D4 FB_A20

142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21

80 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22

144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23

5.2 Recommended connection for unused analog and digital

Table 62. Recommended connection for unused analog interfaces Table continues on the next page...

Table 62. Recommended connection for unused analog interfaces (continued)

5.3 K66 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. used on which pin, see the previous section.

108 VDD

116 PTC11/LLWU_P11

124 PTC17

132 PTD5

140 PTD11/LLWU_P25

Figure 39. K66 144 LQFP Pinout Diagram

Figure 40. K66 144 MAPBGA Pinout Diagram

6 Ordering parts

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: PK66 and MK66

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format: Q K## A M FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification K## Kinetis family • K65
• K66 A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory FFF Program flash memory size • 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 768 = 768 KB Table continues on the next page... Part identification Kinetis K66 Sub-Family, Rev. 4, 04/2017 85 NXP Semiconductors

• 1M0 = 1 MB
• 2M0 = 2 MB R Silicon revision • Z = Initial
• (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MI= 169 MAPBGA (9 mm x 9 mm)
• AC= 169 WLCSP (5.6 mm x 5.5 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 16 = 168 MHz
• 18 = 180 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

7.4 Example

This is an example part number: MK66FN2M0VMD18

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table: Terminology and guidelines 86 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

8.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE Terminology and guidelines Kinetis K66 Sub-Family, Rev. 4, 04/2017 87 NXP Semiconductors

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V

8.4 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. Terminology and guidelines 88 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

9 Revision History

The following table provides a revision history for this document. Table 63. Revision History

• Updated OTG/EH and BC rev. 1.2 specification references in USB Full Speed Transceiver and High Speed PHY specifications section
• Updated USBDCD electrical specifications table
• Updated the typical values and maximum values of specs in Power consumption operating behaviors table
• Removed PSTOP2 current from Power consumption operating behaviors table
• Updated the values of DS5 and DS7 in Master mode DSPI timing (full voltage range) table
• Updated the footnote and description of V DIO, VAIO and ID in Voltage and current operating ratings table
• Updated the values and description of specs in Voltage and current operating requirements table
• Updated the leakage current specs in Voltage and current operating behaviors table
• Added Notes column in Thermal operating requirements
• Updated the values of 48MHz IRC in Low power mode peripheral adders table
• Added new footnotes for I INRUSH in USB VREG electrical specifications table to better document operation.
• Updated the figures "SDRAM write timing diagram" and SDRAM read timing diagram" in the section "SDRAM controller specifications."
• Updated the pinout table, and pinout diagrams in the section "Pinouts." 2 05/2015 • Added new footnotes for I INRUSH in USB VREG electrical specifications table to better document operation.
• Updated the figures "SDRAM write timing diagram" and SDRAM read timing diagram" in the section "SDRAM controller specifications."
• Updated the pinout table, and pinout diagrams in the section "Pinouts." 3 01/2016 • Updated the symbol in footnote of Thermal Operating specs
• Updated the description of PLL operating current in MCG specifications table
• Updated the values of IRC48M specifications table
• Added USB FS and USB HS logo in front page
• Updated Terminology and guidelines section
• Updated the maximum values of I DD_LLS2 and IDD_LLS3 in Power consumption operating behaviors table 4 03/2017 • Removed the verbiage of "except RTC_WAKEUP pins" from the description for R PU and RPD in Voltage and current operating behaviors table
• Updated the unit of ADC conversion rate from "Kbps" to "kS/s" in 16-bit ADC operating conditions table
• Added MII signal switching specifications table and RMII signal switching specifications table for full voltage range
• Added MDIO serial management timing specifications section
• Updated I2C switching specifications section
• Updated the minimum and maximum value of Voltage reference output with factory trim in VREF full-range operating requirements table in Voltage reference electrical specifications section

Revision History

Kinetis K66 Sub-Family, Rev. 4, 04/2017 89 NXP Semiconductors

90 Kinetis K66 Sub-Family, Rev. 4, 04/2017 NXP Semiconductors

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