DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 76

Technical content

Kinetis K64 Sub-Family Data Sheet With 1 MB Flash

120 MHz ARM® Cortex®-M4-based Microcontroller with FPU

The K64 product family features high memory densities, low power capabilities, optimized integration, in an ultra-small package. It shares the comprehensive enablement and scalability of the Kinetis family. This product offers:

  • Up to 1 MB flash, with 256 KB of embedded SRAM 10/100 Mbit/s Ethernet MAC with MII and RMII interfaces
  • Run power consumption down to 250 μA/MHz. Static power consumption down to 5.8 μA with full state retention and 5 μs wakeup. Lowest Static mode down to 339 nA
  • USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO voltage regulator with USB device crystal-less operation Performance
  • Up to 120 MHz ARM® Cortex®-M4 core with DSP instructions and Floating Point Unit delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces Up to 1 MB program flash memory and 256 KB RAM
  • FlexBus external bus interface System peripherals
  • Multiple low-power modes, low-leakage wakeup unit
  • Memory protection unit with multi-master protection
  • 16-channel DMA controller
  • External watchdog monitor and software watchdog Clocks
  • 3 to 32 MHz and 32 kHz crystal oscillator
  • Multi-purpose clock generator
  • 1 kHz, 32 kHz, and 4 MHz internal reference clock
  • 48 MHz internal reference Security and integrity modules
  • Hardware CRC module
  • Hardware random-number generator
  • Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms
  • 128-bit unique identification (ID) number per chip Communication interfaces
  • Ethernet controller with MII and RMII interface USB full-/low-speed On-the-Go controller
  • Controller Area Network (CAN) module
  • Three SPI modules
  • Three I2C modules
  • Six UART modules
  • Secure Digital Host Controller (SDHC)
  • I2S module Timers
  • Programmable delay block
  • Two 8-channel FlexTimers (PWM/Motor Control)
  • Two 2-channel FlexTimer (Quad Decoder/PWM)
  • IEEE 1588 timers
  • PIT and 16-bit low-power timer
  • Carrier modulator transmitter
  • Real-time clock Analog modules
  • Two 16-bit SAR ADCs
  • Two 12-bit DACs
  • Three analog comparators (CMP)
  • Voltage reference Operating Characteristics
  • Voltage range: 1.71 to 3.6 V
  • Flash write voltage range: 1.71 to 3.6 V
  • Temperature range (ambient): –40 to 85°C MK64FN1M0CAJ12R

142 WLCSP

4.84 x 5.58 x 0.60 mm Pitch 0.4 mm NXP Semiconductors K64P142M120SF5 Data Sheet: Technical Data Rev. 7, 10/2016 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

Part Number Memory Maximum number of I\\O's Flash SRAM (KB) MK64FN1M0CAJ12R 1 MB 256 100 1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. K60PB1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K64P144M120SF5RM 1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document Package drawing Package dimensions are provided in package drawings. • WLCSP 142-pin: 98ASA00639D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

Figure 1. K64 block diagram

3.8.6 DSPI switching specifications (limited voltage

3.8.7 DSPI switching specifications (full voltage

8.4 Relationship between ratings and operating

4 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 1 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 5 NXP Semiconductors

  1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Figure 2. Input signal measurement reference

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

  • 2.7 V ≤ V DD ≤ 3.6 V
  • 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
  • 2.7 V ≤ V DD ≤ 3.6 V
  • 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICDIO Digital pin negative DC injection current — single pin
  • V IN < VSS-0.3V -5 — mA IICAIO Analog2, EXTAL, and XTAL pin DC injection current — single pin
  • V IN < VSS-0.3V (Negative current injection)
  • V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
  • Negative current injection
  • Positive current injection -25 +25 mA VODPU Open drain pullup voltage level VDD VDD V 4 VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN- VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. General Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 7 NXP Semiconductors

2.2.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements

  • Level 1 falling (LVWV=00)
  • Level 2 falling (LVWV=01)
  • Level 3 falling (LVWV=10)
  • Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
  • Level 1 falling (LVWV=00)
  • Level 2 falling (LVWV=01)
  • Level 3 falling (LVWV=10)
  • Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors Table continues on the next page...

Table 4. Voltage and current operating behaviors (continued)

  • 2.7 V ≤ V DD ≤ 3.6 V, IOH = -8mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
  • 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOH_RTC_WA KEUP Output high voltage — high drive strength
  • 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -10mA
  • 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -3mA VBAT – 0.5 VBAT – 0.5 V V Output high voltage — low drive strength
  • 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -2mA
  • 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -0.6mA VBAT – 0.5 VBAT – 0.5 V V IOH_RTC_WAK EUP Output high current total for RTC_WAKEUP pins — 100 mA VOL Output low voltage — high drive strength
  • 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
  • 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
  • 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA VOL_RTC_WA KEUP Output low voltage — high drive strength
  • 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 10mA
  • 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
  • 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 2mA
  • 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOL_RTC_WAK EUP Output low current total for RTC_WAKEUP pins — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 1 IIN Input leakage current (per pin) at 25°C — 0.025 μA 1 IIN_RTC_WAK EUP Input leakage current (per RTC_WAKEUP pin) for full temperature range — 1 μA IIN_RTC_WAK EUP Input leakage current (per RTC_WAKEUP pin) at 25°C — 0.025 μA Table continues on the next page... General Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 9 NXP Semiconductors
  1. Measured at VDD supply voltage = VDD min and Vinput = VSS
  2. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

  • CPU and system clocks = 100 MHz
  • Bus clock = 50 MHz
  • FlexBus clock = 50 MHz
  • Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

  • VLLS0 → RUN — 156 μs
  • VLLS1 → RUN — 156 μs
  • VLLS2 → RUN — 78 μs
  • VLLS3 → RUN — 78 μs
  • LLS → RUN — 4.8 μs
  • VLPS → RUN — 4.5 μs
  • STOP → RUN — 4.5 μs General 10 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

2.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

  • @ 1.8V
  • @ 3.0V 31.1 35.3 35.3 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
  • @ 1.8V
  • @ 3.0V
  • @ 25°C
  • @ 85°C 42.7 41.6 46.95 41.6 44.1 mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 17.9 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 6.9 — mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1 — mA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.7 — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled — 0.678 — mA 8 IDD_STOP Stop mode current at 3.0 V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 0.49 1.18 1.76 1.24 4.3 7.7 mA mA mA IDD_VLPS Very-low-power stop mode current at 3.0 V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 291 494.5 139.31 679.33 850.6 μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V 9 Table continues on the next page... General Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 11 NXP Semiconductors

Table 6. Power consumption operating behaviors (continued)

  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 5.8 26.7 50.2 10.48 47.99 88.55 μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 4.4 39.5 5.54 36.46 67.45 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 2.1 6.84 12.6 2.34 10.36 19.0 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 0.817 3.97 8.23 0.86 5.77 12.47 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 0.520 3.67 7.94 0.62 5.7 11.7 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 0.339 3.36 7.55 0.412 4.2 9.96 μA μA μA IDD_VBAT Average current with RTC and 32kHz disabled
  • @ 1.8V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C
  • @ 3.0V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 0.16 0.55 1.28 0.18 0.66 1.52 0.19 0.72 1.88 0.21 0.86 2.24 μA μA μA μA μA μA Table continues on the next page... General 12 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors
  • @ 1.8V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C
  • @ 3.0V
  • @ –40 to 25°C
  • @ 70°C
  • @ 85°C 0.59 1.0 1.76 0.71 1.22 2.08 0.70 1.30 2.59 0.84 1.59 3.06 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120 MHz core and system clock, 60 MHz bus, 40 Mhz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 120 MHz core and system clock, 60 MHz bus clock, 40 MHz Flexbus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 256 KB of RAM. 10. Includes 32kHz oscillator current and RTC operation.

Table 7. Low power mode peripheral adders — typical value VLPS mode with 4 MHz IRC enabled. with the 32 kHz IRC enabled. IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled. all modes with the crystal enabled. Table continues on the next page...

Table 7. Low power mode peripheral adders — typical value (continued) 6-bit DAC power consumption. selected clock source power consumption.

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

  • No GPIOs toggled General 14 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors
  • Code execution from flash with cache enabled
  • For the ALLOFF curve, all peripheral clocks are disabled except FTFE Temp (C)=25, VDD=3.6V, CACHE=ENABLE, Code Residence=Flash Run Mode Current Consumption vs Core Frequency All Peripheral Clk Gates ALLOFF ALLON Clk Ratio Core-Bus- Flaxbus-Flash Core Freq (MHz) Current Consumption on VDD (A) 40.00E-03 000.00E+00 10.00E-03 15.00E-03 20.00E-03 25.00E-03 30.00E-03 35.00E-03 5.00E-03 '1-1-1 '1-1-1 '1-1-1 '1-1-1 6.25 '1-1-1 12.5 '1-1-1 '1-2-3 '1-1-2 '1-2-4 100 '1-2-5 120

Figure 3. Run mode supply current vs. core frequency

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 8. EMC radiated emissions operating behaviors

144 LQFP

  1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. from among the measured orientations in each frequency range.

  1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

2.2.7 Designing with radiated emissions in mind

  1. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 9. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 10. Device clock specifications

  • 10 Mbps
  • 100 Mbps MHz fBUS Bus clock — 60 MHz FB_CLK FlexBus clock — 50 MHz fFLASH Flash clock — 25 MHz Table continues on the next page... General Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 17 NXP Semiconductors

Table 10. Device clock specifications (continued)

  1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

2.3.2 General switching specifications

CAN, CMT, IEEE 1588 timer, timers, and I2C signals. Table 11. General switching specifications

  • Slew disabled
  • 1.71 ≤ V DD ≤ 2.7V
  • Slew enabled ns ns ns Table continues on the next page... General 18 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

Table 11. General switching specifications (continued)

  • 1.71 ≤ V DD ≤ 2.7V — 12 ns Port rise and fall time (high drive strength) - 5 V
  • Slew disabled
  • 1.71 ≤ V DD ≤ 2.7V
  • Slew enabled
  • 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength) - 3 V
  • Slew disabled
  • 1.71 ≤ V DD ≤ 2.7V
  • Slew enabled
  • 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength) - 5 V
  • Slew disabled
  • 1.71 ≤ V DD ≤ 2.7V
  • Slew enabled
  • 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 25 pF load 5. 15 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 12. Thermal operating requirements

  1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

2.4.2 Thermal attributes

  1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
  2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.

  1. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental

Conditions—Forced Convection (Moving Air) with the board horizontal.

  1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

  1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

the top of the package and the cold plate.

  1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 14. Debug trace operating behaviors Figure 5. TRACE_CLKOUT specifications Figure 6. Trace data specifications

3.1.2 JTAG electricals

Table 15. JTAG limited voltage range electricals

  • Boundary Scan
  • JTAG and CJTAG
  • Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
  • Boundary Scan
  • JTAG and CJTAG
  • Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.6 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns

Table 16. JTAG full voltage range electricals

  • Boundary Scan
  • JTAG and CJTAG
  • Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
  • Boundary Scan
  • JTAG and CJTAG
  • Serial Wire Debug 12.5 ns ns ns Table continues on the next page... Peripheral operating requirements and behaviors 22 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

Figure 9. Test Access Port timing Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG specifications

Table 17. MCG specifications Table continues on the next page...

Table 17. MCG specifications (continued)

  • f DCO = 48 MHz
  • f DCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fvco VCO operating frequency 48.0 — 120 MHz Ipll PLL operating current
  • PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) — 1060 — µA 8 Ipll PLL operating current
  • PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) — 600 — µA 8 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter (RMS)
  • f vco = 48 MHz
  • f vco = 120 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
  • f vco = 48 MHz
  • f vco = 120 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors 26 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

3.3.2 IRC48M specifications

Table 18. IRC48M specifications

  • Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
  • Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 0.5 ± 1.5 ± 2.0 %firc48m Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over full temperature
  • Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 1.5 %firc48m Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over 0 to 85 °C
  • Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 1.0 %firc48m Δfirc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature — — ± 0.1 %fhost 2 Jcyc_irc48m Period Jitter (RMS) — 35 150 ps tirc48mst Startup time — 2 3 μs 3 1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard deviation (mean ± 3 sigma) 2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by setting USB_CLK_RECOVER_IRC_EN[IRC_EN]=1.

3.3.3 Oscillator electrical specifications

3.3.3.1 Oscillator DC electrical specifications

Table 19. Oscillator DC electrical specifications

  • 32 kHz
  • 4 MHz
  • 8 MHz (RANGE=01)
  • 16 MHz
  • 24 MHz
  • 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high-gain mode (HGO=1)
  • 32 kHz
  • 4 MHz
  • 8 MHz (RANGE=01)
  • 16 MHz
  • 24 MHz
  • 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Table continues on the next page... Peripheral operating requirements and behaviors 28 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

Table 19. Oscillator DC electrical specifications (continued)

  1. VDD=3.3 V, Temperature =25 °C
  2. See crystal or resonator manufacturer's recommendation
  3. Cx and Cy can be provided by using either integrated capacitors or external components.
  4. When low-power mode is selected, RF is integrated and must not be attached externally.
  5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.3.3.2 Oscillator frequency specifications

Table 20. Oscillator frequency specifications

  1. Other frequency limits may apply when external clock is being used as a reference for the FLL
  2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

  1. Proper PC board layout procedures must be followed to achieve specifications.
  1. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

and cannot be moved into high power/gain mode. Table 21. 32kHz oscillator DC electrical specifications

  1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. Table 22. 32 kHz oscillator frequency specifications

  1. Proper PC board layout procedures must be followed to achieve specifications.
  2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

  1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied

clock must be within the range of VSS to VBAT.

3.4 Memories and memory interfaces

3.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

3.4.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 23. NVM program/erase timing specifications

  1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 24. Flash command timing specifications

  • 512 KB program flash 1.8 ms trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs tersblk512k Erase Flash Block execution time
  • 512 KB program flash 435 3700 ms tersscr Erase Flash Sector execution time — 15 115 ms 2 tpgmsec1k Program Section execution time (1KB flash) — 5 — ms trd1alln Read 1s All Blocks execution time
  • Program flash only devices 3.4 ms trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 70 — μs tersall Erase All Blocks execution time — 870 7400 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tswapx01 tswapx02 Swap Control execution time
  • control code 0x01 200 150 μs μs Peripheral operating requirements and behaviors Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 31 NXP Semiconductors
  • control code 0x02
  • control code 0x04
  • control code 0x08 150 μs μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3.4.1.3 Flash high voltage current behaviors

Table 25. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 26. NVM reliability specifications

  1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
  2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.

3.4.2 EzPort switching specifications

Table 27. EzPort switching specifications Table continues on the next page...

Table 27. EzPort switching specifications (continued) Figure 11. EzPort Timing Diagram

3.4.3 Flexbus switching specifications

be derived from these values. Table 28. Flexbus limited voltage range switching specifications

  1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
  2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 29. Flexbus full voltage range switching specifications

  1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
  2. Specification is valid for all FB_AD[31:0] and FB_TA.

Figure 12. FlexBus read timing diagram

Figure 13. FlexBus write timing diagram

3.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

3.6 Analog

3.6.1 ADC electrical specifications

the differential pins ADCx_DP0, ADCx_DM0. Table 30. 16-bit ADC operating conditions

1.13 VDDA VDDA V

  • All other modes VREFL VREFL 31/32 × VREFH VREFH V CADIN Input capacitance
  • 16-bit mode
  • 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging 37.037 461.467 ksps Peripheral operating requirements and behaviors Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 37 NXP Semiconductors
  1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

  1. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

RAS/CAS time constant should be kept to < 1 ns.

  1. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
  2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Figure 14. ADC input impedance equivalency diagram Table 31. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page...

Table 31. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

  • ADLPC = 1, ADHSC = 0
  • ADLPC = 1, ADHSC = 1
  • ADLPC = 0, ADHSC = 0
  • ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
  • 12-bit modes
  • <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
  • 12-bit modes
  • <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes
  • <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
  • <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
  • ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
  • Avg = 32
  • Avg = 4 16-bit single-ended mode
  • Avg = 32
  • Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
  • Avg = 32 16-bit single-ended mode
  • Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
  • Avg = 32 16-bit single-ended mode dB dB Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 39 NXP Semiconductors
  • Avg = 32 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input ENOB ADC Clock Frequency (MHz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 12 11 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples

Figure 15. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Figure 16. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

3.6.2 CMP and 6-bit DAC electrical specifications

Table 32. Comparator and 6-bit DAC electrical specifications

  • CR0[HYSTCTR] = 00
  • CR0[HYSTCTR] = 01
  • CR0[HYSTCTR] = 10
  • CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB Peripheral operating requirements and behaviors Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 41 NXP Semiconductors
  1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
  2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. Figure 17. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 33. 12-bit DAC operating requirements

  1. The DAC reference can be selected to be VDDA or VREFH.
  2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Table 34. 12-bit DAC operating behaviors

  • High power (SP HP)
  • Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
  • High power (SP HP)
  • Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV Peripheral operating requirements and behaviors 44 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors
  1. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC

Figure 19. Typical INL error vs. digital code

Figure 20. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 35. VREF full-range operating requirements

  1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
  2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range

Table 36. VREF full-range operating behaviors

  • current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs — Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled 35 ms Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 0.5 2 mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 37. VREF limited-range operating requirements Table 38. VREF limited-range operating behaviors

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

3.8.1 Ethernet switching specifications

appropriately to arrive at timing specs/constraints for the physical interface.

3.8.1.1 MII signal switching specifications

Table 39. MII signal switching specifications Figure 21. RMII/MII transmit signal timing diagram

Figure 22. RMII/MII receive signal timing diagram

3.8.1.2 RMII signal switching specifications

range of transceiver devices. Table 40. RMII signal switching specifications

3.8.2 USB electrical specifications

date standards, visit usb.org. clock/crystal for both Device and Host modes.

rate specifications for certification.

3.8.3 USB DCD electrical specifications

Table 41. USB0 DCD electrical specifications

3.8.4 USB VREG electrical specifications

Table 42. USB VREG electrical specifications

  • VREGIN = 5.0 V and temperature=25 °C
  • Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
  • Run mode
  • Standby mode 2.1 3.3 2.8 3.6 3.6 V V Table continues on the next page... Peripheral operating requirements and behaviors 50 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors
  1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
  2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

3.8.5 CAN switching specifications

See General switching specifications.

3.8.6 DSPI switching specifications (limited voltage range)

formats used for communicating with slower peripheral devices. Table 43. Master mode DSPI timing (limited voltage range)

  1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
  1. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 23. DSPI classic SPI timing — master mode Table 44. Slave mode DSPI timing (limited voltage range)

  1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

Figure 24. DSPI classic SPI timing — slave mode

3.8.7 DSPI switching specifications (full voltage range)

formats used for communicating with slower peripheral devices. Table 45. Master mode DSPI timing (full voltage range)

  1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

  1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
  2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

3.8.8 Inter-Integrated Circuit Interface (I2C) timing

Table 47. I 2C timing Hold time (repeated) START condition.

  1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the

High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.

  1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
  2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
  3. Input signal Slew = 10 ns and Output Load = 50 pF
  4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
  5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
  6. Cb = total capacitance of the one bus line in pF.

Table 48. I 2C 1 Mbps timing period, the first clock pulse is generated. Table continues on the next page...

Table 48. I 2C 1 Mbps timing (continued)

  1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across
  2. Cb = total capacitance of the one bus line in pF.

Figure 27. Timing definition for devices on the I2C bus

3.8.9 UART switching specifications

See General switching specifications.

3.8.10 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 49. SDHC switching specifications Table continues on the next page...

Figure 28. SDHC timing

3.8.11 I2S switching specifications

the frame sync (I2S_FS) shown in the figures below. Table 50. I 2S master mode timing Figure 29. I2S timing — master mode Table 51. I 2S slave mode timing Table continues on the next page...

Table 51. I 2S slave mode timing (continued)

  1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 30. I2S timing — slave modes

3.8.11.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 52. I2S/SAI master mode timing Table continues on the next page...

Table 52. I2S/SAI master mode timing (continued) Figure 31. I2S/SAI timing — master modes Table 53. I2S/SAI slave mode timing Table continues on the next page...

Table 53. I2S/SAI slave mode timing (continued)

  1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 32. I2S/SAI timing — slave modes

3.8.11.2 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 54. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Table continues on the next page...

Figure 33. I2S/SAI timing — master modes Table 55. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

  1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 34. I2S/SAI timing — slave modes

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

5 Pinout

5.1 K64 Signal Multiplexing and Pin Assignments

responsible for selecting which ALT functionality is available on each pin.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort C10 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1TRACE_ CLKOUT I2C1_SDARTC_ CLKOUT D8 PTE1/ LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RXSDHC0_D0TRACE_D3I2C1_SCL SPI1_SIN D9 PTE2/ LLWU_P1 ADC0_DP2/ ADC1_SE6a ADC0_DP2/ ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCKUART1_CTS_ b SDHC0_ DCLK TRACE_D2 C11 PTE3 ADC0_DM2/ ADC1_SE7a ADC0_DM2/ ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_ b SDHC0_CMDTRACE_D1 SPI1_SOUT F6 VDD VDD VDD E6 VSS VSS VSS D10 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TXSDHC0_D3TRACE_D0 D11 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2 FTM3_CH0 E7 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CTS_ b I2S0_MCLK FTM3_CH1USB_SOF_ OUT E8 PTE7 DISABLED PTE7 UART3_RTS_ b I2S0_RXD0 FTM3_CH2 E9 PTE8 DISABLED PTE8 I2S0_RXD1UART5_TXI2S0_RX_FS FTM3_CH3 E10 PTE9 DISABLED PTE9 I2S0_TXD1UART5_RXI2S0_RX_ BCLK FTM3_CH4 E11 PTE10 DISABLED PTE10 UART5_CTS_ b I2S0_TXD0 FTM3_CH5 F9 PTE11 DISABLED PTE11 UART5_RTS_ b I2S0_TX_FS FTM3_CH6 F10 PTE12 DISABLED PTE12 I2S0_TX_ BCLK FTM3_CH7 F7 VDD VDD VDD F11 VSS VSS VSS G11 USB0_DP USB0_DP USB0_DP H11 USB0_DMUSB0_DMUSB0_DM G10 VOUT33 VOUT33 VOUT33 H10 VREGIN VREGIN VREGIN F8 ADC0_DP1ADC0_DP1ADC0_DP1 G8 ADC0_DM1ADC0_DM1ADC0_DM1 J11 ADC1_DP1ADC1_DP1ADC1_DP1 K11 ADC1_DM1ADC1_DM1ADC1_DM1 G9 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 H9 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 J10 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 K10 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 Pinout 64 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort L11 VDDA VDDA VDDA L10 VREFH VREFH VREFH M11 VREFL VREFL VREFL N11 VSSA VSSA VSSA M10 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 K9 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 L9 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 N10 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 M9 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 J9 RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B N9 XTAL32 XTAL32 XTAL32 N8 EXTAL32 EXTAL32 EXTAL32 M8 VBAT VBAT VBAT H8 VDD VDD VDD G7 VSS VSS VSS L8 PTE24 ADC0_SE17ADC0_SE17PTE24 UART4_TX I2C0_SCL EWM_OUT_b K8 PTE25 ADC0_SE18ADC0_SE18PTE25 UART4_RX I2C0_SDAEWM_IN N7 PTE26 DISABLED PTE26 ENET_1588_ CLKIN UART4_CTS_ b RTC_ CLKOUT USB_CLKIN J8 PTE27 DISABLED PTE27 UART4_RTS_ b M7 PTE28 DISABLED PTE28 L7 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_CTS_ UART0_COL_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK K7 PTA1 JTAG_TDI/ EZP_DI PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI J7 PTA2 JTAG_TDO/ TRACE_ SWO/ EZP_DO PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO Pinout Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 65 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort N6 PTA3 JTAG_TMS/ SWD_DIO PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO M6 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b L6 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2RMII0_RXER/ MII0_RXER CMP2_OUTI2S0_TX_ BCLK JTAG_TRST_ b H7 VDD VDD VDD H6 VSS VSS VSS N5 PTA6 DISABLED PTA6 FTM0_CH3 CLKOUT TRACE_ CLKOUT M5 PTA7 ADC0_SE10ADC0_SE10PTA7 FTM0_CH4 RMII0_MDIO/ MII0_MDIO TRACE_D3 K6 PTA8 ADC0_SE11ADC0_SE11PTA8 FTM1_CH0 RMII0_MDC/ MII0_MDC FTM1_QD_ PHA TRACE_D2 L5 PTA9 DISABLED PTA9 FTM1_CH1MII0_RXD3 FTM1_QD_ PHB TRACE_D1 N4 PTA10 DISABLED PTA10 FTM2_CH0MII0_RXD2 FTM2_QD_ PHA TRACE_D0 J6 PTA11 DISABLED PTA11 FTM2_CH1MII0_RXCLKI2C2_SDAFTM2_QD_ PHB K5 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0RMII0_RXD1/ MII0_RXD1 I2C2_SCL I2S0_TXD0FTM1_QD_ PHA M4 PTA13/ LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RX FTM1_CH1RMII0_RXD0/ MII0_RXD0 I2C2_SDAI2S0_TX_FSFTM1_QD_ PHB J5 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TXRMII0_CRS_ DV/ MII0_RXDV I2C2_SCL I2S0_RX_ BCLK I2S0_TXD1 N3 PTA15 DISABLED PTA15 SPI0_SCKUART0_RXRMII0_TXEN/ MII0_TXEN I2S0_RXD0 L4 PTA16 DISABLED PTA16 SPI0_SOUTUART0_CTS_ UART0_COL_ b RMII0_TXD0/ MII0_TXD0 I2S0_RX_FSI2S0_RXD1 M3 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS_ b RMII0_TXD1/ MII0_TXD1 I2S0_MCLK N2 VDD VDD VDD M2 VSS VSS VSS N1 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 M1 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ ALT1 L1 RESET_b RESET_b RESET_b L2 PTA24 DISABLED PTA24 MII0_TXD2FB_A15 FB_A29 L3 PTA25 DISABLED PTA25 MII0_TXCLKFB_A14 FB_A28 K4 PTA26 DISABLED PTA26 MII0_TXD3FB_A13 FB_A27 K3 PTA27 DISABLED PTA27 MII0_CRS FB_A12 FB_A26 Pinout 66 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K2 PTA28 DISABLED PTA28 MII0_TXER FB_A25 K1 PTA29 DISABLED PTA29 MII0_COL FB_A24 J4 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8 ADC0_SE8/ ADC1_SE8 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0RMII0_MDIO/ MII0_MDIO FTM1_QD_ PHA J3 PTB1 ADC0_SE9/ ADC1_SE9 ADC0_SE9/ ADC1_SE9 PTB1 I2C0_SDAFTM1_CH1RMII0_MDC/ MII0_MDC FTM1_QD_ PHB J2 PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL UART0_RTS_ b ENET0_ 1588_TMR0 FTM0_FLT3 J1 PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDAUART0_CTS_ UART0_COL_ b ENET0_ 1588_TMR1 FTM0_FLT0 H4 PTB4 ADC1_SE10ADC1_SE10PTB4 ENET0_ 1588_TMR2 FTM1_FLT0 H3 PTB5 ADC1_SE11ADC1_SE11PTB5 ENET0_ 1588_TMR3 FTM2_FLT0 H2 PTB6 ADC1_SE12ADC1_SE12PTB6 FB_AD23 H1 PTB7 ADC1_SE13ADC1_SE13PTB7 FB_AD22 G4 PTB8 DISABLED PTB8 UART3_RTS_ b FB_AD21 G3 PTB9 DISABLED PTB9 SPI1_PCS1UART3_CTS_ b FB_AD20 G1 PTB10 ADC1_SE14ADC1_SE14PTB10 SPI1_PCS0UART3_RX FB_AD19 FTM0_FLT1 G2 PTB11 ADC1_SE15ADC1_SE15PTB11 SPI1_SCKUART3_TX FB_AD18 FTM0_FLT2 H5 VSS VSS VSS F3 VDD VDD VDD F1 PTB16 DISABLED PTB16 SPI1_SOUTUART0_RXFTM_CLKIN0FB_AD17 EWM_IN F2 PTB17 DISABLED PTB17 SPI1_SIN UART0_TXFTM_CLKIN1FB_AD16 EWM_OUT_b E1 PTB18 DISABLED PTB18 CAN0_TX FTM2_CH0I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA E2 PTB19 DISABLED PTB19 CAN0_RX FTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_ PHB E3 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT E4 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT D4 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT D1 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28 D2 PTC0 ADC0_SE14ADC0_SE14PTC0 SPI0_PCS4PDB0_ EXTRG USB_SOF_ OUT FB_AD14 I2S0_TXD1 D3 PTC1/ LLWU_P6 ADC0_SE15ADC0_SE15PTC1/ LLWU_P6 SPI0_PCS3UART1_RTS_ b FTM0_CH0FB_AD13 I2S0_TXD0 C1 PTC2 ADC0_SE4b/ CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2UART1_CTS_ b FTM0_CH1FB_AD12 I2S0_TX_FS B1 PTC3/ LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK Pinout Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 67 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort F4 VSS VSS VSS G5 VDD VDD VDD A1 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11 CMP1_OUT C2 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0FB_AD10 CMP0_OUTFTM0_CH2 B2 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_ EXTRG I2S0_RX_ BCLK FB_AD9 I2S0_MCLK A2 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FSFB_AD8 B3 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4I2S0_MCLKFB_AD7 A3 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5I2S0_RX_ BCLK FB_AD6 FTM2_FLT0 C3 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCL FTM3_CH6I2S0_RX_FSFB_AD5 B4 PTC11/ LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDAFTM3_CH7I2S0_RXD1FB_RW_b A4 PTC12 DISABLED PTC12 UART4_RTS_ b FB_AD27 FTM3_FLT0 C4 PTC13 DISABLED PTC13 UART4_CTS_ b FB_AD26 B5 PTC14 DISABLED PTC14 UART4_RX FB_AD25 A5 PTC15 DISABLED PTC15 UART4_TX FB_AD24 F5 VSS VSS VSS E5 VDD VDD VDD C5 PTC16 DISABLED PTC16 UART3_RXENET0_ 1588_TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_ 16_BLS15_8_ b A6 PTC17 DISABLED PTC17 UART3_TXENET0_ 1588_TMR1 FB_CS4_b/ FB_TSIZ0/ FB_BE31_ 24_BLS7_0_b B6 PTC18 DISABLED PTC18 UART3_RTS_ b ENET0_ 1588_TMR2 FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ BLS23_16_b D5 PTC19 DISABLED PTC19 UART3_CTS_ b ENET0_ 1588_TMR3 FB_CS3_b/ FB_BE7_0_ BLS31_24_b FB_TA_b D6 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_RTS_ b FTM3_CH0FB_ALE/ FB_CS1_b/ FB_TS_b A7 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_CTS_ b FTM3_CH1FB_CS0_b Pinout 68 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

5.2 Unused analog interfaces

Table 56. Unused analog interfaces ground, as this causes a latch-up risk.

  1. Unused DAC signals do not apply to all parts. See the Pinout section for details.
  2. USB0_VBUS and USB0_GND are board level signals

5.3 K64 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. used on which pin, see the previous section. Figure 35. 142 CSP Pinout Diagram

6 Ordering parts

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: MK64

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format: Q K## A M FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow, full reels

  • P = Prequalification
  • K = Fully qualified, general market flow, 100 piece reels K## Kinetis family • K64 = USB and Ethernet with high RAM density Table continues on the next page... Ordering parts Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 71 NXP Semiconductors

A Key attribute • D = Cortex-M4 w/ DSP

  • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
  • X = Program flash and FlexMemory FFF Program flash memory size • 512 = 512 KB
  • 1M0 = 1 MB R Silicon revision • Z = Initial
  • (Blank) = Main
  • A = Revision after main T Temperature range (°C) • C = –40 to 85 CC Maximum CPU frequency (MHz) • 12 = 120 MHz N Packaging type • R = Tape and reel

7.4 Example

This is an example part number: MK64FN1M0CAJ12R

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

  • Operating ratings apply during operation of the chip.
  • Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that: Terminology and guidelines 72 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors
  • Lies within the range of values specified by the operating behavior
  • Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

8.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V Terminology and guidelines Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 73 NXP Semiconductors

8.4 Relationship between ratings and operating requirements

  • No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

  • Never exceed any of the chip’s ratings.
  • During normal operation, don’t exceed any of the chip’s operating requirements.
  • If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

9 Revision History

The following table provides a revision history for this document. Table 57. Revision History 2 01/2014 Initial public release. Table continues on the next page...

Revision History

74 Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 NXP Semiconductors

Table 57. Revision History (continued)

  • Updated Table 23 "Flash command timing specifications." 4 09/2014 • Updated Table 6 "Power consumption operating behavior."
  • Updated Table 17 "IRC48M specifications
  • Updated Table 35 "VREF full-range operating behavior" 5 12/2014 • Updated Table 6 "Power consumption operating behavior."
  • Added a note to the section "Power consumption operating behaviors." 6 08/2015 • Added a footnote to the maximum SCL clock frequency value in the table "I 2C timing"
  • Changed the title of the table "I 2C 1 MHZ timing" to "I2C 1 Mbps timing"
  • Added a footnote and updated the table "IRC48M specifications" for open loop total deviation of IRC48M frequency at high voltage and low voltage.
  • Added a footnote on the ambient temperature entry to the section "Thermal operating requirements."
  • Added a note to the section "Power consumption operating behaviors" and updated values in the table "Power consumption operating behaviors."
  • Added a note to the maximum frequency value in the table "Slave mode DSPI timing (limited voltage range)."
  • Redeveloped the section "Terminology and guidelines." 7 10/2016 • Updated the values of I DD_STOP and IDD_VLLS0 in the table "Power consumption operating behavior."

Kinetis K64 Sub-Family Data Sheet With 1 MB Flash, Rev. 7, 10/2016 75 NXP Semiconductors

How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. NXP, NXP logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. The USB-IF Logo is a registered trademark of USB Implementers Forum, Inc. All rights reserved. ©2014–2016 NXP B.V. Document Number K64P142M120SF5 Revision 7, 10/2016