MK63FN1M0VLQ12

K63P144M120SF5 NXP | Alldatasheet

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Technical content

Kinetis K63F Sub-Family Data Sheet

120 MHz ARM® Cortex®-M4-based Microcontroller with FPU

The K63 product family members are optimized for cost-sensitive applications requiring low-power, USB/Ethernet connectivity, up to 256 KB of embedded SRAM and the need for extensive tamper protection, such as Electronic Point of Sales. These devices share the comprehensive enablement and scalability of the Kinetis family. This product offers: Run power consumption down to 250 μA/MHz. Static power consumption down to 5.8 μA with full state retention and 5 μs wakeup. Lowest Static mode down to 339 nA

• DryIce Tamper Detection with active/passive pin, temperature, clock, supply voltage monitoring
• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO Vreg, with USB device crystal-less operation
• 10/100 Mbit/s Ethernet MAC with MII and RMII interfaces Performance Up to 120 MHz ARM® Cortex®-M4 core with DSP instructions and floating point unit Memories and memory interfaces
• Up to 1 MB program flash memory and 256 KB RAM
• FlexBus external bus interface System peripherals
• Multiple low-power modes, low-leakage wake-up unit
• Memory protection unit with multi-master protection
• 16-channel DMA controller
• External watchdog monitor and software watchdog Security and integrity modules
• Hardware CRC module
• Tamper detect and secure storage
• Hardware random-number generator
• Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms
• 128-bit unique identification (ID) number per chip Analog modules
• Two 16-bit SAR ADCs
• Two 12-bit DACs
• Three analog comparators (CMP)
• Voltage reference Communication interfaces Ethernet controller with MII and RMII interface
• USB full-/low-speed On-the-Go controller
• Controller Area Network (CAN) module
• Three SPI modules
• Three I2C modules. Support for up to 1 Mbit/s
• Six UART modules
• Secure Digital Host Controller (SDHC)
• I2S module Timers
• Two 8-channel Flex-Timers (PWM/Motor control)
• Two 2-channel FlexTimers (PWM/Quad decoder)
• IEEE 1588 timers
• 32-bit PITs and 16-bit low-power timers
• Real-time clock
• Programmable delay block Clocks
• 3 to 32 MHz and 32 kHz crystal oscillator
• PLL, FLL, and multiple internal oscillators
• 48 MHz Internal Reference Clock (IRC48M) Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): –40 to 105°C MK63FN1M0VLQ12 MK63FN1M0VMD12

144 LQFP

20 x 20 x 1.6 mm Pitch 0.5 mm

144 MAPBGA

13 x 13 x 1.46 mm Pitch 1 mm NXP Semiconductors K63P144M120SF5 Data Sheet: Technical Data Rev. 7, 11/2016 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

Part Number Memory Maximum number of I\\O's Flash SRAM (KB) MK63FN1M0VLQ12 1 MB 256 100 MK63FN1M0VMD12 1 MB 256 95 1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. Related Resources Type Description Resource Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. K60PB 1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K63P144M120SF5RM 1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. K63P144M120SF51 Package drawing Package dimensions are provided in package drawings. • LQFP 144-pin: 98ASS23177W1

• MAPBGA 144-pin: 98ASA00222D1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Figure 1. K63 block diagram

3.8.6 DSPI switching specifications (limited voltage

3.8.7 DSPI switching specifications (full voltage

8.4 Relationship between ratings and operating

4 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 Solder temperature, leaded — 245 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 5 NXP Semiconductors

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Figure 2. Input signal measurement reference

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICDIO Digital pin (except Tamper pins) negative DC injection current — single pin
• V IN < VSS-0.3V -5 — mA IICAIO Analog2, EXTAL, and XTAL pin DC injection current — single pin
• V IN < VSS-0.3V (Negative current injection)
• V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection -25 +25 mA VODPU Open drain pullup voltage level VDD VDD V 4 VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN- VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. General Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 7 NXP Semiconductors

2.2.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors Table continues on the next page...

Table 4. Voltage and current operating behaviors (continued)

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -8mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — 100 mA VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -3mA VBAT – 0.5 VBAT – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -0.6mA VBAT – 0.5 VBAT – 0.5 V V IOH_Tamper Output high current total for Tamper pins — 100 mA VOL Output low voltage — high drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 9mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — 100 mA VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOL_Tamper Output low current total for Tamper pins — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 1 IIN Input leakage current (per pin) at 25°C — 0.025 μA 1 IIN_Tamper Input leakage current (per Tamper pin) for full temperature range — 1 μA IIN_Tamper Input leakage current (per Tamper pin) at 25°C — 0.025 μA IOZ Hi-Z (off-state) leakage current (per pin) — 0.25 μA IOZ_Tamper Hi-Z (off-state) leakage current (per Tamper pin) — 0.25 μA Table continues on the next page... General Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 9 NXP Semiconductors

1. Measured at VDD supply voltage = VDD min and Vinput = VSS
2. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

• VLLS0 → RUN — 156 μs
• VLLS1 → RUN — 156 μs
• VLLS2 → RUN — 78 μs
• VLLS3 → RUN — 78 μs
• LLS → RUN — 4.8 μs
• VLPS → RUN — 4.5 μs
• STOP → RUN — 4.5 μs General 10 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

2.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

• @ 1.8V
• @ 3.0V 31.1 36.65 36.75 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
• @ 1.8V
• @ 3.0V
• @ 25°C
• @ 105°C 42.7 48.33 48.35 41.60 51.50 mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 17.9 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 6.9 — mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.0 — mA 6 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.7 — mA 7 IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled — 0.678 — mA 8 IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.49 1.18 3.0 1.24 4.3 12.5 mA mA mA IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 291 927.3 139.31 679.33 1869.85 μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C — 5.8 26.7 10.48 47.99 μA μA Table continues on the next page... General Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 11 NXP Semiconductors

Table 6. Power consumption operating behaviors (continued)

• @ 70°C
• @ 105°C — 114.9 196.49 μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 4.4 90.2 5.54 36.46 150.17 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 2.1 6.84 29.4 2.34 10.36 46.74 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.817 3.97 21.3 0.86 5.77 33.99 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.52 3.67 21.20 0.62 5.7 34.9 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.339 3.36 20.3 0.412 4.2 29.9 μA μA μA IDD_VBAT Average current with RTC and 32 kHz disabled
• @ 1.8 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.16 0.55 2.5 0.18 0.66 2.92 0.19 0.72 3.68 0.21 0.86 4.30 μA μA μA μA μA μA IDD_VBAT Average current when CPU is not accessing RTC registers General 12 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

• @ 1.8 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.59 1.0 3.0 0.71 1.22 3.5 0.70 1.30 4.42 0.84 1.59 5.15 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120 MHz core and system clock, 60 MHz bus, 30 Mhz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 120 MHz core and system clock, 60 MHz bus clock, 30 MHz Flexbus clock, and 20 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, FlexBus, and bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 256 KB of RAM. 10. Includes 32kHz oscillator current and RTC operation.

Table 7. Low power mode peripheral adders — typical value VLPS mode with 4 MHz IRC enabled. mode with the 32 kHz IRC enabled. IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled. Table continues on the next page...

Table 7. Low power mode peripheral adders — typical value (continued) a single external input for compare. the RTC ALARM set for 1 minute.

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE General 14 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Figure 3. Run mode supply current vs. core frequency

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 8. EMC radiated emissions operating behaviors

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code. from among the measured orientations in each frequency range.

1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

2.2.7 Designing with radiated emissions in mind

1. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 9. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 10. Device clock specifications

• 10 Mbps
• 100 Mbps MHz fBUS Bus clock — 60 MHz FB_CLK FlexBus clock — 50 MHz fFLASH Flash clock — 25 MHz Table continues on the next page... General Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 17 NXP Semiconductors

Table 10. Device clock specifications (continued)

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

2.3.2 General switching specifications

CAN, CMT, IEEE 1588 timer, timers, and I2C signals. Table 11. General switching specifications

• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled ns ns ns Table continues on the next page... General 18 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Table 11. General switching specifications (continued)

• 1.71 ≤ V DD ≤ 2.7V — 12 ns Port rise and fall time (high drive strength) - 5 V
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength) - 3 V
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength) - 5 V
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 25 pF load 5. 15 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 12. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

2.4.2 Thermal attributes

Table 13. Thermal attributes

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Method Environmental Conditions—Forced Convection (Moving Air).

1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

between the top of the package and the cold plate.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 14. Debug trace operating behaviors

Figure 5. TRACE_CLKOUT specifications Figure 6. Trace data specifications

3.1.2 JTAG electricals

Table 15. JTAG limited voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.6 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns Table continues on the next page... Peripheral operating requirements and behaviors 22 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Table 15. JTAG limited voltage range electricals (continued) Table 16. JTAG full voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug 12.5 ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 2.9 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J3 J3 J4 J4 TCLK (input)

Figure 7. Test clock input timing

Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

3.3.1 MCG specifications

Table 17. MCG specifications Table continues on the next page...

Table 17. MCG specifications (continued)

• f DCO = 48 MHz
• f DCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fvco VCO operating frequency 48.0 — 120 MHz Ipll PLL operating current
• PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) — 1060 — µA 8 Ipll PLL operating current
• PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) — 600 — µA 8 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter (RMS)
• f vco = 48 MHz
• f vco = 120 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS) 9 Table continues on the next page... Peripheral operating requirements and behaviors 26 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

• f vco = 48 MHz
• f vco = 120 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

3.3.2 IRC48M specifications

Table 18. IRC48M specifications

• Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 0.5 ± 1.5 ± 2.0 %firc48m Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89V-3.6V) over full temperature
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 1.5 %firc48m Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 27 NXP Semiconductors

Table 18. IRC48M specifications (continued)

• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 1.0 %firc48m Δfirc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature — — ± 0.1 %fhost 2 Jcyc_irc48m Period Jitter (RMS) — 35 150 ps tirc48mst Startup time — 2 3 μs 3 1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard deviation (mean ± 3 sigma) 2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by setting USB_CLK_RECOVER_IRC_EN[IRC_EN]=1.

3.3.3 Oscillator electrical specifications

3.3.3.1 Oscillator DC electrical specifications

Table 19. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high-gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Table continues on the next page... Peripheral operating requirements and behaviors 28 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Table 19. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.3.3.2 Oscillator frequency specifications

Table 20. Oscillator frequency specifications

1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

and cannot be moved into high power/gain mode. Table 21. 32kHz oscillator DC electrical specifications Table continues on the next page...

Table 21. 32kHz oscillator DC electrical specifications (continued)

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. Table 22. 32 kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the

applied clock must be within the range of VSS to VBAT.

3.4 Memories and memory interfaces

3.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

3.4.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 23. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 24. Flash command timing specifications

• 512 KB program flash 1.8 ms trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs tersblk512k Erase Flash Block execution time
• 512 KB program flash 435 3700 ms tersscr Erase Flash Sector execution time — 15 115 ms 2 trd1alln Read 1s All Blocks execution time
• Program flash only devices 3.4 ms trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 70 — μs tersall Erase All Blocks execution time — 870 7400 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 tswapx01 tswapx02 tswapx04 tswapx08 Swap Control execution time
• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08 200 150 150 μs μs μs μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3.4.1.3 Flash high voltage current behaviors

Table 25. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 26. NVM reliability specifications

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.

3.4.2 EzPort switching specifications

Table 27. EzPort switching specifications

Figure 11. EzPort Timing Diagram

3.4.3 Flexbus switching specifications

be derived from these values. Table 28. Flexbus limited voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,

1. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 29. Flexbus full voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Figure 12. FlexBus read timing diagram

Figure 13. FlexBus write timing diagram

3.5 Security and integrity modules

3.5.1 DryIce Tamper Electrical Specifications

NDA, please contact your local NXP sales representative.

3.6 Analog

3.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 30. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps Table continues on the next page... Peripheral operating requirements and behaviors 38 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Table 30. 16-bit ADC operating conditions (continued)

1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

1. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

RAS/CAS time constant should be kept to < 1 ns.

1. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Figure 14. ADC input impedance equivalency diagram

Table 31. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes
• <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 82 95 — dB dB Table continues on the next page... Peripheral operating requirements and behaviors 40 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Table 31. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• Avg = 32 78 90 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input ENOB ADC Clock Frequency (MHz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 12 11 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples

Figure 15. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Figure 16. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

3.6.2 CMP and 6-bit DAC electrical specifications

Table 32. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB Peripheral operating requirements and behaviors 42 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. Figure 17. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 33. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Table 34. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV Peripheral operating requirements and behaviors Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 45 NXP Semiconductors

1. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

Figure 19. Typical INL error vs. digital code

Figure 20. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 35. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature

Table 36. VREF full-range operating behaviors

• current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs — Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled 35 ms Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 0.5 2 mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 37. VREF limited-range operating requirements Table 38. VREF limited-range operating behaviors

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

3.8.1 Ethernet switching specifications

appropriately to arrive at timing specs/constraints for the physical interface.

3.8.1.1 MII signal switching specifications

Table 39. MII signal switching specifications Figure 21. RMII/MII transmit signal timing diagram

Figure 22. RMII/MII receive signal timing diagram

3.8.1.2 RMII signal switching specifications

Table 40. RMII signal switching specifications

3.8.1.3 MDIO serial management timing specifications

Table 41. MDIO serial management channel signal timing

Figure 23. MDIO serial management channel timing diagram

3.8.2 USB electrical specifications

date standards, visit usb.org. clock/crystal for both Device and Host modes. signaling rate specifications for certification.

3.8.3 USB DCD electrical specifications

Table 42. USB0 DCD electrical specifications Table continues on the next page...

Table 42. USB0 DCD electrical specifications (continued)

3.8.4 USB VREG electrical specifications

Table 43. USB VREG electrical specifications

• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
• Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

3.8.5 CAN switching specifications

See General switching specifications.

3.8.6 DSPI switching specifications (limited voltage range)

formats used for communicating with slower peripheral devices. Table 44. Master mode DSPI timing (limited voltage range)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 24. DSPI classic SPI timing — master mode

Table 45. Slave mode DSPI timing (limited voltage range)

1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

Figure 25. DSPI classic SPI timing — slave mode

3.8.7 DSPI switching specifications (full voltage range)

formats used for communicating with slower peripheral devices. Table 46. Master mode DSPI timing (full voltage range)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 26. DSPI classic SPI timing — master mode Table 47. Slave mode DSPI timing (full voltage range) Table continues on the next page...

Table 47. Slave mode DSPI timing (full voltage range) (continued) Figure 27. DSPI classic SPI timing — slave mode

3.8.8 Inter-Integrated Circuit Interface (I2C) timing

Table 48. I 2C timing Hold time (repeated) START condition. Table continues on the next page...

Table 48. I 2C timing (continued)

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the

High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
6. Cb = total capacitance of the one bus line in pF.

Table 49. I 2C 1 Mbps timing period, the first clock pulse is generated.

1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins

across the full voltage range.

1. Cb = total capacitance of the one bus line in pF.

Figure 28. Timing definition for devices on the I2C bus

3.8.9 UART switching specifications

See General switching specifications.

3.8.10 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 50. SDHC switching specifications

Figure 29. SDHC timing

3.8.11 I2S switching specifications

the frame sync (I2S_FS) shown in the figures below. Table 51. I 2S master mode timing

Figure 30. I2S timing — master mode Table 52. I 2S slave mode timing

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 31. I2S timing — slave modes

3.8.11.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 53. I2S/SAI master mode timing

Figure 32. I2S/SAI timing — master modes Table 54. I2S/SAI slave mode timing

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 33. I2S/SAI timing — slave modes

3.8.11.2 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 55. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Figure 34. I2S/SAI timing — master modes Table 56. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 35. I2S/SAI timing — slave modes

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

5 Pinout

5.1 K63 Signal Multiplexing and Pin Assignments

responsible for selecting which ALT functionality is available on each pin.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort — M3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 — L3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 — L4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 — J4 TAMPER3TAMPER3TAMPER3 — H4 TAMPER4TAMPER4TAMPER4 — M4 TAMPER5TAMPER5TAMPER5 — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC

1 D3 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1TRACE_

I2C1_SDARTC_ CLKOUT

2 D2 PTE1/

LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RXSDHC0_D0TRACE_D3I2C1_SCLSPI1_SIN

3 D1 PTE2/

LLWU_P1 ADC0_DP2/ ADC1_SE6a ADC0_DP2/ ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCKUART1_ CTS_b SDHC0_ DCLK TRACE_D2

4 E4 PTE3 ADC0_DM2/

ADC1_SE7a ADC0_DM2/ ADC1_SE7a PTE3 SPI1_SIN UART1_ RTS_b SDHC0_ CMD TRACE_D1 SPI1_SOUT

5 E5 VDD VDD VDD

6 F6 VSS VSS VSS

7 E3 PTE4/

LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TXSDHC0_D3TRACE_D0

8 E2 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2 FTM3_CH0

9 E1 PTE6 DISABLED PTE6 SPI1_PCS3UART3_

CTS_b I2S0_MCLK FTM3_CH1USB_SOF_ OUT

10 F4 PTE7 DISABLED PTE7 UART3_

RTS_b I2S0_RXD0 FTM3_CH2

11 F3 PTE8 DISABLED PTE8 I2S0_RXD1UART5_TXI2S0_RX_FS FTM3_CH3

12 F2 PTE9 DISABLED PTE9 I2S0_TXD1UART5_RXI2S0_RX_

FTM3_CH4

13 F1 PTE10 DISABLED PTE10 UART5_

CTS_b I2S0_TXD0 FTM3_CH5

14 G4 PTE11 DISABLED PTE11 UART5_

RTS_b I2S0_TX_FS FTM3_CH6

15 G3 PTE12 DISABLED PTE12 I2S0_TX_

FTM3_CH7 Pinout 66 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

16 E6 VDD VDD VDD

17 F7 VSS VSS VSS

18 H3 VSS VSS VSS

19 H1 USB0_DPUSB0_DPUSB0_DP

20 H2 USB0_DMUSB0_DMUSB0_DM

21 G1 VOUT33 VOUT33 VOUT33

22 G2 VREGIN VREGIN VREGIN

23 J1 ADC0_DP1ADC0_DP1ADC0_DP1

24 J2 ADC0_DM1ADC0_DM1ADC0_DM1

25 K1 ADC1_DP1ADC1_DP1ADC1_DP1

26 K2 ADC1_DM1ADC1_DM1ADC1_DM1

27 L1 ADC0_DP0/

ADC1_DP3 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3

28 L2 ADC0_DM0/

ADC1_DM3 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3

29 M1 ADC1_DP0/

ADC0_DP3 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3

30 M2 ADC1_DM0/

ADC0_DM3 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3

31 H5 VDDA VDDA VDDA

32 G5 VREFH VREFH VREFH

33 G6 VREFL VREFL VREFL

34 H6 VSSA VSSA VSSA

35 K3 ADC1_SE16/

CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22

36 J3 ADC0_SE16/

CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21

37 L5 TAMPER0/

RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B

38 K5 TAMPER1TAMPER1TAMPER1

39 K4 TAMPER2TAMPER2TAMPER2

40 M7 XTAL32 XTAL32 XTAL32

41 M6 EXTAL32 EXTAL32 EXTAL32

42 L6 VBAT VBAT VBAT

43 — VDD VDD VDD 44 — VSS VSS VSS 45 — PTE24 ADC0_SE17ADC0_SE17PTE24 UART4_TX I2C0_SCLEWM_OUT_ b 46 — PTE25 ADC0_SE18ADC0_SE18PTE25 UART4_RX I2C0_SDAEWM_IN Pinout Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 67 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 47 — PTE26 DISABLED PTE26 ENET_1588_ CLKIN UART4_ CTS_b RTC_ CLKOUT USB_CLKIN 48 — PTE27 DISABLED PTE27 UART4_ RTS_b 49 — PTE28 DISABLED PTE28

50 J5 PTA0 JTAG_TCLK/

SWD_CLK/ EZP_CLK PTA0 UART0_ CTS_b/ UART0_ COL_b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK

51 J6 PTA1 JTAG_TDI/

EZP_DI PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI

52 K6 PTA2 JTAG_TDO/

TRACE_ SWO/ EZP_DO PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_ SWO EZP_DO

53 K7 PTA3 JTAG_TMS/

SWD_DIO PTA3 UART0_ RTS_b FTM0_CH0 JTAG_TMS/ SWD_DIO

54 L7 PTA4/

LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b

55 M8 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2RMII0_

MII0_RXER CMP2_OUTI2S0_TX_ BCLK JTAG_ TRST_b

56 E7 VDD VDD VDD

57 G7 VSS VSS VSS

58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_

59 J8 PTA7 ADC0_SE10ADC0_SE10PTA7 FTM0_CH4 TRACE_D3

60 K8 PTA8 ADC0_SE11ADC0_SE11PTA8 FTM1_CH0 FTM1_QD_

TRACE_D2

61 L8 PTA9 DISABLED PTA9 FTM1_CH1MII0_RXD3 FTM1_QD_

TRACE_D1

62 M9 PTA10 DISABLED PTA10 FTM2_CH0MII0_RXD2 FTM2_QD_

TRACE_D0

63 L9 PTA11 DISABLED PTA11 FTM2_CH1MII0_RXCLKI2C2_SDAFTM2_QD_

64 K9 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TXFTM1_CH0RMII0_

MII0_RXD1 I2C2_SCLI2S0_TXD0FTM1_QD_ PHA

65 J9 PTA13/

LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RXFTM1_CH1RMII0_ RXD0/ MII0_RXD0 I2C2_SDAI2S0_TX_FSFTM1_QD_ PHB

66 L10 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TXRMII0_CRS_

MII0_RXDV I2C2_SCLI2S0_RX_ BCLK I2S0_TXD1 Pinout 68 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

67 L11 PTA15 DISABLED PTA15 SPI0_SCKUART0_RXRMII0_

MII0_TXEN I2S0_RXD0

68 K10 PTA16 DISABLED PTA16 SPI0_SOUTUART0_

CTS_b/ UART0_ COL_b RMII0_TXD0/ MII0_TXD0 I2S0_RX_FSI2S0_RXD1

69 K11 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_

RTS_b RMII0_TXD1/ MII0_TXD1 I2S0_MCLK

70 E8 VDD VDD VDD

71 G8 VSS VSS VSS

72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0

73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_

74 L12 RESET_bRESET_bRESET_b

75 K12 PTA24 DISABLED PTA24 MII0_TXD2 FB_A29

76 J12 PTA25 DISABLED PTA25 MII0_TXCLK FB_A28

77 J11 PTA26 DISABLED PTA26 MII0_TXD3 FB_A27

78 J10 PTA27 DISABLED PTA27 MII0_CRS FB_A26

79 H12 PTA28 DISABLED PTA28 MII0_TXER FB_A25

80 H11 PTA29 DISABLED PTA29 MII0_COL FB_A24

81 H10 PTB0/

LLWU_P5 ADC0_SE8/ ADC1_SE8 ADC0_SE8/ ADC1_SE8 PTB0/ LLWU_P5 I2C0_SCLFTM1_CH0RMII0_MDIO/ MII0_MDIO FTM1_QD_ PHA

82 H9 PTB1 ADC0_SE9/

ADC1_SE9 ADC0_SE9/ ADC1_SE9 PTB1 I2C0_SDAFTM1_CH1RMII0_MDC/ MII0_MDC FTM1_QD_ PHB

83 G12 PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCLUART0_

RTS_b ENET0_ 1588_TMR0 FTM0_FLT3

84 G11 PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDAUART0_

CTS_b/ UART0_ COL_b ENET0_ 1588_TMR1 FTM0_FLT0

85 G10 PTB4 ADC1_SE10ADC1_SE10PTB4 ENET0_

1588_TMR2 FTM1_FLT0

86 G9 PTB5 ADC1_SE11ADC1_SE11PTB5 ENET0_

1588_TMR3 FTM2_FLT0

87 F12 PTB6 ADC1_SE12ADC1_SE12PTB6 FB_AD23

88 F11 PTB7 ADC1_SE13ADC1_SE13PTB7 FB_AD22

89 F10 PTB8 DISABLED PTB8 UART3_

RTS_b FB_AD21

90 F9 PTB9 DISABLED PTB9 SPI1_PCS1UART3_

CTS_b FB_AD20

91 E12 PTB10 ADC1_SE14ADC1_SE14PTB10 SPI1_PCS0UART3_RX FB_AD19 FTM0_FLT1

92 E11 PTB11 ADC1_SE15ADC1_SE15PTB11 SPI1_SCKUART3_TX FB_AD18 FTM0_FLT2

93 H7 VSS VSS VSS

Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 69 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

94 F5 VDD VDD VDD

95 E10 PTB16 DISABLED PTB16 SPI1_SOUTUART0_RXFTM_CLKIN0FB_AD17 EWM_IN

96 E9 PTB17 DISABLED PTB17 SPI1_SIN UART0_TXFTM_CLKIN1FB_AD16 EWM_OUT_

b

97 D12 PTB18 DISABLED PTB18 CAN0_TXFTM2_CH0I2S0_TX_

FB_AD15 FTM2_QD_ PHA

98 D11 PTB19 DISABLED PTB19 CAN0_RXFTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_

99 D10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT

100 D9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT

101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT

102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28

103 B12 PTC0 ADC0_SE14ADC0_SE14PTC0 SPI0_PCS4PDB0_

USB_SOF_ OUT FB_AD14 I2S0_TXD1

104 B11 PTC1/

LLWU_P6 ADC0_SE15ADC0_SE15PTC1/ LLWU_P6 SPI0_PCS3UART1_ RTS_b FTM0_CH0FB_AD13 I2S0_TXD0

105 A12 PTC2 ADC0_SE4b/

CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2UART1_ CTS_b FTM0_CH1FB_AD12 I2S0_TX_FS

106 A11 PTC3/

LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK

107 H8 VSS VSS VSS

108 — VDD VDD VDD

109 A9 PTC4/

LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11 CMP1_OUT

110 D8 PTC5/

LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0FB_AD10 CMP0_OUTFTM0_CH2

111 C8 PTC6/

LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_ EXTRG I2S0_RX_ BCLK FB_AD9 I2S0_MCLK

112 B8 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_

I2S0_RX_FSFB_AD8

113 A8 PTC8 ADC1_SE4b/

CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4I2S0_MCLKFB_AD7

114 D7 PTC9 ADC1_SE5b/

CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5I2S0_RX_ BCLK FB_AD6 FTM2_FLT0

115 C7 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCLFTM3_CH6I2S0_RX_FSFB_AD5

116 B7 PTC11/

LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDAFTM3_CH7I2S0_RXD1FB_RW_b

117 A7 PTC12 DISABLED PTC12 UART4_

RTS_b FB_AD27 FTM3_FLT0

118 D6 PTC13 DISABLED PTC13 UART4_

CTS_b FB_AD26

119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25

120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24

121 — VSS VSS VSS Pinout 70 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort 122 — VDD VDD VDD

123 A6 PTC16 DISABLED PTC16 UART3_RXENET0_

1588_TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_ 16_BLS15_ 8_b

124 D5 PTC17 DISABLED PTC17 UART3_TXENET0_

1588_TMR1 FB_CS4_b/ FB_TSIZ0/ FB_BE31_ 24_BLS7_0_ b

125 C5 PTC18 DISABLED PTC18 UART3_

RTS_b ENET0_ 1588_TMR2 FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ BLS23_16_b

126 B5 PTC19 DISABLED PTC19 UART3_

CTS_b ENET0_ 1588_TMR3 FB_CS3_b/ FB_BE7_0_ BLS31_24_b FB_TA_b

127 A5 PTD0/

LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_ RTS_b FTM3_CH0FB_ALE/ FB_CS1_b/ FB_TS_b

128 D4 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_

CTS_b FTM3_CH1FB_CS0_b

129 C4 PTD2/

LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RXFTM3_CH2FB_AD4 I2C0_SCL

130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TXFTM3_CH3FB_AD3 I2C0_SDA

131 A4 PTD4/

LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_ RTS_b FTM0_CH4FB_AD2 EWM_IN SPI1_PCS0

132 A3 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_

CTS_b/ UART0_ COL_b FTM0_CH5FB_AD1 EWM_OUT_ b SPI1_SCK

133 A2 PTD6/

LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0SPI1_SOUT

134 M10 VSS VSS VSS

135 F8 VDD VDD VDD

136 A1 PTD7 DISABLED PTD7 CMT_IROUART0_TXFTM0_CH7 FTM0_FLT1SPI1_SIN

137 C9 PTD8 DISABLED PTD8 I2C0_SCLUART5_RX FB_A16

138 B9 PTD9 DISABLED PTD9 I2C0_SDAUART5_TX FB_A17

139 B3 PTD10 DISABLED PTD10 UART5_

RTS_b FB_A18

140 B2 PTD11 DISABLED PTD11 SPI2_PCS0UART5_

CTS_b SDHC0_ CLKIN FB_A19

141 B1 PTD12 DISABLED PTD12 SPI2_SCKFTM3_FLT0SDHC0_D4 FB_A20

142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21

143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22

Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 71 NXP Semiconductors

144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23

5.2 Unused analog interfaces

Table 57. Unused analog interfaces ground, as this causes a latch-up risk.

1. Unused DAC signals do not apply to all parts. See the Pinout section for details.
2. USB0_VBUS and USB0_GND are board level signals

5.3 K63 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. used on which pin, see the previous section.

108 VDD

116 PTC11/LLWU_P11

124 PTC17

132 PTD5

140 PTD11

Figure 36. K63 144 LQFP Pinout Diagram

Figure 37. K63 144 MAPBGA Pinout Diagram

6 Ordering parts

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: MK63

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format: Q K## A M FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification K## Kinetis family • K63 = Ethernet, Tamper, and high RAM density A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory FFF Program flash memory size • 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB Table continues on the next page... Part identification Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 75 NXP Semiconductors

• 1M0 = 1 MB
• 2M0 = 2 MB R Silicon revision • Z = Initial
• (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 16 = 168 MHz
• 18 = 180 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

7.4 Example

This is an example part number: MK63FN1M0VMD12

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table: Terminology and guidelines 76 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

8.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE Terminology and guidelines Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 77 NXP Semiconductors

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V

8.4 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. Terminology and guidelines 78 Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 NXP Semiconductors

9 Revision History

The following table provides a revision history for this document. Table 58. Revision History 2 01/2014 Initial public release.

• Updated Table 17 "IRC48M specifications
• Updated Table 35 "VREF full-range operating behavior" 5 12/2014 • Updated Table 6 "Power consumption operating behavior."
• Added a note to the section "Power consumption operating behaviors." 6 08/2015 • Added a footnote to the maximum SCL clock frequency value in the table "I 2C timing"
• Changed the title of the table "I 2C 1 MHZ timing" to "I2C 1 Mbps timing"
• Added a footnote and updated the table "IRC48M specifications" for open loop total deviation of IRC48M frequency at high voltage and low voltage.
• Added a footnote on the ambient temperature entry to the section "Thermal operating requirements."
• Added a note to the section "Power consumption operating behaviors" and updated values in the table "Power consumption operating behaviors."
• Added a note to the maximum frequency value in the table "Slave mode DSPI timing (limited voltage range)."
• Redeveloped the section "Terminology and guidelines." 7 10/2016 • Updated the values of I DD_STOP and IDD_VLLS0 in the table "Power consumption operating behaviors"

Revision History

Kinetis K63F Sub-Family Data Sheet, Rev. 7, 11/2016 79 NXP Semiconductors

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