MK61FX512VMJ15

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Document overview

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• PDF pages: 94

Technical content

Supports the following: MK61FX512VMJ15, MK61FN1M0VMJ15 Key features

• Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
• Performance – Up to 150 MHz Arm® Cortex®-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
• Memories and memory interfaces – Up to 1024 KB program flash memory on non- FlexMemory devices – Up to 512 KB program flash memory on FlexMemory devices – Up to 512 KB FlexNVM on FlexMemory devices – 16 KB FlexRAM on FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface – DDR controller interface – NAND flash controller interface
• Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
• System peripherals – Multiple low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 32-channel DMA controller, supporting up to 128 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
• Security and integrity modules – Hardware CRC module to support fast cyclic redundancy checks – Tamper detect and secure storage – Hardware random-number generator – Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms – 128-bit unique identification (ID) number per chip
• Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
• Analog modules – Four 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – Two 12-bit DACs – Four analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
• Timers – Programmable delay block – Two 8-channel motor control/general purpose/PWM timers – Two 2-channel quadrature decoder/general purpose timers – IEEE 1588 timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock NXP Semiconductors Document Number K61P256M150SF3 Data Sheet: Technical Data Rev. 7, 02/2018 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Communication interfaces – Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability – USB high-/full-/low-speed On-the-Go controller with ULPI interface – USB full-/low-speed On-the-Go controller with on-chip transceiver – USB Device Charger detect (USBDCD) – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital Host Controller (SDHC) – Two I2S modules K61 Sub-Family, Rev. 7, 02/2018

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6.8.7 DSPI switching specifications (limited voltage

K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 3

K61 Sub-Family, Rev. 7, 02/2018

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1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: PK61 and MK61

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q K## A M FFF T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification K## Kinetis family • K61 A Key attribute • F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory FFF Program flash memory size • 512 = 512 KB
• 1M0 = 1 MB Table continues on the next page... Ordering parts K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 5

T Temperature range (°C) • V = –40 to 105

• C = –40 to 85 CC Maximum CPU frequency (MHz) • 15 = 150 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

2.4 Example

This is an example part number: MK61FN1M0VMJ15

3 Terminology and guidelines

3.1 Definitions

Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines K61 Sub-Family, Rev. 7, 02/2018

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3.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE

3.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V Terminology and guidelines K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 7

3.4 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

3.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

4 Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. Ratings K61 Sub-Family, Rev. 7, 02/2018

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4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4.4 Voltage and current operating ratings

Symbol Description Min. Max. Unit VDD Digital supply voltage1 –0.3 3.8 V VDD_INT Core supply voltage –0.3 3.8 V VDD_DDR DDR I/O supply voltage –0.3 3.8 V IDD Digital supply current — 300 mA IDD_INT Core supply current — 185 mA IDD_DDR DDR supply current — 220 mA VDIO Digital input voltage (except RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1) 2 –0.3 5.5 V VDDDR DDR input voltage –0.3 VDD_DDR + 0.3 V VAIO Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input voltage –0.3 VDD + 0.3 V ID Maximum current single pin limit (applies to all digital pins) –25 25 mA VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V VUSB0_DP USB0_DP input voltage –0.3 3.63 V VUSB1_DP USB1_DP input voltage –0.3 3.63 V Table continues on the next page... Ratings K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 9

1. It applies for all port pins except Tamper pins.
2. It covers digital pins except Tamper pins and DDR pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General

5.1 AC electrical characteristics

Figure 1. Input signal measurement reference

• have C L=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)

5.2 Nonswitching electrical specifications

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5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• DDR1
• DDR2/LPDDR1 2.3 1.71 2.7 1.9 V V VREF_DDR Input reference voltage (DDR1/DDR2/ LPDDR1) 0.49 × VDD_DDR VDD_DDR V 1 VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V VBAT RTC battery supply voltage 1.71 3.6 V VIH Input high voltage (digital pins except Tamper pins and DDR pins)
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage (digital pins except Tamper pins and DDR pins)
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VIH_DDR Input high voltage (DDR pins)
• DDR1
• DDR2
• LPDDR1 VREF_DDR + 0.15 VREF_DDR + 0.125 0.7 × VDD_DDR V V V VIL_DDR Input low voltage (DDR pins)
• DDR1
• DDR2
• LPDDR1 VREF_DDR – 0.15 VREF_DDR – 0.125 0.3 × VDD_DDR V V V VHYS Input hysteresis (digital pins except Tamper pins and DDR pins) 0.06 × VDD — V IICDIO Digital pin (except Tamper pins) negative DC injection current — single pin
• V IN < VSS-0.3V -5 — mA IICAIO Analog3, EXTAL0/XTAL0, and EXTAL1/ XTAL1 pin DC injection current — single pin
• V IN < VSS-0.3V (Negative current injection)
• V IN > VDD+0.3V (Positive current injection) mA Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 11

Table 1. Voltage and current operating requirements (continued)

• Negative current injection
• Positive current injection -25 +25 mA VODPU Open drain pullup voltage level VDD VDD V 5 VRAM VDD (VDD_INT) voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. For DDR1/DDR2, connect VREF_DDR to the same reference voltage used for the memory. For LPDDR1, connect VREF_DDR to the VDD_DDR voltage. 2. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 4. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 5. Open drain outputs must be pulled to VDD.

5.2.2 LVD and POR operating requirements

Table 2. LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00) 1.74 1.84 1.80 1.90 1.86 1.96 V V Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018

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Table 2. LVD and POR operating requirements (continued)

• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.94 2.04 2.00 2.10 2.06 2.16 V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -9mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — — 100 mA IOHT_io60 Output high current total for fast digital ports — — 100 mA VOH_DDR Output high voltage for DDR pins
• DDR1 (I OH = -16.2 mA)
• DDR2 half strength (I OH = -5.36 mA)
• DDR2 full strength (I OH = -13.4 mA)
• LPDDR1 half strength (I OH = -0.1 mA)
• LPDDR1 full strength (I OH = -0.1 mA) VDD_DDR - 0.36 VDD_DDR - 0.28 VDD_DDR - 0.28 0.9 x VDD_DDR 0.9 x VDD_DDR V V V V V Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 13

Table 4. Voltage and current operating behaviors (continued)

• DDR1
• DDR2
• LPDDR1 100 mA mA mA VOH_Tamper Output high voltage — high drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -3mA VBAT – 0.5 VBAT – 0.5 V V Output high voltage — low drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -0.6mA VBAT – 0.5 VBAT – 0.5 V V IOH_Tamper Output high current total for Tamper pins — — 100 mA VOL Output low voltage — high drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 5 mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = 2 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 1 mA 0.5 0.5 V V IOLT Output low current total for all ports — — 100 mA IOLT_io60 Output low current total for fast digital ports — — 100 mA VOL_DDR Output low voltage for DDR pins
• DDR1 (I OL = 16.2 mA)
• DDR2 half strength (I OL = 5.36 mA)
• DDR2 full strength (I OL = 13.4 mA)
• LPDDR1 half strength (I OL = 0.1 mA)
• LPDDR1 full strength (I OL = 0.1 mA) 0.37 0.28 0.28 0.1 x VDD_DDR 0.1 x VDD_DDR V V V V V IOLT_DDR Output low current total for DDR pins
• DDR1
• DDR2
• LPDDR1 — — 100 mA mA mA VOL_Tamper Output low voltage — high drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018

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• V SS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32, EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32 0.002 0.004 0.075 0.5 1.5 μA μA μA 1, 2 IIND Input leakage current, digital pins
• V SS ≤ VIN ≤ VIL
• All digital pins
• V IN = VDD
• All digital pins except PTD7
• PTD7 0.002 0.002 0.004 0.5 0.5 μA μA μA 2, 3 IIND Input leakage current, digital pins
• V IL < VIN < VDD
• V DD = 3.6 V
• V DD = 3.0 V
• V DD = 2.5 V
• V DD = 1.7 V μA μA μA μA 2, 3, 4 IIND Input leakage current, digital pins
• V DD < VIN < 5.5 V μA 2, 3 ZIND Input impedance examples, digital pins
• V DD = 3.6 V
• V DD = 3.0 V
• V DD = 2.5 V
• V DD = 1.7 V kΩ kΩ kΩ kΩ 2, 5 IIN_DDR Input leakage current (per DDR pin) for full temperature range — — 1 μA IIN_DDR Input leakage current (per DDR pin) at 25°C — — 0.025 μA IIN_Tamper Input leakage current (per Tamper pin) for full temperature range — — 1 μA IIN_Tamper Input leakage current (per Tamper pin) at 25°C — — 0.025 μA RPU Internal pullup resistors (except Tamper pins) 20 — 50 kΩ 6 RPD Internal pulldown resistors (except Tamper pins) 20 — 50 kΩ 7 RODT On-die termination (ODT) resistance for DDR2
• R tt1(eff) - 75 Ω
• R tt2(eff) - 150 Ω 120 180 Ω Ω General K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 15

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL.
3. Internal pull-up/pull-down resistors disabled.
4. Characterized, not tested in production.
5. Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high
6. Measured at VDD supply voltage = VDD min and Vinput = VSS
7. Measured at VDD supply voltage = VDD min and Vinput = VDD

Figure 2. 5 V Tolerant Input IIND Parameter

5.2.4 Power mode transition operating behaviors

• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

• V DD slew rate ≥ 5.7 kV/s
• V DD slew rate < 5.7 kV/s 300

1.7 V / (VDD

• VLLS1 → RUN — 160 μs
• VLLS2 → RUN — 114 μs Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018

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Table 5. Power mode transition operating behaviors (continued)

• VLLS3 → RUN — 114 μs
• LLS → RUN — 5.0 μs
• VLPS → RUN — 5 μs
• STOP → RUN — 4.8 μs 1. Normal boot (FTFE_FOPT[LPBOOT]=1)

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

• @ 1.8V
• @ 3.0V 58.01 57.93 83.95 84.14 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
• @ 1.8V
• @ 3.0V 89.26 89.23 116.53 117.26 mA mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 40.18 65.25 mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 18.08 42.96 mA 4 IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 1.25 2.93 7.08 1.62 4.39 10.74 mA mA mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.03 4.48 mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled — 1.58 4.96 mA 5 IDD_VLPW Very-low-power wait mode current at 3.0 V — 0.64 4.29 mA 5 IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ –40 to 25°C — 0.22 0.78 0.38 1.33 mA mA Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 17

Table 6. Power consumption operating behaviors (continued)

• @ 70°C
• @ 105°C — 2.18 3.56 mA IDD_LLS Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.22 0.78 2.16 0.37 1.33 3.52 mA mA mA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 4.09 20.98 84.95 5.58 28.93 111.15 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 2.68 8.8 37.28 4.22 10.74 43.61 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 2.46 7.04 30.68 4.02 8.99 37.04 μA μA μA IDD_VBAT Average current when CPU is not accessing RTC registers at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.89 1.28 3.10 1.10 1.85 4.30 μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 150 MHz core and system clock, 75 MHz bus, 50 MHz FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled, but peripherals are not in active operation. 4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 0.5 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 6. Includes 32kHz oscillator current and RTC operation.

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater than 50 MHz frequencies. MCG in PEE mode at greater than 100 MHz frequencies. General K61 Sub-Family, Rev. 7, 02/2018

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• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Figure 3. Run mode supply current vs. core frequency

Figure 4. VLPR mode supply current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors for 256MAPBGA

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

measured orientations in each frequency range.

1. Determined according to IEC Standard JESD78, IC Latch-Up Test

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5.2.7 Designing with radiated emissions in mind

1. Perform a keyword search for “EMC design.”

5.2.8 Capacitance attributes

Table 8. Capacitance attributes

5.3 Switching specifications

5.3.1 Device clock specifications

Table 9. Device clock specifications

• 10 Mbps
• 100 Mbps MHz fBUS Bus clock — 75 MHz FB_CLK FlexBus clock — 50 MHz fFLASH Flash clock — 25 MHz fDDR DDR clock — 150 MHz fLPTMR LPTMR clock — 25 MHz VLPR mode1 Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 21

Table 9. Device clock specifications (continued)

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

5.3.2 General switching specifications

• GPIO signaling
• Other peripheral module signaling not explicitly stated elsewhere

Table 10. General switching specifications

• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled ns ns ns Table continues on the next page... General K61 Sub-Family, Rev. 7, 02/2018

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Table 10. General switching specifications (continued)

• 1.71 ≤ V DD ≤ 2.7V — 24 ns tio50 Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns tio50 Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns tio60 Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns tio60 Port rise and fall time (low drive strength)
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load 6. 25 pF load General K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 23

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

5.4.2 Thermal attributes

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1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions

—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.

1. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental Conditions

—Forced Convection (Moving Air) with the board horizontal.

1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions

—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.

1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

the top of the package and the cold plate.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions

—Natural Convection (Still Air).

5.5 Power sequencing

must power up. Note that VDD and VDD_INT can use the same power source.

6 Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 Debug trace timing specifications

Table 12. Debug trace operating behaviors Table continues on the next page...

Table 12. Debug trace operating behaviors (continued) Figure 5. TRACE_CLKOUT specifications Figure 6. Trace data specifications

6.1.2 JTAG electricals

Table 13. JTAG limited voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan ns ns Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

26 NXP Semiconductors

Table 13. JTAG limited voltage range electricals (continued)

• JTAG and CJTAG
• Serial Wire Debug 10 — ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.4 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns

Table 14. JTAG full voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug 12.5 ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.4 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 27

Figure 7. Test clock input timing Figure 8. Boundary scan (JTAG) timing

28 NXP Semiconductors

Figure 9. Test Access Port timing Figure 10. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

6.3.1 MCG specifications

Table 15. MCG specifications Table continues on the next page...

30 NXP Semiconductors

Table 15. MCG specifications (continued)

• f VCO = 48 MHz
• f VCO = 98 MHz — 150 — tfll_acquire FLL target frequency acquisition time — — 1 ms 6 PLL0,1 fpll_ref PLL reference frequency range 8 — 16 MHz fvcoclk_2x VCO output frequency 180 — 360 MHz fvcoclk PLL output frequency 90 — 180 MHz fvcoclk_90 PLL quadrature output frequency 90 — 180 MHz Ipll PLL0 operating current
• VCO @ 184 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 23) — 2.8 — mA Ipll PLL0 operating current
• VCO @ 360 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) — 4.7 — mA 7 Ipll PLL1 operating current
• VCO @ 184 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 23) — 2.3 — mA 7 Ipll PLL1 operating current
• VCO @ 360 MHz (f osc_hi_1 = 32 MHz, fpll_ref = 8 MHz, VDIV multiplier = 45) — 3.6 — mA 7 tpll_lock Lock detector detection time — — 100 × 10-6 + 1075(1/ fpll_ref) s 8 Jcyc_pll PLL period jitter (RMS)
• f vco = 180 MHz
• f vco = 360 MHz 100 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
• f vco = 180 MHz
• f vco = 360 MHz 600 300 ps ps 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. Accumulated jitter depends on VCO frequency and VDIV. Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 31

6.3.2 Oscillator electrical specifications

6.3.2.1 Oscillator DC electrical specifications

Table 16. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high-gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

32 NXP Semiconductors

Table 16. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

6.3.2.2 Oscillator frequency specifications

Table 17. Oscillator frequency specifications

1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
3. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

cannot be moved into high power/gain mode. Table 18. 32kHz oscillator DC electrical specifications

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. Table 19. 32 kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied

clock must be within the range of VSS to VBAT.

6.4 Memories and memory interfaces

6.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

34 NXP Semiconductors

6.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 20. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

6.4.1.2 Flash timing specifications — commands

Table 21. Flash command timing specifications

• 128 KB data flash
• 256 KB program flash

256 KB data flash

• 128 KB data flash
• 256 KB program flash
• FlexNVM devices
• Program flash only devices 3.4 3.4 ms ms trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 70 — μs tersall Erase All Blocks execution time — 650 5600 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 Swap Control execution time Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 35

Table 21. Flash command timing specifications (continued)

• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08 200 150 150 μs μs μs μs tpgmpart64k tpgmpart256k Program Partition for EEPROM execution time
• 64 KB EEPROM backup
• 256 KB EEPROM backup 235 240 ms ms tsetramff tsetram64k tsetram128k tsetram256k Set FlexRAM Function execution time:
• Control Code 0xFF
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 205 1.6 2.7 4.8 2.5 3.8 6.2 μs ms ms ms t eewr8bers Byte-write to erased FlexRAM location execution time — 140 225 μs 3 teewr8b64k teewr8b128k teewr8b256k Byte-write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 400 450 525 1700 1800 2000 μs μs μs t eewr16bers 16-bit write to erased FlexRAM location execution time — 140 225 μs teewr16b64k teewr16b128k teewr16b256k 16-bit write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 400 450 525 1700 1800 2000 μs μs μs teewr32bers 32-bit write to erased FlexRAM location execution time — 180 275 μs teewr32b64k teewr32b128k teewr32b256k 32-bit write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 475 525 600 1850 2000 2200 μs μs μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

36 NXP Semiconductors

6.4.1.3 Flash high voltage current behaviors

Table 22. Flash high voltage current behaviors

6.4.1.4 Reliability specifications

Table 23. NVM reliability specifications

• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048 70 K 630 K 2.5 M 10 M 175 K 1.6 M 6.4 M 25 M writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM and the allocated EEPROM backup per subsystem. Minimum and typical values assume all 16- bit or 32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.

6.4.1.5 Write endurance to FlexRAM for EEPROM

can be set to any of several non-zero values.

The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFE to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = × Write_efficiency × nEEPROM – 2 × EEESPLIT × EEESIZEEEESPLIT × EEESIZEnvmcycee where

• Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• n nvmcycee — EEPROM-backup cycling endurance Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

38 NXP Semiconductors

Figure 11. EEPROM backup writes to FlexRAM

6.4.2 EzPort switching specifications

Table 24. EzPort switching specifications

Figure 12. EzPort Timing Diagram

6.4.3 NAND flash controller specifications

memory devices. This section describes the timing parameters of the NFC.

• T H is the flash clock high time and
• T L is flash clock low time, which are defined as: input clockT SCALER=NFCT = HTLT + The SCALER value is derived from the fractional divider specified in the SIM's CLKDIV4 register: SCALER = SIM_CLKDIV4[NFCFRAC] + 1 SIM_CLKDIV4[NFCDIV] + 1 In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%, means TH = TL. In case the reciprocal of SCALER is not an integer: (1 + SCALER / 2) x=LT NFCT Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

40 NXP Semiconductors

For example, if SCALER is 0.2, then TH = TL = TNFC/2. However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC. Table 25. NFC specifications

Figure 13. Command latch cycle timing Figure 14. Address latch cycle timing Figure 15. Write data latch cycle timing

42 NXP Semiconductors

Figure 16. Read data latch cycle timing in Slow mode Figure 17. Read data latch cycle timing in Fast mode and EDO mode

6.4.4 DDR controller specifications

DDR memory bus. All timing numbers are relative to the DQS byte lanes. Table 26. DDR controller — AC timing specifications

• DDR1
• DDR2
• LPDDR 83.3 1251 150 150 150 MHz MHz MHz tDDRCK Clock period
• DDR1 6.6 6.6 ns ns Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 43

Table 26. DDR controller — AC timing specifications (continued)

• DDR2
• LPDDR 6.6 20 ns VOX-AC DDRCK AC differential cross point voltage
• DDR1
• DDR2
• LPDDR 0.5 x VDD_DDR – 0.2 V 0.5 x VDD_DDR – 0.125 V 0.4 x VDD_DDR 0.5 x VDD_DDR + 0.2 V 0.5 x VDD_DDR + 0.125 V 0.4 x VDD_DDR V V V tDDRCKH Pulse width high 0.45 0.55 tDDRCK 3 tDDRCKL Pulse width low 0.45 0.55 tDDRCK 3 tCMV Address, DDR_CKE, DDR_CAS, DDR_RAS, DDR_WE, DDR_CSn — output setup 0.5 x tDDRCK – — ns 4 tCMH Address, DDR_CKE, DDR_CAS, DDR_RAS, DDR_WE, DDR_CSn — output hold 0.5 x tDDRCK – — ns tDQSS DQS rising edge to CK rising edge -0.2 x tDDRCK 0.2 x tDDRCK ns tQS Data and data mask output setup (DQ→DQS) relative to DQS (DDR write mode) 0.25 x tDDRCK – — ns 5, 6 tQH Data and data mask output hold (DQS→DQ) relative to DQS (DDR write mode) 0.25 x tDDRCK – — ns 7 tDQSQ DQS-DQ skew for DQS and associated DQ signals – (0.25 x tDDRCK – 1) 0.25 x tDDRCK – ns 8 1. This is minimum frequency of operation according to JEDEC DDR2 specification. 2. DDR data rate = 2 x DDR clock frequency 3. Pulse width high plus pulse width low cannot exceed min and max clock period. 4. Command output setup should be 1/2 the memory bus clock (tDDRCK) plus some minor adjustments for process, temperature, and voltage variations. 5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation. DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0]. 6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats are valid for each subsequent DQS edge. 7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0] 8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

44 NXP Semiconductors

Figure 20. DDR read timing, DQ vs. DQS

6.4.5 Flexbus switching specifications

the same as the internal system bus frequency or an integer divider of that frequency. Table 27. Flexbus limited voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 28. Flexbus full voltage range switching specifications Table continues on the next page...

46 NXP Semiconductors

Table 28. Flexbus full voltage range switching specifications (continued)

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Figure 21. FlexBus read timing diagram

Figure 22. FlexBus write timing diagram

6.5 Security and integrity modules

6.5.1 DryIce Tamper Electrical Specifications

NDA, please contact your local NXP sales representative.

48 NXP Semiconductors

6.6 Analog

6.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 29. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• All other modes VREFL VREFL 31/32 × VREFH VREFH V CADIN Input capacitance • 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes 5 Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 49

Table 29. 16-bit ADC operating conditions (continued)

1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

1. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

time constant should be kept to < 1 ns.

1. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Figure 23. ADC input impedance equivalency diagram

50 NXP Semiconductors

Table 30. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes
• <12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode dB dB Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 51

Table 30. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• Avg = 32 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input ENOB ADC Clock Frequency (MHz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 12 11 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples

Figure 24. Typical ENOB vs. ADC_CLK for 16-bit differential mode

52 NXP Semiconductors

Figure 25. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode Table 31. 16-bit ADC with PGA operating conditions

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. ADC must be configured to use the internal voltage reference (VREF_OUT)
2. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other

than the output of the VREF module, the VREF module must be disabled.

1. For single ended configurations the input impedance of the driven input is RPGAD/2
2. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop

in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.

1. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
2. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
3. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1

Table 32. 16-bit ADC with PGA characteristics

• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 RAS < 100Ω BW Input signal bandwidth
• 16-bit modes
• < 16-bit modes kHz kHz PSRR Power supply rejection ratio Gain=1 — -84 — dB VDDA= 3V ±100mV, Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

54 NXP Semiconductors

Table 32. 16-bit ADC with PGA characteristics (continued)

• Gain=1
• Gain=64 -84 -85 dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage
• Chopping disabled (ADC_PGA[PGACHPb] =1)
• Chopping enabled (ADC_PGA[PGACHPb] =0) 2.4 0.2 mV mV Output offset = VOFS*(Gain+1) TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over full temperature range
• Gain=1
• Gain=64 ppm/°C ppm/°C dG/dVDDA Gain drift over supply voltage
• Gain=1
• Gain=64 0.07 0.14 0.21 0.31 %/V %/V VDDA from 1.71 to 3.6V EIL Input leakage error All modes IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VPP,DIFF Maximum differential input signal swing where VX = VREFPGA × 0.583 V 6 SNR Signal-to-noise ratio
• Gain=1
• Gain=64 dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion
• Gain=1
• Gain=64 100 dB dB 16-bit differential mode, Average=32, fin=100Hz SFDR Spurious free dynamic range
• Gain=1
• Gain=64 105 dB dB 16-bit differential mode, Average=32, fin=100Hz ENOB Effective number of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8 11.6 8.0 7.2 6.3 12.8 13.4 13.6 9.6 9.6 14.5 bits bits bits bits bits 16-bit differential mode,fin=100Hz Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 55

• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32 11.0 7.9 7.3 6.8 6.8 7.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 33. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA Table continues on the next page... Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

56 NXP Semiconductors

Table 33. Comparator and 6-bit DAC electrical specifications (continued)

1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 34. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREF_OUT.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

58 NXP Semiconductors

Table 35. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 59

Figure 28. Typical INL error vs. digital code

60 NXP Semiconductors

Figure 29. Offset at half scale vs. temperature

6.6.4 Voltage reference electrical specifications

Table 36. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of

Table 37. VREF full-range operating behaviors

• current = + 1.0 mA
• current = - 1.0 mA mV 1, 2 Tstup Buffer startup time — — 100 µs Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 38. VREF limited-range operating requirements Table 39. VREF limited-range operating behaviors

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

62 NXP Semiconductors

6.8.1 Ethernet switching specifications

appropriately to arrive at timing specs/constraints for the physical interface.

6.8.1.1 MII signal switching specifications

Table 40. MII signal switching specifications Figure 30. RMII/MII transmit signal timing diagram

Figure 31. RMII/MII receive signal timing diagram

6.8.1.2 RMII signal switching specifications

Table 41. RMII signal switching specifications

6.8.1.3 MDIO serial management timing specifications

Table 42. MDIO serial management channel signal timing

64 NXP Semiconductors

1. MDIO output valid and hold time can be adjusted using the ENET_MSCR[HOLDTIME] field. The minimum specification

Figure 32. MDIO serial management channel timing diagram

6.8.2 USB electrical specifications

crystal for both Device and Host modes. rate specifications for certification.

6.8.3 USB DCD electrical specifications

Table 43. USB0 DCD electrical specifications

6.8.4 USB VREG electrical specifications

Table 44. USB VREG electrical specifications

• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
• Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

6.8.5 ULPI timing specifications

measured with respect to the clock as seen at the USB_CLKIN pin. Table 45. ULPI timing specifications Table continues on the next page...

66 NXP Semiconductors

Table 45. ULPI timing specifications (continued) Figure 33. ULPI timing diagram

6.8.6 CAN switching specifications

See General switching specifications.

6.8.7 DSPI switching specifications (limited voltage range)

for communicating with slower peripheral devices. Table 46. Master mode DSPI timing (limited voltage range)

1. The delay is programmable in DSPIx_CTARn[PSSCK] and DSPIx_CTARn[CSSCK].
2. The delay is programmable in DSPIx_CTARn[PASC] and DSPIx_CTARn[ASC].

Figure 34. DSPI classic DSPI timing — master mode Table 47. Slave mode DSPI timing (limited voltage range) Table continues on the next page...

68 NXP Semiconductors

Table 47. Slave mode DSPI timing (limited voltage range) (continued) Figure 35. DSPI classic DSPI timing — slave mode

6.8.8 DSPI switching specifications (full voltage range)

for communicating with slower peripheral devices. Table 48. Master mode DSPItiming (full voltage range) Table continues on the next page...

Table 48. Master mode DSPItiming (full voltage range) (continued)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 36. DSPI classic SPI timing — master mode Table 49. Slave mode DSPI timing (full voltage range)

70 NXP Semiconductors

Figure 37. DSPI classic SPI timing — slave mode

6.8.9 Inter-Integrated Circuit Interface (I2C) timing

Table 50. I 2C timing Hold time (repeated) START condition.

1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using a pin

configured for high drive across the full voltage range and when using the a pin configured for low drive with VDD ≥ 2.7 V.

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must

= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

1. Cb = total capacitance of the one bus line in pF.

Figure 38. Timing definition for fast and standard mode devices on the I2C bus

6.8.10 UART switching specifications

See General switching specifications.

6.8.11 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 51. SDHC switching specifications over a limited operating voltage range

72 NXP Semiconductors

Table 52. SDHC switching specifications over the full operating voltage range Figure 39. SDHC timing

6.8.12 I2S/SAI switching specifications

frame sync (FS) signal shown in the following figures.

6.8.12.1 Normal Run, Wait and Stop mode performance over a limited

device in Normal Run, Wait and Stop modes. Table 53. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage

74 NXP Semiconductors

Figure 40. I2S/SAI timing — master modes Table 54. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage

• Multiple SAI Synchronous mode
• All other modes ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 75

Figure 41. I2S/SAI timing — slave modes

6.8.12.2 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 55. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage

76 NXP Semiconductors

Figure 42. I2S/SAI timing — master modes Table 56. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage

• Multiple SAI Synchronous mode
• All other modes 20.6 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 5.8 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 77

Figure 43. I2S/SAI timing — slave modes

6.8.12.3 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 57. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

78 NXP Semiconductors

Figure 44. I2S/SAI timing — master modes Table 58. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 45. I2S/SAI timing — slave modes

6.9 Human-machine interfaces (HMI)

6.9.1 TSI electrical specifications

Table 59. TSI electrical specifications

• 2 μA setting (REFCHRG = 0)
• 32 μA setting (REFCHRG = 15) μA 2, 6 IELE Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
• 32 μA setting (EXTCHRG = 15) μA 2, 7 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.008 1.46 — fF/count 11 Res Resolution — — 16 bits TCon20 Response time @ 20 pF 8 15 25 μs 12 ITSI_RUN Current added in run mode — 55 — μA ITSI_LP Low power mode current adder — 1.3 2.5 μA 13 Peripheral operating requirements and behaviors K61 Sub-Family, Rev. 7, 02/2018

80 NXP Semiconductors

1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. VDD = 3.0 V. 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN) The typical value is calculated with the following configuration: Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to nxp.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 256-pin MAPBGA 98ASA00346D

8 Pinout

8.1 Pins with active pull control after reset

The following pins are actively pulled up or down after reset: Dimensions K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 81

Table 60. Pins with active pull control after reset

8.2 K61 Signal Multiplexing and Pin Assignments

for selecting which ALT functionality is available on each pin.

82 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort K1 PTE11 ADC3_SE16ADC3_SE16PTE11 UART5_RTS_ b I2S0_TX_FS FTM3_CH6 K3 PTE12 ADC3_SE17ADC3_SE17PTE12 I2S0_TX_ BCLK FTM3_CH7 G8 VDD VDD VDD H9 VSS VSS VSS J3 PTE16 ADC0_SE4aADC0_SE4aPTE16 SPI0_PCS0UART2_TXFTM_CLKIN0 FTM0_FLT3 K2 PTE17 ADC0_SE5aADC0_SE5aPTE17 SPI0_SCKUART2_RXFTM_CLKIN1 LPTMR0_ ALT3 L4 PTE18 ADC0_SE6aADC0_SE6aPTE18 SPI0_SOUTUART2_CTS_ b I2C0_SDA M3 PTE19 ADC0_SE7aADC0_SE7aPTE19 SPI0_SIN UART2_RTS_ b I2C0_SCL CMP3_OUT L2 VSS VSS VSS M1 USB0_DP USB0_DP USB0_DP M2 USB0_DM USB0_DM USB0_DM L1 VOUT33 VOUT33 VOUT33 L3 VREGIN VREGIN VREGIN N1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 N2 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 P1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 P2 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 R1 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 R2 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 T1 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 T2 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 N5 VDDA VDDA VDDA P4 VREFH VREFH VREFH Pinout K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 83

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort M4 VREFL VREFL VREFL N4 VSSA VSSA VSSA P3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 N3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 T3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 R3 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 R4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 M5 TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B L5 TAMPER1 TAMPER1 TAMPER1 L6 TAMPER2 TAMPER2 TAMPER2 R5 TAMPER3 TAMPER3 TAMPER3 P6 TAMPER4 TAMPER4 TAMPER4 R6 TAMPER5 TAMPER5 TAMPER5 T6 XTAL32 XTAL32 XTAL32 T5 EXTAL32 EXTAL32 EXTAL32 P5 VBAT VBAT VBAT N6 TAMPER6 TAMPER6 TAMPER6 M6 TAMPER7 TAMPER7 TAMPER7 G9 VDD VDD VDD H10 VDDINT VDDINT VDDINT J8 VSS VSS VSS P7 PTE24 ADC0_SE17/ EXTAL1 ADC0_SE17/ EXTAL1 PTE24 CAN1_TX UART4_TXI2S1_TX_FS EWM_OUT_bI2S1_RXD1 R7 PTE25 ADC0_SE18/ XTAL1 ADC0_SE18/ XTAL1 PTE25 CAN1_RX UART4_RXI2S1_TX_ BCLK EWM_IN I2S1_TXD1 M7 PTE26 ADC3_SE5bADC3_SE5bPTE26 ENET_1588_ CLKIN UART4_CTS_ b I2S1_TXD0 RTC_ CLKOUT USB_CLKIN K7 PTE27 ADC3_SE4bADC3_SE4bPTE27 UART4_RTS_ b I2S1_MCLK L7 PTE28 ADC3_SE7aADC3_SE7aPTE28 Pinout K61 Sub-Family, Rev. 7, 02/2018

84 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort T7 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ UART0_COL_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK N8 PTA1 JTAG_TDI/ EZP_DI TSI0_CH2 PTA1 UART0_RXFTM0_CH6 JTAG_TDI EZP_DI T8 PTA2 JTAG_TDO/ TRACE_SWO/ EZP_DO TSI0_CH3 PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO P8 PTA3 JTAG_TMS/ SWD_DIO TSI0_CH4 PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO R8 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b T12 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2RMII0_RXER/ MII0_RXER CMP2_OUTI2S0_TX_ BCLK JTAG_TRST_ b G10 VDD VDD VDD J9 VSS VSS VSS P9 PTF21 ADC3_SE6bADC3_SE6bPTF21 FTM2_CH1UART5_RTS_ b N9 PTF22 ADC3_SE7bADC3_SE7bPTF22 I2C0_SCL FTM1_CH0UART5_CTS_ b R12 PTA6 ADC3_SE6aADC3_SE6aPTA6 ULPI_CLK FTM0_CH3I2S1_RXD0 TRACE_ CLKOUT P12 PTA7 ADC0_SE10ADC0_SE10PTA7 ULPI_DIR FTM0_CH4I2S1_RX_ BCLK TRACE_D3 N12 PTA8 ADC0_SE11ADC0_SE11PTA8 ULPI_NXTFTM1_CH0I2S1_RX_FS FTM1_QD_ PHA TRACE_D2 T13 PTA9 ADC3_SE5aADC3_SE5aPTA9 ULPI_STP FTM1_CH1MII0_RXD3 FTM1_QD_ PHB TRACE_D1 P13 PTA10 ADC3_SE4aADC3_SE4aPTA10 ULPI_DATA0FTM2_CH0MII0_RXD2 FTM2_QD_ PHA TRACE_D0 R13 PTA11 ADC3_SE15ADC3_SE15PTA11 ULPI_DATA1FTM2_CH1MII0_RXCLK FTM2_QD_ PHB M10 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0RMII0_RXD1/ MII0_RXD1 I2S0_TXD0FTM1_QD_ PHA N10 PTA13/ LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RX FTM1_CH1RMII0_RXD0/ MII0_RXD0 I2S0_TX_FSFTM1_QD_ PHB R11 PTA14 CMP3_IN0CMP3_IN0PTA14 SPI0_PCS0UART0_TXRMII0_CRS_ DV/ MII0_RXDV I2S0_RX_ BCLK I2S0_TXD1 P11 PTA15 CMP3_IN1CMP3_IN1PTA15 SPI0_SCKUART0_RXRMII0_TXEN/ MII0_TXEN I2S0_RXD0 T14 VSS VSS VSS N11 PTA16 CMP3_IN2CMP3_IN2PTA16 SPI0_SOUTUART0_CTS_ UART0_COL_ b RMII0_TXD0/ MII0_TXD0 I2S0_RX_FSI2S0_RXD1 Pinout K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 85

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort T11 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS_ b RMII0_TXD1/ MII0_TXD1 I2S0_MCLK P10 PTF23 ADC3_SE10ADC3_SE10PTF23 I2C0_SDA FTM1_CH1 TRACE_ CLKOUT R10 PTF24 ADC3_SE11ADC3_SE11PTF24 CAN1_RX FTM1_QD_ PHA TRACE_D3 R9 PTF25 ADC3_SE12ADC3_SE12PTF25 CAN1_TX FTM1_QD_ PHB TRACE_D2 T9 PTF26 ADC3_SE13ADC3_SE13PTF26 FTM2_QD_ PHA TRACE_D1 T10 PTF27 ADC3_SE14ADC3_SE14PTF27 FTM2_QD_ PHB TRACE_D0 J7 VDD VDD VDD K8 VSS VSS VSS T15 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 T16 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ ALT1 R16 RESET_b RESET_b RESET_b N13 PTA24 CMP3_IN4CMP3_IN4PTA24 ULPI_DATA2 MII0_TXD2 FB_A29 R14 PTA25 CMP3_IN5CMP3_IN5PTA25 ULPI_DATA3 MII0_TXCLK FB_A28 M13 PTA26 ADC2_SE15ADC2_SE15PTA26 ULPI_DATA4 MII0_TXD3 FB_A27 R15 PTA27 ADC2_SE14ADC2_SE14PTA27 ULPI_DATA5 MII0_CRS FB_A26 P14 PTA28 ADC2_SE13ADC2_SE13PTA28 ULPI_DATA6 MII0_TXER FB_A25 N14 PTA29 ADC2_SE12ADC2_SE12PTA29 ULPI_DATA7 MII0_COL FB_A24 P16 PTF0 ADC2_SE11ADC2_SE11PTF0 CAN0_TX FTM3_CH0 I2S1_RXD1 L13 PTF1 ADC2_SE10ADC2_SE10PTF1 CAN0_RX FTM3_CH1 I2S1_RX_ BCLK M12 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ ADC2_SE8/ ADC3_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0RMII0_MDIO/ MII0_MDIO FTM1_QD_ PHA M11 PTB1 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ ADC2_SE9/ ADC3_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1RMII0_MDC/ MII0_MDC FTM1_QD_ PHB P15 PTB2 ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_ b ENET0_1588_ TMR0 FTM0_FLT3 M14 PTB3 ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ UART0_COL_ b ENET0_1588_ TMR1 FTM0_FLT0 N15 PTB4 ADC1_SE10ADC1_SE10PTB4 ENET0_1588_ TMR2 FTM1_FLT0 M15 PTB5 ADC1_SE11ADC1_SE11PTB5 ENET0_1588_ TMR3 FTM2_FLT0 Pinout K61 Sub-Family, Rev. 7, 02/2018

86 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort L14 PTB6 ADC1_SE12ADC1_SE12PTB6 FB_AD23 L15 PTB7 ADC1_SE13ADC1_SE13PTB7 FB_AD22 K14 PTB8 DISABLED PTB8 UART3_RTS_ b FB_AD21 K15 PTB9 DISABLED PTB9 SPI1_PCS1UART3_CTS_ b FB_AD20 J13 PTB10 ADC1_SE14ADC1_SE14PTB10 SPI1_PCS0UART3_RXI2S1_TX_ BCLK FB_AD19 FTM0_FLT1 J14 PTB11 ADC1_SE15ADC1_SE15PTB11 SPI1_SCKUART3_TXI2S1_TX_FSFB_AD18 FTM0_FLT2 K9 VSS VSS VSS J10 VDD VDD VDD N16 PTF2 ADC2_SE6aADC2_SE6aPTF2 I2C1_SCL FTM3_CH2 I2S1_RX_FS M16 PTF3 ADC2_SE7aADC2_SE7aPTF3 I2C1_SDA FTM3_CH3 I2S1_RXD0 L16 PTF4 ADC2_SE4bADC2_SE4bPTF4 FTM3_CH4 I2S1_TXD0 J15 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUTUART0_RXI2S1_TXD0FB_AD17 EWM_IN H13 PTB17 TSI0_CH10TSI0_CH10PTB17 SPI1_SIN UART0_TXI2S1_TXD1FB_AD16 EWM_OUT_b H14 PTB18 TSI0_CH11TSI0_CH11PTB18 CAN0_TX FTM2_CH0I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA K16 PTF5 ADC2_SE5bADC2_SE5bPTF5 FTM3_CH5 I2S1_TX_FS J16 PTF6 ADC2_SE6bADC2_SE6bPTF6 FTM3_CH6 I2S1_TX_ BCLK H15 PTB19 TSI0_CH12TSI0_CH12PTB19 CAN0_RX FTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_ PHB G13 PTB20 ADC2_SE4aADC2_SE4aPTB20 SPI2_PCS0 FB_AD31/ NFC_DATA15 CMP0_OUT G14 PTB21 ADC2_SE5aADC2_SE5aPTB21 SPI2_SCK FB_AD30/ NFC_DATA14 CMP1_OUT G15 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29/ NFC_DATA13 CMP2_OUT H16 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28/ NFC_DATA12 CMP3_OUT G16 PTC0 ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXTRG FB_AD14/ NFC_DATA11 I2S0_TXD1 F13 PTC1/ LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_RTS_ b FTM0_CH0FB_AD13/ NFC_DATA10 I2S0_TXD0 F14 PTC2 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CTS_ b FTM0_CH1FB_AD12/ NFC_DATA9 I2S0_TX_FS E13 PTC3/ LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK F15 PTF7 ADC2_SE7bADC2_SE7bPTF7 FTM3_CH7UART3_RXI2S1_TXD1 L9 VSS VSS VSS K10 VDD VDD VDD F16 PTF8 DISABLED PTF8 FTM3_FLT0UART3_TXI2S1_MCLK Pinout K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 87

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E14 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11/ NFC_DATA8 CMP1_OUTI2S1_TX_ BCLK E15 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0FB_AD10/ NFC_DATA7 CMP0_OUTI2S1_TX_FS F12 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_EXTRGI2S0_RX_ BCLK FB_AD9/ NFC_DATA6 I2S0_MCLK G12 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FSFB_AD8/ NFC_DATA5 H12 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4I2S0_MCLKFB_AD7/ NFC_DATA4 F11 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5I2S0_RX_ BCLK FB_AD6/ NFC_DATA3 FTM2_FLT0 G11 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCL FTM3_CH6I2S0_RX_FSFB_AD5/ NFC_DATA2 I2S1_MCLK H11 PTC11/ LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDA FTM3_CH7I2S0_RXD1FB_RW_b/ NFC_WE J12 PTC12 DISABLED PTC12 UART4_RTS_ b FB_AD27 FTM3_FLT0 K13 PTC13 DISABLED PTC13 UART4_CTS_ b FB_AD26 J11 PTC14 DISABLED PTC14 UART4_RX FB_AD25 K12 PTF9 CMP2_IN4CMP2_IN4PTF9 UART3_RTS_ b L12 PTF10 CMP2_IN5CMP2_IN5PTF10 UART3_CTS_ b F10 PTC15 DISABLED PTC15 UART4_TX FB_AD24 N7 VSS VSS VSS L10 VDD VDD VDD K11 PTF11 DISABLED PTF11 UART2_RTS_ b L11 PTF12 DISABLED PTF12 UART2_CTS_ b F9 PTC16 DISABLED PTC16 CAN1_RX UART3_RXENET0_1588_ TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_16_ b NFC_RB E9 PTC17 DISABLED PTC17 CAN1_TX UART3_TXENET0_1588_ TMR1 FB_CS4_b/ FB_TSIZ0/ FB_BE31_24_ b NFC_CE0_b M9 PTC18 DISABLED PTC18 UART3_RTS_ b ENET0_1588_ TMR2 FB_TBST_b/ FB_CS2_b/ FB_BE15_8_b NFC_CE1_b M8 PTC19 DISABLED PTC19 UART3_CTS_ b ENET0_1588_ TMR3 FB_CS3_b/ FB_BE7_0_b FB_TA_b L8 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_RTS_ b FTM3_CH0FB_ALE/ FB_CS1_b/ FB_TS_b I2S1_RXD1 Pinout K61 Sub-Family, Rev. 7, 02/2018

88 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort F8 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_CTS_ b FTM3_CH1FB_CS0_bI2S1_RXD0 K6 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RXFTM3_CH2FB_AD4 I2S1_RX_FS J6 PTD3 DISABLED PTD3 SPI0_SIN UART2_TXFTM3_CH3FB_AD3 I2S1_RX_ BCLK K5 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_RTS_ b FTM0_CH4FB_AD2/ NFC_DATA1 EWM_IN J5 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_CTS_ UART0_COL_ b FTM0_CH5FB_AD1/ NFC_DATA0 EWM_OUT_b K4 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0 H6 PTF13 DISABLED PTF13 UART2_RX G6 PTF14 DISABLED PTF14 UART2_TX T4 VSS VSS VSS E7 PTD7 DISABLED PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1 J4 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16/ NFC_CLE F7 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17/ NFC_ALE E6 PTD10 DISABLED PTD10 UART5_RTS_ b FB_A18/ NFC_RE G5 PTD11 DISABLED PTD11 SPI2_PCS0UART5_CTS_ b SDHC0_ CLKIN FB_A19 F5 PTD12 DISABLED PTD12 SPI2_SCKFTM3_FLT0SDHC0_D4 FB_A20 F4 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 E5 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 E4 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23 F6 PTF15 DISABLED PTF15 UART0_RTS_ b E1 PTF16 DISABLED PTF16 SPI2_PCS0FTM0_CH3UART0_CTS_ UART0_COL_ b B1 DDR_VDDDDR_VDD DDR_VDD A1 DDR_VSS DDR_VSS DDR_VSS D3 DDR_DQS1DISABLED DDR_DQS1 D1 DDR_DQ8DISABLED DDR_DQ8 C1 DDR_DQ9DISABLED DDR_DQ9 B5 DDR_VDDDDR_VDD DDR_VDD A5 DDR_VSS DDR_VSS DDR_VSS D5 DDR_VSS DDR_VSS DDR_VSS C2 DDR_DQ10DISABLED DDR_DQ10 Pinout K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 89

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort B2 DDR_DQ11DISABLED DDR_DQ11 C3 DDR_DQ12DISABLED DDR_DQ12 B8 DDR_VDDDDR_VDD DDR_VDD A12 DDR_VSS DDR_VSS DDR_VSS C4 DDR_DQ13DISABLED DDR_DQ13 B3 DDR_DQ14DISABLED DDR_DQ14 A2 DDR_DQ15DISABLED DDR_DQ15 A3 DDR_DM1DISABLED DDR_DM1 E8 DDR_VSS DDR_VSS DDR_VSS B12 DDR_VDDDDR_VDD DDR_VDD A16 DDR_VSS DDR_VSS DDR_VSS C6 DDR_VREFDDR_VREF DDR_VREF C5 DDR_DQ0DISABLED DDR_DQ0 B4 DDR_DQ1DISABLED DDR_DQ1 A4 DDR_DQ2DISABLED DDR_DQ2 C16 DDR_VDDDDR_VDD DDR_VDD C7 DDR_VSS DDR_VSS DDR_VSS B6 DDR_DQ3DISABLED DDR_DQ3 D6 DDR_DQ4DISABLED DDR_DQ4 A6 DDR_DQ5DISABLED DDR_DQ5 A7 DDR_ODTDISABLED DDR_ODT E11 DDR_VSS DDR_VSS DDR_VSS D2 DDR_VDDDDR_VDD DDR_VDD C9 DDR_VSS DDR_VSS DDR_VSS B7 DDR_DQ6DISABLED DDR_DQ6 A8 DDR_DQ7DISABLED DDR_DQ7 C8 DDR_DQS0DISABLED DDR_DQS0 D9 DDR_DM0DISABLED DDR_DM0 D4 DDR_VDDDDR_VDD DDR_VDD C14 DDR_VSS DDR_VSS DDR_VSS A9 DDR_BA0 DISABLED DDR_BA0 B10 DDR_BA1 DISABLED DDR_BA1 B9 DDR_BA2 DISABLED DDR_BA2 A10 DDR_CKBDISABLED DDR_CKB A11 DDR_CK DISABLED DDR_CK D7 DDR_VDDDDR_VDD DDR_VDD D8 DDR_VSS DDR_VSS DDR_VSS D10 DDR_A0 DISABLED DDR_A0 C11 DDR_A1 DISABLED DDR_A1 B11 DDR_A2 DISABLED DDR_A2 Pinout K61 Sub-Family, Rev. 7, 02/2018

90 NXP Semiconductors

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort C12 DDR_A3 DISABLED DDR_A3 E10 DDR_VDDDDR_VDD DDR_VDD D12 DDR_VSS DDR_VSS DDR_VSS C10 DDR_A4 DISABLED DDR_A4 A13 DDR_A5 DISABLED DDR_A5 A14 DDR_A6 DISABLED DDR_A6 D11 DDR_A7 DISABLED DDR_A7 A15 DDR_A8 DISABLED DDR_A8 E12 DDR_VDDDDR_VDD DDR_VDD E3 DDR_VSS DDR_VSS DDR_VSS B16 DDR_CKEDISABLED DDR_CKE B15 DDR_A9 DISABLED DDR_A9 B13 DDR_A10 DISABLED DDR_A10 B14 DDR_A11 DISABLED DDR_A11 C15 DDR_A12 DISABLED DDR_A12 D16 DDR_A13 DISABLED DDR_A13 D15 DDR_A14 DISABLED DDR_A14 E16 DDR_RAS_BDISABLED DDR_RAS_B C13 DDR_CAS_BDISABLED DDR_CAS_B D14 DDR_CS_BDISABLED DDR_CS_B D13 DDR_WE_BDISABLED DDR_WE_B

8.3 K61 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 91

A DDR_VSS B DDR_VDD C DDR_DQ9 D DDR_DQ8 E PTF16 F PTF17 G PTF18 H PTF19 J PTE9 K PTE11 L VOUT33 M USB0_DP N PGA2_DP/ ADC2_DP0/ ADC3_DP3/ ADC0_DP1 P PGA3_DP/ ADC3_DP0/ ADC2_DP3/ ADC1_DP1 R PGA0_DP/ ADC0_DP0/ ADC1_DP3 T PGA1_DP/ ADC1_DP0/ ADC0_DP3 DDR_DQ15 DDR_DQ11 DDR_DQ10 DDR_VDD PTE0 PTE1/ LLWU_P0 PTE3 PTE6 PTE10 PTE17 VSS USB0_DM PGA2_DM/ ADC2_DM0/ ADC3_DM3/ ADC0_DM1 PGA3_DM/ ADC3_DM0/ ADC2_DM3/ ADC1_DM1 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 DDR_DM1 DDR_DQ14 DDR_DQ12 DDR_DQS1 DDR_VSS PTE2/ LLWU_P1 PTE4/ LLWU_P2 PTE7 PTE16 PTE12 VREGIN PTE19 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 DDR_DQ2 DDR_DQ1 DDR_DQ13 DDR_VDD PTD15 PTD13 PTE5 PTE8 PTD8 PTD6/ LLWU_P15 PTE18 VREFL VSSA VREFH DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 VSS DDR_VSS DDR_VDD DDR_DQ0 DDR_VSS PTD14 PTD12 PTD11 PTF20 PTD5 PTD4/ LLWU_P14 TAMPER1 TAMPER0/ RTC_ WAKEUP_B VDDA VBAT TAMPER3 EXTAL32 DDR_DQ5 DDR_DQ3 DDR_VREF DDR_DQ4 PTD10 PTF15 PTF14 PTF13 PTD3 PTD2/ LLWU_P13 TAMPER2 TAMPER7 TAMPER6 TAMPER4 TAMPER5 XTAL32 DDR_ODT DDR_DQ6 DDR_VSS DDR_VDD PTD7 PTD9 VDD VDDINT VDD PTE27 PTE28 PTE26 VSS PTE24 PTE25 PTA0 DDR_DQ7 DDR_VDD DDR_DQS0 DDR_VSS DDR_VSS PTD1 VDD VSS VSS VSS PTD0/ LLWU_P12 PTC19 PTA1 PTA3 PTA4/ LLWU_P3 PTA2 DDR_BA0 DDR_BA2 DDR_VSS DDR_DM0 PTC17 PTC16 VDD VSS VSS VSS VSS PTC18 PTF22 PTF21 PTF25 PTF26 DDR_CKB DDR_BA1 DDR_A4 DDR_A0 DDR_VDD PTC15 VDD VDDINT VDD VDD VDD PTA12 PTA13/ LLWU_P4 PTF23 PTF24 PTF27 DDR_CK DDR_A2 DDR_A1 DDR_A7 DDR_VSS PTC9 PTC10 PTC11/ LLWU_P11 PTC14 PTF11 PTF12 PTB1 PTA16 PTA15 PTA14 PTA17 DDR_VSS DDR_VDD DDR_A3 DDR_VSS DDR_VDD PTC6/ LLWU_P10 PTC7 PTC8 PTC12 PTF9 PTF10 PTB0/ LLWU_P5 PTA8 PTA7 PTA6 PTA5 DDR_A5 DDR_A10 DDR_CAS_B DDR_WE_B PTC3/ LLWU_P7 PTC1/ LLWU_P6 PTB20 PTB17 PTB10 PTC13 PTF1 PTA26 PTA24 PTA10 PTA11 PTA9 DDR_A6 DDR_A11 DDR_VSS DDR_CS_B PTC4/ LLWU_P8 PTC2 PTB21 PTB18 PTB11 PTB8 PTB6 PTB3 PTA29 PTA28 PTA25 VSS DDR_A8 DDR_A9 DDR_A12 DDR_A14 PTC5/ LLWU_P9 PTF7 PTB22 PTB19 PTB16 PTB9 PTB7 PTB5 PTB4 PTB2 PTA27 PTA18 ADDR_VSS BDDR_CKE CDDR_VDD DDDR_A13 EDDR_ RAS_B FPTF8 GPTC0 HPTB23 JPTF6 KPTF5 LPTF4 MPTF3 NPTF2 PPTF0 RRESET_b TPTA19 Figure 46. K61 256 MAPBGA Pinout Diagram

9 Revision History

The following table provides a revision history for this document.

Revision History

K61 Sub-Family, Rev. 7, 02/2018

92 NXP Semiconductors

Table 61. Revision History 4 10/2012 Replaced TBDs throughout.

• Min VDD operating requirement specification updated to support operation down to 1.71V. New specifications:
• Updated Vdd_ddr min specification.
• Added Vodpu specification.
• Removed Ioz, Ioz_ddr, and Ioz_tamper Hi-Z leakage specfications. They have been replaced by new Iina, Iind, and Zind specifications.
• Fpll_ref_acc specification has been added.
• I 2C module was previously covered by the general switching specifications. To provide more detail on I2C operation a dedicated Inter-Integrated Circuit Interface (I2C) timing section has been added. Modified specifications:
• Vref_ddr max spec has been updated.
• Tpor spec has been split into two specifications based on VDD slew rate.
• Trd1allx and Trd1alln max have been updated.
• 16-bit ADC Temp sensor slope and Temp sensor voltage (Vtemp25) have been modified. The typical values that were listed previously have been updated, and min and max specifications have been added. Corrections:
• Some versions of the datasheets listed incorrect clock mode information in the "Diagram: Typical IDD_RUN operating behavior section." These errors have been corrected.
• Fintf_ft specification was previously shown as a max value. It has been corrected to be shown as a typical value as originally intended.
• Corrected DDR write and read timing diagrams to show the correct location of the Tcmv specification.
• SDHC peripheral 50MHz high speed mode options were left out of the last datasheet. These have been added to the SDHC specifications section. 6 09/2015 • Updated Power Sequencing section
• Added footnote to ambient temperature specification of Thermal Operating requirements
• Updated the data and DQS waveforms in DDR read timing diagram
• Removed "USB HS/LS/FS on-the-go controller with on-chip high speed transceiver" from features section
• Updated Terminology and guidelines section
• Updated the footnotes and the values of Power consumption operating behaviors table
• Added Notes in USB electrical specification section
• Updated I2C timing table 7 02/2018 • Updated maximum SDHC frequency in SDHC specifications
• Added MDIO serial management timing specifications section in Ethernet Switching SPecifications

K61 Sub-Family, Rev. 7, 02/2018 NXP Semiconductors 93

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