MK60DN512ZVLL10

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Technical content

Datasheet sections

• 1.1 Overview
• 1.1.1 Purpose
• 1.1.2 Audience
• 1.2 Conventions
• 1.2.1 Numbering systems
• 1.2.2 Typographic notation
• 1.2.3 Special terms
• 2.1 Overview
• 2.2 K60 Family Introduction
• 2.3 Module Functional Categories
• 2.3.1 ARM Cortex-M4 Core Modules
• 2.3.2 System Modules
• 2.3.3 Memories and Memory Interfaces
• 2.3.4 Clocks
• 2.3.5 Security and Integrity modules
• 2.3.6 Analog modules
• 2.3.7 Timer modules
• 2.3.8 Communication interfaces
• 2.3.9 Human-machine interfaces
• 2.4 Orderable part numbers
• 3.1 Introduction

K60 Sub-Family Reference Manual Supports: MK60DN256ZVLL10, MK60DX256ZVLL10, MK60DN512ZVLL10 Document Number: K60P100M100SF2RM Rev. 6, Nov 2011

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 2 Freescale Semiconductor, Inc.

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Signal Multiplexing and Signal Descriptions Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 10 Freescale Semiconductor, Inc.

System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 11

Power Management Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 12 Freescale Semiconductor, Inc.

Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 13

Miscellaneous Control Module (MCM) Chapter 17 Crossbar Switch (AXBS) Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 14 Freescale Semiconductor, Inc.

Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 15

Direct memory access multiplexer (DMAMUX) Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 16 Freescale Semiconductor, Inc.

21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

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21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 18 Freescale Semiconductor, Inc.

Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 19

Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 20 Freescale Semiconductor, Inc.

Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 21

Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 22 Freescale Semiconductor, Inc.

Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 23

External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 24 Freescale Semiconductor, Inc.

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Cyclic redundancy check (CRC) Chapter 32 Memory-Mapped Cryptographic Acceleration Unit (MMCAU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 26 Freescale Semiconductor, Inc.

Random Number Generator (RNGB) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 27

Analog-to-Digital Converter (ADC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 28 Freescale Semiconductor, Inc.

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 29

Comparator (CMP) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 30 Freescale Semiconductor, Inc.

12-bit Digital-to-Analog Converter (DAC) Chapter 37 Voltage Reference (VREFV1) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 31

Programmable Delay Block (PDB) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 32 Freescale Semiconductor, Inc.

FlexTimer (FTM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 33

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Periodic Interrupt Timer (PIT) Chapter 41 Low power timer (LPTMR) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 36 Freescale Semiconductor, Inc.

Carrier Modulator Transmitter (CMT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 37

Real Time Clock (RTC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 38 Freescale Semiconductor, Inc.

10/100-Mbps Ethernet MAC (ENET) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 39

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Universal Serial Bus OTG Controller (USBOTG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 41

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USB Device Charger Detection Module (USBDCD) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 43

CAN (FlexCAN) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 44 Freescale Semiconductor, Inc.

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SPI (DSPI) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 46 Freescale Semiconductor, Inc.

Inter-Integrated Circuit (I2C) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 47

Universal Asynchronous Receiver/Transmitter (UART) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 48 Freescale Semiconductor, Inc.

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Secured digital host controller (SDHC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 50 Freescale Semiconductor, Inc.

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Integrated interchip sound (I2S) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 53

General purpose input/output (GPIO) Chapter 55 Touch sense input (TSI) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 54 Freescale Semiconductor, Inc.

JTAG Controller (JTAGC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 55

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 56 Freescale Semiconductor, Inc.

1.1.1 Purpose

This document describes the features, architecture, and programming model of the Freescale K60 microcontroller.

1.1.2 Audience

This document is primarily for system architects and software application developers who are using or considering using the K60 microcontroller in a system. Conventions

1.2.1 Numbering systems

The following suffixes identify different numbering systems: This suffix Identifies a b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b. d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix. h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. 1.1 1.2 K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 57

1.2.2 Typographic notation

The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers. code Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR. SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the Scaling Mode (SCM) field in the Status Register (SR). REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:

• A subset of a register's named field For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7–0 of the XAD bus.

1.2.3 Special terms

The following terms have special meanings: Term Meaning asserted Refers to the state of a signal as follows:

• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0). deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1). In some cases, deasserted signals are described as negated. reserved Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. Conventions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 58 Freescale Semiconductor, Inc.

2.1 Overview

This chapter provides an overview of the Kinetis portfolio and K60 family of products. It also presents high-level descriptions of the modules available on the devices covered by this document.

2.2 K60 Family Introduction

The K60 MCU family includes IEEE 1588 Ethernet, full- and high-speed USB 2.0 On- The-Go with device charger detect capability, hardware encryption and tamper detection capabilities. Devices start from 256 KB of flash in 100LQFP packages extending up to 1 MB in a 256MAPBGA package with a rich suite of analog, communication, timing and control peripherals. High memory density K60 family devices include an optional single precision floating point unit, NAND flash controller and DRAM controller.

2.3 Module Functional Categories

The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ARM Cortex-M4 core • 32-bit MCU core from ARM’s Cortex-M class adding DSP instructions, 1.25 DMIPS/MHz, based on ARMv7 architecture Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 59

Table 2-1. Module functional categories (continued) Module category Description System • System integration module

• Power management and mode controllers
• Multiple power modes available based on run, wait, stop, and power- down modes
• Low-leakage wakeup unit
• Miscellaneous control module
• Crossbar switch
• Memory protection unit
• Peripheral bridge
• Direct memory access (DMA) controller with multiplexer to increase available DMA requests
• External watchdog monitor
• Watchdog Memories • Internal memories include:
• Program flash memory
• On devices with FlexMemory: FlexMemory
• FlexNVM
• FlexRAM
• On devices with program flash only: Programming acceleration RAM
• SRAM
• External memory or peripheral bus interface: FlexBus
• Serial programming interface: EzPort Clocks • Multiple clock generation options available from internally- and externally- generated clocks
• System oscillator to provide clock source for the MCU
• RTC oscillator to provide clock source for the RTC Security • Cyclic Redundancy Check module for error detection
• Hardware encryption, along with a random number generator Analog • High speed analog-to-digital converter with integrated programmable gain amplifier
• Comparator
• Digital-to-analog converter
• Internal voltage reference Timers • Programmable delay block
• FlexTimers
• Periodic interrupt timer
• Low power timer
• Carrier modulator transmitter
• Independent real time clock Communications • Ethernet MAC with IEEE 1588 capability
• USB OTG controller with built-in FS/LS transceiver
• USB device charger detect
• USB voltage regulator
• CAN
• Serial peripheral interface
• Inter-integrated circuit (I 2C)
• UART
• Secured Digital host controller
• Integrated interchip sound (I 2S) Human-Machine Interfaces (HMI) • General purpose input/output controller
• Capacitive touch sense input interface enabled in hardware Module Functional Categories K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 60 Freescale Semiconductor, Inc.

2.3.1 ARM Cortex-M4 Core Modules

The following core modules are available on this device. Table 2-2. Core modules Module Description ARM Cortex-M4 The ARM Cortex-M4 is the newest member of the Cortex M Series of processors targeting microcontroller cores focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M4 processor is based on the ARMv7 Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing 32-bit instructions with SIMD (single instruction multiple data) DSP style multiply- accumulates and saturating arithmetic. NVIC The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels. The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts. AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing. Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. Four debug interfaces are supported:

• IEEE 1149.1 JTAG
• IEEE 1149.7 JTAG (cJTAG)
• Serial Wire Debug (SWD)
• ARM Real-Time Trace Interface

2.3.2 System Modules

The following system modules are available on this device. Table 2-3. System modules Module Description System integration module (SIM) The SIM includes integration logic and several module configuration settings. Mode controller The MC provides control and protection on entry and exit to each power mode, control for the Power management controller (PMC), and reset entry and exit for the complete MCU. Table continues on the next page... Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 61

Table 2-3. System modules (continued) Module Description Power management controller (PMC) The PMC provides the user with multiple power options. Ten different modes are supported that allow the user to optimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points. Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and VLLS) through various internal peripheral and external pin sources. Miscellaneous control module (MCM) The MCM includes integration logic and embedded trace buffer details. Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access different bus slaves simultaneously and providing arbitration among the bus masters when they access the same slave. Memory protection unit (MPU) The MPU provides memory protection and task isolation. It concurrently monitors all bus master transactions for the slave connections. Peripheral bridges The peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device. DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 16 for the DMA controller. Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128- bit data values. External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that monitors both internal and external system operation for fail conditions. Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of failure. It can run from an independent 1 KHz low power oscillator with a programmable refresh window to detect deviations in program flow or system frequency.

2.3.3 Memories and Memory Interfaces

The following memories and memory interfaces are available on this device. Table 2-4. Memories and memory interfaces Module Description Flash memory • Program flash memory — non-volatile flash memory that can execute program code

• FlexMemory — encompasses the following memory types:
• For devices with FlexNVM: FlexNVM — Non-volatile flash memory that can execute program code, store data, or backup EEPROM data
• For devices with FlexNVM: FlexRAM — RAM memory that can be used as traditional RAM or as high-endurance EEPROM storage, and also accelerates flash programming
• For devices with only program flash memory: Programming acceleration RAM — RAM memory that accelerates flash programming Flash memory controller Manages the interface between the device and the on-chip flash memory. Table continues on the next page... Module Functional Categories K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 62 Freescale Semiconductor, Inc.

Table 2-4. Memories and memory interfaces (continued) Module Description SRAM Internal system RAM. Partial SRAM kept powered in VLLS2 low leakage mode. SRAM controller Manages simultaneous accesses to system RAM by multiple master peripherals and core. System register file 32-byte register file that is accessible during all power modes and is powered by VDD. VBAT register file 32-byte register file that is accessible during all power modes and is powered by VBAT. Serial programming interface (EzPort) Same serial interface as, and subset of, the command set used by industry- standard SPI flash memories. Provides the ability to read, erase, and program flash memory and reset command to boot the system after flash programming. FlexBus External bus interface with multiple independent, user-programmable chip-select signals that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals via 8-, 16- and 32-bit port sizes. Configurations include multiplexed or non-multiplexed address and data buses using 8-bit, 16-bit, 32-bit, and 16-byte line-sized transfers.

2.3.4 Clocks

The following clock modules are available on this device. Table 2-5. Clock modules Module Description Multi-clock generator (MCG) The MCG provides several clock sources for the MCU that include:

• Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO)
• Frequency-locked loop (FLL) — Digitally-controlled oscillator (DCO)
• Internal reference clocks — Can be used as a clock source for other on-chip peripherals System oscillator The system oscillator, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. Real-time clock oscillator The RTC oscillator has an independent power supply and supports a 32 kHz crystal oscillator to feed the RTC clock. Optionally, the RTC oscillator can replace the system oscillator as the main oscillator source.

2.3.5 Security and Integrity modules

The following security and integrity modules are available on this device: Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 63

Table 2-6. Security and integrity modules Module Description Cryptographic acceleration unit (CAU) Supports DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms via simple C calls to optimized security functions provided by Freescale. Random number generator (RNG) Supports the key generation algorithm defined in the Digital Signature Standard. Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all single, double, odd, and most multi-bit errors, programmable initial seed value, and optional feature to transpose input data and CRC result via transpose register.

2.3.6 Analog modules

The following analog modules are available on this device: Table 2-7. Analog modules Module Description 16-bit analog-to-digital converters (ADC) and programmable-gain amplifiers (PGA) 16-bit successive-approximation ADC designed with integrated programmable gain amplifiers (PGA) Analog comparators Compares two analog input voltages across the full range of the supply voltage. 6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for applications where voltage reference is needed. 12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. Voltage reference (VREF) Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF can be used in medical applications, such as glucose meters, to provide a reference voltage to biosensors or as a reference to analog peripherals, such as the ADC, DAC, or CMP.

2.3.7 Timer modules

The following timer modules are available on this device: Module Functional Categories K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 64 Freescale Semiconductor, Inc.

Table 2-8. Timer modules Module Description Programmable delay block (PDB) • 16-bit resolution

• 3-bit prescaler
• Positive transition of trigger event signal initiates the counter
• Supports two triggered delay output signals, each with an independently- controlled delay from the trigger event
• Outputs can be OR'd together to schedule two conversions from one input trigger event and can schedule precise edge placement for a pulsed output. This feature is used to generate the control signal for the CMP windowing feature and output to a package pin if needed for applications, such as critical conductive mode power factor correction.
• Continuous-pulse output or single-shot mode supported, each output is independently enabled, with possible trigger events
• Supports bypass mode
• Supports DMA Flexible timer modules (FTM) • Selectable FTM source clock, programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
• Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels with independent outputs
• Deadtime insertion is available for each complementary pair
• Generation of hardware triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• Configurable channel polarity
• Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition
• Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event
• DMA support for FTM events Periodic interrupt timers (PIT) • Four general purpose interrupt timers
• Interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by system clock frequency
• DMA support Low-power timer (LPTimer) • Selectable clock for prescaler/glitch filter of 1 kHz (internal LPO), 32.768 kHz (external crystal), or internal reference clock
• Configurable Glitch Filter or Prescaler with 16-bit counter
• 16-bit time or pulse counter with compare
• Interrupt generated on Timer Compare
• Hardware trigger generated on Timer Compare Carrier modulator timer (CMT) • Four CMT modes of operation:
• Time with independent control of high and low times
• Baseband
• Frequency shift key (FSK)
• Direct software control of CMT_IRO pin
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divider
• Interrupt on end of cycle with the ability to disable CMT_IRO pin and use as timer interrupt
• DMA support Table continues on the next page... Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 65

Table 2-8. Timer modules (continued) Module Description Real-time clock (RTC) • Independent power supply, POR, and 32 kHz Crystal Oscillator

• 32-bit seconds counter with 32-bit Alarm
• 16-bit Prescaler with compensation that can correct errors between 0.12 ppm and 3906 ppm IEEE 1588 timers • The 10/100 Ethernet module contains timers to provide IEEE 1588 time stamping

2.3.8 Communication interfaces

The following communication interfaces are available on this device: Table 2-9. Communication modules Module Description Ethernet MAC with IEEE 1588 capability (ENET) 10/100 MB/s Ethernet MAC (MII and RMII) with hardware support for IEEE 1588 USB OTG (low-/full-speed) USB 2.0 compliant module with support for host, device, and On-The-Go modes. Includes an on-chip transceiver for full and low speeds. USB Device Charger Detect (USBDCD) The USBDCD monitors the USB data lines to detect a smart charger meeting the USB Battery Charging Specification Rev1.1. This information allows the MCU to better manage the battery charging IC in a portable device. USB voltage regulator Up to 5 V regulator input typically provided by USB VBUS power with 3.3 V regulated output that powers on-chip USB subsystem, capable of sourcing 120 mA to external board components. Controller Area Network (CAN) Supports the full implementation of the CAN Specification Version 2.0, Part B Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System Management Bus (SMBus) Specification, version 2. Universal asynchronous receiver/ transmitters (UART) Asynchronous serial bus communication interface with programmable 8- or 9-bit data format and support of ISO 7816 smart card interface Secure Digital host controller (SDHC) Interface between the host system and the SD, SDIO, MMC, or CE-ATA cards. The SDHC acts as a bridge, passing host bus transactions to the cards by sending commands and performing data accesses to/from the cards. It handles the SD, SDIO, MMC, and CE-ATA protocols at the transmission level. I2S The I2S is a full-duplex, serial port that allows the chip to communicate with a variety of serial devices, such as standard codecs, digital signal processors (DSPs), microprocessors, peripherals, and audio codecs that implement the inter- IC sound bus (I2S) and the Intel® AC97 standards

2.3.9 Human-machine interfaces

The following human-machine interfaces (HMI) are available on this device: Module Functional Categories K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 66 Freescale Semiconductor, Inc.

Table 2-10. HMI modules Module Description General purpose input/output (GPIO) All general purpose input or output (GPIO) pins are capable of interrupt and DMA request generation. All GPIO pins have 5 V tolerance. Capacitive touch sense input (TSI) Contains up to 16 channel inputs for capacitive touch sensing applications. Operation is available in low-power modes via interrupts.

2.4 Orderable part numbers

The following table summarizes the part numbers of the devices covered by this document. Table 2-11. Orderable part numbers summary Freescale part number CPU frequenc y Pin count Package Total flash memory Program flash EEPROM SRAM GPIO MK60DN256ZVLL10 100 MHz 100 LQFP 256 KB 256 KB — 64 KB 66 MK60DX256ZVLL10 100 MHz 100 LQFP 512 KB 256 KB 4 KB 64 KB 66 MK60DN512ZVLL10 100 MHz 100 LQFP 512 KB 512 KB — 128 KB 66 Chapter 2 Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 67

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 68 Freescale Semiconductor, Inc.

3.1 Introduction

This chapter provides details on the individual modules of the microcontroller. It includes:

• module block diagrams showing immediate connections within the device,
• specific module-to-module interactions not necessarily discussed in the individual module chapters, and
• links for more information. Core modules

3.2.1 ARM Cortex-M4 Core Configuration

This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. 3.2 K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 69

Figure 3-1. Core configuration Table 3-1. Reference links to related information Topic Related module Reference Full description ARM Cortex-M4 core, r0p0 http://www.arm.com System memory map System memory map Clocking Clock distribution Power management Power management System/instruction/data bus module Crossbar switch Crossbar switch System/instruction/data bus module SRAM SRAM Debug IEEE 1149.1 JTAG IEEE 1149.7 JTAG (cJTAG) Serial Wire Debug (SWD) ARM Real-Time Trace Interface Debug Interrupts Nested Vectored Interrupt Controller (NVIC) NVIC Private Peripheral Bus (PPB) module Miscellaneous Control Module (MCM) MCM Private Peripheral Bus (PPB) module Memory-Mapped Cryptographic Acceleration Unit (MMCAU) MMCAU

3.2.1.1 Buses, interconnects, and interfaces

The ARM Cortex-M4 core has four buses as described in the following table. Core modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 70 Freescale Semiconductor, Inc.

Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is connected to the crossbar switch via a single master port. In addition, the CODE bus is also tightly coupled to the lower half of the system RAM (SRAM_L).Data code (DCODE) bus System bus The system bus is connected to a separate master port on the crossbar. In addition, the system bus is tightly coupled to the upper half system RAM (SRAM_U). Private peripheral (PPB) bus The PPB provides access to these modules:

• ARM modules such as the NVIC, ETM, ITM, DWT, FBP, and ROM table
• Freescale Miscellaneous Control Module (MCM)
• Memory-Mapped Cryptographic Acceleration Unit (MMCAU)

3.2.1.2 System Tick Timer

The System Tick Timer's clock source is always the core clock, FCLK. This results in the following:

• The CLKSOURCE bit in SysTick Control and Status register is always set to select the core clock.
• Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero.
• The NOREF bit in SysTick Calibration Value Register is always set, implying that FCLK is the only available source of reference timing.

3.2.1.3 Debug facilities

This device has extensive debug capabilities including run control and tracing capabilities. The standard ARM debug port that supports JTAG and SWD interfaces. Also the cJTAG interface is supported on this device.

3.2.1.4 Core privilege levels

The ARM documentation uses different terms than this document to distinguish between privilege levels. Privileged Supervisor Unprivileged or user User Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 71

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration

This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. Nested Vectored Interrupt Controller (NVIC) ARM Cortex-M4 core Interrupts Module Module Module PPB Figure 3-2. NVIC configuration Table 3-2. Reference links to related information Topic Related module Reference Full description Nested Vectored Interrupt Controller (NVIC) http://www.arm.com System memory map System memory map Clocking Clock distribution Power management Power management Private Peripheral Bus (PPB) ARM Cortex-M4 core ARM Cortex-M4 core

3.2.2.1 Interrupt priority levels

This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 4 bits. For example, IPR0 is shown below: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IRQ3 0 0 0 0 IRQ2 0 0 0 0 IRQ1 0 0 0 0 IRQ0 0 0 0 0 W

3.2.2.2 Non-maskable interrupt

The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request. Core modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 72 Freescale Semiconductor, Inc.

3.2.2.3 Interrupt channel assignments

The interrupt source assignments are defined in the following table.

• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus 16. The IRQ number is used within ARM's NVIC documentation. Table 3-4. Interrupt vector assignments Address Vector IRQ1 NVIC non-IPR register number NVIC IPR register number Source module Source description ARM Core System Handler Vectors 0x0000_0000 0 – – – ARM core Initial Stack Pointer 0x0000_0004 1 – – – ARM core Initial Program Counter 0x0000_0008 2 – – – ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 – – – ARM core Hard Fault 0x0000_0010 4 – – – ARM core MemManage Fault 0x0000_0014 5 – – – ARM core Bus Fault 0x0000_0018 6 – – – ARM core Usage Fault 0x0000_002C 11 – – – ARM core Supervisor call (SVCall) 0x0000_0030 12 – – – ARM core Debug Monitor 0x0000_0038 14 – – – ARM core Pendable request for system service (PendableSrvReq) 0x0000_003C 15 – – – ARM core System tick timer (SysTick) Non-Core Vectors 0x0000_0040 16 0 0 0 DMA DMA channel 0 transfer complete 0x0000_0044 17 1 0 0 DMA DMA channel 1 transfer complete 0x0000_0048 18 2 0 0 DMA DMA channel 2 transfer complete 0x0000_004C 19 3 0 0 DMA DMA channel 3 transfer complete 0x0000_0050 20 4 0 1 DMA DMA channel 4 transfer complete Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 73

Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC non-IPR register number NVIC IPR register number Source module Source description 0x0000_0054 21 5 0 1 DMA DMA channel 5 transfer complete 0x0000_0058 22 6 0 1 DMA DMA channel 6 transfer complete 0x0000_005C 23 7 0 1 DMA DMA channel 7 transfer complete 0x0000_0060 24 8 0 2 DMA DMA channel 8 transfer complete 0x0000_0064 25 9 0 2 DMA DMA channel 9 transfer complete 0x0000_0068 26 10 0 2 DMA DMA channel 10 transfer complete 0x0000_006C 27 11 0 2 DMA DMA channel 11 transfer complete 0x0000_0070 28 12 0 3 DMA DMA channel 12 transfer complete 0x0000_0074 29 13 0 3 DMA DMA channel 13 transfer complete 0x0000_0078 30 14 0 3 DMA DMA channel 14 transfer complete 0x0000_007C 31 15 0 3 DMA DMA channel 15 transfer complete 0x0000_0080 32 16 0 4 DMA DMA error interrupt channels 0-15 0x0000_0084 33 17 0 4 MCM Normal interrupt 0x0000_0088 34 18 0 4 Flash memory Command complete 0x0000_008C 35 19 0 4 Flash memory Read collision 0x0000_0090 36 20 0 5 Mode Controller Low-voltage detect, low-voltage warning 0x0000_0094 37 21 0 5 LLWU Low Leakage Wakeup NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. 0x0000_0098 38 22 0 5 WDOG Watchdog interrupt 0x0000_009C 39 23 0 5 RNG Randon Number Generator 0x0000_00A0 40 24 0 6 I2C0 — 0x0000_00A4 41 25 0 6 I2C1 — 0x0000_00A8 42 26 0 6 SPI0 Single interrupt vector for all sources 0x0000_00AC 43 27 0 6 SPI1 Single interrupt vector for all sources 0x0000_00B0 44 28 0 7 SPI2 Single interrupt vector for all sources 0x0000_00B4 45 29 0 7 CAN0 OR'ed Message buffer (0-15) 0x0000_00B8 46 30 0 7 CAN0 Bus Off 0x0000_00BC 47 31 0 7 CAN0 Error 0x0000_00C0 48 32 1 8 CAN0 Transmit Warning Table continues on the next page... Core modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 74 Freescale Semiconductor, Inc.

Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC non-IPR register number NVIC IPR register number Source module Source description 0x0000_00C4 49 33 1 8 CAN0 Receive Warning 0x0000_00C8 50 34 1 8 CAN0 Wake Up 0x0000_00CC 51 35 1 8 — — 0x0000_00D0 52 36 1 9 — — 0x0000_00D4 53 37 1 9 CAN1 OR'ed Message buffer (0-15) 0x0000_00D8 54 38 1 9 CAN1 Bus off 0x0000_00DC 55 39 1 9 CAN1 Error 0x0000_00E0 56 40 1 10 CAN1 Transmit Warning 0x0000_00E4 57 41 1 10 CAN1 Receive Warning 0x0000_00E8 58 42 1 10 CAN1 Wake Up 0x0000_00EC 59 43 1 10 — — 0x0000_00F0 60 44 1 11 — — 0x0000_00F4 61 45 1 11 UART0 Single interrupt vector for UART status sources 0x0000_00F8 62 46 1 11 UART0 Single interrupt vector for UART error sources 0x0000_00FC 63 47 1 11 UART1 Single interrupt vector for UART status sources 0x0000_0100 64 48 1 12 UART1 Single interrupt vector for UART error sources 0x0000_0104 65 49 1 12 UART2 Single interrupt vector for UART status sources 0x0000_0108 66 50 1 12 UART2 Single interrupt vector for UART error sources 0x0000_010C 67 51 1 12 UART3 Single interrupt vector for UART status sources 0x0000_0110 68 52 1 13 UART3 Single interrupt vector for UART error sources 0x0000_0114 69 53 1 13 UART4 Single interrupt vector for UART status sources 0x0000_0118 70 54 1 13 UART4 Single interrupt vector for UART error sources 0x0000_011C 71 55 1 13 — — 0x0000_0120 72 56 1 14 — — 0x0000_0124 73 57 1 14 ADC0 — 0x0000_0128 74 58 1 14 ADC1 — Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 75

Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC non-IPR register number NVIC IPR register number Source module Source description 0x0000_012C 75 59 1 14 CMP0 — 0x0000_0130 76 60 1 15 CMP1 — 0x0000_0134 77 61 1 15 CMP2 — 0x0000_0138 78 62 1 15 FTM0 Single interrupt vector for all sources 0x0000_013C 79 63 1 15 FTM1 Single interrupt vector for all sources 0x0000_0140 80 64 2 16 FTM2 Single interrupt vector for all sources 0x0000_0144 81 65 2 16 CMT — 0x0000_0148 82 66 2 16 RTC Alarm interrupt 0x0000_014C 83 67 2 16 — — 0x0000_0150 84 68 2 17 PIT Channel 0 0x0000_0154 85 69 2 17 PIT Channel 1 0x0000_0158 86 70 2 17 PIT Channel 2 0x0000_015C 87 71 2 17 PIT Channel 3 0x0000_0160 88 72 2 18 PDB — 0x0000_0164 89 73 2 18 USB OTG — 0x0000_0168 90 74 2 18 USB Charger Detect 0x0000_016C 91 75 2 18 Ethernet MAC IEEE 1588 Timer Interrupt 0x0000_0170 92 76 2 19 Ethernet MAC Transmit interrupt 0x0000_0174 93 77 2 19 Ethernet MAC Receive interrupt 0x0000_0178 94 78 2 19 Ethernet MAC Error and miscellaneous interrupt 0x0000_017C 95 79 2 19 I2S0 — 0x0000_0180 96 80 2 20 SDHC — 0x0000_0184 97 81 2 20 DAC0 — 0x0000_0188 98 82 2 20 — — 0x0000_018C 99 83 2 20 TSI Single interrupt vector for all sources 0x0000_0190 100 84 2 21 MCG — 0x0000_0194 101 85 2 21 Low Power Timer — 0x0000_0198 102 86 2 21 — — 0x0000_019C 103 87 2 21 Port control module Pin detect (Port A) 0x0000_01A0 104 88 2 22 Port control module Pin detect (Port B) Table continues on the next page... Core modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 76 Freescale Semiconductor, Inc.

Table 3-4. Interrupt vector assignments (continued) Address Vector IRQ1 NVIC non-IPR register number NVIC IPR register number Source module Source description 0x0000_01A4 105 89 2 22 Port control module Pin detect (Port C) 0x0000_01A8 106 90 2 22 Port control module Pin detect (Port D) 0x0000_01AC 107 91 2 22 Port control module Pin detect (Port E) 0x0000_01B0 108 92 2 23 — — 0x0000_01B4 109 93 2 23 — — 0x0000_01B8 110 94 2 23 Software Software interrupt4 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 4. This interrupt can only be pended or cleared via the NVIC registers.

3.2.2.3.1 Determining the bitfield and register location for configuring a

Suppose you need to configure the low-power timer (LPTMR) interrupt. The following table is an excerpt of the LPTMR row from Interrupt channel assignments. Table 3-5. LPTMR interrupt vector assignment Address Vector IRQ1 NVIC non-IPR register number NVIC IPR register number Source module Source description 0x0000_0194 101 85 2 21 Low Power Timer — 1. Indicates the NVIC's interrupt source number. 2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this value is: IRQ div 32 3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4

• The NVIC registers you would use to configure the interrupt are:
• NVICISER2
• NVICICER2
• NVICISPR2
• NVICICPR2 Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 77

• NVICIABR2
• NVICIPR21
• To determine the particular IRQ's bitfield location within these particular registers:
• NVICISER2, NVICICER2, NVICISPR2, NVICICPR2, NVICIABR2 bit location = IRQ mod 32 = 21
• NVICIPR21 bitfield starting location = 8 * (IRQ mod 4) + 4 = 12 Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR21 bitfield range is 12-15 Therefore, the following bitfield locations are used to configure the LPTMR interrupts:
• NVICISER2[21]
• NVICICER2[21]
• NVICISPR2[21]
• NVICICPR2[21]
• NVICIABR2[21]
• NVICIPR21[15:12]

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC)

This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at http:// www.arm.com. Asynchronous Wake-up Interrupt Controller (AWIC) Nested vectored interrupt controller (NVIC) Wake-up requests Module Module Clock logic Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration Table 3-6. Reference links to related information Topic Related module Reference System memory map System memory map Clocking Clock distribution Table continues on the next page... Core modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 78 Freescale Semiconductor, Inc.

Table 3-6. Reference links to related information (continued) Topic Related module Reference Power management Power management Nested Vectored Interrupt Controller (NVIC) NVIC Wake-up requests AWIC wake-up sources

3.2.3.1 Wake-up sources

The device uses the following internal and external inputs to the AWIC module. Table 3-7. AWIC Stop and VLPS Wake-up Sources Wake-up source Description Available system resets RESET pin and WDOG when LPO is its clock source, and JTAG Low-voltage detect Mode Controller Low-voltage warning Mode Controller Pin interrupts Port Control Module - Any enabled pin interrupt is capable of waking the system ADCx The ADC is functional when using internal clock source CMPx Since no system clocks are available, functionality is limited I2C Address match wakeup UART Active edge on RXD USB Wakeup LPTMR Functional in Stop/VLPS modes RTC Functional in Stop/VLPS modes Ethernet Magic Packet wakeup SDHC Wakeup I2S Wakeup

1588 Timer Wakeup

3.2.4 JTAG Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 79

Figure 3-4. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC JTAGC Signal multiplexing Port control Signal multiplexing System modules

3.3.1 SIM Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Peripheral bridge System integration module (SIM) Figure 3-5. SIM configuration Table 3-9. Reference links to related information Topic Related module Reference Full description SIM SIM System memory map System memory map Clocking Clock distribution Power management Power management 3.3 System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 80 Freescale Semiconductor, Inc.

3.3.2 Mode Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Power management controller (PMC) Register access Peripheral bridge Mode controller Resets Figure 3-6. Mode controller configuration Table 3-10. Reference links to related information Topic Related module Reference Full description Mode Controller Mode Controller System memory map System memory map Power management Power management Power management controller (PMC) PMC

3.3.3 PMC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 81

controller (PMC) Figure 3-7. PMC configuration Table 3-11. Reference links to related information Topic Related module Reference Full description PMC PMC System memory map System memory map Power management Power management Full description Mode Controller Mode Controller Low-Leakage Wakeup Unit (LLWU) LLWU

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Low-Leakage Wake-up Unit (LLWU) Power Management Controller (PMC) Peripheral bridge 0 Register access Wake-up requests Module Module Figure 3-8. Low-Leakage Wake-up Unit configuration Table 3-12. Reference links to related information Topic Related module Reference Full description LLWU LLWU System memory map System memory map Table continues on the next page... System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 82 Freescale Semiconductor, Inc.

Table 3-12. Reference links to related information (continued) Topic Related module Reference Clocking Clock distribution Power management Power management chapter Power Management Controller (PMC) Power Management Controller (PMC) Mode Controller Mode Controller Wake-up requests LLWU wake-up sources

3.3.4.1 Wake-up Sources

This chip uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module:

• LLWU_P0-15 are external pin inputs. See the chip's signal multiplexing table for the individual input signal options.
• LLWU_M0IF-M7IF are connections to the internal peripheral interrupt flags. NOTE RESET is also a wakeup source, depending on the bit setting in the LLWU_CS register. On devices where RESET is not a dedicated pin, it must also be enabled in the explicit port mux control. Table 3-13. Wakeup sources for LLWU inputs Input Wakeup source Input Wakeup source LLWU_P0 PTE1/LLWU_P0 pin LLWU_P12 PTD0/LLWU_P12 pin LLWU_P1 PTE2/LLWU_P1 pin LLWU_P13 PTD2/LLWU_P13 pin LLWU_P2 PTE4/LLWU_P2 pin LLWU_P14 PTD4/LLW14_P0 pin LLWU_P3 PTA4/LLWU_P3 pin1 LLWU_P15 PTD6/LLWU_P15 pin LLWU_P4 PTA13/LLWU_P4 pin LLWU_M0IF LPTMR2 LLWU_P5 PTB0/LLWU_P5 pin LLWU_M1IF CMP02 LLWU_P6 PTC1/LLWU_P6 pin LLWU_M2IF CMP12 LLWU_P7 PTC3/LLWU_P7 pin LLWU_M3IF CMP22 LLWU_P8 PTC4/LLWU_P8 pin LLWU_M4IF TSI2 LLWU_P9 PTC5/LLWU_P9 pin LLWU_M5IF RTC Alarm2 LLWU_P10 PTC6/LLWU_P10 pin LLWU_M6IF Reserved LLWU_P11 PTC11/LLWU_P11 pin LLWU_M7IF Error Detect - wake-up source unknown 1. A falling edge input that remains low on this pin when waking up the MCU from VLLSx modes with the EzPort enabled causes entry into EzPort mode during the reset sequence. A falling edge input that remains low on this pin when waking Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 83

up the MCU from any non-VLLSx mode with the NMI function selected in its port control register asserts an NMI exception on low power mode recovery. The same occurs when recovering from VLLSx modes if EzPort is disabled; otherwise, EzPort mode is entered. See the "EzPort Configuration" section in this chapter for more information. 2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism.

3.3.5 MCM Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Miscellaneous Control Module (MCM) Transfers ARM Cortex-M4 core PPB Figure 3-9. MCM configuration Table 3-14. Reference links to related information Topic Related module Reference Full description Miscellaneous control module (MCM) MCM System memory map System memory map Clocking Clock distribution Power management Power management Transfers Private Peripheral Bus (PPB) ARM Cortex-M4 core ARM Cortex-M4 core

3.3.6 Crossbar Switch Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 84 Freescale Semiconductor, Inc.

(MPU) Mux Peripheral bridge 1 GPIO controller S4 FlexBus MPU USB Ethernet Figure 3-10. Crossbar switch configuration Table 3-15. Reference links to related information Topic Related module Reference Full description Crossbar switch Crossbar Switch System memory map System memory map Clocking Clock Distribution Memory protection MPU MPU Crossbar switch master ARM Cortex-M4 core ARM Cortex-M4 core Crossbar switch master DMA controller DMA controller Crossbar switch master EzPort EzPort Crossbar switch master Ethernet Ethernet Crossbar switch master USB FS/LS USB FS/LS Crossbar switch master SDHC SDHC Crossbar switch slave Flash Flash Crossbar switch slave SRAM backdoor SRAM backdoor Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 85

Table 3-15. Reference links to related information (continued) Topic Related module Reference Crossbar switch slave Peripheral bridges Peripheral bridge Crossbar switch slave GPIO controller GPIO controller Crossbar switch slave FlexBus FlexBus

3.3.6.1 Crossbar Switch Master Assignments

The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core code bus 0 ARM core system bus 1 DMA/EzPort 2 Ethernet 3 USB OTG 4 SDHC 5 NOTE The DMA and EzPort share a master port. Since these modules never operate at the same time, no configuration or arbitration explanations are necessary.

3.3.6.2 Crossbar Switch Slave Assignments

The slaves connected to the crossbar switch are assigned as follows: Slave module Slave port number Protected by MPU? Flash memory controller 0 Yes SRAM backdoor 1 Yes Peripheral bridge 01 2 No. Protection built into bridge. Peripheral bridge 1/GPIO1 3 No. Protection built into bridge. FlexBus 4 Yes 1. See System memory map for access restrictions.

3.3.6.3 PRS register reset values

The AXBS_PRSn registers reset to 0054_3210h. System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 86 Freescale Semiconductor, Inc.

3.3.7 Memory Protection Unit (MPU) Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Memory Protection Unit (MPU) Transfers Slave Slave Slave Peripheral bridge 0 Register access TransfersLogical Master Logical Master Logical Master Figure 3-11. Memory Protection Unit configuration Table 3-16. Reference links to related information Topic Related module Reference Full description Memory Protection Unit (MPU) MPU System memory map System memory map Clocking Clock distribution Power management Power management Logical masters Logical master assignments Slave modules Slave module assignments

3.3.7.1 MPU Slave Port Assignments

The memory-mapped resources protected by the MPU are: Table 3-17. MPU Slave Port Assignments Source MPU Slave Port Assignment Destination Crossbar slave port 0 MPU slave port 0 Flash Controller Crossbar slave port 1 MPU slave port 1 SRAM backdoor Code Bus MPU slave port 2 SRAM_L frontdoor System Bus MPU slave port 3 SRAM_U frontdoor Crossbar slave port 4 MPU slave port 4 FlexBus Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 87

3.3.7.2 MPU Logical Bus Master Assignments

The logical bus master assignments for the MPU are: Table 3-18. MPU Logical Bus Master Assignments MPU Logical Bus Master Number Bus Master

0 Core

1 Debugger

2 DMA

3 ENET

4 USB

5 SDHC

3.3.7.3 MPU Access Violation Indications

Access violations detected by the MPU are signaled to the appropriate bus master as shown below: Table 3-19. Access Violation Indications Bus Master Core Indication Core Bus fault (interrupt vector #5) Note: To enable bus faults set the core's System Handler Control and State Register's BUSFAULTENA bit. If this bit is not set, MPU violations result in a hard fault (interrupt vector #3). Debugger The STICKYERROR flag is set in the Debug Port Control/Status Register. DMA Interrupt vector #32 Ethernet Interrupt vector #94 USB_OTG Interrupt vector #89 SDHC Interrupt vector #96

3.3.7.4 Reset Values for RGD0 Registers

At reset, the MPU is enabled with a single region descriptor (RGD0) that maps the entire

4 GB address space with read, write and execute permissions given to the core, debugger

and the DMA bus masters. The following table shows the chip-specific reset values for RGD0 and RGDAAC0. System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 88 Freescale Semiconductor, Inc.

Table 3-20. Reset Values for RGD0 Registers Register Reset value RGD0_WORD0 0000_0000h RGD0_WORD1 FFFF_FFFFh RGD0_WORD2 0061_F7DFh RGD0_WORD3 0000_0001h RGDAAC0 0061_F7DFh

3.3.7.5 Write Access Restrictions for RGD0 Registers

In addition to configuring the initial state of RGD0, the MPU implements further access control on writes to the RGD0 registers. Specifically, the MPU assigns a priority scheme where the debugger is treated as the highest priority master followed by the core and then all the remaining masters. The MPU does not allow writes from the core to affect the RGD0 start or end addresses nor the permissions associated with the debugger; it can only write the permission fields associated with the other masters. These protections (summarized below) guarantee that the debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master. Table 3-21. Write Access to RGD0 Registers Bus Master Write Access? Core Partial. The Core cannot write to the following registers or register fields:

• RGD0_WORD0, RGD0_WORD1, RGD0_WORD3
• RGD0_WORD2[M1SM, M1UM]
• RGDAAC0[M1SM, M1UM] NOTE: Changes to the RGD0_WORD2 alterable fields should be done via a write to RGDAAC0. Debugger Yes All other masters No

3.3.8 Peripheral Bridge Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 89

Figure 3-12. Peripheral bridge configuration Table 3-22. Reference links to related information Topic Related module Reference Full description Peripheral bridge (AIPS-Lite) Peripheral bridge (AIPS-Lite) System memory map System memory map Clocking Clock Distribution Crossbar switch Crossbar switch Crossbar switch

3.3.8.1 Number of peripheral bridges

This device contains two identical peripheral bridges.

3.3.8.2 Memory maps

The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map and AIPS1 Memory Map for the memory slot assignment for each module.

3.3.8.3 MPRA register

Each of the two peripheral bridges supports up to 8 crossbar switch masters, each assigned to a MPROTx field in the MPRA register. However, fewer are supported on this device. See Crossbar switch for details of the master port assignments for this device.

3.3.8.4 AIPS_Lite MPRA register reset value

• AIPS x_MPRA reset value is 0x7770_0000 Therefore, masters 0, 1, and 2 are trusted bus masters after reset. System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 90 Freescale Semiconductor, Inc.

3.3.8.5 PACR registers

Each of the two peripheral bridges support up to 128 peripherals each assigned to an PACRx field within the PACRA-PACRP registers. However, fewer peripherals are supported on this device. See AIPS0 Memory MapandAIPS1 Memory Map for details of the peripheral slot assignments for this device. Unused PACRx fields are reserved.

3.3.8.6 AIPS_Lite PACRE-P register reset values

The AIPSx_PACRE-P reset values depend on if the module is available on your particular device. For each populated slot in slots 32-127 in Peripheral Bridge 0 (AIPS- Lite 0) Memory Map and Peripheral Bridge 1 (AIPS-Lite 1) Memory Map, the corresponding module's PACR[32:127] field resets to 0x4.

3.3.9 DMA request multiplexer configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. DMA Request Multiplexer DMA controller Requests Module Module Module Peripheral bridge 0 Register access Channel request Figure 3-13. DMA request multiplexer configuration Table 3-23. Reference links to related information Topic Related module Reference Full description DMA request multiplexer DMA Mux System memory map System memory map Clocking Clock distribution Power management Power management Channel request DMA controller DMA Controller Requests DMA request sources Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 91

3.3.9.1 DMA MUX request sources

This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels. Because of the mux there is not a hard correlation between any of the DMA request sources and a specific DMA channel. Table 3-24. DMA request sources - MUX 0 Source number Source module Source description 0 — Channel disabled1

1 Reserved Not used

2 UART0 Receive

3 UART0 Transmit

4 UART1 Receive

5 UART1 Transmit

6 UART2 Receive

7 UART2 Transmit

8 UART3 Receive

9 UART3 Transmit

10 UART4 Receive

11 UART4 Transmit

12 Reserved —

13 Reserved —

14 I2S0 Receive

15 I2S0 Transmit

16 SPI0 Receive

17 SPI0 Transmit

18 SPI1 Receive

19 SPI1 Transmit

22 I2C0 —

23 I2C1 —

24 FTM0 Channel 0

25 FTM0 Channel 1

26 FTM0 Channel 2

Table continues on the next page... System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 92 Freescale Semiconductor, Inc.

Table 3-24. DMA request sources - MUX 0 (continued) Source number Source module Source description

27 FTM0 Channel 3

28 FTM0 Channel 4

29 FTM0 Channel 5

30 FTM0 Channel 6

31 FTM0 Channel 7

32 FTM1 Channel 0

33 FTM1 Channel 1

34 FTM2 Channel 0

35 FTM2 Channel 1

36 FTM3 Channel 0

37 FTM3 Channel 1

38 FTM3 Channel 2

39 FTM1 Channel 3

40 ADC0 —

41 ADC1 —

42 CMP0 —

43 CMP1 —

44 CMP2 —

45 DAC0 —

46 Reserved —

47 CMT —

48 PDB —

49 Port control module Port A

50 Port control module Port B

51 Port control module Port C

52 Port control module Port D

53 Port control module Port E

54 FTM3 Channel 4

55 FTM3 Channel 5

56 FTM3 Channel 6

57 FTM3 Channel 7

58 DMA MUX Always enabled

59 DMA MUX Always enabled

60 DMA MUX Always enabled

Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 93

Table 3-24. DMA request sources - MUX 0 (continued) Source number Source module Source description

61 DMA MUX Always enabled

62 DMA MUX Always enabled

63 DMA MUX Always enabled

1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.

3.3.9.2 DMA transfers via PIT trigger

The PIT module can trigger a DMA transfer on the first four DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments .

3.3.10 DMA Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. DMA Controller Crossbar switch Requests Peripheral bridge 0 Register access Transfers DMA Multiplexer Figure 3-14. DMA Controller configuration Table 3-25. Reference links to related information Topic Related module Reference Full description DMA Controller DMA Controller System memory map System memory map Register access Peripheral bridge (AIPS-Lite 0) AIPS-Lite 0 Clocking Clock distribution Power management Power management Transfers Crossbar switch Crossbar switch System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 94 Freescale Semiconductor, Inc.

3.3.11 External Watchdog Monitor (EWM) Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. External Watchdog Monitor (EWM) Peripheral bridge 0 Register access Signal multiplexing Module signals Figure 3-15. External Watchdog Monitor configuration Table 3-26. Reference links to related information Topic Related module Reference Full description External Watchdog Monitor (EWM) EWM System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port Control Module Signal multiplexing

3.3.11.1 EWM clocks

This table shows the EWM clocks and the corresponding chip clocks. Table 3-27. EWM clock connections Module clock Chip clock Low Power Clock 1 kHz LPO Clock

3.3.11.2 EWM low-power modes

This table shows the EWM low-power modes and the corresponding chip low-power modes. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 95

Table 3-28. EWM low-power modes Module mode Chip mode Wait Wait, VLPW Stop Stop, VLPS, LLS Power Down VLLS3, VLLS2, VLLS1

3.3.11.3 EWM_OUT pin state in low power modes

During Wait, Stop and Power Down modes the EWM_OUT pin enters a high-impedance state. A user has the option to control the logic state of the pin using an external pull device or by configuring the internal pull device. When the CPU enters a Run mode from Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop mode. When the CPU enters Run mode from Power Down, the pin returns to its reset state.

3.3.12 Watchdog Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. WDOG Mode Controller Peripheral bridge 0 Register access Figure 3-16. Watchdog configuration Table 3-29. Reference links to related information Topic Related module Reference Full description Watchdog Watchdog System memory map System memory map Clocking Clock distribution Power management Power management Mode Controller (MC) Mode Controller System modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 96 Freescale Semiconductor, Inc.

3.3.12.1 WDOG clocks

This table shows the WDOG module clocks and the corresponding chip clocks. Table 3-30. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Alt Clock Bus Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock

3.3.12.2 WDOG low-power modes

This table shows the WDOG low-power modes and the corresponding chip low-power modes. Table 3-31. WDOG low-power modes Module mode Chip mode Wait Wait, VLPW Standby Stop, VLPS Stop Stop, VLPS Power Down LLS, VLLSx NOTE To enable the WDOG module when the chip is in Stop mode, write ones to both the STNDBYEN bit and the STOPEN bit of the Watchdog Status and Control Register High. Clock Modules

3.4.1 MCG Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. 3.4 Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 97

Generator (MCG) RTC oscillator System oscillator System integration module (SIM) Figure 3-17. MCG configuration Table 3-32. Reference links to related information Topic Related module Reference Full description MCG MCG System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing

3.4.2 OSC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge System oscillator MCG Module signals Figure 3-18. OSC configuration Table 3-33. Reference links to related information Topic Related module Reference Full description OSC OSC System memory map System memory map Clocking Clock distribution Table continues on the next page... Clock Modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 98 Freescale Semiconductor, Inc.

Table 3-33. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal multiplexing Port control Signal multiplexing Full description MCG MCG

3.4.2.1 OSC modes of operation with MCG

The MCG's C2 register bits configure the oscillator frequency range. See the OSC and MCG chapters for more details.

3.4.3 RTC OSC configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing 32-kHz RTC oscillator MCG Module signals Figure 3-19. RTC OSC configuration Table 3-34. Reference links to related information Topic Related module Reference Full description RTC OSC RTC OSC Signal multiplexing Port control Signal multiplexing Full description MCG MCG Memories and Memory Interfaces

3.5.1 Flash Memory Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. 3.5 Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 99

Figure 3-20. Flash memory configuration Table 3-35. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory System memory map System memory map Clocking Clock Distribution Transfers Flash memory controller Flash memory controller Register access Peripheral bridge Peripheral bridge

3.5.1.1 Flash memory types

This device contains the following types of flash memory:

• Program flash memory — non-volatile flash memory that can execute program code
• FlexMemory — encompasses the following memory types:
• For devices with FlexNVM: FlexNVM — Non-volatile flash memory that can execute program code, store data, or backup EEPROM data
• For devices with FlexNVM: FlexRAM — RAM memory that can be used as traditional RAM or as high-endurance EEPROM storage, and also accelerates flash programming
• For devices with only program flash memory: Programming acceleration RAM — RAM memory that accelerates flash programming

3.5.1.2 Flash Memory Sizes

The devices covered in this document contain:

• For devices with program flash only: 2 blocks of program flash consisting of 2 KB sectors Memories and Memory Interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 100 Freescale Semiconductor, Inc.

• For devices that contain FlexNVM: 1 block of program flash consisting of 2 KB sectors
• For devices that contain FlexNVM: 1 block of FlexNVM consisting of 2 KB sectors
• For devices that contain FlexNVM: 1 block of FlexRAM The amounts of flash memory for the devices covered in this document are: Device Program flash (KB) Block 0 (P- Flash) address range1 FlexNVM (KB) Block 1 (FlexNVM/ P- Flash) address range1 FlexRAM (KB) FlexRAM address range MK60DN256ZV LL10 256 0x0000_0000 – 0x0001_FFFF — 0x0002_0000 – 0x0003_FFFF — N/A MK60DX256ZV LL10 256 0x0000_0000 – 0x0003_FFFF 256 0x1000_0000 – 0x1003_FFFF 4 0x1400_0000 – 0x1400_0FFF MK60DN512ZV LL10 512 0x0000_0000 – 0x0003_FFFF — 0x0004_0000 – 0x0007_FFFF — N/A 1. For program flash only devices: The addresses shown assume program flash swap is disabled (default configuration).

3.5.1.3 Flash Memory Size Considerations

Since this document covers devices that contain program flash only and devices that contain program flash and FlexNVM, there are some items to consider when reading the flash memory chapter.

• The flash memory chapter shows a mixture of information depending on the device you are using.
• For the program flash only devices:
• Two program flash blocks are supported: program flash 1 and program flash 2. The two blocks are contiguous in the system memory map.
• The program flash blocks support a swap feature in which the starting address of the program flash blocks can be swapped.
• The FlexRAM is not available as EEPROM or traditional RAM. Its space is only used for programming acceleration through the Program Section command.
• For the devices containing program flash and FlexNVM:
• Since there is only one program flash block, the program flash swap feature is not available. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 101

3.5.1.4 Flash Memory Map

The various flash memories and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Program flash Flash configuration field Program flash base address Flash memory base address Registers RAM Programming acceleration RAM base address Figure 3-21. Flash memory map for devices containing only program flash Program flash Flash configuration field FlexNVM base address Program flash base address Flash memory base address Registers FlexNVM FlexRAM FlexRAM base address Figure 3-22. Flash memory map for devices containing FlexNVM

3.5.1.5 Flash Security

How flash security is implemented on this device is described in Chip Security.

3.5.1.6 Flash Modes

The flash memory operates in NVM normal and NVM special modes. The flash memory enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset), or the system is under debug mode. Otherwise, flash memory operates in NVM normal mode. Memories and Memory Interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 102 Freescale Semiconductor, Inc.

3.5.1.7 Erase All Flash Contents

In addition to software, the entire flash memory may be erased external to the flash memory in two ways: 1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for more details. 2. Via the SWJ-DP debug port by setting DAP_CONTROL[0]. DAP_STATUS[0] is set to indicate the mass erase command has been accepted. DAP_STATUS[0] is cleared when the mass erase completes.

3.5.1.8 FTFL_FOPT Register

The flash memory's FTFL_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition.

3.5.2 Flash Memory Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Flash memory controller Transfers Memory protection unit Peripheral bus controller 0 Transfers Flash memory Crossbar switch Figure 3-23. Flash memory controller configuration Table 3-36. Reference links to related information Topic Related module Reference Full description Flash memory controller Flash memory controller System memory map System memory map Clocking Clock Distribution Transfers Flash memory Flash memory Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 103

Table 3-36. Reference links to related information (continued) Topic Related module Reference Transfers MPU MPU Transfers Crossbar switch Crossbar Switch Register access Peripheral bridge Peripheral bridge

3.5.2.1 Number of masters

The Flash Memory Controller supports up to eight crossbar switch masters. However, this device has a different number of crossbar switch masters. See Crossbar Switch Configuration for details on the master port assignments.

3.5.2.2 Program Flash Swap

On devices that contain program flash memory only, the program flash memory blocks may swap their base addresses. While not using swap:

• FMC_PFB0CR controls the lower code addresses (block 0)
• FMC_PFB1CR controls the upper code addresses (block 1) If swap is used, the opposite is true:
• FMC_PFB0CR controls the upper code addresses (now in block 0)
• FMC_PFB1CR controls the lower code addresses (now in block 1)

3.5.3 SRAM Configuration

This section summarizes how the module has been configured in the chip. Memories and Memory Interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 104 Freescale Semiconductor, Inc.

Figure 3-24. SRAM configuration Table 3-37. Reference links to related information Topic Related module Reference Full description SRAM SRAM System memory map System memory map Clocking Clock Distribution Transfers SRAM controller SRAM controller ARM Cortex-M4 core ARM Cortex-M4 core Memory protection unit Memory protection unit

3.5.3.1 SRAM sizes

This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of SRAM for the devices covered in this document is shown in the following table. Device SRAM (KB) MK60DN256ZVLL10 64 MK60DX256ZVLL10 64 MK60DN512ZVLL10 128

3.5.3.2 SRAM Arrays

The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and SRAM_U. The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. As such:

• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 105

Valid address ranges for SRAM_L and SRAM_U are then defined as:

• SRAM_L = [0x2000_0000–(SRAM_size/2)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size/2)-1] This is illustrated in the following figure. SRAM_U 0x2000_0000 SRAM size / 2 SRAM_L 0x1FFF_FFFF SRAM size / 2 0x2000_0000 – SRAM_size/2 0x2000_0000 + SRAM_size/2 - 1 Figure 3-25. SRAM blocks memory map For example, for a device containing 64 KB of SRAM the ranges are:
• SRAM_L: 0x1FFF_8000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_7FFF

3.5.3.3 SRAM retention in low power modes

The SRAM is retained down to VLLS3 mode. In VLLS2 the 4 KB region of SRAM_U from 0x2000_0000 is powered. In VLLS1 no SRAM is retained. However, the 32-byte register file is available in VLLS1.

3.5.3.4 SRAM accesses

The SRAM is split into two logical arrays that are 32-bits wide.

• SRAM_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor port.
• SRAM_U — Accessible by the system bus of the Cortex-M4 core and by the backdoor port. Memories and Memory Interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 106 Freescale Semiconductor, Inc.

The backdoor port makes the SRAM accessible to the non-core bus masters (such as DMA). The following figure illustrates the SRAM accesses within the device. Cortex-M4 core Code bus System bus SRAM controller Backdoor SRAM_L SRAM_U Crossbar switch non-core master non-core master non-core master Frontdoor MPU MPU Figure 3-26. SRAM access diagram The following simultaneous accesses can be made to different logical halves of the SRAM:

• Core code and core system
• Core code and non-core master
• Core system and non-core master NOTE Two non-core masters cannot access SRAM simultaneously. The required arbitration and serialization is provided by the crossbar switch. The SRAM_{L,U} arbitration is controlled by the SRAM controller based on the configuration bits in the MCM module. NOTE Burst-access cannot occur across the 0x2000_0000 boundary that separates the two SRAM arrays. The two arrays should be treated as separate memory ranges for burst accesses.

3.5.3.5 SRAM arbitration and priority control

The MCM's SRAMAP register controls the arbitration and priority schemes for the two SRAM arrays. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 107

3.5.4 SRAM Controller Configuration

This section summarizes how the module has been configured in the chip. Cortex-M4 core MPU Crossbar switch SRAM controller Transfers SRAM upper SRAM lower MPU Figure 3-27. SRAM controller configuration Table 3-38. Reference links to related information Topic Related module Reference System memory map System memory map Power management Power management Power management controller (PMC) PMC Transfers SRAM SRAM ARM Cortex-M4 core ARM Cortex-M4 core MPU Memory protection unit Configuration MCM MCM

3.5.5 System Register File Configuration

This section summarizes how the module has been configured in the chip. Memories and Memory Interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 108 Freescale Semiconductor, Inc.

Figure 3-28. System Register file configuration Table 3-39. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Clocking Clock distribution Power management Power management

3.5.5.1 System Register file

This device includes a 32-byte register file that is powered in all power modes. Also, it retains contents during low-voltage detect (LVD) events and is only reset during a power-on reset.

3.5.6 VBAT Register File Configuration

This section summarizes how the module has been configured in the chip. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 109

Figure 3-29. VBAT Register file configuration Table 3-40. Reference links to related information Topic Related module Reference Full description VBAT register file VBAT register file System memory map System memory map Clocking Clock distribution Power management Power management

3.5.6.1 VBAT register file

This device includes a 32-byte register file that is powered in all power modes and is powered by VBAT. It is only reset during VBAT power-on reset.

3.5.7 EzPort Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals EzPort Transfers Crossbar switch Figure 3-30. EzPort configuration Table 3-41. Reference links to related information Topic Related module Reference Full description EzPort EzPort Table continues on the next page... Memories and Memory Interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 110 Freescale Semiconductor, Inc.

Table 3-41. Reference links to related information (continued) Topic Related module Reference System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing

3.5.7.1 JTAG instruction

The system JTAG controller implements an EZPORT instruction. When executing this instruction, the JTAG controller resets the core logic and asserts the EzPort chip select signal to force the processor into EzPort mode.

3.5.7.2 Flash Option Register (FOPT)

The FOPT[EZPORT_DIS] bit can be used to prevent entry into EzPort mode during reset. If the FOPT[EZPORT_DIS] bit is cleared, then the state of the chip select signal (EZP_CS) is ignored and the MCU always boots in normal mode. This option is useful for systems that use the EZP_CS/NMI signal configured for its NMI function. Disabling EzPort mode prevents possible unwanted entry into EzPort mode if the external circuit that drives the NMI signal asserts it during reset. The FOPT register is loaded from the flash option byte. If the flash option byte is modified the new value takes effect for any subsequent resets, until the value is changed again.

3.5.8 FlexBus Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 111

Figure 3-31. FlexBus configuration Table 3-42. Reference links to related information Topic Related module Reference Full description FlexBus FlexBus System memory map System memory map Clocking Clock distribution Power management Power management Transfers Memory protection unit (MPU) Memory protection unit (MPU) Signal multiplexing Port control Signal multiplexing

3.5.8.1 FlexBus clocking

The system provides a dedicated clock source to the FlexBus module's external FB_CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See Clock Distribution for more details.

3.5.8.2 FlexBus signal multiplexing

The multiplexing of the FlexBus address and data signals is controlled by the port control module. However, the multiplexing of some of the FlexBus control signals are controlled by the port control and FlexBus modules. The port control module registers control whether the FlexBus or another module signals are available on the external pin, while the FlexBus's CSPMCR register configures which FlexBus signals are available from the module. The control signals are grouped as illustrated: Memories and Memory Interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 112 Freescale Semiconductor, Inc.

FlexBus Port Control Module To other modulesTo other modulesTo other modulesTo other modulesTo other modules External Pins FB_ALE Reserved FB_TSIZ0 Reserved FB_TSIZ1 Reserved Reserved Reserved FB_CS1 FB_TS FB_CS4 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 FB_CS5 FB_TBST FB_CS2 FB_TA FB_CS3 Figure 3-32. FlexBus control signal multiplexing Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 113

Therefore, use the CSPMCR and port control registers to configure which control signal is available on the external pin. All control signals, except for FB_TA, are assigned to the ALT5 function in the port control module. Since, unlike the other control signals, FB_TA is an input signal, it is assigned to the ALT6 function.

3.5.8.3 FlexBus CSCR0 reset value

On this device the CSCR0 resets to 0x003F_FC00. Configure this register as needed before performing any FlexBus access.

3.5.8.4 FlexBus Security

When security is enabled on the device, FlexBus accesses may be restricted by configuring the FBSEL field in the SIM's SOPT2 register. See System Integration Module (SIM) for details.

3.5.8.5 FlexBus line transfers

Line transfers are not possible from the ARM Cortex-M4 core. Ignore any references to line transfers in the FlexBus chapter. Security

3.6.1 CRC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. 3.6 Security K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 114 Freescale Semiconductor, Inc.

Figure 3-33. CRC configuration Table 3-43. Reference links to related information Topic Related module Reference Full description CRC CRC System memory map System memory map Power management Power management

3.6.2 MMCAU Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. MMCAU Transfers ARM Cortex M4 Core PPB Figure 3-34. MMCAU configuration Table 3-44. Reference links to related information Topic Related module Reference Full description MMCAU MMCAU System memory map System memory map Clocking Clock Distribution Power Management Power Management Transfers Private Peripheral Bus (PPB) ARM Cortex M4 Core Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 115

3.6.3 RNG Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Peripheral bridge Random number generator Figure 3-35. RNG configuration Table 3-45. Reference links to related information Topic Related module Reference Full description RNG RNG System memory map System memory map Clocking Clock distribution Power management Power management Analog 3.7.1 16-bit SAR ADC with PGA Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. 3.7 Analog K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 116 Freescale Semiconductor, Inc.

Figure 3-36. 16-bit SAR ADC with PGA configuration Table 3-46. Reference links to related information Topic Related module Reference Full description 16-bit SAR ADC with PGA 16-bit SAR ADC with PGA System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing

3.7.1.1 ADC instantiation information

This device contains two ADCs. Each ADC contains a PGA channel for a total of two separate PGAs.

3.7.1.1.1 Number of ADC channels

The number of ADC channels present on the device is determined by the pinout of the specific device package. For details regarding the number of ADC channel available on a particular package, refer to the signal multiplexing chapter of this MCU.

3.7.1.2 DMA Support on ADC

Applications may require continuous sampling of the ADC (4K samples/sec) that may have considerable load on the CPU. Though using PDB to trigger ADC may reduce some CPU load, The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate or cases were PDB is bypassed. The ADC can trigger the DMA (via DMA req) on conversion completion. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 117

3.7.1.3 ADC0 Connections/Channel Assignment

As indicated by the following sections, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode.

3.7.1.3.1 ADC0 Channel Assignment for 100-Pin Package

(SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0)

00000 DAD0 ADC0_DP0 and ADC0_DM01 ADC0_DP02

00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1

00010 DAD2 PGA0_DP and PGA0_DM PGA0_DP

00011 DAD3 ADC0_DP3 and ADC0_DM33 ADC0_DP34

001005 AD4a Reserved Reserved

001015 AD5a Reserved Reserved

001105 AD6a Reserved Reserved

001115 AD7a Reserved Reserved

001005 AD4b Reserved ADC0_SE4b

001015 AD5b Reserved ADC0_SE5b

001105 AD6b Reserved ADC0_SE6b

001115 AD7b Reserved ADC0_SE7b

01000 AD8 Reserved ADC0_SE86

01001 AD9 Reserved ADC0_SE97

01010 AD10 Reserved Reserved

01011 AD11 Reserved Reserved

01100 AD12 Reserved ADC0_SE12

01101 AD13 Reserved ADC0_SE13

01110 AD14 Reserved ADC0_SE14

01111 AD15 Reserved ADC0_SE15

10000 AD16 Reserved Reserved

10001 AD17 Reserved ADC0_SE17

10010 AD18 Reserved ADC0_SE18

10011 AD19 Reserved ADC0_DM08

10100 AD20 Reserved ADC0_DM1

10101 AD21 Reserved

10110 AD22 Reserved

10111 AD23 Reserved 12-bit DAC0 Output

11000 AD24 Reserved Reserved

Table continues on the next page... Analog K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 118 Freescale Semiconductor, Inc.

(SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0)

11001 AD25 Reserved Reserved

11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)9 Bandgap (S.E)9

11100 AD28 Reserved Reserved

11101 AD29 -VREFH (Diff) VREFH (S.E)

11110 AD30 Reserved VREFL

11111 AD31 Module Disabled Module Disabled

1. Interleaved with ADC1_DP3 and ADC1_DM3 2. Interleaved with ADC1_DP3 3. Interleaved with ADC1_DP0 and ADC1_DM0 4. Interleaved with ADC1_DP0 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC1_SE8 7. Interleaved with ADC1_SE9 8. Interleaved with ADC1_DM3 9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification.

3.7.1.4 ADC1 Connections/Channel Assignment

As indicated in the following tables, each ADCx_DPx input and certain ADCx_DMx inputs may operate as single-ended ADC channels in single-ended mode.

3.7.1.4.1 ADC1 Channel Assignment for 100-Pin Package

(SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0)

00000 DAD0 ADC1_DP0 and ADC1_DM01 ADC1_DP02

00001 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1

00010 DAD2 PGA1_DP and PGA1_DM PGA1_DP

00011 DAD3 ADC1_DP3 and ADC1_DM33 ADC1_DP34

001005 AD4a Reserved ADC1_SE4a

001015 AD5a Reserved ADC1_SE5a

001105 AD6a Reserved ADC1_SE6a

001115 AD7a Reserved ADC1_SE7a

001005 AD4b Reserved ADC1_SE4b

001015 AD5b Reserved ADC1_SE5b

001105 AD6b Reserved ADC1_SE6b

Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 119

(SC1n[ADCH]) Channel Input signal (SC1n[DIFF]= 1) Input signal (SC1n[DIFF]= 0)

001115 AD7b Reserved ADC1_SE7b

01000 AD8 Reserved ADC1_SE86

01001 AD9 Reserved ADC1_SE97

01100 AD12 Reserved Reserved

01101 AD13 Reserved ADC1_SE13Reserved

01110 AD14 Reserved ADC1_SE14

01111 AD15 Reserved ADC1_SE15

10001 AD17 Reserved ADC1_SE17

10010 AD18 Reserved VREF Output

10011 AD19 Reserved ADC1_DM08

10100 AD20 Reserved ADC1_DM1

10101 AD21 Reserved Reserved

10111 AD23 Reserved

11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)9 Bandgap (S.E)9 11101 AD29 -VREFH (Diff) VREFH (S.E)

1. Interleaved with ADC0_DP3 and ADC0_DM3 2. Interleaved with ADC0_DP3 3. Interleaved with ADC0_DP0 and ADC0_DM0 4. Interleaved with ADC0_DP0 5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter for details. 6. Interleaved with ADC0_SE8 7. Interleaved with ADC0_SE9 8. Interleaved with ADC0_DM3 9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification.

3.7.1.5 ADC Channels MUX Selection

The following figure shows the assignment of ADCx_SEn channels a and b through a MUX selection to ADC. To select between alternate set of channels, refer to ADCx_CFG2[MUXSEL] bit settings for more details. Analog K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 120 Freescale Semiconductor, Inc.

AD5 [00101] ADCx_SE4a ADCx_SE5a ADCx_SE6a ADCx_SE7a ADCx_SE4b ADCx_SE5b ADCx_SE6b ADCx_SE7b AD4 [00100] AD6 [00110] AD7 [00111] ADC Figure 3-37. ADCx_SEn channels a and b selection

3.7.1.6 ADC Hardware Interleaved Channels

The AD8 and AD9 channels on ADCx are interleaved in hardware using the following configuration. ADC0 AD8 AD9 ADC1 AD8 AD9 ADC0_SE8/ADC1_SE8 ADC0_SE9/ADC1_SE9 Figure 3-38. ADC hardware interleaved channels integration

3.7.1.7 ADC and PGA Reference Options

The ADC supports the following references: Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 121

• VREFH/VREFL - connected as the primary reference option
• 1.2 V VREF_OUT - connected as the V ALT reference option ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to REFSEL description in ADC chapter for more details. The only reference option for the PGA is the 1.2 V VREF_OUT source. The VREF_OUT signal can either be driven by an external voltage source via the VREF_OUT pin or from the output of the VREF module. Ensure that the VREF module is disabled when an external voltage source is used instead. For PGA maximum differential input signal swing range, refer to the device data sheet for 16-bit ADC with PGA characteristics.

3.7.1.8 ADC triggers

The ADC supports both software and hardware triggers. The primary hardware mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions in run mode (where PDB is enabled). On the other hand, the ADC can conduct conversions in low power modes, not triggered by PDB. This allows the ADC to do conversions in low power mode and store the output in the result register. The ADC generates interrupt when the data is ready in the result register that wakes the system from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits in the SOPT7 register. For operation of triggers in different modes, refer to Power Management chapter.

3.7.1.9 Alternate clock

For this device, the alternate clock is connected to OSCERCLK. NOTE This clock option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency.

3.7.1.10 ADC low-power modes

This table shows the ADC low-power modes and the corresponding chip low-power modes. Analog K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 122 Freescale Semiconductor, Inc.

Table 3-47. ADC low-power modes Module mode Chip mode Wait Wait, VLPW Normal Stop Stop, VLPS Low Power Stop LLS, VLLS3, VLLS2, VLLS1

3.7.1.11 PGA Integration

• No additional external pins are required for the PGA as it is part of the ADC and is selected as a separate channel
• Each PGA connects to the differential ADC channels
• The PGA outputs differential pairs that are connected to ADC differential input
• When the PGA is used, differential input from the pins is connected to differential input channel 2 on ADCx Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 123

PGA0PGA0_DP/ADC0_DP0/ADC1_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA1_DP/ADC1_DP0/ADC0_DP3 PGA1_DM/ADC1_DM0/ADC0_DM3 ADC1_DP1 ADC1_DM1 ADC0_DP1 ADC0_DM1 Figure 3-39. PGA Integration

3.7.2 CMP Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Analog K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 124 Freescale Semiconductor, Inc.

Figure 3-40. CMP configuration Table 3-48. Reference links to related information Topic Related module Reference Full description Comparator (CMP) Comparator System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing

3.7.2.1 CMP input connections

The following table shows the fixed internal connections to the CMP. CMP Inputs CMP0 CMP1 CMP2 IN0 CMP0_IN0 CMP1_IN0 CMP2_IN0 IN1 CMP0_IN1 CMP1_IN1 CMP2_IN1 IN2 CMP0_IN2 — — IN3 CMP0_IN3 12b DAC0 reference/ CMP1_IN3 CMP2_IN3 IN4 CMP0_IN4 — — IN5 VREF output/CMP0_IN5 VREF output/CMP1_IN5 —CMP2_IN5 IN6 Bandgap Bandgap Bandgap IN7 6b DAC0 reference 6b DAC1 reference —

3.7.2.2 CMP external references

The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows:

• VREF_OUT - V in1 input
• VDD - V in2 input Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 125

3.7.2.3 External window/sample input

PDB pulse-out controls the CMP Sample/Window timing. 3.7.3 12-bit DAC Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access 12-bit DAC Peripheral bus controller 0 Other peripherals Transfers Figure 3-41. 12-bit DAC configuration Table 3-49. Reference links to related information Topic Related module Reference Full description 12-bit DAC 12-bit DAC System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing 3.7.3.1 12-bit DAC Overview This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a FIFO for DMA support. 3.7.3.2 12-bit DAC Output The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator or ADC. Analog K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 126 Freescale Semiconductor, Inc.

3.7.3.3 12-bit DAC Reference For this device VREF_OUT and VDDA are selectable as the DAC reference. VREF_OUT is connected to the DACREF_1 input and VDDA is connected to the DACREF_2 input. Use DACx_C0[DACRFS] control bit to select between these two options. Be aware that if the DAC and ADC use the VREF_OUT reference simultaneously, some degradation of ADC accuracy is to be expected due to DAC switching.

3.7.4 VREF Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access VREF Peripheral bus controller 0 Other peripherals Transfers Figure 3-42. VREF configuration Table 3-50. Reference links to related information Topic Related module Reference Full description VREF VREF System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing

3.7.4.1 VREF Overview

This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage output. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 127

The voltage reference can provide a reference voltage to external peripherals or a reference to analog peripherals, such as the ADC, DAC, or CMP. NOTE For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be connected to an output load capacitor. Refer the device data sheet for more details. Timers

3.8.1 PDB Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access PDB Peripheral bus controller 0 Other peripherals Transfers Figure 3-43. PDB configuration Table 3-51. Reference links to related information Topic Related module Reference Full description PDB PDB System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing

3.8.1.1 PDB Instantiation

3.8 Timers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 128 Freescale Semiconductor, Inc.

3.8.1.1.1 PDB Output Triggers

Table 3-52. PDB output triggers Number of PDB channels for ADC trigger 2 Number of pre-triggers per PDB channel 2 Number of DAC triggers 1 Number of PulseOut 1

3.8.1.1.2 PDB Input Trigger Connections

Table 3-53. PDB Input Trigger Options PDB Trigger PDB Input

0000 External Trigger

0001 CMP 0

0010 CMP 1

0011 CMP 2

0100 PIT Ch 0 Output

0101 PIT Ch 1 Output

0110 PIT Ch 2 Output

0111 PIT Ch 3 Output

1000 FTM0 Init and Ext Trigger Outputs

1001 FTM1 Init and Ext Trigger Outputs

1010 FTM2 Init and Ext Trigger Outputs

1011 Reserved

1100 RTC Alarm

1101 RTC Seconds

1110 LPTMR Output

1111 Software Trigger

3.8.1.2 PDB Module Interconnections

PDB trigger outputs Connection Channel 0 triggers ADC0 trigger Channel 1 triggers ADC1 trigger and synchronous input 1 of FTM0 DAC triggers DAC0 trigger Pulse-out Pulse-out connected to each CMP module's sample/window input to control sample operation Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 129

3.8.1.3 Back-to-back acknowledgement connections

In this MCU, PDB back-to-back operation acknowledgment connections are implemented as follows:

• PDB channel 0 pre-trigger 0 acknowledgement input: ADC1SC1B_COCO
• PDB channel 0 pre-trigger 1 acknowledgement input: ADC0SC1A_COCO
• PDB channel 1 pre-trigger 0 acknowledgement input: ADC0SC1B_COCO
• PDB channel 1 pre-trigger 1 acknowledgement input: ADC1SC1A_COCO So, the back-to-back chain is connected as a ring: Channel 0 pre-trigger 0 Channel 1 pre-trigger 0 Channel 0 pre-trigger 1 Channel 1 pre-trigger 1 Figure 3-44. PDB back-to-back chain The application code can set the PDBx_CHnC1[BB] bits to configure the PDB pre- triggers as a single chain or several chains.

3.8.1.4 PDB Interval Trigger Connections to DAC

In this MCU, PDB interval trigger connections to DAC are implemented as follows.

• PDB interval trigger 0 connects to DAC0 hardware trigger input.

3.8.1.5 DAC External Trigger Input Connections

In this MCU, two DAC external trigger inputs are implemented.

• DAC external trigger input 0: ADC0SC1A_COCO
• DAC external trigger input 1: ADC1SC1A_COCO Timers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 130 Freescale Semiconductor, Inc.

Application code can set the PDBx_DACINTCn[EXT] bit to allow DAC external trigger input when the corresponding ADC Conversion complete flag, ADCx_SC1n[COCO], is set.

3.8.1.6 Pulse-Out Connection

The Pulse-Out of PDB is connected to all the CMP blocks and used as the sample window.

3.8.1.7 Pulse-Out Enable Register Implementation

The following table shows the comparison of pulse-out enable register at the module and chip level. Table 3-54. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 31:8 - Reserved 0 - POEN 31:1 - Reserved

3.8.2 FlexTimer Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 131

Figure 3-45. FlexTimer configuration Table 3-55. Reference links to related information Topic Related module Reference Full description FlexTimer FlexTimer System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing

3.8.2.1 Instantiation Information

This device contains three FlexTimer modules. The following table shows how these modules are configured. Table 3-56. FTM Instantiations FTM instance Number of channels Features/usage FTM0 8 3-phase motor + 2 general purpose or stepper motor FTM1 2 Quadrature decoder or general purpose FTM2 2 Quadrature decoder or general purpose Compared with the FTM0 configuration, the FTM1 and FTM2 configuration adds the Quadrature decoder feature and reduces the number of channels. Timers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 132 Freescale Semiconductor, Inc.

3.8.2.2 External Clock Options

By default each FTM is clocked by the internal bus clock (the FTM refers to it as system clock). Each module contains a register setting that allows the module to be clocked from an external clock instead. There are two external FTM_CLKINx pins that can be selected by any FTM module via the SOPT4 register in the SIM module.

3.8.2.3 Fixed frequency clock

The fixed frequency clock for each FTM is MCGFFCLK.

3.8.2.4 FTM Interrupts

The FlexTimer has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an FTM interrupt occurs, read the FTM status registers (FMS, SC, and STATUS) to determine the exact interrupt source.

3.8.2.5 FTM Fault Detection Inputs

The following fault detection input options for the FTM modules are selected via the SOPT4 register in the SIM module. The external pin option is selected by default.

• FTM0 FAULT0 = FTM0_FLT0 pin or CMP0 output
• FTM0 FAULT1 = FTM0_FLT1 pin or CMP1 output
• FTM0 FAULT2 = FTM0_FLT2 pin or CMP2 output
• FTM0 FAULT3 = FTM0_FLT3 pin
• FTM1 FAULT0 = FTM1_FLT0 pin or CMP0 output
• FTM1 FAULT1 = CMP1 output
• FTM1 FAULT2 = CMP2 output
• FTM2 FAULT0 = FTM2_FLT0 pin or CMP0 output
• FTM2 FAULT1 = CMP1 output
• FTM2 FAULT2 = CMP2 output

3.8.2.6 FTM Hardware Triggers

The FTM synchronization hardware triggers are connected in the chip as follows: Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 133

• FTM0 hardware trigger 0 = CMP0 Output
• FTM0 hardware trigger 1 = PDB channel 1 Trigger Output
• FTM0 hardware trigger 2 = FTM0_FLT0 pin
• FTM1 hardware trigger 0 = CMP0 Output
• FTM1 hardware trigger 1 = CMP1 Output
• FTM1 hardware trigger 2 = FTM1_FLT0 pin
• FTM2 hardware trigger 0 = CMP0 Output
• FTM2 hardware trigger 1 = CMP2 Output
• FTM2 hardware trigger 2 = FTM2_FLT0 pin

3.8.2.7 Input capture options for FTM module instances

The following channel 0 input capture source options are selected via the SOPT4 register in the SIM module. The external pin option is selected by default.

• FTM1 channel 0 input capture = FTM1_CH0 pin or CMP0 output or CMP1 output
• FTM2 channel 0 input capture = FTM2_CH0 pin or CMP0 output or CMP1 output

3.8.2.8 FTM output triggers for other modules

FTM output triggers can be selected as input triggers for the PDB and ADC modules. See PDB Instantiation and ADC triggers.

3.8.2.9 FTM Global Time Base

This chip provides the optional FTM global time base feature (see Global Time Base (GTB)). FTM0 provides the only source for the FTM global time base. The other FTM modules can share the time base as shown in the following figure: Timers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 134 Freescale Semiconductor, Inc.

gtb_in FTM1 GTBEEN = 1 FTM Counter CONF Register GTBEOUT = 0FTM0 GTBEEN = 1 FTM Counter CONF Register GTBEOUT = 1 gtb_out gtb_in gtb_in FTM2 GTBEEN = 1 FTM Counter CONF Register GTBEOUT = 0 Figure 3-46. FTM Global Time Base Configuration

3.8.2.10 FTM BDM and debug halt mode

In the FTM chapter, references to the chip being in "BDM" are the same as the chip being in “debug halt mode".

3.8.3 PIT Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Peripheral bridge Periodic interrupt timer Figure 3-47. PIT configuration Table 3-57. Reference links to related information Topic Related module Reference Full description PIT PIT System memory map System memory map Clocking Clock Distribution Power management Power management Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 135

3.8.3.1 PIT/DMA Periodic Trigger Assignments

The PIT generates periodic trigger events to the DMA Mux as shown in the table below. Table 3-58. PIT channel assignments for periodic DMA triggering DMA Channel Number PIT Channel DMA Channel 0 PIT Channel 0 DMA Channel 1 PIT Channel 1 DMA Channel 2 PIT Channel 2 DMA Channel 3 PIT Channel 3

3.8.3.2 PIT/ADC Triggers

PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits in the SIM module. For more details, refer to SIM chapter.

3.8.4 Low-power timer configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge Module signals Low-power timer Figure 3-48. LPT configuration Table 3-59. Reference links to related information Topic Related module Reference Full description Low-power timer Low-power timer System memory map System memory map Clocking Clock Distribution Table continues on the next page... Timers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 136 Freescale Semiconductor, Inc.

Table 3-59. Reference links to related information (continued) Topic Related module Reference Power management Power management Signal Multiplexing Port control Signal Multiplexing

3.8.4.1 LPTMR prescaler/glitch filter clocking options

The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield. NOTE The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. LPTMR0_PSR[PCS] Prescaler/glitch filter clock number Chip clock 00 0 MCGIRCLK — internal reference clock (not available in VLPS/LLS/VLLS modes) 01 1 LPO — 1 kHz clock 10 2 ERCLK32K — secondary external reference clock 11 3 OSCERCLK — external reference clock See Clock Distribution for more details on these clocks.

3.8.4.2 LPTMR pulse counter input options

The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input 00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 Reserved Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 137

3.8.5 CMT Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access CMT Peripheral bus controller 0 Figure 3-49. CMT configuration Table 3-60. Reference links to related information Topic Related module Reference Full description Carrier modulator transmitter (CMT) CMT System memory map System memory map Clocking Clock distribution Power management Power management Signal multiplexing Port control Signal multiplexing

3.8.5.1 Instantiation Information

This device contains one CMT module.

3.8.5.2 IRO Drive Strength

The IRO pad requires higher current drive than can be obtained from a single pad. For this device, the pin associated with the CMT_IRO signal is doubled bonded to two pads. The SOPT2[CMTUARTPAD] field in SIM module can be used to configure the pin associated with the CMT_IRO signal as a higher current output port pin. Timers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 138 Freescale Semiconductor, Inc.

3.8.6 RTC configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge Module signals Real-time clock Figure 3-50. RTC configuration Table 3-61. Reference links to related information Topic Related module Reference Full description RTC RTC System memory map System memory map Clocking Clock Distribution Power management Power management

3.8.6.1 RTC_CLKOUT signal

When the RTC is enabled and the port control module selects the RTC_CLKOUT function, the RTC_CLKOUT signal is fixed to a 1 Hz output.

3.8.6.2 RTC_WAKEUP signal

The RTC_WAKEUP pin is not supported on this device.

3.8.6.3 RTC seconds interrupt

The RTC seconds interrupt is not supported on this device. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 139

3.9.1 Ethernet Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access Ethernet Peripheral bridge 1 Crossbar switch Transfers Figure 3-51. Ethernet configuration Table 3-62. Reference links to related information Topic Related module Reference Full description Ethernet Ethernet System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing

3.9.1.1 Ethernet Clocking Options

The Ethernet module uses the following clocks:

• The device's system clock is connected to the module clock, as named in the Ethernet chapter. The minimum system clock frequency for 100 Mbps operation is 25 MHz.
• An externally-supplied 25 MHz MII clock or 50 MHz RMII clock. This clock is used as the timing reference for the external MII or RMII interface.
• A time-stamping clock for the IEEE 1588 timers. For more details on the Ethernet module clocking options, see Ethernet Clocking. 3.9 Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 140 Freescale Semiconductor, Inc.

3.9.1.2 RMII Clocking

On this device, RMII_REF_CLK is internally tied to EXTAL. See Clock Distribution for clocking requirements.

3.9.1.3 IEEE 1588 Timers

The ethernet module includes a four channel timer module for IEEE 1588 timestamping. The timer supports input capture (rising, falling, or both edges), output compare (toggle or pulse with programmable polarity). The timer matches on greater than or equal (the 1588 can skip numbers, so the counter might not ever exactly match the compare value). The counter is able to operate asynchronously to the ethernet bus by using one of four clock sources. See Ethernet Clocking for more details.

3.9.1.4 Ethernet Operation in Low Power Modes

The Ethernet module is not fully operational in any low power modes. However, the module does support magic packet detection that can generate a wakeup in stop mode if enabled. During low power operation:

• The MAC transmit logic is disabled
• The core FIFO receive/transmit functions are disabled
• The MAC receive logic is kept in normal mode, but it ignores all traffic from the line except magic packets. The recieve logic needed for magic packet detection is clocked using the externally- supplied MII or RMII clock. This allows for the wakeup functionality in stop mode. No Ethernet operation, including magic packet wakeup, is supported in VLPx modes.

3.9.1.4.1 IEEE 1588 Timer Operation in Low Power Modes

The 1588 counter and 1588 timer channels can continue operating in low power modes provided their clock is enabled in that mode. The 1588 timer channels can also generate an interrupt to exit the low power mode if the clock is enabled in that mode. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 141

3.9.1.5 Ethernet Doze Mode

The doze mode for the Ethernet module is the same as the wait and VLPW modes for the chip.

3.9.1.6 Ethernet Interrupts

The Ethernet has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate an interrupt request. See below for a summary: Interrupt request Interrupt source IEEE 1588 timer interrupt • Time stamp available

• 1588 timer interrupt Transmit interrupt • Transmit frame interrupt
• Transmit buffer interrupt Receive interrupt • Receive frame interrupt
• Receive buffer interrupt Error and miscellaneous interrupt • Wake-up
• Payload receive error
• Babbling receive error
• Babbling transmit error
• Graceful stop complete
• MII interrupt – Data transfer done
• Ethernet bus error
• Late collision
• Collision retry limit

3.9.1.7 Ethernet event signal

The event signal output is not supported on this device. Therefore, ATCR[PINPER] has no effect.

3.9.2 Universal Serial Bus (USB) Subsystem

The USB subsystem includes these components:

• Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) device or FS/LS host. The module complies with the USB 2.0 specification.
• USB transceiver that includes internal 15 k Ω pulldowns on the D+ and D- lines for host mode functionality.
• A 3.3 V regulator.
• USB device charger detection module.
• VBUS detect signal: To detect a valid VBUS in device mode, use a GPIO signal that can wake the chip in all power modes. Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 142 Freescale Semiconductor, Inc.

Figure 3-52. USB Subsystem Overview

3.9.2.1 USB Wakeup

When the USB detects that there is no activity on the USB bus for more than 3 ms, the INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the appropriate action. Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBTRC0[USBRESMEN] bit enables this function.

3.9.2.2 USB Power Distribution

This chip includes an internal 5 V to 3.3 V USB regulator that powers the USB transceiver or the MCU (depending on the application).

3.9.2.2.1 AA/AAA cells power supply

The chip can be powered by two AA/AAA cells. In this case, the MCU is powered through VDD which is within the 1.8 to 3.0 V range. After USB cable insertion is detected, the USB regulator is enabled to power the USB transceiver. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 143

USB0_DP USB0_DM VDD VOUT33 VREGIN TYPE A VBUS

2 AA Cells

Figure 3-53. USB regulator AA cell usecase

3.9.2.2.2 Li-Ion battery power supply

The chip can also be powered by a single Li-ion battery. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU. When connected to a USB host, the input source of this regulator is switched to the USB bus supply from the Li-ion battery. To charge the battery, the MCU can configure the battery charger according to the charger detection information. Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 144 Freescale Semiconductor, Inc.

USBXCVRUSBControllerUSB0_DM USB0_DP VDD VOUT33 VREGINTYPE A VBUS Cstab To PMC and Pads Chip ChargerDetect VBUS SenseVSS Charger Li-Ion Si2301 Figure 3-54. USB regulator Li-ion usecase

3.9.2.2.3 USB bus power supply

The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU, then to power USB transceiver or external sensor. USB Regulator USB XCVR USB Controller USB0_DP USB0_DM VDD VOUT33 VREGIN TYPE A VBUS Cstab To PMC and Pads Chip Figure 3-55. USB regulator bus supply Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 145

3.9.2.3 USB power management

The regulator should be put into STANDBY mode whenever the chip is in Stop mode. This can be done by setting the SIM_SOPT1[USBSTBY] bit.

3.9.2.4 USB controller configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signals Register access USB controller Peripheral bridge 0 Crossbar switch Transfers Figure 3-56. USB controller configuration Table 3-63. Reference links to related information Topic Related module Reference Full description USB controller USB controller System memory map System memory map Clocking Clock Distribution Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing NOTE When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating.

3.9.2.5 USB DCD Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 146 Freescale Semiconductor, Inc.

Figure 3-57. USB DCD configuration Table 3-64. Reference links to related information Topic Related module Reference Full description USB DCD USB DCD System memory map System memory map Clocking Clock Distribution USB controller USB controller

3.9.2.6 USB Voltage Regulator Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Module signalsUSB Voltage Regulator USB OTG Figure 3-58. USB Voltage Regulator configuration Table 3-65. Reference links to related information Topic Related module Reference Full description USB Voltage Regulator USB Voltage Regulator System memory map System memory map Clocking Clock Distribution USB controller USB controller Signal Multiplexing Port control Signal Multiplexing Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 147

When USB is not used in the application, it is recommended that the USB regulator VREGIN and VOUT33 pins remain floating.

3.9.3 CAN Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access FlexCAN Peripheral bridge Module signals Figure 3-59. CAN configuration Table 3-66. Reference links to related information Topic Related module Reference Full description CAN CAN System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing

3.9.3.1 Number of FlexCAN modules

This device contains 2 identical FlexCAN modules.

3.9.3.2 Reset value of MDIS bit

The CAN_MCR[MDIS] bit is set after reset. Therefore, FlexCAN module is disabled following a reset. Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 148 Freescale Semiconductor, Inc.

3.9.3.3 Number of message buffers

Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes.

3.9.3.4 FlexCAN Clocking

3.9.3.4.1 Clocking Options

The FlexCAN module has a register bit CANCTRL[CLK_SRC] that selects between clocking the FlexCAN from the internal bus clock or the input clock (EXTAL).

3.9.3.4.2 Clock Gating

The clock to each CAN module can be gated on and off using the SCGCn[CANx] bits. These bits are cleared after any reset, which disables the clock to the corresponding module. The appropriate clock enable bit should be set by software at the beginning of the FlexCAN initialization routine to enable the module clock before attempting to initialize any of the FlexCAN registers.

3.9.3.5 FlexCAN Interrupts

The FlexCAN has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: Request Sources Message buffer Message buffers 0-15 Bus off Bus off Error • Bit1 error

• Bit0 error
• Acknowledge error
• Cyclic redundancy check (CRC) error
• Form error
• Stuffing error
• Transmit error warning
• Receive error warning Transmit Warning Transmit Warning Receive Warning Receive Warning Wake-up Wake-up Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 149

3.9.3.6 FlexCAN Operation in Low Power Modes

The FlexCAN module is operational in VLPR and VLPW modes. With the 2 MHz bus clock, the fastest supported FlexCAN transfer rate is 256 kbps. The bit timing parameters in the module must be adjusted for the new frequency, but full functionality is possible. The FlexCAN module can be configured to generate a wakeup interrupt in STOP and VLPS modes. When the FlexCAN is configured to generate a wakeup, a recessive to dominant transition on the CAN bus generates an interrupt.

3.9.3.7 FlexCAN Doze Mode

The Doze mode for the FlexCAN module is the same as the Wait and VLPW modes for the chip.

3.9.4 SPI configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access SPI Peripheral bridge Module signals Figure 3-60. SPI configuration Table 3-67. Reference links to related information Topic Related module Reference Full description SPI SPI System memory map System memory map Clocking Clock Distribution Signal Multiplexing Port control Signal Multiplexing Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 150 Freescale Semiconductor, Inc.

3.9.4.1 SPI Modules Configuration

This device contains three SPI modules.

3.9.4.2 SPI clocking

The SPI module is clocked by the internal bus clock (the DSPI refers to it as system clock). The module has an internal divider, with a minimum divide is two. So, the SPI can run at a maximum frequency of bus clock/2.

3.9.4.3 Number of CTARs

SPI CTAR registers define different transfer attribute configurations. The SPI module supports up to eight CTAR registers. This device supports two CTARs on all instances of the SPI. In master mode, the CTAR registers define combinations of transfer attributes, such as frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer attributes.

3.9.4.4 TX FIFO size

Table 3-68. SPI transmit FIFO size SPI Module Transmit FIFO size SPI0 4 SPI1 4 SPI2 4

3.9.4.5 RX FIFO Size

SPI supports up to 16-bit frame size during reception. Table 3-69. SPI receive FIFO size SPI Module Receive FIFO size SPI0 4 SPI1 4 SPI2 4 Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 151

3.9.4.6 Number of PCS signals

The following table shows the number of peripheral chip select signals available per SPI module. Table 3-70. SPI PCS signals SPI Module PCS Signals SPI0 SPI_PCS[5:0] SPI1 SPI_PCS[3:0] SPI2 SPI_PCS[1:0]

3.9.4.7 SPI Operation in Low Power Modes

In VLPR and VLPW modes the SPI is functional; however, the reduced system frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW modes the max SPI_CLK frequency is 1MHz. In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not functional, but it is powered so that it retains state. There is one way to wake from stop mode via the SPI, which is explained in the following section.

3.9.4.7.1 Using GPIO Interrupt to Wake from stop mode

Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave mode: 1. Point the GPIO interrupt vector to the desired interrupt handler. 2. Enable the GPIO input to generate an interrupt on either the rising or falling edge (depending on the polarity of the chip select signal). 3. Enter Stop or VLPS mode and Wait for the GPIO interrupt. NOTE It is likely that in using this approach the first word of data from the SPI host might not be received correctly. This is dependent on the transfer rate used for the SPI, the delay between chip select assertion and presentation of data, and the system interrupt latency. Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 152 Freescale Semiconductor, Inc.

3.9.4.8 SPI Doze Mode

The Doze mode for the SPI module is the same as the Wait and VLPW modes for the chip.

3.9.4.9 SPI Interrupts

The SPI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request per SPI module to the interrupt controller. When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source.

3.9.4.10 SPI clocks

This table shows the SPI module clocks and the corresponding chip clocks. Table 3-71. SPI clock connections Module clock Chip clock System Clock Bus Clock

3.9.5 I2C Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 153

Figure 3-61. I2C configuration Table 3-72. Reference links to related information Topic Related module Reference Full description I2C I2C System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing

3.9.5.1 Number of I2C modules

This device has two I2C modules.

3.9.6 UART Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 154 Freescale Semiconductor, Inc.

Figure 3-62. UART configuration Table 3-73. Reference links to related information Topic Related module Reference Full description UART UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing

3.9.6.1 UART configuration information

This device contains five UART modules. This section describes how each module is configured on this device. 1. Standard features of all UARTs:

• RS-485 support
• Hardware flow control (RTS/CTS)
• 9-bit UART to support address mark with parity
• MSB/LSB configuration on data 2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are clocked on the bus clock. The maximum baud rate is 1/16 of related source clock frequency. 3. IrDA is available on all UARTs 4. UART0 contains the standard features plus ISO7816 5. AMR support on all UARTs. The pin control and interrupts (PORT) module supports open-drain for all I/O. 6. UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs 7. All other UARTs contain a 1-entry transmit and receive FIFOs Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 155

3.9.6.2 UART wakeup

The UART can be configured to generate an interrupt/wakeup on the first active edge that it receives.

3.9.6.3 UART interrupts

The UART has multiple sources of interrupt requests. However, some of these sources are OR'd together to generate a single interrupt request. See below for the mapping of the individual interrupt sources to the interrupt request: The status interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 UART 3 UART 4 Transmit data empty x x x x x Transmit complete x x x x x Idle line x x x x x Receive data full x x x x x LIN break detect x x x x x RxD pin active edge x x x x x Initial character detect x — — — — The error interrupt combines the following interrupt sources: Source UART 0 UART 1 UART 2 UART 3 UART 4 Receiver overrun x x x x x Noise flag x x x x x Framing error x x x x x Parity error x x x x x Transmitter buffer overflow x x x x x Receiver buffer underflow x x x x x Transmit threshold (ISO7816) x — — — — Receiver threshold (ISO7816) x — — — — Wait timer (ISO7816) x — — — — Character wait timer (ISO7816) x — — — — Table continues on the next page... Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 156 Freescale Semiconductor, Inc.

Source UART 0 UART 1 UART 2 UART 3 UART 4 Block wait timer (ISO7816) x — — — — Guard time violation (ISO7816) x — — — —

3.9.7 SDHC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Crossbar switch Register access Peripheral bridge Module signals SDHC Transfers Signal multiplexing Figure 3-63. SDHC configuration Table 3-74. Reference links to related information Topic Related module Reference Full description SDHC SDHC System memory map System memory map Clocking Clock Distribution Power management Power management Transfers Crossbar switch Crossbar switch Signal Multiplexing Port control Signal Multiplexing

3.9.7.1 SDHC clocking

In addition to the system clock, the SDHC needs a clock for the base for the external card clock. There are four possible clock sources for this clock, selected by the SIM’s SOPT2 register:

• Core/system clock
• MCGPLLCLK or MCGFLLCLK
• EXTAL
• Bypass clock from off-chip (SDHC0_CLKIN) Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 157

3.9.7.2 SD bus pullup/pulldown constraints

The SD standard requires the SD bus signals (except the SD clock) to be pulled up during data transfers. The SDHC also provides a feature of detecting card insertion/removal, by detecting voltage level changes on DAT[3] of the SD bus. To support this DAT[3] must be pulled down. To avoid a situation where the SDHC detects voltage changes due to normal data transfers on the SD bus as card insertion/removal, the interrupt relating to this event must be disabled after the card has been inserted and detected. It can be re- enabled after the card is removed.

3.9.8 I2S configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge Module signals2I S Figure 3-64. I2S configuration Table 3-75. Reference links to related information Topic Related module Reference Full description I2S I2S System memory map System memory map Clocking Clock Distribution Power management Power management Signal multiplexing Port control Signal Multiplexing NOTE The I2S master clock can be output on the I2S0_MCLK pin or input on the I2S0_CLKIN pin. Using the I2S0_RX_BCLK pin to output the I2S master clock in synchronous mode is not supported on this device. Communication interfaces K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 158 Freescale Semiconductor, Inc.

3.9.8.1 Interrupts

The interrupt outputs from the I2S module are OR'd to create a single interrupt to the interrupt control logic.

3.9.8.2 DMA requests

The I2S module has two DMA requests:

• Transmit FIFO
• Receive FIFO

3.9.8.3 I2S clock generation

To generate the desired frequencies for the I2S module there are multiple clocking options as shown below:

• The core/system clock is routed to an 8-bit fractional divider to generate the I 2S clock.
• The PLL output is routed to an 8-bit fractional divider to generate the I 2S clock.
• The EXTAL pin directly drives the I 2S clock.
• The I2S0_CLKIN pin directly drives the I 2S clock. These options are controlled by the SIM_SOPT2[I2SSRC] field, and the 8-bit fractional divider is controlled by the SIM_CLKDIV2[I2SDIV, I2SFRAC] fields. See the SIM module for details.

3.9.8.4 I2S operation in low power modes

The I2S module requires interaction with the rest of the system to move data in or out of the FIFOs. Since the rest of the system is not active in stop, VLPS, and LLS modes, there is no use for the I2S in these modes. The I2S is powered so that it retains state in these modes, but it is not functional. In VLPR and VLPW modes, the I2S is functional. However, the I2S is limited to 400 kHz maximum frequency. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 159

Human-machine interfaces (HMI)

3.10.1 GPIO configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge Module signals GPIO controller Crossbar switch Transfers Figure 3-65. GPIO configuration Table 3-76. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking Clock Distribution Power management Power management Transfers Crossbar switch Clock Distribution Signal Multiplexing Port control Signal Multiplexing

3.10.1.1 GPIO access protection

The GPIO module does not have access protection because it is not connected to a peripheral bridge slot and is not protected by the MPU.

3.10.1.2 Number of GPIO signals

The number of GPIO signals available on the devices covered by this document are detailed in Orderable part numbers. 3.10 Human-machine interfaces (HMI) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 160 Freescale Semiconductor, Inc.

3.10.2 TSI Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Signal multiplexing Register access Peripheral bridge Module signalsTouch sense input module Figure 3-66. TSI configuration Table 3-77. Reference links to related information Topic Related module Reference Full description TSI TSI System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing

3.10.2.1 Number of inputs

This device includes one TSI module containing 16 inputs. In low-power modes, one selectable pin is active.

3.10.2.2 TSI module functionality in MCU operation modes

Table 3-78. TSI module functionality in MCU operation modes MCU operation mode TSI clock sources TSI operation mode when GENCS[TSIEN] is 1 Functional electrode pins Required GENCS[STPE] state Run BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care Wait BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care Table continues on the next page... Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 161

Table 3-78. TSI module functionality in MCU operation modes (continued) MCU operation mode TSI clock sources TSI operation mode when GENCS[TSIEN] is 1 Functional electrode pins Required GENCS[STPE] state Stop MCGIRCLK, OSCERCLK Active mode All 1 VLPR BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care VLPW BUSCLK, MCGIRCLK, OSCERCLK Active mode All Don’t care VLPS OSCERCLK Active mode All 1 LLS LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP] VLLS3 LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP] VLLS2 LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP] VLLS1 LPOCLK, VLPOSCCLK Low power mode Determined by PEN[LPSP]

3.10.2.3 TSI clocks

This table shows the TSI clocks and the corresponding chip clocks. Table 3-79. TSI clock connections Module clock Chip clock BUSCLK Bus clock MCGIRCLK MCGIRCLK OSCERCLK OSCERCLK LPOCLK 1 kHz LPO clock VLPOSCCLK ERCLK32K

3.10.2.4 TSI Interrupts

The TSI has multiple sources of interrupt requests. However, these sources are OR'd together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI status register to determine the exact interrupt source. Human-machine interfaces (HMI) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 162 Freescale Semiconductor, Inc.

3.10.2.5 Shield drive signal

The shield drive signal is not supported on this device. Ignore this feature in the TSI chapter. Chapter 3 Chip Configuration K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 163

Human-machine interfaces (HMI) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 164 Freescale Semiconductor, Inc.

4.1 Introduction

This device contains various memories and memory-mapped peripherals which are located in one 32-bit contiguous memory space. This chapter describes the memory and peripheral locations within that memory space.

4.2 System memory map

The following table shows the high-level device memory map. Table 4-1. System memory map System 32-bit Address Range Destination Slave Access 0x0000_0000–0x0FFF_FFFF Program flash and read-only data (Includes exception vectors in first 1024 bytes) All masters 0x1000_0000–0x13FF_FFFF • For MK60DN256ZVLL10: Reserved

• For MK60DX256ZVLL10: FlexNVM
• For MK60DN512ZVLL10: Reserved All masters 0x1400_0000–0x17FF_FFFF For devices with FlexNVM: FlexRAM For devices with program flash only: Programming acceleration RAM All masters 0x1800_0000–0x1FFF_FFFF SRAM_L: Lower SRAM (ICODE/DCODE) All masters 0x2000_0000–0x200F_FFFF SRAM_U: Upper SRAM bitband region All masters 0x2010_0000–0x21FF_FFFF Reserved – 0x2200_0000–0x23FF_FFFF Aliased to SRAM_U bitband Cortex-M4 core only 0x2400_0000–0x3FFF_FFFF Reserved – 0x4000_0000–0x4007_FFFF Bitband region for peripheral bridge 0 (AIPS-Lite0) Cortex-M4 core & DMA/EzPort Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 165

Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0x4008_0000–0x400F_EFFF Bitband region for peripheral bridge 1 (AIPS-Lite1) Cortex-M4 core & DMA/EzPort 0x400F_F000–0x400F_FFFF Bitband region for general purpose input/output (GPIO) Cortex-M4 core & DMA/EzPort 0x4010_0000–0x41FF_FFFF Reserved – 0x4200_0000–0x43FF_FFFF Aliased to peripheral bridge (AIPS-Lite) and general purpose input/output (GPIO) bitband Cortex-M4 core only 0x4400_0000–0x5FFF_FFFF Reserved – 0x6000_0000–0x7FFF_FFFF FlexBus (External Memory - Write-back) All masters 0x8000_0000–0x9FFF_FFFF FlexBus (External Memory - Write-through) All masters 0xA000_0000–0xDFFF_FFFF FlexBus (External Peripheral - Not executable) All masters 0xE000_0000–0xE00F_FFFF Private peripherals Cortex-M4 core only 0xE010_0000–0xFFFF_FFFF Reserved – NOTE 1. EzPort master port is statically muxed with DMA master port. Access rights to AIPS-Lite peripheral bridges and general purpose input/output (GPIO) module address space is limited to the core, DMA, and EzPort. 2. ARM Cortex-M4 core access privileges also includes accesses via the debug interface.

4.2.1 Aliased bit-band regions

The SRAM_U, AIPS-Lite, and general purpose input/output (GPIO) module resources reside in the Cortex-M4 processor bit-band regions. The processor also includes two 32 MB aliased bit-band regions associated with the two 1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit in the bit-band region. A 32-bit write in the alias region has the same effect as a read- modify-write operation on the targeted bit in the bit-band region. Bit 0 of the value written to the alias region determines what value is written to the target bit:

• Writing a value with bit 0 set writes a 1 to the target bit.
• Writing a value with bit 0 clear writes a 0 to the target bit. A 32-bit read in the alias region returns either: System memory map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 166 Freescale Semiconductor, Inc.

• a value of 0x0000_0000 to indicate the target bit is clear
• a value of 0x0000_0001 to indicate the target bit is set 31 0 031 Bit-band region Alias bit-band region

1 MByte

32 MByte

Figure 4-1. Alias bit-band mapping NOTE Each bit in bit-band region has an equivalent bit that can be manipulated through bit 0 in a corresponding long word in the alias bit-band region.

4.3 Flash Memory Map

The various flash memories and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map. Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 167

Program flash base address Flash memory base address Registers RAM Programming acceleration RAM base address Figure 4-2. Flash memory map for devices containing only program flash Program flash Flash configuration field FlexNVM base address Program flash base address Flash memory base address Registers FlexNVM FlexRAM FlexRAM base address Figure 4-3. Flash memory map for devices containing FlexNVM

4.3.1 Alternate Non-Volatile IRC User Trim Description

The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers. Non-Volatile Byte Address Alternate IRC Trim Value 0x0000_03FC Reserved 0x0000_03FD Reserved 0x0000_03FE (bit 0) SCFTRIM 0x0000_03FE (bit 4:1) FCTRIM 0x0000_03FF SCTRIM Flash Memory Map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 168 Freescale Semiconductor, Inc.

4.4 SRAM memory map

The on-chip RAM is split evenly among SRAM_L and SRAM_U. The RAM is also implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Arrays for details. Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master.

4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory

The peripheral memory map is accessible via two slave ports on the crossbar switch in the 0x4000_0000–0x400F_FFFF region. The device implements two peripheral bridges (AIPS-Lite 0 and 1):

• AIPS-Lite0 covers 512 KB
• AIPS-Lite1 covers 508 KB with 4 KB assigned to the general purpose input/output module (GPIO) AIPS-Lite0 is connected to crossbar switch slave port 2, and is accessible at locations 0x4000_0000–0x4007_FFFF. AIPS-Lite1 and the general purpose input/output module share the connection to crossbar switch slave port 3. The AIPS-Lite1 is accessible at locations 0x4008_0000– 0x400F_EFFF. The general purpose input/output module is accessible in a 4-kbyte region at 0x400F_F000–0x400F_FFFF. Its direct connection to the crossbar switch provides master access without incurring wait states associated with accesses via the AIPS-Lite controllers. Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination. For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination. Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 169

4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map

Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot number Module 0x4000_0000 0 Peripheral bridge 0 (AIPS-Lite 0) 0x4000_1000 1 — 0x4000_2000 2 — 0x4000_3000 3 — 0x4000_4000 4 Crossbar switch 0x4000_5000 5 — 0x4000_6000 6 — 0x4000_7000 7 — 0x4000_8000 8 DMA controller 0x4000_9000 9 DMA controller transfer control descriptors 0x4000_A000 10 — 0x4000_B000 11 — 0x4000_C000 12 FlexBus 0x4000_D000 13 MPU 0x4000_E000 14 — 0x4000_F000 15 — 0x4001_0000 16 — 0x4001_1000 17 — 0x4001_2000 18 — 0x4001_3000 19 — 0x4001_4000 20 — 0x4001_5000 21 — 0x4001_6000 22 — 0x4001_7000 23 — 0x4001_8000 24 — 0x4001_9000 25 — 0x4001_A000 26 — 0x4001_B000 27 — 0x4001_C000 28 — 0x4001_D000 29 — 0x4001_E000 30 — 0x4001_F000 31 Flash memory controller 0x4002_0000 32 Flash memory Table continues on the next page... Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 170 Freescale Semiconductor, Inc.

Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4002_1000 33 DMA channel mutiplexer 0 0x4002_2000 34 — 0x4002_3000 35 — 0x4002_4000 36 FlexCAN 0 0x4002_5000 37 — 0x4002_6000 38 — 0x4002_7000 39 — 0x4002_8000 40 — 0x4002_9000 41 — 0x4002_A000 42 — 0x4002_B000 43 — 0x4002_C000 44 SPI 0 0x4002_D000 45 SPI 1 0x4002_E000 46 — 0x4002_F000 47 I2S 0 0x4003_0000 48 — 0x4003_1000 49 — 0x4003_2000 50 CRC 0x4003_3000 51 — 0x4003_4000 52 — 0x4003_5000 53 USB DCD 0x4003_6000 54 Programmable delay block (PDB) 0x4003_7000 55 Periodic interrupt timers (PIT) 0x4003_8000 56 FlexTimer (FTM) 0 0x4003_9000 57 FlexTimer (FTM) 1 0x4003_A000 58 — 0x4003_B000 59 Analog-to-digital converter (ADC) 0 0x4003_C000 60 — 0x4003_D000 61 Real-time clock (RTC) 0x4003_E000 62 VBAT register file 0x4003_F000 63 — 0x4004_0000 64 Low-power timer (LPTMR) 0x4004_1000 65 System register file 0x4004_2000 66 — Table continues on the next page... Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 171

Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4004_3000 67 — 0x4004_4000 68 — 0x4004_5000 69 Touch sense interface (TSI) 0x4004_6000 70 — 0x4004_7000 71 SIM low-power logic 0x4004_8000 72 System integration module (SIM) 0x4004_9000 73 Port A multiplexing control 0x4004_A000 74 Port B multiplexing control 0x4004_B000 75 Port C multiplexing control 0x4004_C000 76 Port D multiplexing control 0x4004_D000 77 Port E multiplexing control 0x4004_E000 78 — 0x4004_F000 79 — 0x4005_0000 80 — 0x4005_1000 81 — 0x4005_2000 82 Software watchdog 0x4005_3000 83 — 0x4005_4000 84 — 0x4005_5000 85 — 0x4005_6000 86 — 0x4005_7000 87 — 0x4005_8000 88 — 0x4005_9000 89 — 0x4005_A000 90 — 0x4005_B000 91 — 0x4005_C000 92 — 0x4005_D000 93 — 0x4005_E000 94 — 0x4005_F000 95 — 0x4006_0000 96 — 0x4006_1000 97 External watchdog 0x4006_2000 98 Carrier modulator timer (CMT) 0x4006_3000 99 — 0x4006_4000 100 Multi-purpose Clock Generator (MCG) Table continues on the next page... Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 172 Freescale Semiconductor, Inc.

Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot number Module 0x4006_5000 101 System oscillator (OSC) 0x4006_6000 102 I2C 0 0x4006_7000 103 I2C 1 0x4006_8000 104 0x4006_9000 105 — 0x4006_A000 106 UART 0 0x4006_B000 107 UART 1 0x4006_C000 108 UART 2 0x4006_D000 109 UART 3 0x4006_E000 110 — 0x4006_F000 111 — 0x4007_0000 112 — 0x4007_1000 113 — 0x4007_2000 114 USB OTG FS/LS 0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 116 Voltage reference (VREF) 0x4007_5000 117 — 0x4007_6000 118 — 0x4007_7000 119 — 0x4007_8000 120 — 0x4007_9000 121 — 0x4007_A000 122 — 0x4007_B000 123 — 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 —

4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map

Table 4-3. Peripheral bridge 1 slot assignments System 32-bit base address Slot number Module 0x4008_0000 0 Peripheral bridge 1 (AIPS-Lite 1) Table continues on the next page... Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 173

Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot number Module 0x4008_1000 1 — 0x4008_2000 2 — 0x4008_3000 3 — 0x4008_4000 4 — 0x4008_5000 5 — 0x4008_6000 6 — 0x4008_7000 7 — 0x4008_8000 8 — 0x4008_9000 9 — 0x4008_A000 10 — 0x4008_B000 11 — 0x4008_C000 12 — 0x4008_D000 13 — 0x4008_E000 14 — 0x4008_F000 15 — 0x4009_0000 16 — 0x4009_1000 17 — 0x4009_2000 18 — 0x4009_3000 19 — 0x4009_4000 20 — 0x4009_5000 21 — 0x4009_6000 22 — 0x4009_7000 23 — 0x4009_8000 24 — 0x4009_9000 25 — 0x4009_A000 26 — 0x4009_B000 27 — 0x4009_C000 28 — 0x4009_D000 29 — 0x4009_E000 30 — 0x4009_F000 31 — 0x400A_0000 32 Random number generator (RNGB) 0x400A_1000 33 — 0x400A_2000 34 — Table continues on the next page... Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 174 Freescale Semiconductor, Inc.

Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot number Module 0x400A_3000 35 — 0x400A_4000 36 FlexCAN 1 0x400A_5000 37 — 0x400A_6000 38 — 0x400A_7000 39 — 0x400A_8000 40 — 0x400A_9000 41 — 0x400A_A000 42 — 0x400A_B000 43 — 0x400A_C000 44 SPI 2 0x400A_D000 45 — 0x400A_E000 46 — 0x400A_F000 47 — 0x400B_0000 48 — 0x400B_1000 49 SDHC 0x400B_2000 50 — 0x400B_3000 51 — 0x400B_4000 52 — 0x400B_5000 53 — 0x400B_6000 54 — 0x400B_7000 55 — 0x400B_8000 56 FlexTimer (FTM) 2 0x400B_9000 57 — 0x400B_A000 58 — 0x400B_B000 59 Analog-to-digital converter (ADC) 1 0x400B_C000 60 — 0x400B_D000 61 — 0x400B_E000 62 — 0x400B_F000 63 — 0x400C_0000 64 Ethernet MAC and IEEE 1588 timers 0x400C_1000 65 — 0x400C_2000 66 — 0x400C_3000 67 — 0x400C_4000 68 — Table continues on the next page... Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 175

Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot number Module 0x400C_5000 69 — 0x400C_6000 70 — 0x400C_7000 71 — 0x400C_8000 72 — 0x400C_9000 73 — 0x400C_A000 74 — 0x400C_B000 75 — 0x400C_C000 76 12-bit digital-to-analog converter (DAC) 0 0x400C_D000 77 — 0x400C_E000 78 — 0x400C_F000 79 — 0x400D_0000 80 — 0x400D_1000 81 — 0x400D_2000 82 — 0x400D_3000 83 — 0x400D_4000 84 — 0x400D_5000 85 — 0x400D_6000 86 — 0x400D_7000 87 — 0x400D_8000 88 — 0x400D_9000 89 — 0x400D_A000 90 — 0x400D_B000 91 — 0x400D_C000 92 — 0x400D_D000 93 — 0x400D_E000 94 — 0x400D_F000 95 — 0x400E_0000 96 — 0x400E_1000 97 — 0x400E_2000 98 — 0x400E_3000 99 — 0x400E_4000 100 — 0x400E_5000 101 — 0x400E_6000 102 — Table continues on the next page... Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 176 Freescale Semiconductor, Inc.

Table 4-3. Peripheral bridge 1 slot assignments (continued) System 32-bit base address Slot number Module 0x400E_7000 103 — 0x400E_8000 104 — 0x400E_9000 105 — 0x400E_A000 106 UART 4 0x400E_B000 107 — 0x400E_C000 108 — 0x400E_D000 109 — 0x400E_E000 110 — 0x400E_F000 111 — 0x400F_0000 112 — 0x400F_1000 113 — 0x400F_2000 114 — 0x400F_3000 115 — 0x400F_4000 116 — 0x400F_5000 117 — 0x400F_6000 118 — 0x400F_7000 119 — 0x400F_8000 120 — 0x400F_9000 121 — 0x400F_A000 122 — 0x400F_B000 123 — 0x400F_C000 124 — 0x400F_D000 125 — 0x400F_E000 126 — 0x400F_F000 Not an AIPS-Lite slot. The 32-bit general purpose input/output module that shares the crossbar switch slave port with the AIPS-Lite is accessed at this address. Chapter 4 Memory Map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 177

4.6 Private Peripheral Bus (PPB) memory map

The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them. Table 4-4. PPB memory map System 32-bit Address Range Resource 0xE000_0000–0xE000_0FFF Instrumentation Trace Macrocell (ITM) 0xE000_1000–0xE000_1FFF Data Watchpoint and Trace (DWT) 0xE000_2000–0xE000_2FFF Flash Patch and Breakpoint (FPB) 0xE000_3000–0xE000_DFFF Reserved 0xE000_E000–0xE000_EFFF System Control Space (SCS) (for NVIC) 0xE000_F000–0xE003_FFFF Reserved 0xE004_0000–0xE004_0FFF Trace Port Interface Unit (TPIU) 0xE004_1000–0xE004_1FFF Embedded Trace Macrocell (ETM) 0xE004_2000–0xE004_2FFF Embedded Trace Buffer (ETB) 0xE004_3000–0xE004_3FFF Embedded Trace Funnel 0xE004_4000–0xE007_FFFF Reserved 0xE008_0000–0xE008_0FFF Miscellaneous Control Module (MCM)(including ETB Almost Full) 0xE008_1000–0xE008_1FFF Memory Mapped Cryptographic Acceleration Unit (MMCAU) 0xE008_2000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF ROM Table - allows auto-detection of debug components Private Peripheral Bus (PPB) memory map K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 178 Freescale Semiconductor, Inc.

5.1 Introduction

The MCG module controls which clock source is used to derive the system clocks. The clock generation logic divides the selected clock source into a variety of clock domains, including the clocks for the system bus masters, system bus slaves, and flash memory. The clock generation logic also implements module-specific clock gating to allow granular shutoff of modules. The primary clocks for the system are generated from the MCGOUTCLK clock. The clock generation circuitry provides several clock dividers that allow different portions of the device to be clocked at different frequencies. This allows for trade-offs between performance and power dissipation. Various modules, such as the USB OTG Controller, have module-specific clocks that can be generated from the MCGPLLCLK or MCGFLLCLK clock. In addition, there are various other module-specific clocks that have other alternate sources. Clock selection for most modules is controlled by the SOPT registers in the SIM module.

5.2 Programming model

The selection and multiplexing of system clock sources is controlled and programmed via the MCG module. The setting of clock dividers and module clock gating for the system are programmed via the SIM module. Reference those sections for detailed register and bit descriptions.

5.3 High-Level device clocking diagram

The following system oscillator, MCG, and SIM module registers control the multiplexers, dividers, and clock gates shown in the below figure: K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 179

Muliplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx 32 kHz IRC PLL FLL MCGOUTCLK MCGPLLCLK MCG MCGFLLCLK OUTDIV1 Core / system clocks

4 MHz IRC

XTAL_CLK MCGFFCLK OSCERCLK OSC logic OSC logic Clock options for some peripherals (see note) Clock options for some peripherals (see note) MCGFLLCLK MCGPLLCLK/ Note: See subsequent sections for details on where these clocks are used. PMC logic PMC LPO OSCCLK CG CG CG CG CG CG — Clock gate OUTDIV3 FlexBus clockCG Figure 5-1. Clocking diagram

5.4 Clock definitions

The following table describes the clocks in the previous block diagram. Clock name Description Core clock MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex- M4 core System clock MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters directly connected to the crossbar. In addition, this clock is used for UART0 and UART1. Table continues on the next page... Clock definitions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 180 Freescale Semiconductor, Inc.

Bus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding memories) FlexBus clock MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memory MCGIRCLK MCG output of the slow or fast internal reference clock MCGFFCLK MCG output of the slow internal reference clock or a divided MCG external reference clock. The MCGFFCLK is further divided by 2 before being made available to modules outside the MCG (as shown in the preceding figure). MCGOUTCLK MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or MCG's external reference clock that sources the core, system, bus, FlexBus, and flash clock. It is also an option for the debug trace clock. MCGFLLCLK MCG output of the FLL. MCGFLLCLK or MCGPLLCLK may clock some modules. MCGPLLCLK MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may clock some modules. MCG external reference clock Input clock to the MCG sourced by the system oscillator (OSCCLK) or RTC oscillator OSCCLK System oscillator output of the internal oscillator or sourced directly from EXTAL OSCERCLK System oscillator output sourced from OSCCLKthat may clock some on-chip modules OSC32KCLK System oscillator 32kHz output ERCLK32K Clock source for some modules that is chosen as OSC32KCLK or the RTC clock RTC clock RTC oscillator output for the RTC module LPO PMC 1kHz output

5.4.1 Device clock summary

The following table provides more information regarding the on-chip clocks. Table 5-1. Clock Summary Clock name Run mode clock frequency VLPR mode clock frequency Clock source Clock is disabled when… MCGOUTCLK Up to 100 MHz Up to 2 MHz MCG In all stop modes Core clock Up to 100 MHz Up to 2 MHz MCGOUTCLK clock divider In all wait and stop modes System clock Up to 100 MHz Up to 2 MHz MCGOUTCLK clock divider In all stop modes Bus clock Up to 50 MHz Up to 2 MHz MCGOUTCLK clock divider In all stop modes Table continues on the next page... Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 181

Table 5-1. Clock Summary (continued) Clock name Run mode clock frequency VLPR mode clock frequency Clock source Clock is disabled when… FlexBus clock (FB_CLK) Up to 50 MHz Up to 2 MHz MCGOUTCLK clock divider In all stop modes or FlexBus disabled Flash clock Up to 25 MHz Up to 1 MHz MCGOUTCLK clock divider In all stop modes Internal reference (MCGIRCLK) 30-40 kHz or 2 MHz 2 MHz only MCG MCG_C1[IRCLKEN] cleared, Stop mode and MCG_C1[IREFSTEN] cleared, or VLPS/LLS/VLLS mode External reference (OSCERCLK) Up to 50 MHz (bypass), 30-40 kHz, or 4-32 MHz (crystal) Up to 4 MHz (bypass), 30-40 kHz (low-range crystal) or Up to 4 MHz (high- range crystal) System OSC System OSC's OSC_CR[ERCLKEN] cleared, or Stop mode and OSC_CR[EREFSTEN] cleared External reference 32kHz (ERCLK32K) 30-40 kHz 30-40 kHz System OSC or RTC OSC depending on SIM_SOPT1[OSC32K SEL] System OSC's OSC_CR[ERCLKEN] cleared or RTC's RTC_CR[OSCE] cleared RTC_CLKOUT 1 Hz 1 Hz RTC clock Clock is disabled in LLS and VLLSx modes LPO 1 kHz 1 kHz PMC Available in all power modes USB FS clock 48 MHz N/A MCGPLLCLK or MCGFLLCLK with fractional clock divider, or USB_CLKIN USB FS OTG is disabled I2S master clock Up to 50 MHz N/A System clock, MCGPLLCLK, or MCGFLLCLK with fractional clock divider, OSCERCLK, or I2S_CLKIN I2S is disabled SDHC clock Up to 50 MHz N/A System clock, MCGPLLCLK/ MCGFLLCLK, or OSCERCLK SDHC is disabled Ethernet RMII clock 50 MHz N/A OSCERCLK Ethernet is disabled Table continues on the next page... Clock definitions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 182 Freescale Semiconductor, Inc.

Table 5-1. Clock Summary (continued) Clock name Run mode clock frequency VLPR mode clock frequency Clock source Clock is disabled when… Ethernet IEEE 1588 clock Up to 100 MHz N/A System clock, OSCERCLK, MCGPLLCLK/ MCGFLLCLK, or ENET_1588_CLKIN Ethernet is disabled TRACE clock Up to 100 MHz Up to 2 MHz System clock or MCGOUTCLK Trace is disabled

5.5 Internal clocking requirements

The clock dividers are programmed via the SIM module’s CLKDIV registers. Each divider is programmable from a divide-by-1 through divide-by-16 setting. The following requirements must be met when configuring the clocks for this device: 1. The core and system clock frequencies must be 100 MHz or slower. 2. The bus clock frequency must be programmed to 50 MHz or less and an integer divide of the core clock. 3. The flash clock frequency must be programmed to 25 MHz or less and an integer divide of the bus clock. 4. The FlexBus clock frequency must be programmed to be less than or equal to the bus clock frequency. The following are a few of the more common clock configurations for this device: Option 1: Clock Frequency Core clock 50 MHz System clock 50 MHz Bus clock 50 MHz FlexBus clock 50 MHz Flash clock 25 MHz Option 2: Clock Frequency Core clock 100 MHz Table continues on the next page... Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 183

Option 3: Clock Frequency Core clock 96 MHz System clock 96 MHz Bus clock 48 MHz FlexBus clock 48 MHz Flash clock 24 MHz

5.5.1 Clock divider values after reset

Each clock divider is programmed via the SIM module’s CLKDIVn registers. The flash memory's FTFL_FOPT[LPBOOT] bit controls the reset value of the core clock, system clock, bus clock, and flash clock dividers as shown below: FTFL_FOPT [LPBOOT] Core/system clock Bus clock FlexBus clock Flash clock Description 0 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) 0xF (divide by 16) Low power boot 1 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) 0x1 (divide by 2) Fast clock boot This gives the user flexibility for a lower frequency, low-power boot option. The flash erased state defaults to fast clocking mode, since where the low power boot (FTFL_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state. To enable the low power boot option program FTFL_FOPT[LPBOOT] to zero. During the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration. Upon any system reset, the clock dividers return to this configurable reset state.

5.5.2 VLPR mode clocking

The clock dividers cannot be changed while in VLPR mode. They must be programmed prior to entering VLPR mode to guarantee:

• the core/system, FlexBus, and bus clocks are less than or equal to 2 MHz, and
• the flash memory clock is less than or equal to 1 MHz Internal clocking requirements K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 184 Freescale Semiconductor, Inc.

5.6 Clock Gating

The clock to each module can be individually gated on and off using the SIM module's SCGCx registers. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing a module, set the corresponding bit in SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. Any bus access to a peripheral that has its clock disabled generates an error termination.

5.7 Module clocks

The following table summarizes the clocks associated with each module. Table 5-2. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules ARM Cortex-M4 core System clock Core clock — NVIC System clock — — DAP System clock — — ITM System clock — — ETM System clock TRACE clock TRACE_CLKOUT ETB System clock — — cJTAG, JTAGC — — JTAG_CLK System modules DMA System clock — — DMA Mux Bus clock — — Port control Bus clock LPO — Crossbar Switch System clock — — Peripheral bridges System clock Bus clock — MPU System clock — — LLWU, PMC, SIM Bus clock LPO — Mode controller Bus clock — — MCM System clock — — EWM Bus clock LPO — Watchdog timer Bus clock LPO — Table continues on the next page... Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 185

Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks Clocks MCG Bus clock MCGOUTCLK, MCGPLLCLK, MCGFLLCLK, MCGIRCLK, OSCERCLK OSC Bus clock OSCERCLK — Memory and memory interfaces Flash Controller System clock Flash clock — Flash memory Flash clock — — FlexBus System clock — FB_CLKOUT EzPort System clock — EZP_CLK Security CRC Bus clock — — MMCAU System clock — — RNGB Bus clock — — Analog ADC Bus clock OSCERCLK — CMP Bus clock — — DAC Bus clock — — VREF Bus clock — — Timers PDB Bus clock — — FlexTimers Bus clock MCGFFCLK FTM_CLKINx PIT Bus clock — — LPTMR Bus clock LPO, OSCERCLK, MCGIRCLK, ERCLK32K CMT Bus clock — — RTC Bus clock EXTAL32 — Communication interfaces Ethernet System clock, Bus clock RMII clock, IEEE 1588 clock MII_RXCLK, MII_TXCLK USB FS OTG System clock USB FS clock — USB DCD Bus clock — — FlexCAN Bus clock OSCERCLK — DSPI Bus clock — DSPI_SCK I2C Bus clock — I2C_SCL UART0, UART1 System clock — — UART2-4 Bus clock — — Table continues on the next page... Module clocks K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 186 Freescale Semiconductor, Inc.

Table 5-2. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks SDHC System clock SDHC clock SDHC_DCLK I2S Bus clock I2S master clock I2S_TX_BCLK, I2S_RX_BCLK Human-machine interfaces GPIO System clock — — TSI Bus clock LPO, ERCLK32K, MCGIRCLK

5.7.1 PMC 1-kHz LPO clock

The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock.

5.7.2 WDOG clocking

The WDOG may be clocked from two clock sources as shown in the following figure. WDOG_STCTRLH[CLKSRC] WDOG clock Bus clock LPO Figure 5-2. WDOG clock generation

5.7.3 Debug trace clock

The debug trace clock source can be clocked as shown in the following figure. Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 187

SIM_SOPT2[TRACECLKSEL] TRACECLKIN Core / system clock MCGOUTCLK TPIU TRACE_CLKOUT Figure 5-3. Trace clock generation NOTE The trace clock frequency observed at the TRACE_CLKOUT pin will be half that of the selected clock source.

5.7.4 PORT digital filter clocking

The digital filters in each of the PORTx modules can be clocked as shown in the following figure. NOTE In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. PORTx_DFCR[CS] PORTx digital input filter clock Bus clock LPO Figure 5-4. PORTx digital input filter clock generation

5.7.5 LPTMR clocking

The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. Module clocks K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 188 Freescale Semiconductor, Inc.

The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. LPTMRx_PSR[PCS] LPTMRx prescaler/glitch filter clock MCGIRCLK OSCERCLK ERCLK32K LPO Figure 5-5. LPTMRx prescaler/glitch filter clock generation

5.7.6 Ethernet Clocking

• The RMII clock source is fixed to OSCERCLK and must be 50 MHz
• The MII clocks are supplied from pins and must be 25 MHz
• The IEEE 1588 timestamp clock can run up to 100 MHz, if generated from internal clock sources. Its period must be an integer number of nanoseconds (eg: 10ns = 100 MHz, 15ns = 66.67 MHz, 20ns = 50 MHz). Its clock source is chosen as shown in the following figure. Core / System clock OSCERCLK MCGPLLCLK or MCGFLLCLK ENET_1588_CLKIN SIM_SOPT2[TIMESRC] Ethernet IEEE 1588 timestamp clock Figure 5-6. Ethernet IEEE1588 timestamp clock generation Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 189

5.7.7 USB FS OTG Controller clocking

The USB FS OTG controller is a bus master attached to the crossbar switch. As such, its clock is connected to the system clock. NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. The USB OTG controller also requires a 48 MHz clock. The clock source options are shown below. USB 48MHz USB_CLKIN MCGPLLCLK or MCGFLLCLK SIM_CLKDIV2 [USBFRAC, USBDIV] SIM_SOPT2[USBSRC] Figure 5-7. USB 48 MHz clock source

5.7.8 FlexCAN clocking

The clock for the FlexCAN's protocol engine can be selected as shown in the following figure. CANx_CTRL1[CLKSRC] FlexCAN clock Bus clock OSCERCLK Figure 5-8. FlexCAN clock generation Module clocks K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 190 Freescale Semiconductor, Inc.

5.7.9 UART clocking

UART0 and UART1 modules operate from the core/system clock, which provides higher performance level for these modules. All other UART modules operate from the bus clock.

5.7.10 SDHC clocking

The SDHC module has four possible clock sources for the external clock source, as shown in the following figure. SIM_SOPT2[SDHCSRC] SDHC clock MCGPLLCLK or MCGFLLCLK Core / system clock OSCERCLK SDHC0_CLKIN Figure 5-9. SDHC clock generation

5.7.11 I2S clocking

In addition to the bus clock, the I2S has a clock source for master clock generation. The maximum frequency of this clock is 50 MHz. The master clock source can be derived from several sources, as shown in the following figure. SIM_SOPT2[I2SSRC] Core/system clock MCGPLLCLK or MCGFLLCLK OSCERCLK S master clockI I2S_CLKIN SIM_CLKDIV2 [I2SFRAC,I2SDIV] Figure 5-10. I2S baud clock generation Chapter 5 Clock Distribution K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 191

5.7.12 TSI clocking

In active mode, the TSI can be clocked as shown in the following figure. TSI_SCANC[AMCLKS] TSI clock in active mode Bus clock MCGIRCLK OSCERCLK Figure 5-11. TSI clock generation In low-power mode, the TSI can be clocked as shown in the following figure. NOTE In the TSI chapter, these two clocks are referred to as LPOCLK and VLPOSCCLK. TSI_GENCS[LPCLKS] TSI clock in low-power mode LPO ERCLK32K Figure 5-12. TSI low-power clock generation Module clocks K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 192 Freescale Semiconductor, Inc.

6.1 Introduction

The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN)

• Low-voltage detect (LVD)
• Computer operating properly (COP) watchdog reset
• Low leakage wakeup (LLWU) reset
• Multipurpose clock generator loss of clock (LOC) reset
• Software reset (SW)
• Lockup reset (LOCKUP)
• EzPort reset
• MDM DAP system reset Debug reset • JTAG reset
• nTRST reset Each of the system reset sources, with the exception of the EzPort and MDM-AP reset, has an associated bit in the system reset status registers (SRSH and SRSL). See the Mode controller for more details. The MCU exits reset in functional mode that is controlled by EZP_CS pin to select between the single chip (default) or serial flash programming (EzPort) modes. See Boot options for more details.

6.2 Reset

This section discusses basic reset mechanisms and sources. Some modules that cause resets can be configured to cause interrupts instead. Consult the individual peripheral chapters for more information. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 193

6.2.1 Power-on reset (POR)

When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (VLVDL). The POR and LVD bits in SRSL register are set following a POR.

6.2.2 System resets

Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following:

• Reads the start SP (SP_main) from vector-table offset 0
• Reads the start PC from vector-table offset 4
• LR is set to 0xFFFF_FFFF The on-chip peripheral modules are disabled and the non-analog I/O pins are initially configured as disabled. The pins with analog functions assigned to them default to their analog function after reset. During and following a reset, the JTAG pins have their associated input pins configured as:
• TDI in pull-up (PU)
• TCK in pull-down (PD)
• TMS in PU and associated output pin configured as:
• TDO with no pull-down or pull-up Note that the nTRST signal is initially configured as disabled, however once configured to its JTAG functionality its associated input pin is configured as:
• nTRST in PU Reset K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 194 Freescale Semiconductor, Inc.

6.2.2.1 External pin reset (PIN)

On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the SRSL[PIN] bit is set.

6.2.2.1.1 Reset pin filter

The RESET pin supports digital filtering in all modes of operation. For LLS and VLLSx modes, the LLWU provides an optional fixed digital filter running off the 1 kHz LPO clock. See the LLWU chapter for operation of this filter. During non-low leakage operation, there are two clock options for the RESET pin filter – the 1kHz LPO clock and the bus clock. This RESET pin filter implemented in SIM logic includes a separate filter for each clock source. In Stop and VLPS operation this logic either switches to bypass operation or has continued filtering operation depending on the filtering mode selected. There are several modes defined – See the SOPT6 register description in module for more details. SOPT6[RSTFLTEN[2:0]] and SOPT6[RSTFLTSEL[4:0]] fields control the desired functionality. Both filters are reset on POR, LVD, and wakeup from VLLS. The reset value for each filter defaults to off (non-detect). The LPO filter is simple with a fixed filter value count of 3. There is also a synchronizer on the input signal that results in an associated latency (2 cycles). As such, it takes 5 cycles to complete a transition from low-to-high or high-to-low. The LPO Filter initializes to off (logic 1) when the LPO filter is not enabled. The Bus Filter initializes to off (logic 1) when the Bus Filter not enabled. When the Bus Filter is enabled, the number of counts is controlled by SOPT6[RSTFLTSEL[4:0]].

6.2.2.2 Low-voltage detect (LVD) reset

This device includes a system to protect against low voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a low-voltage detect (LVD) circuit with a user-selectable trip voltage, either high (VLVDH) or low (VLVDL). The trip voltage is selected by the LVDSC1[LVDV] bits. The LVD system is always enabled in normal run, wait, and stop modes. The LVD system is disabled in VLPx, LLSx, and VLLSx modes. Refer to Power Management Controller (PMC) chapter for more details. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 195

The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDSC1[LVDRE]. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage rises above the low voltage detection threshold. The SRSL[LVD] bit is set following an LVD reset or POR.

6.2.2.3 Computer operating properly (COP) watchdog reset

The watchdog timer monitors the operation of the system by expecting periodic communication from the software, generally known as servicing (or refreshing) the watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. The COP reset causes the SRSL[COP] bit to set.

6.2.2.4 Low leakage wakeup (LLWU) reset

The LLWU allows up to 16 external pins, the RESET pin, and up to seven internal peripherals to wake the MCU from LLS and VLLSx power modes. The LLWU module is only functional in LLS and VLLSx power modes. In both these modes, LLS mode exits via RESET pin and any VLLS mode exits via a wakeup or reset event, the SRSL[WAKEUP] bit in mode controller module is set indicating the low leakage mode was active prior to the last system reset flow. Using the RESET pin to trigger an exit from LLS or VLLS results in the SRSL[PIN] bit being set as well. Refer to the mode controller chapter for more details. After a system reset, the LLWU retains the flags to indicate the source of the last wakeup until the user clears them. NOTE Pin wakeup and error condition flags are cleared in the LLWU and module wakeup flags are required to be cleared in the peripheral module. Refer to the individual peripheral specifications for more information.

6.2.2.5 Multipurpose clock generator loss-of-clock (LOC) reset

The MCG includes a clock monitor. The clock monitor resets the device when the following conditions are met:

• The clock monitor is enabled (MCG_C6[CME] = 1)
• The MCG's external reference clock falls outside of the expected frequency range, depending on the MCG_C2[RANGE] bit Reset K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 196 Freescale Semiconductor, Inc.

The MC_SRSL[LOC] bit is set to indicate the error.

6.2.2.6 Software reset (SW)

The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request. This reset forces a system reset of all major components except for the debug module. A software reset causes SRSH[SW] bit to set.

6.2.2.7 Lockup reset (LOCKUP)

The LOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. The LOCKUP condition causes a system reset and also causes SRSH[LOCKUP] bit to set.

6.2.2.8 EzPort reset

The EzPort supports a system reset request via EzPort signalling. The EzPort generates a system reset request following execution of a Reset Chip (RESET) command via the EzPort interface. This method of reset allows the chip to boot from flash memory after it has been programmed by an external source. The EzPort is enabled or disabled by the EZP_CS pin.

6.2.2.9 MDM-AP system reset request

Set the system reset request bit in the MDM-AP control register to initiate a system reset. This is the primary method for resets via the JTAG interface. The system reset is held until this bit is cleared. Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 197

6.2.3 Debug resets

The following sections detail the debug resets available on the device.

6.2.3.1 JTAG reset

The JTAG module generate a system reset when certain IR codes are selected. This functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are active. The reset source from the JTAG module is released when any other IR code is selected. A JTAG reset causes the SRSH[JTAG] bit to set. 6.2.3.2 nTRST reset The nTRST pin causes a reset of the JTAG logic when asserted. Asserting the nTRST pin allows the debugger to gain control of the TAP controller state machine (after exiting LLS or VLLSx) without resetting the state of the debug modules. The nTRST pin does not cause a system reset.

6.2.3.3 Resetting the Debug subsystem

Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug modules. However, as explained below, using the CDBGRSTREQ bit does not reset all debug-related registers. CDBGRSTREQ resets the debug-related registers within the following modules:

• SWJ-DP
• AHB-AP
• ETM
• ATB replicators
• ATB upsizers
• ATB funnels
• ETB
• TPIU
• MDM-AP (MDM control and status registers)
• MCM (ETB “Almost Full” logic) CDBGRSTREQ does not reset the debug-related registers within the following modules:
• CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)
• FPB Reset K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 198 Freescale Semiconductor, Inc.

• DWT
• ITM
• NVIC
• Crossbar bus switch 1
• AHB-AP 1
• Private peripheral bus 1

6.3 Boot

This section describes the boot sequence, including sources and options.

6.3.1 Boot sources

This device only supports booting from internal flash. Any secondary boot must go through an initialization sequence in flash.

6.3.2 Boot options

The device's functional mode is controlled by the state of the EzPort chip select (EZP_CS) pin during reset. The device can be in single chip (default) or serial flash programming mode (EzPort). While in single chip mode the device can be in run or various low power modes mentioned in Power mode transitions. Table 6-2. Mode select decoding EzPort chip select (EZP_CS) Description

0 Serial flash programming mode (EzPort)

1 Single chip (default)

6.3.3 FOPT boot options

The flash option register (FOPT) in flash memory module (FTFL) allows the user to customize the operation of the MCU at boot time. The register contains read-only bits that are loaded from the NVM's option byte in the flash configuration field. The user can 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 199

reprogram the option byte in flash to change the FOPT values that are used for subsequent resets. For more details on programming the option byte, refer to the flash memory chapter. The MCU uses the FTFL_FOPT register bits to configure the device at reset as shown in the following table. Table 6-3. Flash Option Register (FTFL_FOPT) Bit Definitions Bit Num Field Value Definition 7-2 Reserved Reserved for future expansion. 1 EZPORT_DIS 0 EzPort operation is disabled. The device always boots to normal CPU execution and the state of EZP_CS signal during reset is ignored. This option avoids inadvertent resets into EzPort mode if the EZP_CS/NMI pin is used for its NMI function. 1 EzPort operation is enabled. The state of EZP_CS pin during reset determines if device enters EzPort mode.

0 LPBOOT 0 Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured

at reset exit for higher divide values that produce lower power consumption at reset exit.

• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x7 (divide by 8)
• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0xF (divide by 16)

1 Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at

reset exit for higher frequency values that produce faster operating frequencies at reset exit.

• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) are 0x0 (divide by 1)
• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0x1 (divide by 2)

6.3.4 Boot sequence

At power up, the on-chip regulator holds the system in a POR state until the input supply is above the POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating voltage as determined by the LVD. The Mode Controller reset logic then controls a sequence to exit reset. 1. A system reset is held on internal logic, the RESET pin is driven out low, and the MCG is enabled in its default clocking mode. 2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control). 3. The system reset on internal logic continues to be held, but the Flash Controller is released from reset and begins initialization operation while the Mode Control logic continues to drive the RESET pin out low for a count of ~128 Bus Clock cycles. Boot K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 200 Freescale Semiconductor, Inc.

1. The RESET pin is released, but the system reset of internal logic continues to be held until the Flash Controller finishes initialization. EzPort mode is selected instead of the normal CPU execution if EZP_CS is low when the internal reset is deasserted. EzPort mode can be disabled by programming FTFL_FOPT[EZPORT_DIS]. Note: If recovering from VLLS1, 2, or 3 with the LLWU_P3 wakeup pin (PTA4/ FTM0_CH1/NMI/EZP_CS), use rising-edge wakeup in the LLWU or disable EzPort mode to ensure normal recovery. 5. When Flash Initialization completes, the RESET pin is observed. If RESET continues to be asserted (an indication of a slow rise time on the RESET pin or external drive in low), the system continues to be held in reset. Once the RESET pin is detected high, the system is released from reset. 6. At release of system reset, clocking is switched to a slow clock if FTFL_FOPT[LPBOOT] is configured for Low Power Boot 7. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF. The CPU begins execution at the PC location. EzPort mode is entered instead of the normal CPU execution if Ezport mode was latched during the sequence. 8. If FlexNVM is enabled, the flash controller continues to restore the FlexNVM data. This data is not available immediately out of reset and the system should not access this data until the flash controller completes this initialization step as indicated by the EEERDY flag. Subsequent system resets follow this reset flow beginning with the step where system clocks are enabled. Chapter 6 Reset and Boot K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 201

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 202 Freescale Semiconductor, Inc.

7.1 Introduction

This chapter describes the various chip power modes and functionality of the individual modules in these modes.

7.2 Power modes

The power management controller (PMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed. Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The following table compares the various power modes available. For each run mode there is a corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. The very low power run (VLPR) operating mode can drastically reduce runtime power when the maximum bus frequency is not required to handle the application needs. The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1. Chip power modes Chip mode Description Core mode Normal recovery method Normal run Allows maximum performance of chip. Default mode out of reset; on- chip voltage regulator is on. Run - Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 203

Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method Normal Wait - via WFI Allows peripherals to function while the core is in sleep mode, reducing power. NVIC remains sensitive to interrupts; peripherals continue to be clocked. Sleep Interrupt Normal Stop - via WFI Places chip in static state. Lowest power mode that retains all registers while maintaining LVD protection. NVIC is disabled; AWIC is used to wake up from interrupt; peripheral clocks are stopped. Sleep Deep Interrupt VLPR (Very Low Power Run) On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. Reduced frequency Flash access mode (1 MHz); LVD off; internal oscillator provides a low power 2 MHz source for the core, the bus and the peripheral clocks. Run Interrupt VLPW (Very Low Power Wait) -via WFI Same as VLPR but with the core in sleep mode to further reduce power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. Sleep Interrupt VLPS (Very Low Power Stop)-via WFI Places chip in static state with LVD operation off. Lowest power mode with ADC and pin interrupts functional. Peripheral clocks are stopped, but LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt. On-chip voltage regulator is in a low power mode that supplies only enough power to run the chip at a reduced frequency. All SRAM is operating (content retained and I/O states held). Sleep Deep Interrupt LLS (Low Leakage Stop) State retention power mode. Most peripherals are in state retention mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. NOTE: The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. All SRAM is operating (content retained and I/O states held). Sleep Deep Wakeup Interrupt1 VLLS3 (Very Low Leakage Stop3) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. SRAM_U and SRAM_L remain powered on (content retained and I/O states held). Sleep Deep Wakeup Reset2 VLLS2 (Very Low Leakage Stop2) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. SRAM_L is powered off. A portion of SRAM_U remains powered on (content retained and I/O states held). Sleep Deep Wakeup Reset2 VLLS1 (Very Low Leakage Stop1) Most peripherals are disabled (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU is used to wake up. All of SRAM_U and SRAM_L are powered off. The 32-byte system register file and the 32-byte VBAT register file remain powered for customer-critical data. Sleep Deep Wakeup Reset2 Table continues on the next page... Power modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 204 Freescale Semiconductor, Inc.

Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method BAT (backup battery only) The chip is powered down except for the VBAT supply. The RTC and the 32-byte VBAT register file for customer-critical data remain powered. Off Power-up Sequence 1. Resumes normal run mode operation by executing the LLWU interrupt service routine. 2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.

7.3 Entering and exiting power modes

The WFI instruction invokes wait and stop modes for the chip. The processor exits the low-power mode via an interrupt. The Nested Vectored Interrupt Controller (NVIC) describes interrupt operation and what peripherals can cause interrupts. NOTE The WFE instruction can have the side effect of entering a low- power mode, but that is not its intended usage. See ARM documentation for more on the WFE instruction. Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. The wake-up flow from VLLSx is through reset. The wakeup bit in the SRS registers in the Mode Controller is set indicating that the chip is recovering from a low power mode. Code execution begins; however, the I/O pins are held in their pre low power mode entry states, and the system oscillator and MCG registers are reset (even if EREFSTEN had been set before entering VLLSx). Software must clear this hold by writing a 1 to the ACKISO bit in the Control and Status register in the LLWU module. NOTE To avoid unwanted transitions on the pins, software must re- initialize the I/O pins to their pre-low-power mode entry states before releasing the hold. If the oscillator was configured to continue running during VLLSx modes, it must be re- configured before the ACKISO bit is cleared. The oscillator configuration within the MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is cleared unless the register is re-configured. Chapter 7 Power Management K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 205

7.4 Power mode transitions

The following figure shows the power mode transitions. Any reset always brings the chip back to the normal run state. In run, wait, and stop modes active power regulation is enabled. The VLPx modes are limited in frequency, but offer a lower power operating mode than normal modes. The LLS and VLLSx modes are the lowest power stop modes based on amount of logic or memory that is required to be retained by the application. Wait Stop Run LLS VLLS 3, 2, 1 VLPS VLPR VLPW Any reset Figure 7-1. Power mode state transition diagram Power mode transitions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 206 Freescale Semiconductor, Inc.

7.5 Power modes shutdown sequencing

When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction. The ARM core's outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes:

• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP
• All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence:
• Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately.
• Polls stop acknowledge indications from the non-core crossbar masters (DMA, Ethernet), supporting peripherals (SPI, PIT, RNG) and the Flash Controller for indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a previously initiated operation, effectively stalling entry to the targeted low power mode. When all acknowledges are detected, System Clock, Bus Clock and Flash Clock are turned off at the same time.
• MCG and Mode Controller shut off clock sources and/or the internal supplies driven from the on-chip regulator as defined for the targeted low power mode. In wait modes, most of the system clocks are not affected by the low power mode entry. The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-in- wait functionality and have their clocks disabled under these configurations. The debugger modules support a transition from stop, wait, VLPS, and VLPW back to a halted state when the debugger is enabled. This transition is initiated by setting the Debug Request bit in MDM-AP control register. As part of this transition, system clocking is re- established and is equivalent to normal run/VLPR mode clocking configuration.

7.6 Module Operation in Low Power Modes

The following table illustrates the functionality of each module while the chip is in each of the low power modes. (Debug modules are discussed separately; see Debug in Low Power Modes.) Number ratings (such as 2 MHz and 1 Mbps) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used:

• FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF.
• static = Module register states and associated memories are retained. Chapter 7 Power Management K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 207

• powered = Memory is powered to retain contents.
• low power = Flash has a low power state that retains configuration registers to support faster wakeup.
• OFF = Modules are powered off; module is in reset state upon wakeup.
• wakeup = Modules can serve as a wakeup source for the chip. Table 7-2. Module operation in low power modes Modules Stop VLPR VLPW VLPS LLS VLLSx Core modules NVIC static FF FF static static OFF System modules Mode Controller FF FF FF FF FF FF LLWU1 static static static static FF FF Regulator ON low power low power low power low power low power LVD ON disabled disabled disabled disabled disabled Brown-out Detection ON ON ON ON ON ON DMA static FF FF static static OFF Watchdog FF FF FF FF static OFF EWM static FF static static static OFF Clocks 1kHz LPO ON ON ON ON ON ON System oscillator (OSC) OSCERCLK optional OSCERCLK max of 4MHz crystal OSCERCLK max of 4MHz crystal OSCERCLK max of 4MHz crystal limited to low range/low power limited to low range/low power MCG static - MCGIRCLK optional; PLL optionally on but gated

2 MHz IRC 2 MHz IRC static - no clock

Core clock OFF 2 MHz max OFF OFF OFF OFF System clock OFF 2 MHz max 2 MHz max OFF OFF OFF Bus clock OFF 2 MHz max 2 MHz max OFF OFF OFF Memory and memory interfaces Flash powered 1 MHz max access - no pgm low power low power OFF OFF Portion of SRAM_U2 low power low power low power low power low power low power in VLLS3,2 Remaining SRAM_U and all of SRAM_L low power low power low power low power low power low power in VLLS3 Table continues on the next page... Module Operation in Low Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 208 Freescale Semiconductor, Inc.

Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS LLS VLLSx FlexMemory3 low power low power4 low power low power low power low power in VLLS3, OFF in VLLS2 and VLLS1 Register files5 powered powered powered powered powered powered FlexBus static FF FF static static OFF EzPort disabled disabled disabled disabled disabled disabled Communication interfaces USB FS/LS static static static static static OFF USB DCD static FF FF static static OFF USB Voltage Regulator optional optional optional optional optional optional Ethernet wakeup static static static static OFF UART static, wakeup on edge 125 kbps 125 kbps static, wakeup on edge static OFF SPI static 1 Mbps 1 Mbps static static OFF I2C static, address match wakeup 100 kbps 100 kbps static, address match wakeup static OFF CAN wakeup 256 kbps 256 kbps wakeup static OFF I2S FF with external clock6 FF FF FF with external clock6 static OFF SDHC wakeup FF FF wakeup static OFF Security CRC static FF FF static static OFF RNG static FF static static static OFF Timers FTM static FF FF static static OFF PIT static FF FF static static OFF PDB static FF FF static static OFF LPTMR FF FF FF FF FF FF RTC - 32kHz OSC5 FF FF FF FF FF FF CMT static FF FF static static OFF Analog 16-bit ADC ADC internal clock only FF FF ADC internal clock only static OFF CMP7 HS or LS compare FF FF HS or LS compare LS compare LS compare 6-bit DAC static FF FF static static static Table continues on the next page... Chapter 7 Power Management K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 209

Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS LLS VLLSx VREF FF FF FF FF static OFF 12-bit DAC static FF FF static static static Human-machine interfaces GPIO wakeup FF FF wakeup static, pins latched OFF, pins latched TSI wakeup FF FF wakeup wakeup8 wakeup8 1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a transition to occur to the LLWU. 2. A 4KB portion of SRAM_U block is left powered on in low power mode VLLS2. 3. FlexRAM is always powered in VLLS3. When the FlexRAM is configured for traditional RAM, optionally powered in VLLS2 mode. When the FlexRAM is configured for EEPROM, off in VLLS2 mode. 4. FlexRAM enabled as EEPROM is not writable in VLPR and writes are ignored. Read accesses to FlexRAM as EEPROM while in VLPR are allowed. There are no access restrictions for FlexRAM configured as traditional RAM. 5. These components remain powered in BAT power mode. 6. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL). 7. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered modes of operation are not available while in stop, VLPS, LLS, or VLLSx modes. 8. TSI wakeup from LLS and VLLSx modes is limited to a single selectable pin.

7.7 Clock Gating

To conserve power, the clocks to most modules can be turned off using the SCGCx registers in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module. Prior to initializing a module, set the corresponding bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution and SIM chapters. Clock Gating K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 210 Freescale Semiconductor, Inc.

8.1 Introduction

This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules.

8.2 Flash Security

The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to flash resources. During reset, the flash module initializes the FSEC register using data read from the security byte of the flash configuration field. NOTE The security features apply only to external accesses: debug and EzPort. CPU accesses to the flash are not affected by the status of FSEC. In the unsecured state all flash commands are available to the programming interfaces (JTAG and EzPort), as well as user code execution of Flash Controller commands. When the flash is secured (FSEC[SEC] = 00, 01, or 11), programmer interfaces are only allowed to launch mass erase operations and have no access to memory locations. Further information regarding the flash security options and enabling/disabling flash security is available in the Flash Memory Module. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 211

8.3 Security Interactions with other Modules

The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules.

8.3.1 Security interactions with FlexBus

When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses through the FlexBus interface. The FBSL bitfield also has an option to allow opcode and operand accesses or only operand accesses.

8.3.2 Security Interactions with EzPort

When flash security is active the MCU can still boot in EzPort mode. The EzPort holds the flash logic in NVM special mode and thus limits flash operation when flash security is active. While in EzPort mode and security is active, flash bulk erase (BE) can still be executed. The write FCCOB registers (WRFCCOB) command is limited to the mass erase (Erase All Blocks) and verify all 1s (Read 1s All Blocks) commands. Read accesses to internal memories via the EzPort are blocked when security is enabled. The mass erase can be used to disable flash security, but all of the flash contents are lost in the process. A mass erase via the EzPort is allowed even when some memory locations are protected. When mass erase has been disabled, mass erase via the EzPort is blocked and cannot be defeated.

8.3.3 Security Interactions with Debug

When flash security is active the JTAG port cannot access the memory resources of the MCU. Boundary scan chain operations work, but debugging capabilities are disabled so that the debug port cannot read flash contents. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All Blocks) command. A mass erase via the debugger is allowed even when some memory locations are protected. Security Interactions with other Modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 212 Freescale Semiconductor, Inc.

When mass erase is disabled, mass erase via the debugger is blocked. Chapter 8 Security K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 213

Security Interactions with other Modules K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 214 Freescale Semiconductor, Inc.

9.1 Introduction

This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported:

• IEEE 1149.1 JTAG
• IEEE 1149.7 JTAG (cJTAG)
• Serial Wire Debug (SWD)
• ARM Real-Time Trace Interface The basic Cortex-M4 debug architecture is very flexible. The following diagram shows the topology of the core debug architecture and its components. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 215

(internal) Trigger ITM TPIU Core FPB AHB-AP NVIC SWJ-DP Bus Matrix APB i/f Trace port (serial wire or multi-pin) Cortex-M4 SW/ JTAG Debug Sleep InterruptsINTNMI SLEEPING SLEEPDEEP INTISR[239:0] AWIC DWT ROM Table ETB ETM Instr. Data MCM MMCAU I-code bus D-code bus System bus Code bus MDM-AP Figure 9-1. Cortex-M4 Debug Topology The following table presents a brief description of each one of the debug components. Table 9-1. Debug Components Description Module Description SWJ-DP+ cJTAG Modified Debug Port with support for SWD, JTAG, cJTAG AHB-AP AHB Master Interface from JTAG to debug module and SOC system memory maps JTAG-AP Bridge to DFT/BIST resources. ROM Table Identifies which debug IP is available. Core Debug Singlestep, Register Access, Run, Core Status CoreSight Trace Funnel (not shown in figure) The CSTF combines multiple trace streams onto a single ATB bus. CoreSight Trace Replicator (not shown in figure) The ATB replicator enables two trace sinks to be wired together and operate from the same incoming trace stream. ETM (Embedded Trace Macrocell) ETMv3.5 Architecture CoreSight ETB (Embedded Trace Buffer) Memory mapped buffer used to store trace data. ITM S/W Instrumentation Messaging + Simple Data Trace Messaging + Watchpoint Messaging Table continues on the next page... Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 216 Freescale Semiconductor, Inc.

Table 9-1. Debug Components Description (continued) Module Description DWT (Data and Address Watchpoints) 4 data and address watchpoints (configurable for less, but 4 seems to be accepted) FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space. The FBP also contains six instruction comparators for matching against instruction fetches from Code space, and remapping to a corresponding area in System space. Alternatively, the six instruction comparators can individually configure the comparators to return a Breakpoint Instruction (BKPT) to the processor core on a match, so providing hardware breakpoint capability. TPIU (Trace Port Inteface Unit) Synchronous Mode (5-pin) = TRACE_D[3:0] + TRACE_CLKOUT Synchronous Mode (3-pin) = TRACE_D[1:0] + TRACE_CLKOUT Asynchronous Mode (1-pin) = TRACE_SWO (available on JTAG_TDO) MCM (Miscellaneous Control Module) The MCM provides miscellaneous control functions including control of the ETB and trace path switching.

9.1.1 References

For more information on ARM debug components, see these documents:

• ARMv7-M Architecture Reference Manual
• ARM Debug Interface v5.1
• ARM CoreSight Architecture Specification
• ARM ETM Architecture Specification v3.5

9.2 The Debug Port

The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in the following figure: Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 217

nS Y S _TR S T nS Y S _TDO nS Y S _TDI nS Y S _TC K nS Y S _TMS nTR S T TC K TMS _OUT TMS _IN TMS _OUT_OE TMS TDO TDI S WC L K TC K S WDITMS S WDO S WDOE N S WD/ J TAG S E L E C T S WC L K TC K S WDITMS J TAG S E L S WDS E L 4’b1111 or 4’b0000 TDI TDO P E N J TAG NS W J TAG C TDO TDI nTR S T TC K TMS jtag _updateins tr[3:0] 4’b1111 or 4’b1110 J TAG ir[3:0] IR ==B Y PAS S or IDC ODE IR ==B Y PAS S or IDC ODE A A (1’b0 = 2-pin c J TAG ) (1’b1 = 4-pin J TAG ) To Tes t R es ourc es 1’b1 MDM-AP AHB-AP Figure 9-2. Modified Debug Port The debug port comes out of reset in standard JTAG mode and is switched into either cJTAG or SWD mode by the following sequences. Once the mode has been changed, unused debug pins can be reassigned to any of their alternative muxed functions.

9.2.1 JTAG-to-SWD change sequence

1. Send more than 50 TCK cycles with TMS (SWDIO) =1 2. Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB transmitted first) 3. Send more than 50 TCK cycles with TMS (SWDIO) =1 NOTE See the ARM documentation for the CoreSight DAP Lite for restrictions.

9.2.2 JTAG-to-cJTAG change sequence

1. Reset the debug port The Debug Port K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 218 Freescale Semiconductor, Inc.

1. Set the control level to 2 via zero-bit scans 3. Execute the Store Format (STFMT) command (00011) to set the scan format register to 1149.7 scan format

9.3 Debug Port Pin Descriptions

The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions. Table 9-2. Debug port pins Pin Name JTAG Debug Port cJTAG Debug Port SWD Debug Port Internal Pull- up\\Down Type Description Type Description Type Description JTAG_TMS/ SWD_DIO I/O JTAG Test Mode Selection I/O cJTAG Data I/O Serial Wire Data Pull-up JTAG_TCLK/ SWD_CLK I JTAG Test Clock I cJTAG Clock I Serial Wire Clock Pull-down JTAG_TDI I JTAG Test Data Input - - - - Pull-up JTAG_TDO/ TRACE_SW O O JTAG Test Data Output O Trace output over a single pin O Trace output over a single pin N/C JTAG_TRST I JTAG Reset I cJTAG Reset - - Pull-up

9.4 System TAP connection

The system JTAG controller is connected in parallel to the ARM TAP controller. The system JTAG controller IR codes overlay the ARM JTAG controller IR codes without conflict. Refer to the IR codes table for a list of the available IR codes. The output of the TAPs (TDO) are muxed based on the IR code which is selected. This design is fully JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, ARM's IDCODE (IR=4'b1110) is selected. Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 219

9.4.1 IR Codes

Table 9-3. JTAG Instructions Instruction Code[3:0] Instruction Summary IDCODE 0000 Selects device identification register for shift SAMPLE/PRELOAD 0010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation SAMPLE 0011 Selects boundary scan register for shifting and sampling without disturbing functional operation EXTEST 0100 Selects boundary scan register while applying preloaded values to output pins and asserting functional reset HIGHZ 1001 Selects bypass register while three-stating all output pins and asserting functional reset CLAMP 1100 Selects bypass register while applying preloaded values to output pins and asserting functional reset EZPORT 1101 Enables the EZPORT function for the SoC and asserts functional reset. ARM_IDCODE 1110 ARM JTAG-DP Instruction BYPASS 1111 Selects bypass register for data operations Factory debug reserved 0101, 0110, 0111 Intended for factory debug only ARM JTAG-DP Reserved 1000, 1010, 1011, 1110 These instructions will go the ARM JTAG-DP controller. Please look at ARM JTAG-DP documentation for more information on these instructions. Reserved 1 All other opcodes Decoded to select bypass register 1. The manufacturer reserves the right to change the decoding of reserved instruction codes in the future

9.5 JTAG status and control registers

Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the following figure. These registers provide additional control and status for low power mode recovery and typical run-control scenarios. The status register bits also provide a means for the debugger to get updated status of the core without having to initiate a bus transaction across the crossbar switch, thus remaining less intrusive during a debug session. JTAG status and control registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 220 Freescale Semiconductor, Inc.

It is important to note that these DAP control and status registers are not memory mapped within the system memory map and are only accessible via the Debug Access Port (DAP) using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with the available registers shown in the table below. Table 9-4. MDM-AP Register Summary Address Register Description 0x0100_0000 Status See MDM-AP Status Register 0x0100_0004 Control See MDM-AP Control Register 0x0100_00FC ID Read-only identification register that always reads as 0x001C_0000 SWJ-DP SELECT[31:24] (APSEL) selects the AP SELECT[7:4] (APBANKSEL) selects the bank A[3:2] from the APACC selects the register within the bank AHB Ac c es s P ort (AHB-AP ) MDM -AP S tatus 0x00 C ontrol 0x01 IDR 0x3F AHB-AP SELECT[31:24] = 0x00 selects the AHB-AP See ARM documentation for further details MDM-AP SELECT[31:24] = 0x01 selects the MDM-AP SELECT[7:4] = 0x0 selects the bank with Status and Ctrl A[3:2] = 2’b00 selects the Status Register A[3:2] = 2’b01 selects the Control Register SELECT[7:4] = 0xF selects the bank with IDR A[3:2] = 2’b11 selects the IDR Register (IDR register reads 0x001C_0000) Bus Matrix S ee C ontrol and S tatus R egis ter Des c riptions Debug P ortInternal BusAccess P ort Data[31:0] A[7:4] A[3:2] RnWAPSEL Decode Debug Port ID Register (DPIDR) Control/Status (CTRL/STAT) AP Select (SELECT) Read Buffer (REBUFF) DP Registers 0x00 0x04 0x08 0x0C Data[31:0] A[3:2] RnW DPACC Data[31:0] A[3:2] RnW APACC Debug Port (DP) Generic See the ARM Debug Interface v5p1 Supplement. Figure 9-3. MDM AP Addressing Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 221

9.5.1 MDM-AP Control Register

Table 9-5. MDM-AP Control register assignments Bit Name Secure1 Description 0 Flash Mass Erase in Progress Y Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset. 1 Debug Disable N Set to disable debug. Clear to allow debug operation. When set it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. 2 Debug Request N Set to force the Core to halt. If the Core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state. 3 System Reset Request N Set to force a system reset. The system remains held in reset until this bit is cleared.

4 Core Hold Reset N Configuration bit to control Core operation at the end of system reset

sequencing.

0 Normal operation - release the Core from reset along with the rest of

the system at the end of system reset sequencing.

1 Suspend operation - hold the Core in reset at the end of reset

sequencing. Once the system enters this suspended state, clearing this control bit immediately releases the Core from reset and CPU operation begins.

5 VLLSx Debug Request

(VLLDBGREQ) N Set to configure the system to be held in reset after the next recovery from a VLLSx mode. This bit drives directly to the Mode Controller to control this feature. This bit holds the Core in reset when VLLSx modes are exited to allow the debugger time to re-initialize debug IP before the debug session continues. The Mode Controller captures this bit logic on entry to VLLSx modes. Upon exit from VLLSx modes, the Mode Controller holds the Core in reset at the end of system reset sequencing. The Mode Controller will hold the Core in reset until VLLDBGACK is asserted. The VLLDBGREQ bit clears automatically due to the POR reset generated as part of the VLLSx recovery.

6 VLLSx Debug Acknowledge

(VLLDBGACK) N Set to release a Core being held in reset following a VLLSx recovery This bit is used by the debugger to release the system reset when it is being held on VLLSx mode exit. The debugger re-initializes all debug IP and then assert this control bit to allow the Mode Controller to release the Core from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger or can be left set because it clears automatically due to the POR reset generated as part of the next VLLSx recovery. Table continues on the next page... JTAG status and control registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 222 Freescale Semiconductor, Inc.

Table 9-5. MDM-AP Control register assignments (continued) Bit Name Secure1 Description

7 LLS, VLLSx Status Acknowledge N Set this bit to acknowledge the DAP LLS and VLLS Status bits have

been read. This acknowledge automatically clears the status bits. This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 8 – Reserved for future use N 1. Command available in secure mode

9.5.2 MDM-AP Status Register

Table 9-6. MDM-AP Status register assignments Bit Name Description 0 Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash Mass Erase Acknowledge is set after Flash control logic has started the mass erase operation. When mass erase is disabled (via MEEN and SEC settings), an erase request due to seting of Flash Mass Erase in Progress bit is not acknowledged.

1 Flash Ready Indicate Flash has been initialized and debugger can be configured even

if system is continuing to be held in reset via the debugger. 2 System Security Indicates the security state. When secure, the debugger does not have access to the system bus or any memory mapped peripherals. This bit indicates when the part is locked and no system bus access is possible. 3 System Reset Indicates the system reset state.

0 System is in reset

1 System is not in reset

4 Reserved

5 Mass Erase Enable Indicates if the MCU can be mass erased or not

0 Mass erase is disabled

1 Mass erase is enabled

6 Backdoor Access Key Enable Indicates if the MCU has the backdoor access key enabled.

0 Disabled

1 Enabled

Table continues on the next page... Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 223

Table 9-6. MDM-AP Status register assignments (continued) Bit Name Description

7 LP Enabled Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are

the selected power mode the next time the ARM Core enters Deep Sleep.

0 Low Power Stop Mode is not enabled

1 Low Power Stop Mode is enabled

Usage intended for debug operation in which Run to VLPS is attempted. Per debug definition, the system actually enters the Stop state. A debugger should interpret deep sleep indication (with SLEEPDEEP and SLEEPING asserted), in conjuntion with this bit asserted as the debugger- VLPS status indication. 8 Very Low Power Mode Indicates current power mode is VLPx. This bit is not ‘sticky’ and should always represent whether VLPx is enabled or not. This bit is used to throttle JTAG TCK frequency up/down. 9 LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS. Since the debug modules held their state during LLS, they do not need to be reconfigured. This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is held until the debugger has had a chance to recognize that LLS was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 10 VLLSx Modes Exit This bit indicates an exit from VLLSx mode has occurred. The debugger will lose communication while the system is in VLLSx (including access to this register). Once communication is reestablished, this bit indicates that the system had been in VLLSx. Since the debug modules lose their state during VLLSx modes, they need to be reconfigured. This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit bit is held until the debugger has had a chance to recognize that a VLLS mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. 11 – 15 Reserved for future use Always read 0.

16 Core Halted Indicates the Core has entered debug halt mode

17 Core SLEEPDEEP Indicates the Core has entered a low power mode

SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode. SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode.

18 Core SLEEPING

19 – 31 Reserved for future use Always read 0.

9.6 Debug Resets

The debug system receives the following sources of reset:

• JTAG_TRST_b from an external signal. This signal is optional and may not be available in all packages. Debug Resets K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 224 Freescale Semiconductor, Inc.

• Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the TCLK domain that allows the debugger to reset the debug logic.
• TRST asserted via the cJTAG escape command.
• System POR reset Conversely the debug system is capable of generating system reset using the following mechanism:
• A system reset in the DAP control register which allows the debugger to hold the system in reset.
• SYSRESETREQ bit in the NVIC application interrupt and reset control register
• A system reset in the DAP control register which allows the debugger to hold the Core in reset.

9.7 AHB-AP

AHB-AP provides the debugger access to all memory and registers in the system, including processor registers through the NVIC. System access is independent of the processor status. AHB-AP does not do back-to-back transactions on the bus, so all transactions are non-sequential. AHB-AP can perform unaligned and bit-band transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch debugging such as read/stop/reset the core. AHB-AP transactions are little endian. The MPU includes default settings and protections for the Region Descriptor 0 (RGD0) such that the Debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master. For a short period at the start of a system reset event the system security status is being determined and debugger access to all AHB-AP transactions is blocked. The MDM-AP Status register is accessible and can be monitored to determine when this initial period is completed. After this initial period, if system reset is held via assertion of the RESET pin, the debugger has access via the bus matrix to the private peripheral bus to configure the debug IP even while system reset is asserted. While in system reset, access to other memory and register resources, accessed over the Crossbar Switch, is blocked. Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 225

9.8 ITM

The ITM is an application-driven trace source that supports printf style debugging to trace Operating System (OS) and application events, and emits diagnostic system information. The ITM emits trace information as packets. There are four sources that can generate packets. If multiple sources generate packets at the same time, the ITM arbitrates the order in which packets are output. The four sources in decreasing order of priority are: 1. Software trace -- Software can write directly to ITM stimulus registers. This emits packets. 2. Hardware trace -- The DWT generates these packets, and the ITM emits them. 3. Time stamping -- Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of the Serial Wire Viewer (SWV) output clocks the counter. 4. Global system timestamping. Timestamps can optionally be generated using a system-wide 48-bit count value. The same count value can be used to insert timestamps in the ETM trace stream, allowing coarse-grain correlation.

9.9 Core Trace Connectivity

9.10 Embedded Trace Macrocell v3.5 (ETM) The Cortex-M4 Embedded Trace Macrocell (ETM-M4) is a debug component that enables a debugger to reconstruct program execution. The CoreSight ETM-M4 supports only instruction trace. You can use it either with the Cortex-M4 Trace Port Interface Unit (M4-TPIU), or with the CoreSight ETB. The main features of an ETM are:

• tracing of 16-bit and 32-bit Thumb instructions
• four EmbeddedICE watchpoint inputs
• a Trace Start/Stop block with EmbeddedICE inputs
• one reduced function counter
• two external inputs
• a 24-byte FIFO queue
• global timestamping ITM K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 226 Freescale Semiconductor, Inc.

9.11 Coresight Embedded Trace Buffer (ETB)

The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts trace data from any CoreSight-compliant component trace source with an ATB master port, such as a trace source or a trace funnel. It is included in this device to remove dependencies from the trace pin pad speed, and enable low cost trace solutions. The TraceRAM size is 2 KB. APB i/f ATB slave port ATB i/f TraceRAMControl Trace RAM interface TRIGIN Register Bank Formatter APB (from ETM Trigger out) Figure 9-4. ETB Block Diagram The ETB contains the following blocks:

• Formatter -- Inserts source ID signals into the data packet stream so that trace data can be re-associated with its trace source after the data is read back out of the ETB.
• Control -- Control registers for trace capture and flushing.
• APB interface -- Read, write, and data pointers provide access to ETB registers. In addition, the APB interface supports wait states through the use of a PREADYDBG signal output by the ETB. The APB interface is synchronous to the ATB domain.
• Register bank -- Contains the management, control, and status registers for triggers, flushing behavior, and external control.
• Trace RAM interface -- Controls reads and writes to the Trace RAM.

9.11.1 Performance Profiling with the ETB

To create a performance profile (e.g. gprof) for the target application, a means to collect trace over a long period of time is needed. The ETB buffer is too small to capture a meaningful profile in just one take. What is needed is to collect and concatenate data from the ETB buffer for multiple sequential runs. Using the ETB packet counter (described in Miscellaneous Control Module (MCM)), the trace analysis tool can capture Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 227

multiple sequential runs by executing code until the ETB is almost full, and halting or executing an interrupt handler to allow the buffer to be emptied, and then continuing executing code. The target halts or executes an interrupt handler when the buffer is almost full to empty the data and then the debugger runs the target again.

9.11.2 ETB Counter Control

The ETB packet counter is controlled by the ETB counter control register, ETB reload register, and ETB counter value register implemented in the Miscellaneous Control Module (MCM) accessible via the Private Peripheral Bus. Via the ETB counter control register the ETB control logic can be configured to cause an MCM Alert Interrupt, an NMI Interrupt, or cause a Debug halt when the down counter reaches 0. Other features of the ETB control logic include:

• Down counter to count as many as 512 x 32-bit packets.
• Reload request transfers reload value to counter.
• ATB valid and ready signals used to form counter decrement.
• The counter disarms itself when the count reaches 0.

9.12 TPIU

The TPIU acts as a bridge between the on-chip trace data from the Embedded Trace Macrocell (ETM) and the Instrumentation Trace Macrocell (ITM), with separate IDs, to a data stream, encapsulating IDs where required, that is then captured by a Trace Port Analyzer (TPA). The TPIU is specially designed for low-cost debug.

9.13 DWT

The DWT is a unit that performs the following debug functionality:

• It contains four comparators that you can configure as a hardware watchpoint, an ETM trigger, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT. The second comparator, DWT_COMP1, can also be used as a data comparator.
• The DWT contains counters for:
• Clock cycles (CYCCNT)
• Folded instructions
• Load store unit (LSU) operations TPIU K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 228 Freescale Semiconductor, Inc.

• Sleep cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead NOTE An event is emitted each time a counter overflows.
• The DWT can be configured to emit PC samples at defined intervals, and to emit interrupt event information.

9.14 Debug in Low Power Modes

In low power modes in which the debug modules are kept static or powered off, the debugger cannot gather any debug data for the duration of the low power mode. In the case that the debugger is held static, the debug port returns to full functionality as soon as the low power mode exits and the system returns to a state with active debug. In the case that the debugger logic is powered off, the debugger is reset on recovery and must be reconfigured once the low power mode is exited. Power mode entry logic monitors Debug Power Up and System Power Up signals from the debug port as indications that a debugger is active. These signals can be changed in RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to enter stop or VLPS, FCLK continues to run to support core register access and trace. In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar. With debug enabled, transitions from Run directly to VLPS are not allowed and result in the system entering Stop mode instead. Status bits within the MDM-AP Status register can be evaluated to determine this pseudo-VLPS state. Note with the debug enabled, transitions from Run--> VLPR --> VLPS are still possible but also result in the system entering Stop mode instead. In VLLS mode all debug modules are powered off and reset at wakeup. In LLS mode, the debug modules retain their state but no debug activity is possible. NOTE When using cJTAG and entering LLS mode, the cJTAG controller must be reset on exit from LLS mode. Going into a VLLSx mode causes all the debug controls and settings to be reset. To give time to the debugger to sync up with the HW, the MDM-AP Control register can be configured hold the system in reset on recovery so that the debugger can regain control and reconfigure debug logic prior to the system exiting reset and resuming operation. Chapter 9 Debug K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 229

9.14.1 Debug Module State in Low Power Modes

The following table shows the state of the debug modules in low power modes. These terms are used:

• FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF.
• static = Module register states and associated memories are retained.
• OFF = Modules are powered off; module is in reset state upon wakeup. Table 9-7. Debug Module State in Low Power Modes Module STOP VLPR VLPW VLPS LLS VLLSx Debug Port FF FF FF OFF static OFF AHB-AP FF FF FF OFF static OFF ITM FF FF FF OFF static OFF ETM FF FF FF OFF static OFF ETB FF FF FF OFF static OFF TPIU FF FF FF OFF static OFF DWT FF FF FF OFF static OFF

9.15 Debug & Security

When security is enabled (FSEC[SEC] != 10), the debug port capabilities are limited in order to prevent exploitation of secure data. In the secure state the debugger still has access to the MDM-AP Status Register and can determine the current security state of the device. In the case of a secure device, the debugger also has the capability of performing a mass erase operation via writes to the MDM-AP Control Register. In the case of a secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. Debug & Security K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 230 Freescale Semiconductor, Inc.

Signal Multiplexing and Signal Descriptions

10.1 Introduction

To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. The Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin.

10.2 Signal Multiplexing Integration

This section summarizes how the module is integrated into the device. For a comprehensive description of the module itself, see the module’s dedicated chapter. Register access Signal Multiplexing/ Port Control TransfersModule Peripheral bus controller 1 Module Module External Pins Transfers Figure 10-1. Signal multiplexing integration Table 10-1. Reference links to related information Topic Related module Reference Full description Port control Port control System memory map System memory map Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 231

Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus controller Peripheral bridge

10.2.1 Port control and interrupt module features

• Five 32-pin ports NOTE Not all pins are available on the device. See the following section for details.
• Each 32-pin port is assigned one interrupt.
• The digital filter option has two clock source options: bus clock and 1-kHz LPO. The 1-kHz LPO option gives users this feature in low power modes.
• The digital filter is configurable from 1 to 32 clock cycles when enabled.

10.2.2 Clock gating

The clock to the port control module can be gated on and off using the SCGC5[PORTx] bits in the SIM module. These bits are cleared after any reset, which disables the clock to the corresponding module to conserve power. Prior to initializing the corresponding module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off the clock, make sure to disable the module. For more details, refer to the clock distribution chapter.

10.2.3 Signal multiplexing constraints

1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other.

10.3 Pinout

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 232 Freescale Semiconductor, Inc.

10.3.1 K60 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 100 LQF P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

1 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1 I2C1_SDA

2 PTE1/

LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RXSDHC0_D0 I2C1_SCL

3 PTE2/

LLWU_P1 ADC1_SE6aADC1_SE6aPTE2/ LLWU_P1 SPI1_SCKUART1_CTS SDHC0_DCL K

4 PTE3 ADC1_SE7aADC1_SE7aPTE3 SPI1_SIN UART1_RTS

SDHC0_CM D

5 PTE4/

LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TXSDHC0_D3

6 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2

7 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CTS

I2S0_MCLK I2S0_CLKIN

8 VDD VDD VDD

9 VSS VSS VSS

10 USB0_DP USB0_DP USB0_DP

11 USB0_DM USB0_DM USB0_DM

12 VOUT33 VOUT33 VOUT33

13 VREGIN VREGIN VREGIN

14 ADC0_DP1ADC0_DP1ADC0_DP1

15 ADC0_DM1ADC0_DM1ADC0_DM1

16 ADC1_DP1ADC1_DP1ADC1_DP1

17 ADC1_DM1ADC1_DM1ADC1_DM1

18 PGA0_DP/

ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3

19 PGA0_DM/

ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3

20 PGA1_DP/

ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3

21 PGA1_DM/

ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3

22 VDDA VDDA VDDA

23 VREFH VREFH VREFH

24 VREFL VREFL VREFL

Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 233

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

25 VSSA VSSA VSSA

26 VREF_OUT/

CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18

27 DAC0_OUT/

CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23

28 XTAL32 XTAL32 XTAL32

29 EXTAL32 EXTAL32 EXTAL32

30 VBAT VBAT VBAT

31 PTE24 ADC0_SE17ADC0_SE17PTE24 CAN1_TX UART4_TX EWM_OUT_

b

32 PTE25 ADC0_SE18ADC0_SE18PTE25 CAN1_RX UART4_RX EWM_IN

33 PTE26 DISABLED PTE26 UART4_CTS

ENET_1588 _CLKIN RTC_CLKO UT USB_CLKIN

34 PTA0 JTAG_TCLK/

SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK

35 PTA1 JTAG_TDI/

EZP_DI TSI0_CH2 PTA1 UART0_RXFTM0_CH6 JTAG_TDI EZP_DI

36 PTA2 JTAG_TDO/

TRACE_SW O/EZP_DO TSI0_CH3 PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SW O EZP_DO

37 PTA3 JTAG_TMS/

SWD_DIO TSI0_CH4 PTA3 UART0_RTS FTM0_CH0 JTAG_TMS/ SWD_DIO

38 PTA4/

LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b

39 PTA5 DISABLED PTA5 FTM0_CH2RMII0_RXE

MII0_RXER CMP2_OUTI2S0_RX_BC LK JTAG_TRST

40 VDD VDD VDD

41 VSS VSS VSS

42 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0RMII0_RXD1

/MII0_RXD1 I2S0_TXD FTM1_QD_P HA

43 PTA13/

LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RX FTM1_CH1RMII0_RXD0 /MII0_RXD0 I2S0_TX_FSFTM1_QD_P HB

44 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TXRMII0_CRS_

MII0_RXDV I2S0_TX_BC LK

45 PTA15 DISABLED PTA15 SPI0_SCKUART0_RXRMII0_TXEN

/MII0_TXEN I2S0_RXD

46 PTA16 DISABLED PTA16 SPI0_SOUTUART0_CTS

RMII0_TXD0 /MII0_TXD0 I2S0_RX_FS

47 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS

RMII0_TXD1 /MII0_TXD1 I2S0_MCLKI2S0_CLKIN

48 VDD VDD VDD

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 234 Freescale Semiconductor, Inc.

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

49 VSS VSS VSS

50 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2FTM_CLKIN

51 PTA19 XTAL XTAL PTA19 FTM1_FLT0FTM_CLKIN

LPT0_ALT1

52 RESET_b RESET_b RESET_b

53 PTB0/

LLWU_P5 /ADC0_SE8/ ADC1_SE8/ TSI0_CH0 /ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0RMII0_MDIO /MII0_MDIO FTM1_QD_P HA

54 PTB1 /ADC0_SE9/

ADC1_SE9/ TSI0_CH6 /ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1RMII0_MDC/ MII0_MDC FTM1_QD_P HB

55 PTB2 /

ADC0_SE12/ TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS ENET0_158 8_TMR0 FTM0_FLT3

56 PTB3 /

ADC0_SE13/ TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS ENET0_158 8_TMR1 FTM0_FLT0

57 PTB9 PTB9 SPI1_PCS1UART3_CTS

FB_AD20

58 PTB10 /ADC1_SE14/ADC1_SE14PTB10 SPI1_PCS0UART3_RX FB_AD19 FTM0_FLT1

59 PTB11 /ADC1_SE15/ADC1_SE15PTB11 SPI1_SCKUART3_TX FB_AD18 FTM0_FLT2

60 VSS VSS VSS

61 VDD VDD VDD

62 PTB16 /TSI0_CH9/TSI0_CH9PTB16 SPI1_SOUTUART0_RX FB_AD17 EWM_IN

63 PTB17 /TSI0_CH10/TSI0_CH10PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_

b

64 PTB18 /TSI0_CH11/TSI0_CH11PTB18 CAN0_TX FTM2_CH0I2S0_TX_BC

FB_AD15 FTM2_QD_P HA

65 PTB19 /TSI0_CH12/TSI0_CH12PTB19 CAN0_RX FTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_P

66 PTB20 PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT

67 PTB21 PTB21 SPI2_SCK FB_AD30 CMP1_OUT

68 PTB22 PTB22 SPI2_SOUT FB_AD29 CMP2_OUT

69 PTB23 PTB23 SPI2_SIN SPI0_PCS5 FB_AD28

70 PTC0 /

ADC0_SE14/ TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4PDB0_EXTR G I2S0_TXD FB_AD14

71 PTC1/

LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3UART1_RTS FTM0_CH0FB_AD13

72 PTC2 /

ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2UART1_CTS FTM0_CH1FB_AD12

73 PTC3/

LLWU_P7 /CMP1_IN1/CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2FB_CLKOUT Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 235

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

74 VSS VSS VSS

75 VDD VDD VDD

76 PTC4/

LLWU_P8 PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11 CMP1_OUT

77 PTC5/

LLWU_P9 PTC5/ LLWU_P9 SPI0_SCK LPT0_ALT2FB_AD10 CMP0_OUT

78 PTC6/

LLWU_P10 /CMP0_IN0/CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_EXTR G FB_AD9

79 PTC7 /CMP0_IN1/CMP0_IN1PTC7 SPI0_SIN FB_AD8

80 PTC8 /

ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLKI2S0_CLKINFB_AD7

81 PTC9 /

ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_BC LK FB_AD6 FTM2_FLT0

82 PTC10 /

ADC1_SE6b/ CMP0_IN4 ADC1_SE6b/ CMP0_IN4 PTC10 I2C1_SCL I2S0_RX_FSFB_AD5

83 PTC11/

LLWU_P11 /ADC1_SE7b/ADC1_SE7bPTC11/ LLWU_P11 I2C1_SDA I2S0_RXD FB_RW_b

84 PTC12 PTC12 UART4_RTS

FB_AD27

85 PTC13 PTC13 UART4_CTS

FB_AD26

86 PTC14 PTC14 UART4_RX FB_AD25

87 PTC15 PTC15 UART4_TX FB_AD24

88 VSS VSS VSS

89 VDD VDD VDD

90 PTC16 PTC16 CAN1_RX UART3_RXENET0_158

8_TMR0 FB_CS5_b/ FB_TSIZ1/ FB_BE23_16 _BLS15_8_b

91 PTC17 PTC17 CAN1_TX UART3_TXENET0_158

8_TMR1 FB_CS4_b/ FB_TSIZ0/ FB_BE31_24 _BLS7_0_b

92 PTC18 PTC18 UART3_RTS

ENET0_158 8_TMR2 FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ BLS23_16_b

93 PTD0/

LLWU_P12 PTD0/ LLWU_P12 SPI0_PCS0UART2_RTS FB_ALE/ FB_CS1_b/ FB_TS_b

94 PTD1 /ADC0_SE5b/ADC0_SE5bPTD1 SPI0_SCKUART2_CTS

FB_CS0_b

95 PTD2/

LLWU_P13 PTD2/ LLWU_P13 SPI0_SOUTUART2_RX FB_AD4

96 PTD3 PTD3 SPI0_SIN UART2_TX FB_AD3

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 236 Freescale Semiconductor, Inc.

P Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

97 PTD4/

LLWU_P14 PTD4/ LLWU_P14 SPI0_PCS1UART0_RTS FTM0_CH4FB_AD2 EWM_IN

98 PTD5 /ADC0_SE6b/ADC0_SE6bPTD5 SPI0_PCS2UART0_CTS

FTM0_CH5FB_AD1 EWM_OUT_ b

99 PTD6/

LLWU_P15 /ADC0_SE7b/ADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0

100 PTD7 PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1

10.3.2 K60 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 237

PGA1_DP/ADC1_DP0/ADC0_DP3 PGA0_DM/ADC0_DM0/ADC1_DM3 PGA0_DP/ADC0_DP0/ADC1_DP3 ADC1_DM1 ADC1_DP1 ADC0_DM1 ADC0_DP1 VREGIN VOUT33 USB0_DM USB0_DP VSS VDD PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 75 VDD VSS PTC3 PTC2 PTC1 PTC0 PTB23 PTB22 PTB21 PTB20 PTB19 PTB18 PTB17 PTB16 VDD VSS PTB11 PTB10 PTB9 PTB3 PTB2 PTB1 PTB0 RESET_b PTA1925 VSSA VREFL VREFH VDDA PGA1_DM/ADC1_DM0/ADC0_DM3 PTD6 PTC7 PTC6 PTC5 PTC450 PTA18 VSS VDD PTA17 PTA16 PTA15 PTA14 PTA13 PTA12 VSS VDD PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTE26 PTE25 PTE24 VBAT EXTAL32 XTAL32 DAC0_OUT/ CMP1_IN3/ADC0_SE23 VREF_OUT/CMP1_IN5/ CMP0_IN5/ADC1_SE18

98 PTD5

97 PTD4

96 PTD3

95 PTD2

94 PTD1

93 PTD0

92 PTC18

91 PTC17

90 PTC16

89 VDD

88 VSS

80 PTC8

83 PTC11

84 PTC12

85 PTC13

86 PTC14

87 PTC15

100 PTD7

Figure 10-2. K60 100 LQFP Pinout Diagram

10.4 Module Signal Description Tables

The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 238 Freescale Semiconductor, Inc.

10.4.1 Core Modules

Table 10-2. JTAG Signal Descriptions Chip signal name Module signal name Description I/O JTAG_TMS JTAG_TMS/ SWD_DIO JTAG Test Mode Selection I/O JTAG_TCLK JTAG_TCLK/ SWD_CLK JTAG Test Clock I JTAG_TDI JTAG_TDI JTAG Test Data Input I JTAG_TDO JTAG_TDO/ TRACE_SWO JTAG Test Data Output O JTAG_TRST JTAG_TRST_b JTAG Reset I Table 10-3. SWD Signal Descriptions Chip signal name Module signal name Description I/O SWD_DIO JTAG_TMS/ SWD_DIO Serial Wire Data I/O SWD_CLK JTAG_TCLK/ SWD_CLK Serial Wire Clock I Table 10-4. TPIU Signal Descriptions Chip signal name Module signal name Description I/O TRACE_CLKOUT TRACECLK Trace clock output from the ARM CoreSight debug block O TRACE_D[3:2] TRACEDATA Trace output data from the ARM CoreSight debug block used for 5- pin interface O TRACE_D[1:0] TRACEDATA Trace output data from the ARM CoreSight debug block used for both 5-pin and 3-pin interfaces O TRACE_SWO JTAG_TDO/ TRACE_SWO Trace output data from the ARM CoreSight debug block over a single pin O

10.4.2 System Modules

Table 10-5. System Signal Descriptions Chip signal name Module signal name Description I/O NMI — Non-maskable interrupt NOTE: Driving the NMI signal low forces a non-maskable interrupt, if the NMI function is selected on the corresponding pin. I Table continues on the next page... Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 239

Table 10-5. System Signal Descriptions (continued) Chip signal name Module signal name Description I/O RESET — Reset bi-directional signal I/O VDD — MCU power I VSS — MCU ground I Table 10-6. EWM Signal Descriptions Chip signal name Module signal name Description I/O EWM_IN EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the CTRL[ASSIN] bit. The default polarity is active-low. I EWM_OUT EWM_out EWM reset out signal O

10.4.3 Clock Modules

Table 10-7. OSC Signal Descriptions Chip signal name Module signal name Description I/O EXTAL0 EXTAL External clock/Oscillator input I XTAL0 XTAL Oscillator output O Table 10-8. RTC OSC Signal Descriptions Chip signal name Module signal name Description I/O EXTAL32 EXTAL32 32.768 kHz oscillator input I XTAL32 XTAL32 32.768 kHz oscillator output O

10.4.4 Memories and Memory Interfaces

Table 10-9. EzPort Signal Descriptions Chip signal name Module signal name Description I/O EZP_CLK EZP_CK EzPort Clock Input EZP_CS EZP_CS EzPort Chip Select Input EZP_DI EZP_D EzPort Serial Data In Input EZP_DO EZP_Q EzPort Serial Data Out Output Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 240 Freescale Semiconductor, Inc.

Table 10-10. FlexBus Signal Descriptions Chip signal name Module signal name Description I/O FB_CLKOUT FB_CLK FlexBus clock output O FB_AD[31:0] 1 FB_D[31:0]/ FB_AD[31:0] In a non-multiplexed configuration, this is the data bus. In a multiplexed configuration this bus is the address/data bus, FB_AD[31:0]. In non-multiplexed and multiplexed configurations, during the first cycle, this bus drives the upper address byte, addr[31:24]. I/O FB_CS[5:0] 2 FB_CS[5:0] General purpose chip-selects. The actual number of chip selects available depends upon the device and its pin configuration. O FB_BE31_24_BLS7 _0, FB_BE23_16_BLS1 5_8, FB_BE15_8_BLS23 _16, FB_BE7_0_BLS31_ 243 FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 Byte enables O FB_OE FB_OE Output enable O FB_R W FB_R/W Read/write. 1 = Read, 0 = Write O FB_TS/ FB_ALE FB_TS Transfer start O FB_TSIZ[1:0] FB_TSIZ[1:0] Transfer size O FB_TA4 FB_TA Transfer acknowledge I FB_TBST FB_TBST Burst transfer indicator O 1. FB_AD[23:21] not available on 100-LQFP devices. 2. FB_CS3not available on 100-LQFP devices. 3. FB_BE7_0_BLS31_24not available on 100-LQFP devices. 4. FB_TAnotavailable on 100-LQFP devices.

10.4.5 Analog

Table 10-11. ADC 0 Signal Descriptions Chip signal name Module signal name Description I/O ADC0_DP3, PGA0_DP, ADC0_DP[1:0] DADP[3:0] Differential analog channel inputs I ADC0_DM3, PGA0_DM, ADC0_DM[1:0] DADM[3:0] Differential analog channel inputs I ADC0_SE[18,17,15: AD[23:4] Single-ended analog channel inputs I Table continues on the next page... Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 241

Table 10-11. ADC 0 Signal Descriptions (continued) Chip signal name Module signal name Description I/O VREFH VREFSH Voltage reference select high I VREFL VREFSL Voltage reference select low I VDDA VDDA Analog power supply I VSSA VSSA Analog ground I Table 10-12. ADC 1 Signal Descriptions Chip signal name Module signal name Description I/O ADC1_DP3, PGA1_DP, ADC1_DP[1:0] DADP[3:0] Differential analog channel inputs I ADC1_DM3, PGA1_DM, ADC1_DM[1:0] DADM[3:0] Differential analog channel inputs I ADC1_SE[18:17,15: 13,9:4] AD[23:4] Single-ended analog channel inputs I VREFH VREFSH Voltage reference select high I VREFL VREFSL Voltage reference select low I VDDA VDDA Analog power supply I VSSA VSSA Analog ground I Table 10-13. CMP 0 Signal Descriptions Chip signal name Module signal name Description I/O CMP0_IN[5:0] IN[5:0] Analog voltage inputs I CMP0_OUT CMPO Comparator output O Table 10-14. CMP 1 Signal Descriptions Chip signal name Module signal name Description I/O CMP1_IN[5:0] IN[5:0] Analog voltage inputs I CMP1_OUT CMPO Comparator output O Table 10-15. CMP 2 Signal Descriptions Chip signal name Module signal name Description I/O CMP2_IN[5:0] IN[5:0] Analog voltage inputs I CMP2_OUT CMPO Comparator output O Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 242 Freescale Semiconductor, Inc.

Table 10-16. DAC 0 Signal Descriptions Chip signal name Module signal name Description I/O DAC0_OUT — DAC output O Table 10-17. TRIAMP 1 Signal Descriptions Chip signal name Module signal name Description I/O TRI1_DP inp_3v Amplifier positive input terminal I TRI1_DM inn_3v Amplifier negative input terminal I TRI1_OUT out_3v Amplifier output terminal O Table 10-18. VREF Signal Descriptions Chip signal name Module signal name Description I/O VREF_OUT VREF_OUT Internally-generated Voltage Reference output O

10.4.6 Communication Interfaces

Ethernet MII Signal Descriptions Chip signal name Module signal name Description I/O MII0_COL MII_COL Asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. I MII0_CRS MII_CRS Carrier sense. When asserted, indicates transmit or receive medium is not idle. In RMII mode, this signal is present on the RMII_CRS_DV pin. I MII0_MDC MII_MDC Output clock provides a timing reference to the PHY for data transfers on the MDIO signal. O MII0_MDIO MII_MDIO Transfers control information between the external PHY and the media-access controller. Data is synchronous to MDC. This signal is an input after reset. I/O Table continues on the next page... Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 243

Chip signal name Module signal name Description I/O MII0_RXCLK MII_RXCLK In MII mode, provides a timing reference for RXDV, RXD[3:0], and RXER. I MII0_RXDV MII_RXDV Asserting this input indicates the PHY has valid nibbles present on the MII. RXDV must remain asserted from the first recovered nibble of the frame through to the last nibble. Asserting RXDV must start no later than the SFD and exclude any EOF. In RMII mode, this pin also generates the CRS signal. I MII0_RXD[3:0] MII_RXD[3:0] Contains the Ethernet input data transferred from the PHY to the media-access controller when RXDV is asserted. I MII0_RXER MII_RXER When asserted with RXDV, indicates the PHY detects an error in the current frame. I MII0_TXCLK MII_TXCLK Input clock which provides a timing reference for TXEN, TXD[3:0], and TXER. I MII0_TXD[3:0] MII_TXD[3:0] The serial output Ethernet data and only valid during the assertion of TXEN. O MII0_TXEN MII_TXEN Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first TXCLK following the final nibble of the frame. O MII0_TXER MII_TXER When asserted for one or more clock cycles while TXEN is also asserted, PHY sends one or more illegal symbols. O Ethernet RMII Signal Descriptions Chip signal name Module signal name Description I/O RMII0_MDC RMII_MDC Output clock provides a timing reference to the PHY for data transfers on the MDIO signal. O Table continues on the next page... Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 244 Freescale Semiconductor, Inc.

Chip signal name Module signal name Description I/O RMII0_MDIO RMII_MDIO Transfers control information between the external PHY and the media-access controller. Data is synchronous to MDC. This signal is an input after reset. I/O RMII0_CRS_DV RMII_CRS_DV Asserting this input indicates the PHY has valid nibbles present on the MII. RXDV must remain asserted from the first recovered nibble of the frame through to the last nibble. Asserting RXDV must start no later than the SFD and exclude any EOF. In RMII mode, this pin also generates the CRS signal. I RMII0_RXD[1:0] RMII_RXD[1:0] Contains the Ethernet input data transferred from the PHY to the media-access controller when RXDV is asserted. I RMII0_RXER RMII_RXER When asserted with RXDV, indicates the PHY detects an error in the current frame. I RMII0_TXD[1:0] RMII_TXD[1:0] The serial output Ethernet data and only valid during the assertion of TXEN. O RMII0_TXEN RMII_TXEN Indicates when valid nibbles are present on the MII. This signal is asserted with the first nibble of a preamble and is negated before the first TXCLK following the final nibble of the frame. O Internal OSCERCLK clock1 RMII_REF_CLK In RMII mode, this signal is the reference clock for receive, transmit, and the control interface. I Table 10-19. USB FS OTG Signal Descriptions Chip signal name Module signal name Description I/O USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O USB_CLKIN — Alternate USB clock input I Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 245

Table 10-20. USB VREG Signal Descriptions Chip signal name Module signal name Description I/O VOUT33 reg33_out Regulator output voltage O VREGIN reg33_in Unregulated power supply I Table 10-21. CAN 0 Signal Descriptions Chip signal name Module signal name Description I/O CAN0_RX CAN Rx CAN Receive Pin Input CAN0_TX CAN Tx CAN Transmit Pin Output Table 10-22. CAN 1 Signal Descriptions Chip signal name Module signal name Description I/O CAN1_RX CAN Rx CAN Receive Pin Input CAN1_TX CAN Tx CAN Transmit Pin Output Table 10-23. SPI 0 Signal Descriptions Chip signal name Module signal name Description I/O SPI0_PCS0 PCS0/SS Master mode: Peripheral Chip Select 0 output Slave mode: Slave Select input I/O SPI0_PCS[3:1] PCS[3:1] Master mode: Peripheral Chip Select 1 - 3 Slave mode: Unused O SPI0_PCS4 PCS4 Master mode: Peripheral Chip Select 4 Slave mode: Unused O SPI0_PCS5 PCS5/ PCSS Master mode: Peripheral Chip Select 5 / Peripheral Chip Select Strobe Slave mode: Unused O SPI0_SIN SIN Serial Data In I SPI0_SOUT SOUT Serial Data Out O SPI0_SCK SCK Master mode: Serial Clock (output) Slave mode: Serial Clock (input) I/O Table 10-24. I 2C 0 Signal Descriptions Chip signal name Module signal name Description I/O I2C0_SCL SCL Bidirectional serial clock line of the I2C system. I/O I2C0_SDA SDA Bidirectional serial data line of the I2C system. I/O Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 246 Freescale Semiconductor, Inc.

Table 10-25. I 2C 1 Signal Descriptions Chip signal name Module signal name Description I/O I2C1_SCL SCL Bidirectional serial clock line of the I2C system. I/O I2C1_SDA SDA Bidirectional serial data line of the I2C system. I/O Table 10-26. UART 0 Signal Descriptions Chip signal name Module signal name Description I/O UART0_CTS CTS Clear to send I UART0_RTS RTS Request to send O UART0_TX TXD Transmit data O UART0_RX RXD Receive data I Table 10-27. UART 1 Signal Descriptions Chip signal name Module signal name Description I/O UART1_CTS CTS Clear to send I UART1_RTS RTS Request to send O UART1_TX TXD Transmit data O UART1_RX RXD Receive data I Table 10-28. UART 2 Signal Descriptions Chip signal name Module signal name Description I/O UART2_CTS CTS Clear to send I UART2_RTS RTS Request to send O UART2_TX TXD Transmit data O UART2_RX RXD Receive data I Table 10-29. UART 3 Signal Descriptions Chip signal name Module signal name Description I/O UART3_CTS CTS Clear to send I UART3_RTS RTS Request to send O UART3_TX TXD Transmit data O UART3_RX RXD Receive data I Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 247

Table 10-30. UART 4 Signal Descriptions Chip signal name Module signal name Description I/O UART4_CTS CTS Clear to send I UART4_RTS RTS Request to send O UART4_TX TXD Transmit data O UART4_RX RXD Receive data I Table 10-31. SDHC Signal Descriptions Chip signal name Module signal name Description I/O SDHC0_DCLK SDHC_DCLK Generated clock used to drive the MMC, SD, SDIO or CE-ATA cards. O SDHC0_CMD SDHC_CMD Send commands to and receive responses from the card. I/O SDHC0_D0 SDHC_D0 DAT0 line or busy-state detect I/O SDHC0_D1 SDHC_D1 8-bit mode: DAT1 line 4-bit mode: DAT1 line or interrupt detect 1-bit mode: Interrupt detect I/O SDHC0_D2 SDHC_D2 4-/8-bit mode: DAT2 line or read wait 1-bit mode: Read wait I/O SDHC0_D3 SDHC_D3 4-/8-bit mode: DAT3 line or configured as card detection pin 1-bit mode: May be configured as card detection pin I/O Table 10-32. I 2S 0 Signal Descriptions Chip signal name Module signal name Description I/O I2S0_MCLK — Serial master clock output I/O I2S0_RX_BCLK SRCK Serial receive clock. SRCK can be used as an input or output.

• In asynchronous mode the receiver uses this clock signal and it is always continuous.
• In synchronous mode, the STCK port is used instead for clocking in data. I/O I2S0_RX_FS SRFS Serial receive frame Sync. The SRFS port can be used as an input or output. The frame sync is used by the receiver to synchronize the transfer of data. The frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. If SRFS is configured as an input, the external device should drive SRFS during the rising edge of STCK or SRCK. I/O I2S0_RXD SRXD Serial receive data. The SRXD port is an input and is used to bring serial data into the receive data shift register. I Table continues on the next page... Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 248 Freescale Semiconductor, Inc.

Table 10-32. I 2S 0 Signal Descriptions (continued) Chip signal name Module signal name Description I/O I2S0_TX_BCLK STCK Serial transmit clock. The STCK port can be used as an input or output. This clock signal is used by the transmitter and can be continuous or gated. During gated clock mode, data on STCK is valid only during the transmission of data. Otherwise, it is pulled to the inactive state. In synchronous mode, this port is used by the transmit and receive sections. I/O I2S0_TX_FS STFS Serial transmit frame sync. The STFS port can be used as an input or output. The frame sync is used by the transmitter to synchronize the transfer of data. The frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data or right at the transfer of data. In synchronous mode, this port is used by both the transmit and receive sections. In gated clock mode, frame sync signals are not used. If STFS is configured as an input, the external device should drive STFS during the rising edge of STCK if TSCKP is positive-edge triggered. The external device should drive STFS during the falling edge of STCK if TSCKP is negative-edge triggered. I/O I2S0_TXD STXD Serial transmit data. The STXD port is an output and transmits data from the serial transmit shift register. The STXD port is an output port when data is being transmitted and is disabled between data word transmissions and on the trailing edge of the bit clock after the last bit of a word is transmitted. O

10.4.7 Human-Machine Interfaces (HMI)

Table 10-33. GPIO Signal Descriptions Chip signal name Module signal name Description I/O PTA[31:0]1 PORTA[31:0] General purpose input/output I/O PTB[31:0]1 PORTB[31:0] General purpose input/output I/O PTC[31:0]1 PORTC[31:0] General purpose input/output I/O PTD[31:0]1 PORTD[31:0] General purpose input/output I/O PTE[31:0]1 PORTE[31:0] General purpose input/output I/O 1. The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO signals are available. Table 10-34. TSI 0 Signal Descriptions Chip signal name Module signal name Description I/O TSI0_CH[15:0] TSI_IN[15:0] TSI pins. Switchable driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins I/O Chapter 10 Signal Multiplexing and Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 249

Module Signal Description Tables K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 250 Freescale Semiconductor, Inc.

Port control and interrupts (PORT)

11.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter.

11.1.1 Overview

The port control and interrupt (PORT) module provides support for external interrupt, digital filtering and port control functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state. There is one instance of the PORT module for each port. Not all pins within each port are implemented on a specific device.

11.1.2 Features

• Pin interrupt
• Interrupt flag and enable registers for each pin
• Supports edge sensitive (rising, falling, both) or level sensitive (low, high) configured per pin
• Support for interrupt or DMA request configured per pin
• Asynchronous wakeup in low-power modes
• Pin interrupt is functional in all digital pin muxing modes
• Digital input filter
• Digital input filter for each pin, usable by any digital peripheral muxed onto pin
• Individual enable or bypass control bit per pin K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 251

• Selectable clock source for digital input filter with 5-bit resolution on filter size
• Digital filter is functional in all digital pin muxing modes
• Port control
• Individual pull control registers with pullup, pulldown and pull-disable support
• Individual drive strength register supporting high and low drive strength
• Individual slew rate register supporting fast and slow slew rates
• Individual input passive filter register supporting enabled and disabled
• Individual open-drain register supporting enabled and disabled
• Individual mux control register supporting analog (or pin disabled), GPIO plus up to six chip specific digital functions
• Pad configuration registers are functional in all digital pin muxing modes

11.1.3 Modes of operation

11.1.3.1 Run mode

In run mode, the PORT operates normally.

11.1.3.2 Wait mode

In wait mode, the PORT continues to operate normally and may be configured to exit the low power mode if an enabled interrupt is detected. DMA requests are still generated during wait mode, but do not cause an exit from the low power mode.

11.1.3.3 Stop mode

In stop mode, the digital input filters are bypassed unless they are configured to run from the 1 kHz LPO clock source. The PORT can be configured to exit the low power mode via an asynchronous wakeup signal if an enabled interrupt (but not DMA request) is detected.

11.1.3.4 Debug mode

In debug mode, the PORTx operates normally. Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 252 Freescale Semiconductor, Inc.

11.2 External signal description

Table 11-1. Signal properties Name Function I/O Reset Pull PORTx[31:0] External interrupt I/O 0 - NOTE Not all pins within each port are implemented on each device.

11.3 Detailed signal descriptions

Table 11-2. PORTx interface-detailed signal descriptions Signal I/O Description PORTx[31:0] I/O External interrupt. State meaning Asserted-pin is logic one. Negated-pin is logic zero. Timing Assertion-may occur at any time and can assert asynchronously to the system clock. Negation-may occur at any time and can assert asynchronously to the system clock.

11.4 Memory map and register definition

Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. PORT memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W 0000_0000h 11.4.1/260 4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W 0000_0000h 11.4.1/260 4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W 0000_0000h 11.4.1/260 Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 253

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_900C Pin Control Register n (PORTA_PCR3) 32 R/W 0000_0000h 11.4.1/260 4004_9010 Pin Control Register n (PORTA_PCR4) 32 R/W 0000_0000h 11.4.1/260 4004_9014 Pin Control Register n (PORTA_PCR5) 32 R/W 0000_0000h 11.4.1/260 4004_9018 Pin Control Register n (PORTA_PCR6) 32 R/W 0000_0000h 11.4.1/260 4004_901C Pin Control Register n (PORTA_PCR7) 32 R/W 0000_0000h 11.4.1/260 4004_9020 Pin Control Register n (PORTA_PCR8) 32 R/W 0000_0000h 11.4.1/260 4004_9024 Pin Control Register n (PORTA_PCR9) 32 R/W 0000_0000h 11.4.1/260 4004_9028 Pin Control Register n (PORTA_PCR10) 32 R/W 0000_0000h 11.4.1/260 4004_902C Pin Control Register n (PORTA_PCR11) 32 R/W 0000_0000h 11.4.1/260 4004_9030 Pin Control Register n (PORTA_PCR12) 32 R/W 0000_0000h 11.4.1/260 4004_9034 Pin Control Register n (PORTA_PCR13) 32 R/W 0000_0000h 11.4.1/260 4004_9038 Pin Control Register n (PORTA_PCR14) 32 R/W 0000_0000h 11.4.1/260 4004_903C Pin Control Register n (PORTA_PCR15) 32 R/W 0000_0000h 11.4.1/260 4004_9040 Pin Control Register n (PORTA_PCR16) 32 R/W 0000_0000h 11.4.1/260 4004_9044 Pin Control Register n (PORTA_PCR17) 32 R/W 0000_0000h 11.4.1/260 4004_9048 Pin Control Register n (PORTA_PCR18) 32 R/W 0000_0000h 11.4.1/260 4004_904C Pin Control Register n (PORTA_PCR19) 32 R/W 0000_0000h 11.4.1/260 4004_9050 Pin Control Register n (PORTA_PCR20) 32 R/W 0000_0000h 11.4.1/260 4004_9054 Pin Control Register n (PORTA_PCR21) 32 R/W 0000_0000h 11.4.1/260 4004_9058 Pin Control Register n (PORTA_PCR22) 32 R/W 0000_0000h 11.4.1/260 4004_905C Pin Control Register n (PORTA_PCR23) 32 R/W 0000_0000h 11.4.1/260 4004_9060 Pin Control Register n (PORTA_PCR24) 32 R/W 0000_0000h 11.4.1/260 4004_9064 Pin Control Register n (PORTA_PCR25) 32 R/W 0000_0000h 11.4.1/260 4004_9068 Pin Control Register n (PORTA_PCR26) 32 R/W 0000_0000h 11.4.1/260 4004_906C Pin Control Register n (PORTA_PCR27) 32 R/W 0000_0000h 11.4.1/260 4004_9070 Pin Control Register n (PORTA_PCR28) 32 R/W 0000_0000h 11.4.1/260 4004_9074 Pin Control Register n (PORTA_PCR29) 32 R/W 0000_0000h 11.4.1/260 4004_9078 Pin Control Register n (PORTA_PCR30) 32 R/W 0000_0000h 11.4.1/260 4004_907C Pin Control Register n (PORTA_PCR31) 32 R/W 0000_0000h 11.4.1/260 4004_9080 Global Pin Control Low Register (PORTA_GPCLR) 32 W (always reads zero) 0000_0000h 11.4.2/262 4004_9084 Global Pin Control High Register (PORTA_GPCHR) 32 W (always 0000_0000h 11.4.3/263 Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 254 Freescale Semiconductor, Inc.

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page reads zero) 4004_90A0 Interrupt Status Flag Register (PORTA_ISFR) 32 w1c 0000_0000h 11.4.4/263 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 32 R/W 0000_0000h 11.4.5/264 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 32 R/W 0000_0000h 11.4.6/265 4004_90C8 Digital Filter Width Register (PORTA_DFWR) 32 R/W 0000_0000h 11.4.7/265 4004_A000 Pin Control Register n (PORTB_PCR0) 32 R/W 0000_0000h 11.4.1/260 4004_A004 Pin Control Register n (PORTB_PCR1) 32 R/W 0000_0000h 11.4.1/260 4004_A008 Pin Control Register n (PORTB_PCR2) 32 R/W 0000_0000h 11.4.1/260 4004_A00C Pin Control Register n (PORTB_PCR3) 32 R/W 0000_0000h 11.4.1/260 4004_A010 Pin Control Register n (PORTB_PCR4) 32 R/W 0000_0000h 11.4.1/260 4004_A014 Pin Control Register n (PORTB_PCR5) 32 R/W 0000_0000h 11.4.1/260 4004_A018 Pin Control Register n (PORTB_PCR6) 32 R/W 0000_0000h 11.4.1/260 4004_A01C Pin Control Register n (PORTB_PCR7) 32 R/W 0000_0000h 11.4.1/260 4004_A020 Pin Control Register n (PORTB_PCR8) 32 R/W 0000_0000h 11.4.1/260 4004_A024 Pin Control Register n (PORTB_PCR9) 32 R/W 0000_0000h 11.4.1/260 4004_A028 Pin Control Register n (PORTB_PCR10) 32 R/W 0000_0000h 11.4.1/260 4004_A02C Pin Control Register n (PORTB_PCR11) 32 R/W 0000_0000h 11.4.1/260 4004_A030 Pin Control Register n (PORTB_PCR12) 32 R/W 0000_0000h 11.4.1/260 4004_A034 Pin Control Register n (PORTB_PCR13) 32 R/W 0000_0000h 11.4.1/260 4004_A038 Pin Control Register n (PORTB_PCR14) 32 R/W 0000_0000h 11.4.1/260 4004_A03C Pin Control Register n (PORTB_PCR15) 32 R/W 0000_0000h 11.4.1/260 4004_A040 Pin Control Register n (PORTB_PCR16) 32 R/W 0000_0000h 11.4.1/260 4004_A044 Pin Control Register n (PORTB_PCR17) 32 R/W 0000_0000h 11.4.1/260 4004_A048 Pin Control Register n (PORTB_PCR18) 32 R/W 0000_0000h 11.4.1/260 4004_A04C Pin Control Register n (PORTB_PCR19) 32 R/W 0000_0000h 11.4.1/260 4004_A050 Pin Control Register n (PORTB_PCR20) 32 R/W 0000_0000h 11.4.1/260 4004_A054 Pin Control Register n (PORTB_PCR21) 32 R/W 0000_0000h 11.4.1/260 4004_A058 Pin Control Register n (PORTB_PCR22) 32 R/W 0000_0000h 11.4.1/260 4004_A05C Pin Control Register n (PORTB_PCR23) 32 R/W 0000_0000h 11.4.1/260 4004_A060 Pin Control Register n (PORTB_PCR24) 32 R/W 0000_0000h 11.4.1/260 4004_A064 Pin Control Register n (PORTB_PCR25) 32 R/W 0000_0000h 11.4.1/260 4004_A068 Pin Control Register n (PORTB_PCR26) 32 R/W 0000_0000h 11.4.1/260 4004_A06C Pin Control Register n (PORTB_PCR27) 32 R/W 0000_0000h 11.4.1/260 Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 255

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_A070 Pin Control Register n (PORTB_PCR28) 32 R/W 0000_0000h 11.4.1/260 4004_A074 Pin Control Register n (PORTB_PCR29) 32 R/W 0000_0000h 11.4.1/260 4004_A078 Pin Control Register n (PORTB_PCR30) 32 R/W 0000_0000h 11.4.1/260 4004_A07C Pin Control Register n (PORTB_PCR31) 32 R/W 0000_0000h 11.4.1/260 4004_A080 Global Pin Control Low Register (PORTB_GPCLR) 32 W (always reads zero) 0000_0000h 11.4.2/262 4004_A084 Global Pin Control High Register (PORTB_GPCHR) 32 W (always reads zero) 0000_0000h 11.4.3/263 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 32 w1c 0000_0000h 11.4.4/263 4004_A0C0 Digital Filter Enable Register (PORTB_DFER) 32 R/W 0000_0000h 11.4.5/264 4004_A0C4 Digital Filter Clock Register (PORTB_DFCR) 32 R/W 0000_0000h 11.4.6/265 4004_A0C8 Digital Filter Width Register (PORTB_DFWR) 32 R/W 0000_0000h 11.4.7/265 4004_B000 Pin Control Register n (PORTC_PCR0) 32 R/W 0000_0000h 11.4.1/260 4004_B004 Pin Control Register n (PORTC_PCR1) 32 R/W 0000_0000h 11.4.1/260 4004_B008 Pin Control Register n (PORTC_PCR2) 32 R/W 0000_0000h 11.4.1/260 4004_B00C Pin Control Register n (PORTC_PCR3) 32 R/W 0000_0000h 11.4.1/260 4004_B010 Pin Control Register n (PORTC_PCR4) 32 R/W 0000_0000h 11.4.1/260 4004_B014 Pin Control Register n (PORTC_PCR5) 32 R/W 0000_0000h 11.4.1/260 4004_B018 Pin Control Register n (PORTC_PCR6) 32 R/W 0000_0000h 11.4.1/260 4004_B01C Pin Control Register n (PORTC_PCR7) 32 R/W 0000_0000h 11.4.1/260 4004_B020 Pin Control Register n (PORTC_PCR8) 32 R/W 0000_0000h 11.4.1/260 4004_B024 Pin Control Register n (PORTC_PCR9) 32 R/W 0000_0000h 11.4.1/260 4004_B028 Pin Control Register n (PORTC_PCR10) 32 R/W 0000_0000h 11.4.1/260 4004_B02C Pin Control Register n (PORTC_PCR11) 32 R/W 0000_0000h 11.4.1/260 4004_B030 Pin Control Register n (PORTC_PCR12) 32 R/W 0000_0000h 11.4.1/260 4004_B034 Pin Control Register n (PORTC_PCR13) 32 R/W 0000_0000h 11.4.1/260 4004_B038 Pin Control Register n (PORTC_PCR14) 32 R/W 0000_0000h 11.4.1/260 4004_B03C Pin Control Register n (PORTC_PCR15) 32 R/W 0000_0000h 11.4.1/260 4004_B040 Pin Control Register n (PORTC_PCR16) 32 R/W 0000_0000h 11.4.1/260 4004_B044 Pin Control Register n (PORTC_PCR17) 32 R/W 0000_0000h 11.4.1/260 4004_B048 Pin Control Register n (PORTC_PCR18) 32 R/W 0000_0000h 11.4.1/260 4004_B04C Pin Control Register n (PORTC_PCR19) 32 R/W 0000_0000h 11.4.1/260 Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 256 Freescale Semiconductor, Inc.

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_B050 Pin Control Register n (PORTC_PCR20) 32 R/W 0000_0000h 11.4.1/260 4004_B054 Pin Control Register n (PORTC_PCR21) 32 R/W 0000_0000h 11.4.1/260 4004_B058 Pin Control Register n (PORTC_PCR22) 32 R/W 0000_0000h 11.4.1/260 4004_B05C Pin Control Register n (PORTC_PCR23) 32 R/W 0000_0000h 11.4.1/260 4004_B060 Pin Control Register n (PORTC_PCR24) 32 R/W 0000_0000h 11.4.1/260 4004_B064 Pin Control Register n (PORTC_PCR25) 32 R/W 0000_0000h 11.4.1/260 4004_B068 Pin Control Register n (PORTC_PCR26) 32 R/W 0000_0000h 11.4.1/260 4004_B06C Pin Control Register n (PORTC_PCR27) 32 R/W 0000_0000h 11.4.1/260 4004_B070 Pin Control Register n (PORTC_PCR28) 32 R/W 0000_0000h 11.4.1/260 4004_B074 Pin Control Register n (PORTC_PCR29) 32 R/W 0000_0000h 11.4.1/260 4004_B078 Pin Control Register n (PORTC_PCR30) 32 R/W 0000_0000h 11.4.1/260 4004_B07C Pin Control Register n (PORTC_PCR31) 32 R/W 0000_0000h 11.4.1/260 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) 32 W (always reads zero) 0000_0000h 11.4.2/262 4004_B084 Global Pin Control High Register (PORTC_GPCHR) 32 W (always reads zero) 0000_0000h 11.4.3/263 4004_B0A0 Interrupt Status Flag Register (PORTC_ISFR) 32 w1c 0000_0000h 11.4.4/263 4004_B0C0 Digital Filter Enable Register (PORTC_DFER) 32 R/W 0000_0000h 11.4.5/264 4004_B0C4 Digital Filter Clock Register (PORTC_DFCR) 32 R/W 0000_0000h 11.4.6/265 4004_B0C8 Digital Filter Width Register (PORTC_DFWR) 32 R/W 0000_0000h 11.4.7/265 4004_C000 Pin Control Register n (PORTD_PCR0) 32 R/W 0000_0000h 11.4.1/260 4004_C004 Pin Control Register n (PORTD_PCR1) 32 R/W 0000_0000h 11.4.1/260 4004_C008 Pin Control Register n (PORTD_PCR2) 32 R/W 0000_0000h 11.4.1/260 4004_C00C Pin Control Register n (PORTD_PCR3) 32 R/W 0000_0000h 11.4.1/260 4004_C010 Pin Control Register n (PORTD_PCR4) 32 R/W 0000_0000h 11.4.1/260 4004_C014 Pin Control Register n (PORTD_PCR5) 32 R/W 0000_0000h 11.4.1/260 4004_C018 Pin Control Register n (PORTD_PCR6) 32 R/W 0000_0000h 11.4.1/260 4004_C01C Pin Control Register n (PORTD_PCR7) 32 R/W 0000_0000h 11.4.1/260 4004_C020 Pin Control Register n (PORTD_PCR8) 32 R/W 0000_0000h 11.4.1/260 4004_C024 Pin Control Register n (PORTD_PCR9) 32 R/W 0000_0000h 11.4.1/260 4004_C028 Pin Control Register n (PORTD_PCR10) 32 R/W 0000_0000h 11.4.1/260 4004_C02C Pin Control Register n (PORTD_PCR11) 32 R/W 0000_0000h 11.4.1/260 Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 257

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_C030 Pin Control Register n (PORTD_PCR12) 32 R/W 0000_0000h 11.4.1/260 4004_C034 Pin Control Register n (PORTD_PCR13) 32 R/W 0000_0000h 11.4.1/260 4004_C038 Pin Control Register n (PORTD_PCR14) 32 R/W 0000_0000h 11.4.1/260 4004_C03C Pin Control Register n (PORTD_PCR15) 32 R/W 0000_0000h 11.4.1/260 4004_C040 Pin Control Register n (PORTD_PCR16) 32 R/W 0000_0000h 11.4.1/260 4004_C044 Pin Control Register n (PORTD_PCR17) 32 R/W 0000_0000h 11.4.1/260 4004_C048 Pin Control Register n (PORTD_PCR18) 32 R/W 0000_0000h 11.4.1/260 4004_C04C Pin Control Register n (PORTD_PCR19) 32 R/W 0000_0000h 11.4.1/260 4004_C050 Pin Control Register n (PORTD_PCR20) 32 R/W 0000_0000h 11.4.1/260 4004_C054 Pin Control Register n (PORTD_PCR21) 32 R/W 0000_0000h 11.4.1/260 4004_C058 Pin Control Register n (PORTD_PCR22) 32 R/W 0000_0000h 11.4.1/260 4004_C05C Pin Control Register n (PORTD_PCR23) 32 R/W 0000_0000h 11.4.1/260 4004_C060 Pin Control Register n (PORTD_PCR24) 32 R/W 0000_0000h 11.4.1/260 4004_C064 Pin Control Register n (PORTD_PCR25) 32 R/W 0000_0000h 11.4.1/260 4004_C068 Pin Control Register n (PORTD_PCR26) 32 R/W 0000_0000h 11.4.1/260 4004_C06C Pin Control Register n (PORTD_PCR27) 32 R/W 0000_0000h 11.4.1/260 4004_C070 Pin Control Register n (PORTD_PCR28) 32 R/W 0000_0000h 11.4.1/260 4004_C074 Pin Control Register n (PORTD_PCR29) 32 R/W 0000_0000h 11.4.1/260 4004_C078 Pin Control Register n (PORTD_PCR30) 32 R/W 0000_0000h 11.4.1/260 4004_C07C Pin Control Register n (PORTD_PCR31) 32 R/W 0000_0000h 11.4.1/260 4004_C080 Global Pin Control Low Register (PORTD_GPCLR) 32 W (always reads zero) 0000_0000h 11.4.2/262 4004_C084 Global Pin Control High Register (PORTD_GPCHR) 32 W (always reads zero) 0000_0000h 11.4.3/263 4004_C0A0 Interrupt Status Flag Register (PORTD_ISFR) 32 w1c 0000_0000h 11.4.4/263 4004_C0C0 Digital Filter Enable Register (PORTD_DFER) 32 R/W 0000_0000h 11.4.5/264 4004_C0C4 Digital Filter Clock Register (PORTD_DFCR) 32 R/W 0000_0000h 11.4.6/265 4004_C0C8 Digital Filter Width Register (PORTD_DFWR) 32 R/W 0000_0000h 11.4.7/265 4004_D000 Pin Control Register n (PORTE_PCR0) 32 R/W 0000_0000h 11.4.1/260 4004_D004 Pin Control Register n (PORTE_PCR1) 32 R/W 0000_0000h 11.4.1/260 4004_D008 Pin Control Register n (PORTE_PCR2) 32 R/W 0000_0000h 11.4.1/260 4004_D00C Pin Control Register n (PORTE_PCR3) 32 R/W 0000_0000h 11.4.1/260 Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 258 Freescale Semiconductor, Inc.

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_D010 Pin Control Register n (PORTE_PCR4) 32 R/W 0000_0000h 11.4.1/260 4004_D014 Pin Control Register n (PORTE_PCR5) 32 R/W 0000_0000h 11.4.1/260 4004_D018 Pin Control Register n (PORTE_PCR6) 32 R/W 0000_0000h 11.4.1/260 4004_D01C Pin Control Register n (PORTE_PCR7) 32 R/W 0000_0000h 11.4.1/260 4004_D020 Pin Control Register n (PORTE_PCR8) 32 R/W 0000_0000h 11.4.1/260 4004_D024 Pin Control Register n (PORTE_PCR9) 32 R/W 0000_0000h 11.4.1/260 4004_D028 Pin Control Register n (PORTE_PCR10) 32 R/W 0000_0000h 11.4.1/260 4004_D02C Pin Control Register n (PORTE_PCR11) 32 R/W 0000_0000h 11.4.1/260 4004_D030 Pin Control Register n (PORTE_PCR12) 32 R/W 0000_0000h 11.4.1/260 4004_D034 Pin Control Register n (PORTE_PCR13) 32 R/W 0000_0000h 11.4.1/260 4004_D038 Pin Control Register n (PORTE_PCR14) 32 R/W 0000_0000h 11.4.1/260 4004_D03C Pin Control Register n (PORTE_PCR15) 32 R/W 0000_0000h 11.4.1/260 4004_D040 Pin Control Register n (PORTE_PCR16) 32 R/W 0000_0000h 11.4.1/260 4004_D044 Pin Control Register n (PORTE_PCR17) 32 R/W 0000_0000h 11.4.1/260 4004_D048 Pin Control Register n (PORTE_PCR18) 32 R/W 0000_0000h 11.4.1/260 4004_D04C Pin Control Register n (PORTE_PCR19) 32 R/W 0000_0000h 11.4.1/260 4004_D050 Pin Control Register n (PORTE_PCR20) 32 R/W 0000_0000h 11.4.1/260 4004_D054 Pin Control Register n (PORTE_PCR21) 32 R/W 0000_0000h 11.4.1/260 4004_D058 Pin Control Register n (PORTE_PCR22) 32 R/W 0000_0000h 11.4.1/260 4004_D05C Pin Control Register n (PORTE_PCR23) 32 R/W 0000_0000h 11.4.1/260 4004_D060 Pin Control Register n (PORTE_PCR24) 32 R/W 0000_0000h 11.4.1/260 4004_D064 Pin Control Register n (PORTE_PCR25) 32 R/W 0000_0000h 11.4.1/260 4004_D068 Pin Control Register n (PORTE_PCR26) 32 R/W 0000_0000h 11.4.1/260 4004_D06C Pin Control Register n (PORTE_PCR27) 32 R/W 0000_0000h 11.4.1/260 4004_D070 Pin Control Register n (PORTE_PCR28) 32 R/W 0000_0000h 11.4.1/260 4004_D074 Pin Control Register n (PORTE_PCR29) 32 R/W 0000_0000h 11.4.1/260 4004_D078 Pin Control Register n (PORTE_PCR30) 32 R/W 0000_0000h 11.4.1/260 4004_D07C Pin Control Register n (PORTE_PCR31) 32 R/W 0000_0000h 11.4.1/260 4004_D080 Global Pin Control Low Register (PORTE_GPCLR) 32 W (always reads zero) 0000_0000h 11.4.2/262 4004_D084 Global Pin Control High Register (PORTE_GPCHR) 32 W (always reads zero) 0000_0000h 11.4.3/263 Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 259

PORT memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 32 w1c 0000_0000h 11.4.4/263 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 32 R/W 0000_0000h 11.4.5/264 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 32 R/W 0000_0000h 11.4.6/265 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 32 R/W 0000_0000h 11.4.7/265

11.4.1 Pin Control Register n (PORTx_PCRn)

For PCR1 to PCR5 of the port A, bit 0, 1, 6, 8, 9,10 reset to 1; for the PCR0 of the port A, bit 1, 6, 8, 9, 10 reset to 1; in other conditions, all bits reset to 0. Addresses: 4004_9000h base + 0h offset + (4d × n), where n = 0d to 31d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 ISF 0 IRQC LK MUX DSE ODE PFE SRE PE PS W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_PCRn field descriptions Field Description 31–25 Reserved This read-only field is reserved and always has the value zero. ISF Interrupt Status Flag The pin interrupt configuration is valid in all digital pin muxing modes. 0 Configured interrupt has not been detected. 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. 23–20 Reserved This read-only field is reserved and always has the value zero. 19–16 IRQC Interrupt Configuration The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured to generate interrupt / DMA Request as follows: 0000 Interrupt/DMA Request disabled. 0001 DMA Request on rising edge. 0010 DMA Request on falling edge. 0011 DMA Request on either edge. 0100 Reserved. 1000 Interrupt when logic zero. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 260 Freescale Semiconductor, Inc.

PORTx_PCRn field descriptions (continued) Field Description 1001 Interrupt on rising edge. 1010 Interrupt on falling edge. 1011 Interrupt on either edge. 1100 Interrupt when logic one. Others Reserved. LK Lock Register 0 Pin Control Register bits [15:0] are not locked. 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. 14–11 Reserved This read-only field is reserved and always has the value zero. 10–8 MUX Pin Mux Control The corresponding pin is configured as follows: 000 Pin Disabled (Analog). 001 Alternative 1 (GPIO). 010 Alternative 2 (chip specific). 011 Alternative 3 (chip specific). 100 Alternative 4 (chip specific). 101 Alternative 5 (chip specific). 110 Alternative 6 (chip specific). 111 Alternative 7 (chip specific / JTAG / NMI). Reserved This read-only field is reserved and always has the value zero. DSE Drive Strength Enable Drive Strength configuration is valid in all digital pin muxing modes. 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. ODE Open Drain Enable Open Drain configuration is valid in all digital pin muxing modes. 0 Open Drain output is disabled on the corresponding pin. 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. PFE Passive Filter Enable Passive Filter configuration is valid in all digital pin muxing modes. 0 Passive Input Filter is disabled on the corresponding pin. 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 261

PORTx_PCRn field descriptions (continued) Field Description SRE Slew Rate Enable Slew Rate configuration is valid in all digital pin muxing modes. 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. PE Pull Enable Pull configuration is valid in all digital pin muxing modes. 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. PS Pull Select Pull configuration is valid in all digital pin muxing modes. 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set.

1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable

Register bit is set.

11.4.2 Global Pin Control Low Register (PORTx_GPCLR)

Addresses: PORTA_GPCLR is 4004_9000h base + 80h offset = 4004_9080h PORTB_GPCLR is 4004_A000h base + 80h offset = 4004_A080h PORTC_GPCLR is 4004_B000h base + 80h offset = 4004_B080h PORTD_GPCLR is 4004_C000h base + 80h offset = 4004_C080h PORTE_GPCLR is 4004_D000h base + 80h offset = 4004_D080h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_GPCLR field descriptions Field Description 31–16 GPWE Global Pin Write Enable When set, causes bits [15:0] of the corresponding Pin Control Register (15 through 0) to update with the value in the Global Pin Write Data field. 15–0 GPWD Global Pin Write Data Value to be written to bits [15:0] of all Pin Control Registers that are enabled by the Global Pin Write Enable field, provided the corresponding register has not been locked. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 262 Freescale Semiconductor, Inc.

11.4.3 Global Pin Control High Register (PORTx_GPCHR)

Addresses: PORTA_GPCHR is 4004_9000h base + 84h offset = 4004_9084h PORTB_GPCHR is 4004_A000h base + 84h offset = 4004_A084h PORTC_GPCHR is 4004_B000h base + 84h offset = 4004_B084h PORTD_GPCHR is 4004_C000h base + 84h offset = 4004_C084h PORTE_GPCHR is 4004_D000h base + 84h offset = 4004_D084h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 W GPWE GPWD Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_GPCHR field descriptions Field Description 31–16 GPWE Global Pin Write Enable When set, causes bits [15:0] of the corresponding Pin Control Register (31 through 16) to update with the value in the Global Pin Write Data field. 15–0 GPWD Global Pin Write Data Value to be written to bits [15:0] of all Pin Control Registers that are enabled by the Global Pin Write Enable field, provided the corresponding register has not been locked.

11.4.4 Interrupt Status Flag Register (PORTx_ISFR)

The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location. Addresses: PORTA_ISFR is 4004_9000h base + A0h offset = 4004_90A0h PORTB_ISFR is 4004_A000h base + A0h offset = 4004_A0A0h PORTC_ISFR is 4004_B000h base + A0h offset = 4004_B0A0h PORTD_ISFR is 4004_C000h base + A0h offset = 4004_C0A0h PORTE_ISFR is 4004_D000h base + A0h offset = 4004_D0A0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ISF W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 263

PORTx_ISFR field descriptions Field Description 31–0 ISF Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the bit. 0 Configured interrupt has not been detected. 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared.

11.4.5 Digital Filter Enable Register (PORTx_DFER)

Addresses: PORTA_DFER is 4004_9000h base + C0h offset = 4004_90C0h PORTB_DFER is 4004_A000h base + C0h offset = 4004_A0C0h PORTC_DFER is 4004_B000h base + C0h offset = 4004_B0C0h PORTD_DFER is 4004_C000h base + C0h offset = 4004_C0C0h PORTE_DFER is 4004_D000h base + C0h offset = 4004_D0C0h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DFE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFER field descriptions Field Description 31–0 DFE Digital Filter Enable The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 264 Freescale Semiconductor, Inc.

11.4.6 Digital Filter Clock Register (PORTx_DFCR)

Addresses: PORTA_DFCR is 4004_9000h base + C4h offset = 4004_90C4h PORTB_DFCR is 4004_A000h base + C4h offset = 4004_A0C4h PORTC_DFCR is 4004_B000h base + C4h offset = 4004_B0C4h PORTD_DFCR is 4004_C000h base + C4h offset = 4004_C0C4h PORTE_DFCR is 4004_D000h base + C4h offset = 4004_D0C4h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CSW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORTx_DFCR field descriptions Field Description 31–1 Reserved This read-only field is reserved and always has the value zero. CS Clock Source The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the digital input filters. Changing the filter clock source should only be done after disabling all enabled digital filters. 0 Digital Filters are clocked by the bus clock. 1 Digital Filters are clocked by the 1 kHz LPO clock.

11.4.7 Digital Filter Width Register (PORTx_DFWR)

The digital filter configuration is valid in all digital pin muxing modes. Addresses: PORTA_DFWR is 4004_9000h base + C8h offset = 4004_90C8h PORTB_DFWR is 4004_A000h base + C8h offset = 4004_A0C8h PORTC_DFWR is 4004_B000h base + C8h offset = 4004_B0C8h PORTD_DFWR is 4004_C000h base + C8h offset = 4004_C0C8h PORTE_DFWR is 4004_D000h base + C8h offset = 4004_D0C8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FILT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 265

PORTx_DFWR field descriptions Field Description 31–5 Reserved This read-only field is reserved and always has the value zero. 4–0 FILT Filter Length The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the glitches (in clock cycles) the digital filter absorbs for enabled digital filters. Glitches that are longer than this register setting (in clock cycles) will pass through the digital filter, while glitches that are equal to or less than this register setting (in clock cycles) will be filtered. Changing the filter length should only be done after disabling all enabled filters.

11.5 Functional description

11.5.1 Pin control

The lower half of the pin control register configures the following functions for each pin within the 32-bit port. These functions apply across all digital pin muxing modes and individual peripherals do not override the configuration in this register (for example, if an I2C function is enabled on a pin then that does not override the pullup or open drain configuration for that pin). When the pin muxing mode is configured for analog/disabled then the all digital functions on that pin are disabled. This includes the pullup and pulldown enables, digital output buffer enable, digital input buffer enable and passive filter enable.

• Pullup or pulldown enable
• Drive strength and slew rate configuration
• Open drain enable
• Passive input filter enable
• Pin muxing mode A lock bit also exists that allows the configuration for each pin to be locked until the next system reset. Once locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. The configuration of each pin control register is retained when the PORT module is disabled. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 266 Freescale Semiconductor, Inc.

11.5.2 Global pin control

The two global pin control registers allow a single register write to update the lower half of the pin control register on up to sixteen pins, all with the same value. Registers that are locked cannot be written using the global pin control registers. The global pin control registers are designed to enable software to quickly configure multiple pins within the one port for the same peripheral function. Note however that interrupt functions are unable to be configured using the global pin control registers. The global pin control registers are write only registers, that always read as zero.

11.5.3 External interrupts

The external interrupt capability of the PORT module are available in all digital pin muxing modes provided the PORT module is enabled. Each pin can be individually configured for any of the following external interrupt modes:

• Interrupt disabled (default out of reset)
• Active high level sensitive interrupt
• Active low level sensitive interrupt
• Rising edge sensitive interrupt
• Falling edge sensitive interrupt
• Rising and falling edge sensitive interrupt
• Rising edge sensitive DMA request
• Falling edge sensitive DMA request
• Rising and falling edge sensitive DMA request The interrupt status flag is set when the configured edge or level is detected on the output of the digital filter (if enabled) or pin (if digital filter is bypassed). When not in stop mode, the input is first synchronized to the bus clock to detect the configured level or edge transition. The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. The interrupt negates once the interrupt status flags for all enabled interrupts have been cleared. The PORT module generates a single DMA request that asserts when the interrupt status flag is set for any enabled DMA request in that port. The DMA request negates once the DMA transfer has been completed, since that clears the interrupt status flags for all enabled DMA requests. Chapter 11 Port control and interrupts (PORT) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 267

During stop mode, the interrupt status flag for any enabled interrupt (but not DMA request) will asynchronously set if the required level or edge is detected. This also generates an asynchronous wakeup signal to exit the low power mode.

11.5.4 Digital filter

The digital filter capabilities of the PORT module are available in all digital pin muxing modes provided the PORT module is enabled. The clock used for all digital filters within the one port can be configured between the bus clock or the 1 kHz LPO clock. This selection should be changed only when all digital filters for that port are disabled. If the digital filters for a port are configured to use the bus clock, then the digital filters are bypassed (and do not update) during stop mode. The filter width in clock size is the same for all enabled digital filters within the one port and should be changed only when all digital filters for that port are disabled. The output of each digital filter is logic zero after system reset and whenever a digital filter is disabled. Once a digital filter is enabled, the input is synchronized to the filter clock (either the bus clock or the 1 kHz LPO clock). If the synchronized input and the output of the digital filter remain different for a number of filter clock cycles equal to the filter width register configuration, then the output of the digital filter updates to equal the synchronized filter input. The minimum latency through a digital filter equals two or three filter clock cycles plus the filter width configuration register. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 268 Freescale Semiconductor, Inc.

System integration module (SIM)

12.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The system integration module (SIM) provides system control and chip configuration registers.

12.1.1 Features

• Configuration for system clocking
• Clock source selection for SDHC, I 2S, Ethernet timestamp, USB, and PLL/FLL source
• System clock divide values
• I 2S and USB clock divide values
• Architectural clock gating control
• Flash configuration
• USB regulator configuration
• RAM size configuration
• Flextimer external clock and fault source selection
• UART0 and UART1 receive/transmit source selection/configuration
• Reset pin filtering

12.1.2 Modes of operation

• Run mode
• Sleep mode K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 269

• Deep sleep mode
• VLLS mode

12.1.3 SIM Signal Descriptions

Table 12-1. SIM Signal Descriptions Signa l Description I/O EZP_ CS EzPort mode select I

12.1.3.1 Detailed signal description

Table 12-2. SIM interface-detailed signal descriptions Signal I/O Description EZP_CS I EZPORT mode select State meaning Assertion-0 - Configure part for EZPORT mode Negation- 1 - Configure part for normal flash operation Timing As a mode select, this signal is only recognized during reset although it can be asserted and negated at any time. Assertion-May occur at any time; input may be asserted asynchronously to the system clock. Negation-May occur at any time; input may be negated asynchronously to the system clock.

12.2 Memory map and register definition

The SIM module contains many bitfields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information including block diagrams and clock definitions. NOTE The SIM_SOPT1 register is located at a different base address than the other SIM registers. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 270 Freescale Semiconductor, Inc.

(hex) Register name Width (in bits) Access Reset value Section/ page 4004_7000 System Options Register 1 (SIM_SOPT1) 32 R/W Undefined 12.2.1/272 4004_8004 System Options Register 2 (SIM_SOPT2) 32 R/W 0000_1000h 12.2.2/274 4004_800C System Options Register 4 (SIM_SOPT4) 32 R/W 0000_0000h 12.2.3/276 4004_8010 System Options Register 5 (SIM_SOPT5) 32 R/W 0000_0000h 12.2.4/279 4004_8014 System Options Register 6 (SIM_SOPT6) 32 R/W 0000_0000h 12.2.5/280 4004_8018 System Options Register 7 (SIM_SOPT7) 32 R/W 0000_0000h 12.2.6/281 4004_8024 System Device Identification Register (SIM_SDID) 32 R Undefined 12.2.7/283 4004_8028 System Clock Gating Control Register 1 (SIM_SCGC1) 32 R/W 0000_0000h 12.2.8/284 4004_802C System Clock Gating Control Register 2 (SIM_SCGC2) 32 R/W 0000_0000h 12.2.9/285 4004_8030 System Clock Gating Control Register 3 (SIM_SCGC3) 32 R/W 0000_0000h 12.2.10/ 286 4004_8034 System Clock Gating Control Register 4 (SIM_SCGC4) 32 R/W 6010_0030h 12.2.11/ 287 4004_8038 System Clock Gating Control Register 5 (SIM_SCGC5) 32 R/W 0004_0180h 12.2.12/ 290 4004_803C System Clock Gating Control Register 6 (SIM_SCGC6) 32 R/W 4000_0001h 12.2.13/ 292 4004_8040 System Clock Gating Control Register 7 (SIM_SCGC7) 32 R/W 0000_0007h 12.2.14/ 294 4004_8044 System Clock Divider Register 1 (SIM_CLKDIV1) 32 R/W Undefined 12.2.15/ 295 4004_8048 System Clock Divider Register 2 (SIM_CLKDIV2) 32 R/W 0000_0000h 12.2.16/ 298 4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R Undefined 12.2.17/ 299 4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R Undefined 12.2.18/ 301 4004_8054 Unique Identification Register High (SIM_UIDH) 32 R Undefined 12.2.19/ 302 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R Undefined 12.2.20/ 303 4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R Undefined 12.2.21/ 303 4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R Undefined 12.2.22/ 304 Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 271

12.2.1 System Options Register 1 (SIM_SOPT1)

The reset value of the SOPT1 register is as follows: Exit from POR and LVD: USBREGEN is set, USBSTBY is cleared, and OSC32KSEL is cleared. Exit from VLLS or other system reset: USBREGEN, USBSTBY and OSC32KSEL are unaffected Address: SIM_SOPT1 is 4004_7000h base + 0h offset = 4004_7000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R USBREGEN USBSTBY Reserved

0 MS 0

W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RAMSIZE 0 W * Notes: x = Undefined at reset.• SIM_SOPT1 field descriptions Field Description USBREGEN USB voltage regulator enable Controls whether the USB voltage regulator is enabled. 0 USB voltage regulator is disabled. 1 USB voltage regulator is enabled. USBSTBY USB voltage regulator in standby mode Controls whether the USB voltage regulator is placed in standby mode. 0 USB voltage regulator not in standby. 1 USB voltage regulator in standby. 29–27 Reserved This field is reserved. 26–24 Reserved This read-only field is reserved and always has the value zero. MS EzPort chip select pin state Reflects the state of the EzPort chip select (EZP_CS) pin during the last reset. This bit is read-only. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 272 Freescale Semiconductor, Inc.

SIM_SOPT1 field descriptions (continued) Field Description 22–20 Reserved This read-only field is reserved and always has the value zero. OSC32KSEL 32K oscillator clock select Selects the 32 kHz clock source (ERCLK32K) for TSI and LPTMR. This bit is reset only for POR/LVD.

0 System oscillator (OSC32KCLK)

1 RTC oscillator

18–16 Reserved This read-only field is reserved and always has the value zero. 15–12 RAMSIZE RAM size This field specifies the amount of system RAM available on the device.

0000 Undefined

0001 Undefined

0010 Undefined

0011 Undefined

0100 Undefined

0110 Undefined

1010 Undefined

1011 Undefined

1100 Undefined

1101 Undefined

1110 Undefined

1111 Undefined

11–0 Reserved This read-only field is reserved and always has the value zero. Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 273

12.2.2 System Options Register 2 (SIM_SOPT2)

SOPT2 contains the controls for selecting many of the module clock source options on this device. See the Clock Distribution chapter for more information including clocking diagrams and definitions of device clocks. Address: SIM_SOPT2 is 4004_7000h base + 1004h offset = 4004_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SDHCSRC I2SSRC TIMESRC USBSRC PLLFLLSELW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 TRACECLKSEL CMTUARTPAD FBSL MCGCLKSEL W Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT2 field descriptions Field Description 31–30 Reserved This read-only field is reserved and always has the value zero. 29–28 SDHCSRC SDHC clock source select Selects the clock source for the SDHC clock. 00 Core/system clock.

01 MCGPLLCLK/MCGFLLCLK clock

10 OSCERCLK clock

11 External bypass clock (SDHC0_CLKIN)

27–26 Reserved This read-only field is reserved and always has the value zero. 25–24 I2SSRC I2S master clock source select Selects the clock source for I2S master clock. 00 Core/system clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions. 01 MCGPLLCLK/MCGFLLCLK clock divided by the I2S fractional clock divider. See the SIM_CLKDIV2[I2SFRAC, I2SDIV] descriptions. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 274 Freescale Semiconductor, Inc.

SIM_SOPT2 field descriptions (continued) Field Description

11 External bypass clock (I2S0_CLKIN)

23–22 Reserved This read-only field is reserved and always has the value zero. 21–20 TIMESRC IEEE 1588 timestamp clock source select Selects the clock source for the Ethernet timestamp clock. 00 Core/system clock. 11 External bypass clock (ENET_1588_CLKIN). Reserved This read-only field is reserved and always has the value zero. USBSRC USB clock source select Selects the clock source for the USB 48 MHz clock. 0 External bypass clock (USB_CLKIN). 1 MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the SIM_CLKDIV2[USBFRAC, USBDIV] descriptions. Reserved This read-only field is reserved and always has the value zero. PLLFLLSEL PLL/FLL clock select Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options.

0 MCGFLLCLK clock

1 MCGPLLCLK clock

15–13 Reserved This read-only field is reserved and always has the value zero. TRACECLKSEL Debug trace clock select Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source.

0 MCGOUTCLK

1 Core/system clock

CMT/UART pad drive strength Controls the output drive strength of the CMT IRO signal or UART0_TXD signal on PTD7 pin by selecting either one or two pads to drive it. 0 Single-pad drive strength for CMT IRO or UART0_TXD. 1 Dual-pad drive strength for CMT IRO or UART0_TXD. Reserved This read-only field is reserved and always has the value zero. 9–8 FBSL FlexBus security level Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 275

SIM_SOPT2 field descriptions (continued) Field Description If flash security is enabled, then this field affects what CPU operations can access off-chip via the FlexBus interface. This field has no effect if flash security is not enabled. 00 All off-chip accesses (instruction and data) via the FlexBus are disallowed. 01 All off-chip accesses (instruction and data) via the FlexBus are disallowed. 10 Off-chip instruction accesses are disallowed. Data accesses are allowed. 11 Off-chip instruction accesses and data accesses are allowed. 7–1 Reserved This read-only field is reserved and always has the value zero. MCGCLKSEL MCG clock select Selects the MCG's external reference clock.

0 System oscillator (OSCCLK)

12.2.3 System Options Register 4 (SIM_SOPT4)

Address: SIM_SOPT4 is 4004_7000h base + 100Ch offset = 4004_800Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 FTM2CLKSEL FTM1CLKSEL FTM0CLKSEL FTM2CH0SRC FTM1CH0SRC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 FTM2FLT0 FTM1FLT0 FTM0FLT2 FTM0FLT1 FTM0FLT0W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT4 field descriptions Field Description 31–27 Reserved This read-only field is reserved and always has the value zero. FTM2CLKSEL FlexTimer 2 External Clock Pin Select Selects the external pin used to drive the clock to the FTM2 module. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 276 Freescale Semiconductor, Inc.

SIM_SOPT4 field descriptions (continued) Field Description NOTE: The selected pin must also be configured for the FTM2 module external clock function through the appropriate pin control register in the port control module. 0 FTM2 external clock driven by FTM_CLK0 pin. 1 FTM2 external clock driven by FTM_CLK1 pin. FTM1CLKSEL FTM1 External Clock Pin Select Selects the external pin used to drive the clock to the FTM1 module. NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module.

0 FTM_CLK0 pin

1 FTM_CLK1 pin

FlexTimer 0 External Clock Pin Select Selects the external pin used to drive the clock to the FTM0 module. NOTE: The selected pin must also be configured for the FTM external clock function through the appropriate pin control register in the port control module. 23–22 Reserved This read-only field is reserved and always has the value zero. 21–20 FTM2CH0SRC FTM2 channel 0 input capture source select Selects the source for FTM2 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field.

00 FTM2_CH0 signal

01 CMP0 output

10 CMP1 output

11 Reserved

19–18 FTM1CH0SRC FTM1 channel 0 input capture source select Selects the source for FTM1 channel 0 input capture. NOTE: When the FTM is not in input capture mode, clear this field.

00 FTM1_CH0 signal

17–9 Reserved This read-only field is reserved and always has the value zero. FTM2FLT0 FTM2 Fault 0 Select Selects the source of FTM2 fault 0. Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 277

SIM_SOPT4 field descriptions (continued) Field Description NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate PORTx pin control register.

0 FTM2_FLT0 pin

1 CMP0 out

7–5 Reserved This read-only field is reserved and always has the value zero. FTM1FLT0 FTM1 Fault 0 Select Selects the source of FTM1 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module.

0 FTM1_FLT0 pin

This read-only field is reserved and always has the value zero. FTM0FLT2 FTM0 Fault 2 Select Selects the source of FTM0 fault 2. NOTE: The pin source for fault 2 must be configured for the FTM module fault function through the appropriate pin control register in the port control module.

0 FTM0_FLT2 pin

1 CMP2 out

Selects the source of FTM0 fault 1. NOTE: The pin source for fault 1 must be configured for the FTM module fault function through the appropriate pin control register in the port control module.

0 FTM0_FLT1 pin

1 CMP1 out

Selects the source of FTM0 fault 0. NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module.

0 FTM0_FLT0 pin

Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 278 Freescale Semiconductor, Inc.

12.2.4 System Options Register 5 (SIM_SOPT5)

Address: SIM_SOPT5 is 4004_7000h base + 1010h offset = 4004_8010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 UART1RXSRC UARTTXSRC UART0RXSRC UART0TXSRC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT5 field descriptions Field Description 31–8 Reserved This read-only field is reserved and always has the value zero. 7–6 UART1RXSRC UART 1 receive data source select Selects the source for the UART 1 receive data.

00 UART1_RX pin

01 CMP0

10 CMP1

5–4 UARTTXSRC UART 1 transmit data source select Selects the source for the UART 1 transmit data.

00 UART1_TX pin

01 UART1_TX pin modulated with FTM1 channel 0 output

10 UART1_TX pin modulated with FTM2 channel 0 output

3–2 UART0RXSRC UART 0 receive data source select Selects the source for the UART 0 receive data.

00 UART0_RX pin

1–0 UART0TXSRC UART 0 transmit data source select Selects the source for the UART 0 transmit data.

00 UART0_TX pin

01 UART0_TX pin modulated with FTM1 channel 0 output

Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 279

SIM_SOPT5 field descriptions (continued) Field Description

10 UART0_TX pin modulated with FTM2 channel 0 output

12.2.5 System Options Register 6 (SIM_SOPT6)

The reset values of the RSTFLTEN and RSTFLTSEL bits are for power-on reset only. They are unaffected by other reset types. Address: SIM_SOPT6 is 4004_7000h base + 1014h offset = 4004_8014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R RSTFLTEN RSTFLTSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT6 field descriptions Field Description 31–29 RSTFLTEN Reset pin filter enable Selects how the reset pin filter is enabled. See Reset pin filter for more details.

000 All filtering disabled

001 Bus clock filter enabled in normal operation. LPO clock filter enabled in stop mode.

010 LPO clock filter enabled

011 Bus clock filter enabled in normal operation. All filtering disabled in stop mode. 100 LPO clock filter enabled in normal operation. All filtering disabled in stop mode.

101 Reserved (all filtering disabled)

110 Reserved (all filtering disabled)

111 Reserved (all filtering disabled)

28–24 RSTFLTSEL Reset pin filter select Selects the reset pin bus clock filter count value. The filter count value is the RSTFL value + 1. 23–0 Reserved This read-only field is reserved and always has the value zero. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 280 Freescale Semiconductor, Inc.

12.2.6 System Options Register 7 (SIM_SOPT7)

Address: SIM_SOPT7 is 4004_7000h base + 1018h offset = 4004_8018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ADC1ALTTRGEN ADC1PRETRGSEL ADC1TRGSEL ADC0ALTTRGEN ADC0PRETRGSEL ADC0TRGSEL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SOPT7 field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. ADC1ALTTRGEN ADC1 alternate trigger enable Enable alternative conversion triggers for ADC1.

0 PDB trigger selected for ADC1

1 Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. 14–13 Reserved This read-only field is reserved and always has the value zero. ADC1PRETRGSEL ADC1 pre-trigger select Selects the ADC1 pre-trigger source when alternative triggers are enabled through ADC1ALTTRGEN. 0 Pre-trigger A selected for ADC1. 1 Pre-trigger B selected for ADC1. 11–8 ADC1TRGSEL ADC1 trigger select Selects the ADC1 trigger source when alternative triggers are functional. NOTE: Not all trigger sources are available in Stop and VLPS modes.

0000 PDB external trigger pin input (PDB0_EXTRG)

Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 281

SIM_SOPT7 field descriptions (continued) Field Description

0001 High speed comparator 0 output

0010 High speed comparator 1 output

0011 High speed comparator 2 output

0100 PIT trigger 0

0101 PIT trigger 1

0110 PIT trigger 2

0111 PIT trigger 3

1000 FTM0 trigger

1001 FTM1 trigger

1010 FTM2 trigger

1011 Unused

1110 Low-power timer trigger

ADC0 alternate trigger enable Enable alternative conversion triggers for ADC0. 0 PDB trigger selected for ADC0. 1 Alternate trigger selected for ADC0. 6–5 Reserved This read-only field is reserved and always has the value zero. ADC0PRETRGSEL ADC0 pretrigger select Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN.

0 Pre-trigger A

1 Pre-trigger B

3–0 ADC0TRGSEL ADC0 trigger select Selects the ADC0 trigger source when alternative triggers are functional. NOTE: Not all trigger sources are available in Stop and VLPS modes. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 282 Freescale Semiconductor, Inc.

SIM_SOPT7 field descriptions (continued) Field Description

12.2.7 System Device Identification Register (SIM_SDID)

Address: SIM_SDID is 4004_7000h base + 1024h offset = 4004_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 REVID 0 0 1 0 FAMID PINID W * Notes: x = Undefined at reset.• SIM_SDID field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. 15–12 REVID Device revision number Specifies the silicon implementation number for the device. 11–10 Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value one. Reserved This read-only field is reserved and always has the value zero. 6–4 FAMID Kinetis family identification Specifies the Kinetis family of the device.

000 K10

001 K20

010 K30

011 K40

100 K60

101 K70

110 K50 and K52

111 K51 and K53

Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 283

SIM_SDID field descriptions (continued) Field Description 3–0 PINID Pincount identification Specifies the pincount of the device.

0000 Reserved

0001 Reserved

0011 Reserved

1101 Reserved

1111 Reserved

12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)

Address: SIM_SCGC1 is 4004_7000h base + 1028h offset = 4004_8028h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 UART4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC1 field descriptions Field Description 31–25 Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero. 23–22 Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero. 20–12 Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 284 Freescale Semiconductor, Inc.

SIM_SCGC1 field descriptions (continued) Field Description Reserved This read-only field is reserved and always has the value zero. UART4 UART4 Clock Gate Control This bit controls the clock gate to the UART4 module.

0 Clock disabled

1 Clock enabled

9–0 Reserved This read-only field is reserved and always has the value zero.

12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)

Address: SIM_SCGC2 is 4004_7000h base + 102Ch offset = 4004_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 DAC0 ENETW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC2 field descriptions Field Description 31–14 Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero. DAC0 DAC0 Clock Gate Control This bit controls the clock gate to the DAC0 module. 11–1 Reserved This read-only field is reserved and always has the value zero. ENET ENET Clock Gate Control This bit controls the clock gate to the ENET module. Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 285

12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)

Address: SIM_SCGC3 is 4004_7000h base + 1030h offset = 4004_8030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 ADC1 FTM2 SDHC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SPI2 FLEXCAN1 RNGBW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_SCGC3 field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero. 29–28 Reserved This read-only field is reserved and always has the value zero. ADC1 ADC1 Clock Gate Control This bit controls the clock gate to the ADC1 module. 26–25 Reserved This read-only field is reserved and always has the value zero. FTM2 FTM2 Clock Gate Control This bit controls the clock gate to the FTM2 module. 23–18 Reserved This read-only field is reserved and always has the value zero. SDHC SDHC Clock Gate Control This bit controls the clock gate to the SDHC module. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 286 Freescale Semiconductor, Inc.

SIM_SCGC3 field descriptions (continued) Field Description 16–13 Reserved This read-only field is reserved and always has the value zero. SPI2 SPI2 Clock Gate Control This bit controls the clock gate to the SPI2 module. 11–5 Reserved This read-only field is reserved and always has the value zero. FLEXCAN1 FlexCAN1 Clock Gate Control This bit controls the clock gate to the FlexCAN1 module. 3–1 Reserved This read-only field is reserved and always has the value zero. RNGB RNGB Clock Gate Control This bit controls the clock gate to the RNGB module.

12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)

Address: SIM_SCGC4 is 4004_7000h base + 1034h offset = 4004_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 1 LLWU VREF CMP USBOTG W Reset 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 UART3 UART2 UART1 UART0 I2C1 I2C0 1 0 CMT EWM W Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 287

SIM_SCGC4 field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. 30–29 Reserved This read-only field is reserved and always has the value one. LLWU LLWU Clock Gate Control This bit controls the clock gate to the LLWU module. 27–21 Reserved This read-only field is reserved and always has the value zero. VREF VREF Clock Gate Control This bit controls the clock gate to the VREF module. Comparator Clock Gate Control This bit controls the clock gate to the comparator module. This bit controls the clock gate to the USB module. 17–14 Reserved This read-only field is reserved and always has the value zero. UART3 UART3 Clock Gate Control This bit controls the clock gate to the UART3 module. This bit controls the clock gate to the UART2 module. This bit controls the clock gate to the UART1 module. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 288 Freescale Semiconductor, Inc.

SIM_SCGC4 field descriptions (continued) Field Description This bit controls the clock gate to the UART0 module. 9–8 Reserved This read-only field is reserved and always has the value zero. I2C1 I2C1 Clock Gate Control This bit controls the clock gate to the I2C1 module. This bit controls the clock gate to the I2C0 module. 5–4 Reserved This read-only field is reserved and always has the value one. Reserved This read-only field is reserved and always has the value zero. CMT CMT Clock Gate Control This bit controls the clock gate to the CMT module. This bit controls the clock gate to the EWM module. This read-only field is reserved and always has the value zero. Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 289

12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)

Address: SIM_SCGC5 is 4004_7000h base + 1038h offset = 4004_8038h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 1 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 PORTE PORTD PORTC PORTB PORTA 1 0 TSI REGFILE LPTIMERW Reset 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 SIM_SCGC5 field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value one. 17–14 Reserved This read-only field is reserved and always has the value zero. PORTE Port E Clock Gate Control This bit controls the clock gate to the Port E module. This bit controls the clock gate to the Port D module. This bit controls the clock gate to the Port C module. This bit controls the clock gate to the Port B module. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 290 Freescale Semiconductor, Inc.

SIM_SCGC5 field descriptions (continued) Field Description This bit controls the clock gate to the Port A module. 8–7 Reserved This read-only field is reserved and always has the value one. Reserved This read-only field is reserved and always has the value zero. TSI TSI Clock Gate Control This bit controls the clock gate to the TSI module. 4–2 Reserved This read-only field is reserved and always has the value zero. REGFILE Register File Clock Gate Control This bit controls the clock gate to the Register File module. Low Power Timer Clock Gate Control This bit controls the clock gate to the Low Power Timer module. Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 291

12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)

Address: SIM_SCGC6 is 4004_7000h base + 103Ch offset = 4004_803Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 1 RTC ADC0 FTM1 FTM0 PIT PDB USBDCD CRC W Reset 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R I2S SPI1 SPI0 FLEXCAN0 DMAMUX FTFLW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SIM_SCGC6 field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value one. RTC RTC Clock Gate Control This bit controls the clock gate to the RTC module. This read-only field is reserved and always has the value zero. ADC0 ADC0 Clock Gate Control This bit controls the clock gate to the ADC0 module. This read-only field is reserved and always has the value zero. FTM1 FTM1 Clock Gate Control This bit controls the clock gate to the FTM1 module. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 292 Freescale Semiconductor, Inc.

SIM_SCGC6 field descriptions (continued) Field Description FTM0 FTM0 Clock Gate Control This bit controls the clock gate to the FTM0 module. This bit controls the clock gate to the PIT module. This bit controls the clock gate to the PDB module. USB DCD Clock Gate Control This bit controls the clock gate to the USB DCD module. 20–19 Reserved This read-only field is reserved and always has the value zero. CRC CRC Clock Gate Control This bit controls the clock gate to the CRC module. 17–16 Reserved This read-only field is reserved and always has the value zero. I2S I2S Clock Gate Control This bit controls the clock gate to the I2S module. This read-only field is reserved and always has the value zero. SPI1 SPI1 Clock Gate Control This bit controls the clock gate to the SPI1 module. Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 293

SIM_SCGC6 field descriptions (continued) Field Description SPI0 SPI0 Clock Gate Control This bit controls the clock gate to the SPI0 module. 11–5 Reserved This read-only field is reserved and always has the value zero. FLEXCAN0 FlexCAN0 Clock Gate Control This bit controls the clock gate to the FlexCAN0 module. 3–2 Reserved This read-only field is reserved and always has the value zero. DMAMUX DMA Mux Clock Gate Control This bit controls the clock gate to the DMA Mux module. Flash Memory Clock Gate Control This bit controls the clock gate to the flash memory.

12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)

Address: SIM_SCGC7 is 4004_7000h base + 1040h offset = 4004_8040h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MPU DMA FLEXBUSW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 294 Freescale Semiconductor, Inc.

SIM_SCGC7 field descriptions Field Description 31–3 Reserved This read-only field is reserved and always has the value zero. MPU MPU Clock Gate Control This bit controls the clock gate to the MPU module. This bit controls the clock gate to the DMA module. FlexBus Clock Gate Control This bit controls the clock gate to the FlexBus module.

12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)

The CLKDIV1 register cannot be written to when the device is in VLPR mode. Address: SIM_CLKDIV1 is 4004_7000h base + 1044h offset = 4004_8044h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R OUTDIV1 OUTDIV2 OUTDIV3 OUTDIV4 W * Notes: x = Undefined at reset.• SIM_CLKDIV1 field descriptions Field Description 31–28 OUTDIV1 Clock 1 output divider value This field sets the divide value for the core/system clock. At the end of reset, it is loaded with either 0000 or 0111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 295

SIM_CLKDIV1 field descriptions (continued) Field Description 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 27–24 OUTDIV2 Clock 2 output divider value This field sets the divide value for the peripheral clock. At the end of reset, it is loaded with either 0000 or 0111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 23–20 OUTDIV3 Clock 3 output divider value This field sets the divide value for the FlexBus clock driven to the external pin (FB_CLK). At the end of reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. Table continues on the next page... Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 296 Freescale Semiconductor, Inc.

SIM_CLKDIV1 field descriptions (continued) Field Description 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 19–16 OUTDIV4 Clock 4 output divider value This field sets the divide value for the flash clock. At the end of reset, it is loaded with either 0001 or 1111 depending on FTFL_FOPT[LPBOOT]. 0000 Divide-by-1. 0001 Divide-by-2. 0010 Divide-by-3. 0011 Divide-by-4. 0100 Divide-by-5. 0101 Divide-by-6. 0110 Divide-by-7. 0111 Divide-by-8. 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 15–0 Reserved This read-only field is reserved and always has the value zero. Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 297

12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)

Address: SIM_CLKDIV2 is 4004_7000h base + 1048h offset = 4004_8048h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R I2SDIV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R I2SFRAC USBDIV USBFRAC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIM_CLKDIV2 field descriptions Field Description 31–20 I2SDIV I2S clock divider value This field sets the divide value for when the fractional clock divider is used as the source for the I2S master clock. The clock input to the fractional clock divider is set by the SOPT2[I2SSRC] bit. Divider output clock = Divider input clock × [(I2SFRAC+1) / (I2SDIV+1) ] NOTE: The I2S clock must be disabled (SCGC6[I2S] = 0) before altering this bitfield. 19–16 Reserved This read-only field is reserved and always has the value zero. 15–8 I2SFRAC I2S clock divider fraction This field sets the multiply value for when the fractional clock divider is used as a the source for I2S master clock. The clock input to the fractional clock divider is set by the SOPT2[I2SSRC] bit. Divider output clock = Divider input clock × [(I2SFRAC+1) / (I2SDIV+1) ] NOTE: The I2S clock must be disabled (SCGC6[I2S] = 0) before altering this bitfield. 7–4 Reserved This read-only field is reserved and always has the value zero. 3–1 USBDIV USB clock divider divisor This field sets the divide value for the fractional clock divider when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] USBFRAC USB clock divider fraction This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK/ MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 298 Freescale Semiconductor, Inc.

12.2.17 Flash Configuration Register 1 (SIM_FCFG1)

For devices with FlexNVM: The reset value of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command. For devices with program flash only: The EESIZE and DEPART filelds are not applicable. Address: SIM_FCFG1 is 4004_7000h base + 104Ch offset = 4004_804Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NVMSIZE PFSIZE 0 EESIZE 0 DEPART 0 W * Notes: x = Undefined at reset.• SIM_FCFG1 field descriptions Field Description 31–28 NVMSIZE FlexNVM size This field specifies the amount of FlexNVM memory available on the device. Undefined values are reserved. 0000 0 KB of FlexNVM 0111 128 KB of FlexNVM, 16 KB protection region 1001 256 KB of FlexNVM, 32 KB protection region 1111 256 KB of FlexNVM, 32 KB protection region 27–24 PFSIZE Program flash size This field specifies the amount of program flash memory available on the device. Undefined values are reserved. 0111 128 KB of program flash memory, 4 KB protection region 1001 256 KB of program flash memory, 8 KB protection region 1011 512 KB of program flash memory, 16 KB protection region

1111 For devices with FlexNVM (SIM_FCFG2[PFLSH]=0): 256 KB of program flash, 8 KB protection

region. For devices without FlexNVM (SIM_FCFG2[PFLSH]=1): 512 KB of program flash memory,

16 KB protection region

23–20 Reserved This read-only field is reserved and always has the value zero. 19–16 EESIZE EEPROM size EEPROM data size. For devices with FlexNVM: This value is only valid with EEPROM partitioning. Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 299

SIM_FCFG1 field descriptions (continued) Field Description For devices without FlexNVM:Reserved 15–12 Reserved This read-only field is reserved and always has the value zero. 11–8 DEPART FlexNVM partition For devices with FlexNVM: Data flash / EEPROM backup split. See DEPART bit description in FTFL chapter. For devices without FlexNVM: Reserved 7–0 Reserved This read-only field is reserved and always has the value zero. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 300 Freescale Semiconductor, Inc.

12.2.18 Flash Configuration Register 2 (SIM_FCFG2)

Address: SIM_FCFG2 is 4004_7000h base + 1050h offset = 4004_8050h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R SWAPPFLSH

0 MAXADDR0

0 MAXADDR1

W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 W * Notes: x = Undefined at reset.• SIM_FCFG2 field descriptions Field Description SWAPPFLSH Swap program flash For devices without FlexNVM: Indicates that swap is active. 0 Swap is not active. 1 Swap is active. Reserved This read-only field is reserved and always has the value zero. 29–24 MAXADDR0 Max address block 0 This field concatenated with 13 zeros indicates the first invalid address of flash block 0 (program flash 0). For example, if MAXADDR0 = 0x20 the first invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 value for a device with 256 KB program flash in flash block 0. PFLSH Program flash For devices with FlexNVM: Indicates whether block 1 is program flash or FlexNVM. Table continues on the next page... Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 301

SIM_FCFG2 field descriptions (continued) Field Description For devices without FlexNVM: This bit is always set.

0 For devices with FlexNVM: Physical flash block 1 is used as FlexNVM

For devices without FlexNVM: Reserved

1 Physical flash block 1 is used as program flash

This read-only field is reserved and always has the value zero. 21–16 MAXADDR1 Max address block 1 For devices with FlexNVM: This field concatenated with 13 zeros plus the FlexNVM base address indicates the first invalid address of the FlexNVM (flash block 1). For example, if MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value for a device with 256 KB FlexNVM. For devices with program flash only: This field concatenated with 13 zeros plus the value of the MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1). For example, if MAXADDR0 = MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be the MAXADDR1 value for a device with 512 KB program flash memory and no FlexNVM. 15–0 Reserved This read-only field is reserved and always has the value zero.

12.2.19 Unique Identification Register High (SIM_UIDH)

Address: SIM_UIDH is 4004_7000h base + 1054h offset = 4004_8054h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W * Notes: x = Undefined at reset.• SIM_UIDH field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device. Memory map and register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 302 Freescale Semiconductor, Inc.

12.2.20 Unique Identification Register Mid-High (SIM_UIDMH)

Address: SIM_UIDMH is 4004_7000h base + 1058h offset = 4004_8058h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W * Notes: x = Undefined at reset.• SIM_UIDMH field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device.

12.2.21 Unique Identification Register Mid Low (SIM_UIDML)

Address: SIM_UIDML is 4004_7000h base + 105Ch offset = 4004_805Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W * Notes: x = Undefined at reset.• SIM_UIDML field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device. Chapter 12 System integration module (SIM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 303

12.2.22 Unique Identification Register Low (SIM_UIDL)

Address: SIM_UIDL is 4004_7000h base + 1060h offset = 4004_8060h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UID W * Notes: x = Undefined at reset.• SIM_UIDL field descriptions Field Description 31–0 UID Unique Identification Unique identification for the device.

12.3 Functional description

See Introduction section. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 304 Freescale Semiconductor, Inc.

13.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. This section discusses the mode controller (MC) which controls power management and reset mechanisms including the various sources of resets on the device. The MC provides:

• control and protection on entry and exit to each power mode
• control for the Power Management Controller (PMC)
• reset entry and exit for the complete MCU The device's operating power modes are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. This chapter also discusses basic information about all reset sources in one place for easy reference. Modules that cause resets (such as the watchdog and the low leakage wake up (LLWU) modules) discuss the reset operation in their own chapters.

13.1.1 Features

• Power mode entry/exit and protection
• Reset control features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• System reset status (SRSH and SRSL) registers to indicate source of most recent reset K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 305

13.1.2 Modes of Operation

The ARM CPU has three primary modes of operation: run, sleep, and deep sleep. The WFI instruction is used to invoke sleep and deep sleep modes. For Freescale microcontrollers, run, wait and stop are the common terminology used for the primary operating modes. The following table shows the translation between the ARM CPU and the MCU power modes. ARM CPU mode MCU mode Sleep Wait Deep sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. This device augments stop, wait, and run in a number of ways. The power management controller (PMC) contains a run and a stop mode regulator. Run regulation is used in normal run, wait and stop modes. Stop mode regulation is used during all very low power and low leakage modes. During stop mode regulation the bus frequencies are limited for the very low power modes. The PMC provides the user with multiple power options. The low power operating modes can drastically reduce run time power when maximum bus frequency is not required to handle the application needs. From normal run mode, the run mode (RUNM) bit field can be modified to change the the MCU into the very lower power run (VLPR) mode when limited frequency is required during the application. For the low power run mode, a corresponding wait and stop mode can be entered. Depending on the needs of the user application, a variety of stop modes are available that allow the state retention, partial power down or full power down of certain logic and/or memory. I/O states are held in all modes of operation. Several registers are used to configure the various modes of operation for the device. The following table describes the power modes available for the device. Table 13-1. Power modes Mode Description Run MCU can be run at full speed and the internal supply is fully regulated (run regulation mode). This mode is also referred to as normal run mode. Wait In ARM architectures, the Core Clock to the ARM Cortex-M4 core is shut off. The System Clock continues to operate; Bus Clocks if enabled continue to operate; run regulation is maintained. Stop In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off immediately.System Clock to other masters and Bus Clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. Table continues on the next page... Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 306 Freescale Semiconductor, Inc.

Table 13-1. Power modes (continued) Mode Description VLPR The Core Clock, System Clock and Bus Clocks maximum frequency is restricted to 2MHz max, Flash Clock is restricted to 1MHz. The slow IRC within the MCG must not be enabled when VLPR is entered. VLPW In ARM architectures, the Core Clock to the ARM Cortex-M4 core is shut off. The System Clock continues to operate; Bus Clocks if enabled continue to operate; System and Bus clock restricted to 2MHz max, Flash Clock is restricted to 1MHz VLPS In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. LLS In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off immediately. System clock and Bus Clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage mode by reducing the voltage to internal logic. Internal logic states are retained. VLLS3 In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering down the internal logic. System RAM contents retained and I/O states held. Internal logic states are not retained. VLLS2 In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering down the internal logic and part of system RAM. The rest of the system RAM contents are retained and I/O states held. FlexRAM contents can optionally be retained. Internal logic states are not retained. NOTE: See the device's Chip Configuration details for the amount of SRAM retained in VLLS2 mode. VLLS1 In ARM architectures, Core Clock and System Clock to the ARM Cortex-M4 core shut off immediately. System clock to other masters and Bus Clocks are stopped after all stop acknowledge signals from supporting peripherals are valid. MCU is placed in a low leakage mode by powering down the internal logic and all system RAM. A 32-byte register file (available in all modes) contents retained and I/O states held. Internal logic states are not retained.

13.1.2.1 Power Mode Transitions

The following shows the power mode state transitions available on the device. Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 307

3, 2, 1 VLPS VLPR VLPW Any reset Figure 13-1. Power Mode State Diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 13-2. Power mode transition triggers Transition # From To Trigger Conditions

1 Run Wait Sleep-now or sleep-on-exit modes entered with SLEEPDEEP

clear, controlled in System Control Register in ARM core. Wait Run Interrupt or Reset

2 Run STOP Sleep-now or sleep-on-exit modes entered with SLEEPDEEP

set, controlled in System Control Register in ARM core STOP Run Interrupt or Reset Table continues on the next page... Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 308 Freescale Semiconductor, Inc.

Table 13-2. Power mode transition triggers (continued) Transition # From To Trigger Conditions

3 Run VLPR Reduce system, bus and core frequency to 2 MHz or less,

Flash access limited to 1MHz. AVLP=1, Set RUNM = 10. NOTE: Poll VLPRS bit before transitioning out of VLPR mode. VLPR Run Set RUNM = 00 or Interrupt with LPWUI =1 or Reset. NOTE: Poll REGONS bit before increasing frequency.

4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEP

clear, controlled in System Control Register in ARM core VLPW VLPR Interrupt with LPWUI = 0

5 VLPW Run Interrupt with LPWUI = 1 or

6 VLPR VLPS LPLLSM=000 or 010, Sleep-now or sleep-on-exit modes

entered with SLEEPDEEP set, controlled in System Control Register in ARM core VLPS VLPR Interrupt with LPWUI = 0

7 Run VLPS AVLP=1, LPLLSM=010, Sleep-now or sleep-on-exit modes

entered with SLEEPDEEP set, controlled in System Control Register in ARM core NOTE: Hardware will set LPWUI and will remain set until software clears. VLPS Run Interrupt with LPWUI =1 or Reset

8 Run LLS LPLLSM=011, Sleep-now or sleep-on-exit modes entered

with SLEEPDEEP set, controlled in System Control Register in ARM core LLS Run Wakeup from enabled LLWU input source or RESET pin

9 VLPR LLS LPLLSM=011, Sleep-now or sleep-on-exit modes entered

with SLEEPDEEP set, controlled in System Control Register in ARM core

10 Run VLLS(3,2,1) LPLLSM = (see PMCTRL register description for VLLS

configuration), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, controlled in System Control Register in ARM core VLLS(3,2,1) Run Wakeup from enabled LLWU input source or RESET pin Table continues on the next page... Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 309

Table 13-2. Power mode transition triggers (continued) Transition # From To Trigger Conditions

11 VLPR VLLS(3,2,1) LPLLSM = (see PMCTRL register description for VLLS

configuration), Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, controlled in System Control Register in ARM core

13.1.2.2 Run Modes

The device contains two different run modes:

• Run
• Very low power run (VLPR)

13.1.2.2.1 Run Mode

This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR):

• The processor reads the start SP (SP_main) from vector-table offset 0x000
• The processor reads the start PC from vector-table offset 0x004
• LR is set to 0xFFFF_FFFF. To reduce power in this mode, disable unused modules by clearing the peripherals corresponding clock gating control bit in the SIM's registers.

13.1.2.2.2 Very Low Power Run (VLPR) Mode

In VLPR, the on-chip voltage regulator is put into a stop mode regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules in the peripherals' corresponding clock gating control bits in the SIM's registers. Before entering this mode, the following conditions must be met:

• One of two clock sources selected:
• Either BLPE is the selected clock mode for the MCG or
• BLPI with the 2MHz IRC.
• The system, bus, and core frequency is 2 MHz or less.
• Flash frequency is 1 MHz or less.
• Mode protection must be set to allow VLP modes (AVLP = 1). Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 310 Freescale Semiconductor, Inc.

• RUNM set to 10b to enter VLPR.
• Flash programming/erasing is not allowed.
• The slow IRC must not be enabled.
• All clock monitors must be disabled before entering VLPR. While in VLPR, the regulator is slow responding and cannot handle fast load transitions. Therefore, do not change the clock frequency. This includes a requirement to not modify the module clock enables in the SIM or any clock divider registers. To re-enter normal run mode, simply clear RUNM. The REGONS and VLPRS bits in the REGSC register are read-only status bits that indicate if the regulator is in run regulation mode or not:
• When REGONS is set, the regulator is in run regulation mode and the MCU can run at full speed in any clock mode. If a higher execution frequency is desired, poll REGONS until it is set when returning from VLPR.
• When VLPRS is set, the system is fully in VLPR mode. NOTE
• Do not enter VLPS, LLS, or VLLSx until the transition to VLPR completes as indicated by the VLPRS bit.
• Do not attempt to transition out of run mode until the REGONS bit sets. VLPR also provides the option to return to run regulation if any interrupt occurs. This is done by setting the low power wake up on interrupt (LPWUI) bit in the PMCTRL register. In the interrupt service routine (ISR) it is not be necessary to poll the REGONS before increasing the frequency. The VLPR frequency limits are such that the regulator is in run regulation and REGONS is set before the ISR is entered. Any reset exits VLPR, clears RUNM, REGONS is set, and the device is in normal run mode after the CPU exits its reset flow.

13.1.2.3 Wait Modes

This device contains two different wait modes:

• Wait
• Very low power wait Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 311

13.1.2.3.1 Wait Mode

Wait mode is entered when the ARM core enters the sleep-now or sleep-on-exit modes. The ARM CPU enters a low-power state in which it is not clocked, but peripherals continue to be clocked provided they are enabled and clock gating to the peripheral is enabled via the SIM. When an interrupt request occurs, the CPU exits wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. An asserted RESET pin or LVD (if the LVD system is enabled) exits wait mode, returning the device to normal run mode.

13.1.2.3.2 Very Low Power Wait (VLPW) Mode

VLPW is entered by the entering the “sleep-now" or "sleep-on-exit” mode while the MCU is in the very low power run (VLPR) mode and configured appropriately. In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency. To further reduce power in this mode, disable the clocks to unused modules by clearing the peripherals' corresponding clock gating control bits in the SIM. VLPR mode restrictions also apply to VLPW. VLPW mode provides the option to return to full-regulated normal run mode if any enabled interrupt occurs. This is done by setting the low power wake up on interrupt (LPWUI) bit in the PMCTRL register. Wait for REGONS status to set before increasing the frequency. If the LPWUI bit is clear when the interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. Wait for VLPRS status to set before transitioning to other power modes. An asserted RESET pin or a watchdog timeout exits VLPW and clears the RUNM and WAITE bits. This returns the regulator to run regulation and the device to normal run mode.

13.1.2.4 Stop Modes

This device contains a variety of stop modes to meet your application needs. The stop modes range from: stopped CPU where all states are saved and certain asynchronous mode peripherals are operating to only I/Os are held, a small register file is retained, and Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 312 Freescale Semiconductor, Inc.

certain asynchronous mode peripherals are operating with the remainer of the MCU powered off. The tradeoffs depend upon the user's application, where power usage and state retention versus functional needs are weighed. The various stop modes are selected by setting the appropriate bits in the power mode protection (PMPROT) and power mode control (PMCTRL) registers. The selected stop mode mode is entered during the sleep-now or sleep-on-exit entry with with the SLEEPDEEP bit set in the System Control Register in the ARM core. The available stop modes are:

• Stop
• Very low power stop (VLPS)
• Low leakage stop (LLS)
• Very low leakage stop 1 (VLLS1)
• Very low leakage stop 2 (VLLS2)
• Very low leakage stop 3 (VLLS3)

13.1.2.4.1 Stop Mode

Stop mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running. A module capable of providing an asynchronous interrupt to the device (for example, an enabled pin interrupt, NMI, RTC, LVW, UART wakeup on edge, CMP, or ADC) takes the device out of stop mode and returns the device to normal run mode. Reference Table 13-1 for peripheral, I/O, and memory operation in stop. When an interrupt request occurs, the CPU exits stop mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. An asserted RESET pin, a watchdog timeout, or LVD with LVDRE set exits stop mode. The device returns to normal run mode via a MCU reset.

13.1.2.4.2 Very Low Power Stop (VLPS) Mode

VLPS mode can be entered in one of two ways:

• Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core while the MCU is in very low power run (VLPR) mode and configured as per Table 13-2.
• When the MCU is in normal run mode with LPLLSM set to 010b, entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 313

Register in the ARM core forces the MCU into VLPS and hardware sets the LPWUI bit set. In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. On transitions from VLPR to VLPS with LPLLSM set to 000b, hardware forces LPLLSM to value of 010b. A module capable of providing an asynchronous interrupt to the device (for example, an enabled pin interrupt, NMI, RTC, UART wakeup on edge, CMP or ADC) takes the device out of VLPS and returns the device to VLPR provided the LPWUI bit is clear. If LPWUI is set, the device returns to normal run mode upon an interrupt request. The REGONS bit must be set before allowing the system to return to a frequency higher than allowed in VLPR. An asserted RESET pin or a watchdog timeout causes VLPS exit. This returns the device to normal run mode.

13.1.2.4.3 Low-Leakage Stop (LLS) Mode

Low leakage stop (LLS) mode can be entered from normal run or VLPR modes. The MCU enters LLS mode if:

• In sleep-now or sleep-on-exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and
• The device is configured as per Table 13-2. In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put in a state-retention mode that does not allow them to operate while in LLS. In LLS, configure the low leakage wake up (LLWU) module to enable the desired wakeup sources. The available wakeup sources in LLS are detailed in the Chip Configuration details for this device. After wakeup from LLS, the device returns to normal run mode with a pending LLWU module interrupt. In the LLWU interrupt service routine (ISR) poll the LLWU module wakeup flags to determine the source of the wakeup. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. An asserted RESET pin exits LLS. This returns the device to normal run mode. When LLS is exiting via the RESET pin, the PIN and WAKEUP bits are set in the SRSL register. Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 314 Freescale Semiconductor, Inc.

13.1.2.4.4 Very Low-Leakage Stop (VLLS3,2,1) Modes

This device contains three very low leakage modes: VLLS3, VLLS2, and VLLS1. When a reference applies to all three low leakage modes, VLLS is used. All three of the VLLS modes can be entered from normal run or VLPR. The MCU enters the configured VLLS mode if:

• In sleep-now or sleep-on-exit mode, the SLEEPDEEP bit is set in the System Control Register in the ARM core, and
• The device is configured as per Table 13-2. In VLLS, the on-chip voltage regulator is in its stop-regulation state. In VLLS, configure the LLWU module to enable the desired wakeup sources. The available wakeup sources in VLLS are detailed LLWU's Chip Configuration details for this device. When entering VLLS, each I/O pin is latched as configured before executing VLLS. Since all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before ACKISO in the LLWU is set. An asserted RESET pin exits any VLLS mode. This returns the device to normal run mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bits are set in the SRSL register.

13.1.2.5 ARM Debug in Low Power Modes

When the MCU is secure the device disables/limits debugger operation. When the MCU is unsecure, the ARM debugger can assert two power-up request signals:

• System power up (SYSPWR bit in the Debug Port Control/Stat register)
• Debug power up (CDBGPWRUPREQ bit in the Debug Port Control/Stat register) When asserted while in run, wait, VLPR, or VLPW, the Mode Controller drives a corresponding acknowledge for each signal (CDBGPWRUPACK, CSYSPWRUPACK). When both requests are asserted, the Mode Controller handles attempts to enter stop and VLPS by entering an emulated stop state. In this emulated stop state:
• The regulator is in stop regulation,
• The MCG-generated clock source is enabled,
• All system clocks, except core clock, are disabled,
• The debug module has access to core registers, and
• Access to the on-chip peripherals is blocked. Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 315

No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention mode and all debug operation can continue after waking from LLS, even in cases where system wakeup is due to a system reset event. Entering into a VLLS mode causes all the debug controls and settings to be powered off. To give time to the debugger to sync with the MCU, the MDM AP Control Register includes a Very Low Leakage Debug Request (VLLDBGREQ) bit that is set to configure the Mode Controller logic to hold the system in reset after the next recovery from a VLLS mode. This bit allows the debugger time to re-initialize the debug module before the debug session continues. The VLLDBGREQ bit clears automatically due to the reset generated as part of the VLLS recovery. The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger re-initializes all debug IP and then asserts the VLLDBGACK control bit to allow the Mode Controller to release the ARM core from reset and allow CPU operation to begin. The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears automatically due to the reset generated as part of the next VLLS recovery.

13.1.3 MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR).

• The processor reads the start SP (SP_main) from vector-table offset 0x000
• The processor reads the start PC from vector-table offset 0x004
• LR is set to 0xFFFF_FFFF The device resets can be generalized into three distinct groups: POR, system resets, and debug resets. POR reset:
• Power-on reset (POR) System resets:
• External pin reset (PIN) Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 316 Freescale Semiconductor, Inc.

• Computer operating properly (COP) timer
• Clock generator (MCG) loss of clock reset (LOC)
• Low-voltage detect (LVD)
• Wakeup from very low leakage stop modes, VLLSx
• Software reset (SW) - by setting SYSRESETREQ bit of the NVIC's Application Interrupt and Reset Control Register
• LOCKUP - core in lockup state
• EzPort
• MDM AP Reset - by setting System Reset Request bit of the MDM AP Control Register Debug reset:
• Asserting JTAG_TRST pin Each of the system reset sources, with the exception of the EzPort and MDM AP reset, has an associated bit in the system reset status low (SRSL) register.

13.1.3.1 Power-On Reset (POR)

When power is initially applied to the device, or when the supply voltage drops below the power-on-reset re-arm voltage level (VPOR), the POR circuit causes a reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply rises above the LVD low threshold (VLVDL). The POR and LVD bits in SRSL are set following a POR.

13.1.3.2 External RESET Pin

RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET resets the device from any run, wait, stop, VLP, LLS, or VLLS mode. When the RESET pin is the cause of reset, the SRSL[PIN] bit is set.

13.1.3.3 Computer Operating Properly (COP) Timer Reset

The watchdog timer monitors the operation of the system by expecting periodic communication from the software. Generally, this is known as servicing, or refreshing, the watchdog. If this periodic refreshing does not occur, the watchdog issues a system reset. When the watchdog timer expiration causes a reset, the SRSL[COP] bit is set. Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 317

13.1.3.4 Multi-Clock Generator (MCG) Loss-of-Clock (LOC) Reset

The MCG module supports an external reference clock. If the clock monitor is enabled (MCG_C6[CME] is set) and the external reference falls below a certain frequency (specified in the MCG_C2[RANGE] field), the MCU resets. If a loss of clock causes a reset, the SRSL[LOC] bit is set. For more details on the clock generator, see Multi-Clock Generator (MCG).

13.1.3.5 Low-Voltage Detect (LVD) Reset

If LVDRE is set, the LVD generates a reset upon detection of a low voltage condition. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage rises above the LVD threshold (specified by the LVDV bits). The SRSL[LVD] bit is set following an LVD reset or POR.

13.1.3.6 Low Leakage Mode Recovery

The LLWU provides the means for up to 16 external pins, the RESET pin, and seven internal peripherals to wake the device from LLS and VLLS power modes. When in VLLS mode, all enabled inputs to the LLWU will generate a system reset flow when detected. When in LLS mode, only a detected RESET pin results in a recovery via a reset flow. For LLS mode exits via RESET pin and any VLLS mode via a wakeup or reset event, the MC_SRS[WAKEUP] is set indicating a low-leakage mode was active prior to the last system reset flow. Using the RESET pin to trigger an exit from LLS or VLLS results in the MC_SRS[PIN] being set as well. After the system reset, the LLWU continues to retain the flags indicating the source of wakeup until the user clears them or the next LLS or VLLS entry occurs. NOTE External pin flags are cleared by software via the LLWU registers and internal peripheral module flags are required to be cleared in associated peripheral's registers. Refer to the individual peripheral chapters for more information. Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 318 Freescale Semiconductor, Inc.

13.1.3.7 Software (SW) Reset

Setting the SYSRESETREQ bit in the NVIC's Application Interrupt and Reset Control Register forces a software reset on the device. A software reset resets of all major components except for debug. When the device is reset by a software reset, the SRSH[SW] bit is set.

13.1.3.8 Lock-Up Reset

When the processor’s built-in system state protection hardware detects the core is locked up because of an unrecoverable exception, a lock-up reset occurs. When a lock-up condition causes a reset, the SRSH[LOCKUP] bit is set.

13.1.3.9 EzPort Reset

The EzPort generates a system reset request following execution of a RESET command via the EzPort interface. This method of reset allows the chip to boot from flash memory after it has been programmed by an external source.

13.1.3.10 MDM-AP System Reset Request

A system reset is initiated by setting the System Reset Request bit in the MDM-AP Control register. This is the primary method for resets via the debug interface. System reset is held until this bit is cleared.

13.1.3.11 JTAG Reset

The JTAG module generates a system reset when certain IR codes are selected. This functional reset is asserted when the EZPORT, EXTEST, HIGHZ and CLAMP instructions are active. The reset source from the JTAG module is released when any other IR code is selected. A JTAG reset causes the SRSH[JTAG] bit to set.

13.2 Mode Control Memory Map/Register Definition

The following table shows the registers related to the Mode Controller. Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 319

(hex) Register name Width (in bits) Access Reset value Section/ page 4007_E000 System Reset Status Register High (MC_SRSH) 8 R/W 00h 13.2.1/320 4007_E001 System Reset Status Register Low (MC_SRSL) 8 R/W 82h 13.2.2/321 4007_E002 Power Mode Protection Register (MC_PMPROT) 8 R/W 00h 13.2.3/322 4007_E003 Power Mode Control Register (MC_PMCTRL) 8 R/W 00h 13.2.4/324

13.2.1 System Reset Status Register High (MC_SRSH)

The SRSH:SRSL registers include read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. Throughout this document, SRS refers to SRSH:SRSL. NOTE The reset value of this register depends on the reset type:

• POR — 0x00
• LVD — 0x00
• Low-leakage wake-up (LLS exit via RESET pin or any exit from VLLS) — 0x00
• Other reset — bits 2-0 are set if their corresponding reset source caused the reset Address: MC_SRSH is 4007_E000h base + 0h offset = 4007_E000h Bit 7 6 5 4 3 2 1 0 Read 0 SW LOCKUP JTAG Write Reset 0 0 0 0 0 0 0 0 MC_SRSH field descriptions Field Description 7–3 Reserved This read-only field is reserved and always has the value zero. SW Software Indicates reset was caused by software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register in the ARM Core

0 Reset not caused by software setting of SYSRESETREQ bit

1 Reset caused by software setting of SYSRESETREQ bit

Table continues on the next page... Mode Control Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 320 Freescale Semiconductor, Inc.

MC_SRSH field descriptions (continued) Field Description Indicates reset was caused by the ARM core indication of a LOCKUP event.

0 Reset not caused by core LOCKUP event

1 Reset caused by core LOCKUP event

Indicates reset was caused by JTAG selection of certain IR codes (EZPORT, EXTEST, HIGHZ, and CLAMP).

0 Reset not caused by JTAG

1 Reset caused by JTAG

13.2.2 System Reset Status Register Low (MC_SRSL)

The SRSH:SRSL registers includes read-only status flags to indicate the source of the most recent reset. The reset state of these bits depends on what caused the MCU to reset. Throughout this document, SRS refers to SRSH:SRSL. NOTE The reset value of this register depends on the reset type:

• POR — 0x82
• LVD — 0x02
• Low-leakage wake-up due to RESET pin assertion — 0x41
• Low-leakage wake-up due to other wake-up sources — 0x01
• Other reset — bits 6-5 and 2 are set if their corresponding reset source caused the reset Address: MC_SRSL is 4007_E000h base + 1h offset = 4007_E001h Bit 7 6 5 4 3 2 1 0 Read POR PIN COP 0 LOC LVD WAKEUP Write Reset 1 0 0 0 0 0 1 0 MC_SRSL field descriptions Field Description POR Power-on reset Indicates a reset was caused by the power-on detection logic. Because the internal supply voltage was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while the internal supply was below the LVD threshold. Table continues on the next page... Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 321

MC_SRSL field descriptions (continued) Field Description

0 Reset not caused by POR

1 Reset caused by POR

Indicates reset was caused by an active-low level on the external RESETpin.

0 Reset not caused by external reset pin

1 Reset caused by external reset pin

Computer Operating Properly (COP) Watchdog Reset was caused by the COP watchdog timer timing out. This reset source can be blocked by disabling the watchdog. For more information, see the watchdog chapter.

0 Reset not caused by COP timeout

1 Reset caused by COP timeout

4–3 Reserved This read-only field is reserved and always has the value zero. LOC Loss-of-clock reset Indicates reset was caused by a loss of external clock. The MCG clock monitor must be enabled for a loss of clock to be detected. See the MCG chapter for information on enabling the clock monitor. 0 Reset not caused by a loss of external clock. 1 Reset caused by a loss of external clock. LVD Low-voltage detect reset If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR.

0 Reset not caused by LVD trip or POR

1 Reset caused by LVD trip or POR

Reset was caused by an enabled LLWU module wakeup source while the device was in LLS or VLLS modes. Wakeup sources in LLS is limited to the RESET pin. In VLLS, any enabled wakeup source causes a reset. This bit is cleared by any reset except WAKEUP.

0 Reset not caused by LLWU module wakeup source

1 Reset caused by LLWU module wakeup source

13.2.3 Power Mode Protection Register (MC_PMPROT)

This write-once register allows low power or low leakage modes to be entered. The actual enabling of the low power or low leakage modes is done by configuring the power mode control register (PMCTRL). Mode Control Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 322 Freescale Semiconductor, Inc.

If the MCU is configured for a disallowed power mode, the MCU remains in its current power mode. For example, if in normal run (RUNM = 00, AVLP = 0) an attempt to enter VLPR using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b indicating MCU is still in normal run mode. PMPROT is write once after any reset. This write to PMPROT clears LPLLSM, which provides protection after wakeup from low power or low leakage modes. The state of LPLLSM prior to clearing due to update of PMPROT indicates which power mode was exited and should be used by initialization software for proper power mode recovery. NOTE The reset value of this register depends on the reset type:

• Low-leakage wake-up (LLS exit via RESET pin or any exit from VLLS) — bits 4, 2-0 unaffected
• Other reset — 0x00 Address: MC_PMPROT is 4007_E000h base + 2h offset = 4007_E002h Bit 7 6 5 4 3 2 1 0 Read 0 AVLP ALLS AVLLS3 AVLLS2 AVLLS1 Write Reset 0 0 0 0 0 0 0 0 MC_PMPROT field descriptions Field Description 7–6 Reserved This read-only field is reserved and always has the value zero. AVLP Allow very low power modes Provided the appropriate control bits are set up in PMCTRL, this write-once bit allows the MCU to enter the very low power modes: VLPR, VLPW, and VLPS.

0 VLPR, VLPW, and VLPS are not allowed

1 VLPR, VLPW, and VLPS are allowed

Allow low leakage stop mode This write once bit allows the MCU to enter low leakage stop mode (LLS) provided the appropriate control bits are set up in PMCTRL.

0 LLS is not allowed

1 LLS is allowed

This read-only field is reserved and always has the value zero. AVLLS3 Allow Very Low Leakage Stop 3 Mode This write once bit allows the MCU to enter very low leakage stop 3 mode (VLLS3) provided the appropriate control bits are set up in PMCTRL. Table continues on the next page... Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 323

MC_PMPROT field descriptions (continued) Field Description

0 VLLS3 is not allowed

1 VLLS3 is allowed

Allow very low leakage stop 2 mode This write once bit allows the MCU to enter very low leakage stop 2 mode (VLLS2) provided the appropriate control bits are set up in PMCTRL.

0 VLLS2 is not allowed

1 VLLS2 is allowed

Allow very low leakage stop 1 mode This write once bit allows the MCU to enter very low leakage stop 1 mode (VLLS1) provided the appropriate control bits are set up in PMCTRL.

0 VLLS1 is not allowed

1 VLLS1 is allowed

13.2.4 Power Mode Control Register (MC_PMCTRL)

The PMCTRL register is used to enter the wait, low power, or low leakage modes provided the selected power mode is allowed via appropriate setting of the protection register (PMPROT). If the MCU is configured for a disallowed power mode or to a reserved RUNM setting, the device remains in its current power mode. For example, if in normal run (RUNM = 00, AVLP = 0) an attempt to enter VLPR using the PMCTRL[RUNM] bits is blocked and RUNM bits remain 00 indicating the device is still in normal run mode. Before configuring the LPLLSM bits, the corresponding allow bit in PMPROT must be set. Writes to LPLLSM that do not meet this criteria are ignored. A successful write to PMPROT clears the LPLLSM bits. The state of PMCTRL[LPLLSM] prior to clearing due to update of PMPROT indicates which power mode was exited and should be used by initialization software for proper power mode recovery. NOTE The reset value of this register depends on the reset type:

• Low-leakage wake-up (LLS exit via RESET pin or any exit from VLLS) — bits 2-0 unaffected
• Other reset — 0x00 Mode Control Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 324 Freescale Semiconductor, Inc.

Address: MC_PMCTRL is 4007_E000h base + 3h offset = 4007_E003h Bit 7 6 5 4 3 2 1 0 Read LPWUI RUNM LPLLSM Write Reset 0 0 0 0 0 0 0 0 MC_PMCTRL field descriptions Field Description LPWUI Low Power Wake Up on Interrupt Controls if the voltage regulator exits stop regulation when any active MCU interrupt occurs, returning the MCU to normal run mode.

0 The voltage regulator remains in stop regulation on an interrupt

1 The voltage regulator exits stop regulation on an interrupt

6–5 RUNM Run Mode Enable This field is used to enter very low power run. Writes to this field are blocked if the protection level has not been enabled using PMPROT register. This field is cleared by hardware on exit from LLS or VLLS modes.

00 Normal run mode

01 Reserved

10 Very low power run mode

4–3 Reserved This read-only field is reserved and always has the value zero. 2–0 LPLLSM Low Power, Low Leakage Stop Mode Select low power or low leakage stop modes provided the PMPROT was set properly and stop mode entry via the sleep-now or sleep-on-exit. After any system reset, writes to reconfigure PMPROT clears LPLLSM.

000 Normal stop

001 Reserved

010 Very low power stop (VLPS)

011 Low leakage stop (LLS)

100 Reserved

101 Very low leakage stop 3 (VLLS3)

110 Very low leakage stop 2 (VLLS2)

111 Very low leakage stop 1 (VLLS1)

Chapter 13 Mode Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 325

Mode Control Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 326 Freescale Semiconductor, Inc.

Power Management Controller

14.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The PMC contains the internal voltage regulator, power on reset (POR), and low voltage detect system. The Mode Controller controls the PMC and its chapter contains description of all device resets, including POR.

14.2 Features

Power management control features include:

• Internal voltage regulator
• Active POR providing brown-out detect
• Low-voltage detect protection including:
• Multiple programmable trip voltages
• Warning and detect interrupt control
• Drive a reset on low voltage detect

14.3 Low-Voltage Detect (LVD) System

This device includes a system to protect against low-voltage conditions to protect memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user- K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 327

selectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by the LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx modes. Two flags are available to indicate the status of the low-voltage detect system:

• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the internal supply voltage falls below the selected internal monitor trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the internal trip point; otherwise, the LVDF bit remains set.
• The low voltage warning flag (LVWF) operates in a level sensitive manner. The LVWF bit is set when the internal supply voltage falls below the selected internal monitor trip point (VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only if the internal supply has returned above the internal trip point; otherwise, the LVWF bit remains set.

14.3.1 LVD Reset Operation

By setting the LVDRE bit, the LVD generates a reset upon detection of a low voltage condition. The low voltage detection threshold is determined by the LVDV bits. After an LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises above this threshold. The LVD bit in the SRS register is set following an LVD or power- on reset.

14.3.2 LVD Interrupt Operation

By configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear), LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low voltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK] bit.

14.3.3 Low-Voltage Warning (LVW) Interrupt Operation

The LVD system contains a low voltage warning flag (LVWF) to indicate that the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt, which is enabled by setting the LVDSC2[LVWIE] bit. If enabled, an LVW interrupt request occurs when the LVWF is set. LVWF is cleared by writing one to the LVDSC2[LVWACK] bit. Low-Voltage Detect (LVD) System K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 328 Freescale Semiconductor, Inc.

The LVDSC2[LVWV] bits select one of four trip voltages:

• Highest (V LVW4)
• Two mid-levels (V LVW3 and VLVW2)
• Lowest (V LVW1)

14.4 PMC Memory Map/Register Definition

The following table shows the registers related to the PMC. See Mode Control Memory Map/Register Definition for the mode controller registers. PMC memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4007_D000 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1) 8 R/W 10h 14.4.1/329 4007_D001 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2) 8 R/W 00h 14.4.2/330 4007_D002 Regulator Status and Control Register (PMC_REGSC) 8 R/W 04h 14.4.3/332

14.4.1 Low Voltage Detect Status and Control 1 Register

(PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect systems that must have LVD always on, configure the power mode protection register (PMPROT) to disallow any very low power or low leakage modes from being enabled. See the device's data sheet for the exact LVD trip voltages. NOTE The reset value of this register depends on the reset type:

• POR -- 0x10
• Other reset -- bit 4 is set, bits 1-0 are unaffected Chapter 14 Power Management Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 329

Address: PMC_LVDSC1 is 4007_D000h base + 0h offset = 4007_D000h Bit 7 6 5 4 3 2 1 0 Read LVDF 0 LVDIE LVDRE LVDV Write LVDACK Reset 0 0 0 1 0 0 0 0 PMC_LVDSC1 field descriptions Field Description LVDF Low-Voltage Detect Flag This read-only status bit indicates a low-voltage detect event.

0 Low-voltage event not detected

1 Low-voltage event detected

Low-Voltage Detect Acknowledge This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads always return 0. LVDIE Low-Voltage Detect Interrupt Enable Enables hardware interrupt requests for LVDF.

0 Hardware interrupt disabled (use polling)

1 Request a hardware interrupt when LVDF = 1. LVDRE Low-Voltage Detect Reset Enable This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored.

0 LVDF does not generate hardware resets

1 Force an MCU reset when LVDF = 1

3–2 Reserved This read-only field is reserved and always has the value zero. 1–0 LVDV Low-Voltage Detect Voltage Select Selects the LVD trip point voltage (VLVD).

00 Low trip point selected (VLVD = VLVDL)

01 High trip point selected (VLVD = VLVDH)

10 Reserved

14.4.2 Low Voltage Detect Status and Control 2 Register

(PMC_LVDSC2) This register contains status and control bits to support the low voltage warning function. While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings. PMC Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 330 Freescale Semiconductor, Inc.

See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV bits. NOTE The reset value of this register depends on the reset type:

• POR -- 0x00
• Other reset -- bits 1-0 are unaffected Address: PMC_LVDSC2 is 4007_D000h base + 1h offset = 4007_D001h Bit 7 6 5 4 3 2 1 0 Read LVWF 0 LVWIE LVWV Write LVWACK Reset 0 0 0 0 0 0 0 0 PMC_LVDSC2 field descriptions Field Description LVWF Low-Voltage Warning Flag This read-only status bit indicates a low-voltage warning event. LVWF is set when VSupply transitions below the trip point or after reset and VSupply is already below VLVW.

0 Low-voltage warning event not detected

1 Low-voltage warning event detected

Low-Voltage Warning Acknowledge This write-only bit is used to acknowledge low voltage warning errors (write 1 to clear LVWF). Reads always return 0. LVWIE Low-Voltage Warning Interrupt Enable Enables hardware interrupt requests for LVWF. 1 Request a hardware interrupt when LVWF = 1. 4–2 Reserved This read-only field is reserved and always has the value zero. 1–0 LVWV Low-Voltage Warning Voltage Select Selects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV].

00 Low trip point selected (VLVW = VLVW1H/L)

01 Mid 1 trip point selected (VLVW = VLVW2H/L)

10 Mid 2 trip point selected (VLVW = VLVW3H/L)

11 High trip point selected (VLVW = VLVW4H/L)

Chapter 14 Power Management Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 331

14.4.3 Regulator Status and Control Register (PMC_REGSC)

The power management controller contains an internal voltage regulator. The voltage regulator design uses a bandgap reference, that is also available through a buffer as input to certain internal peripherals. The internal regulator provides a status bit (REGONS) indicating the regulator is in run regulation. This bit is used when the application moves from a low power or very low power mode where the frequency is limited to normal run mode. The frequency of the application can not be increased until the regulator is back in run regulation (REGONS=1). Address: PMC_REGSC is 4007_D000h base + 2h offset = 4007_D002h Bit 7 6 5 4 3 2 1 0 Read 0 TRAMPO VLPRS REGONS BGBE Write 0 Reset 0 0 0 0 0 1 0 0 PMC_REGSC field descriptions Field Description 7–5 Reserved This read-only field is reserved and always has the value zero. TRAMPO For devices with FlexNVM: Traditional RAM Power Option For devices with program flash only: Reserved For devices with FlexNVM: When the FlexRAM on the device is configured for traditional RAM, this bit enables powering of this RAM in VLLS2 mode.

0 For devices with FlexNVM: Traditional RAM not powered in VLLS2

For devices with program flash only: No effect

1 For devices with FlexNVM: Traditional RAM powered in VLLS2

For devices with program flash only: No effect VLPRS Very Low Power Run Status This read only bit indicates the current run mode is VLPR.

0 MCU is not in VLPR mode

1 MCU is in VLPR mode

Regulator in Run Regulation Status This read-only bit provides the current status of the internal voltage regulator.

0 Regulator is in stop regulation or in transition to/from it

1 Regulator is in run regulation

This field is reserved. Table continues on the next page... PMC Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 332 Freescale Semiconductor, Inc.

PMC_REGSC field descriptions (continued) Field Description BGBE Bandgap Buffer Enable Enables the bandgap buffer.

0 Bandgap buffer not enabled

1 Bandgap buffer enabled

Chapter 14 Power Management Controller K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 333

PMC Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 334 Freescale Semiconductor, Inc.

Low-leakage wake-up unit (LLWU)

15.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The LLWU module allows the user to select up to 16 external pin sources and up to 7 internal modules as a wakeup source from low-leakage power modes (LLS and VLLS). The input sources vary by device and are described in the specific device's Chip Configuration details. Each of the available wakeup sources can be individually enabled. The RESET pin is an additional source for triggering an exit from low-leakage power modes and causes the MCU to exit both LLS and VLLS through a reset flow. On MCUs where the RESET pin is shared with other functions, the explicit port mux control register must be set for RESET pin before the RESET pin can be used as a low-leakage reset source. When in LLS mode, the I/O are released immediately on a wakeup or reset event. In the case of LLS exit via a RESET pin, the I/O default to their reset state. When in VLLS modes, the I/O states are held on a wakeup event until the wakeup has been acknowledged via a write to the ACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and default to their reset state. In this case, no write to the ACKISO is needed. In both LLS mode exits via RESET pin and any VLLS mode via a wakeup or reset event, the MC_SRS[WAKEUP] is set indicating the low-leakage mode was active prior to the last system reset flow. Using the RESET pin to trigger an exit from LLS or VLLS results in the MC_SRS[PIN] being set as well. The LLWU module also includes two optional digital pin filters. One for the external wakeup pins combined and one for the RESET pin. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 335

15.1.1 Features

The LLWU module features include:

• Supports up to 16 external input pins and up to 7 internal modules with individual enable bits
• Input sources may be external pins or from internal peripherals capable of running in LLS or VLLS. See the Chip Configuration details for wakeup input sources for this device.
• Each external pin wakeup input is programmable as falling edge, rising edge, or any change
• Each internal module wakeup input source qualified with programmable enable
• Wakeup inputs are activated if enabled once MCU enters low leakage stop (LLS) or very low leakage stop (VLLS) modes
• Reset exit due to assertion of RESET pin via reset flow. I/O states are reset on exit
• Wakeup from LLS mode is handled as an interrupt. I/O states are released on exit
• Wakeup exit via reset flow when MCU is in VLLS. I/O states remain in held state until wakeup has been acknowledged.
• An optional digital filter provided to qualify an external pin detect and RESET pin detect.

15.1.2 Modes of operation

The LLWU module is only functional in LLS and VLLS modes.

15.1.2.1 LLS mode

The LLWU module provides up to 16 external wakeup inputs and up to seven internal module wakeup inputs. In addition, an LLS reset event can be initiated via assertion of the RESET pin. Wakeup events due to external wakeup inputs and internal module wakeup inputs result in an interrupt flow when exiting LLS. A reset event due to RESET pin assertion results in a reset flow when exiting LLS. NOTE The LLWU interrupt must not be masked by the interrupt controller to avoid a scenario where the system does not fully exit stop mode on an LLS recovery. Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 336 Freescale Semiconductor, Inc.

15.1.2.2 VLLS modes

The LLWU module provides up to 16 external wakeup inputs and up to seven internal module wakeup inputs. In addition, a VLLS reset event can be initiated via assertion of the RESET pin. All wakeup and reset events result in VLLS exit via a reset flow.

15.1.2.3 Non-low leakage modes

The LLWU is not active in all non- LLS and VLLS modes where detection and control logic are in a static state. The LLWU registers are accessible in non-LLS and VLLS modes and are available for configuring and reading status when bus transactions are possible. When the reset pin filter is enabled, filter operation begins immediately so that if LLS or VLLS modes are entered while the the filter logic has seen an active edge on the RESET pin and is currently sensing for minimum assertion duration, there is no restart of pin filtering as RESET filtering transitions from a non-low leakage filter operation (implemented external to LLWU) to the RESET pin filter circuit implemented in the LLWU.

15.1.2.4 Debug mode

In debug mode, when LLS/VLLS modes are entered, the chip enters fully functional VLLS and LLS modes and no debug logic is working; on exit from LLS/VLLS, the LLWU becomes inactive and the debug logic becomes active again.

15.1.3 Block diagram

The following figure is the block diagram for the LLWU module. Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 337

(LLWU_M7IF) Module0 interrupt flag (LLWU_M0IF) WUME7 WUME0 LLWU_MWUF7 occurred LLWU_MWUF0 occurred Internal module sources LLWU controller External pin sources exit low leakge mode (LLS or VLLS) interrupt flow reset flow ACKISO reset occurred FLTRLPO RESET LLWU_P0 LLWU_P15 WUPE15 WUPE0 LPO FLTEP LLWU_P0-LLWU_P15 wakeup occurred Pin filter Interrupt module flag detect Interrupt module flag detect Reset filter Edge detect Edge detect LLS/VLLS entered Module6 interrupt flag (LLWU_M6IF) WUME6 LLWU_MWUF6 occurredInterrupt module flag detect (System Error) Figure 15-1. LLWU block diagram

15.2 LLWU Signal Descriptions

The signal properties of LLWU are shown in the following table. The external wakeup input pins can be enabled to detect either rising edge, falling edge, or on any change. Table 15-1. LLWU Signal Descriptions Signal Description I/O LLWU_Pn Wakeup inputs (n = 0-15) I LLWU Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 338 Freescale Semiconductor, Inc.

15.3 Memory map/register definition

The LLWU includes the following registers:

• Five 8-bit wakeup source enable registers
• Enable external pin input sources
• Enable internal peripheral sources
• Three 8-bit wakeup flag registers
• Indication of wakeup up source that caused exit from LLS or VLLS includes external pin or internal module interrupt
• One 8-bit status and control register
• Digital filter enable for external pin detected and reset
• Low leakage reset pin enable
• Acknowledge bit to allow certain peripherals and pads to release their held low leakage state LLWU memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4007_C000 LLWU Pin Enable 1 Register (LLWU_PE1) 8 R/W 00h 15.3.1/339 4007_C001 LLWU Pin Enable 2 Register (LLWU_PE2) 8 R/W 00h 15.3.2/340 4007_C002 LLWU Pin Enable 3 Register (LLWU_PE3) 8 R/W 00h 15.3.3/342 4007_C003 LLWU Pin Enable 4 Register (LLWU_PE4) 8 R/W 00h 15.3.4/343 4007_C004 LLWU Module Enable Register (LLWU_ME) 8 R/W 00h 15.3.5/344 4007_C005 LLWU Flag 1 Register (LLWU_F1) 8 R/W 00h 15.3.6/345 4007_C006 LLWU Flag 2 Register (LLWU_F2) 8 R/W 00h 15.3.7/347 4007_C007 LLWU Flag 3 Register (LLWU_F3) 8 R/W 00h 15.3.8/349 4007_C008 LLWU Control and Status Register (LLWU_CS) 8 R/W 04h 15.3.9/350

15.3.1 LLWU Pin Enable 1 Register (LLWU_PE1)

LLWU_PE1 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P3-LLWU_P0. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 339

Address: LLWU_PE1 is 4007_C000h base + 0h offset = 4007_C000h Bit 7 6 5 4 3 2 1 0 Read WUPE3 WUPE2 WUPE1 WUPE0 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE1 field descriptions Field Description 7–6 WUPE3 Wakeup Pin Enable for LLWU_P3 Enables and configures the edge detection for the wakeup pin.

00 External input pin disabled as wakeup input

01 External input pin enabled with rising edge detection

10 External input pin enabled with falling edge detection

11 External input pin enabled with any change detection

5–4 WUPE2 Wakeup Pin Enable for LLWU_P2 Enables and configures the edge detection for the wakeup pin. 3–2 WUPE1 Wakeup Pin Enable for LLWU_P1 Enables and configures the edge detection for the wakeup pin. 1–0 WUPE0 Wakeup Pin Enable for LLWU_P0 Enables and configures the edge detection for the wakeup pin.

15.3.2 LLWU Pin Enable 2 Register (LLWU_PE2)

LLWU_PE2 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P7-LLWU_P4. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 340 Freescale Semiconductor, Inc.

This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_PE2 is 4007_C000h base + 1h offset = 4007_C001h Bit 7 6 5 4 3 2 1 0 Read WUPE7 WUPE6 WUPE5 WUPE4 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE2 field descriptions Field Description 7–6 WUPE7 Wakeup Pin Enable for LLWU_P7 Enables and configures the edge detection for the wakeup pin. 5–4 WUPE6 Wakeup Pin Enable for LLWU_P6 Enables and configures the edge detection for the wakeup pin. 3–2 WUPE5 Wakeup Pin Enable for LLWU_P5 Enables and configures the edge detection for the wakeup pin. 1–0 WUPE4 Wakeup Pin Enable for LLWU_P4 Enables and configures the edge detection for the wakeup pin. Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 341

15.3.3 LLWU Pin Enable 3 Register (LLWU_PE3)

LLWU_PE3 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P11-LLWU_P8. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_PE3 is 4007_C000h base + 2h offset = 4007_C002h Bit 7 6 5 4 3 2 1 0 Read WUPE11 WUPE10 WUPE9 WUPE8 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE3 field descriptions Field Description 7–6 WUPE11 Wakeup Pin Enable for LLWU_P11 Enables and configures the edge detection for the wakeup pin. 5–4 WUPE10 Wakeup Pin Enable for LLWU_P10 Enables and configures the edge detection for the wakeup pin. 3–2 WUPE9 Wakeup Pin Enable for LLWU_P9 Enables and configures the edge detection for the wakeup pin. 1–0 WUPE8 Wakeup Pin Enable for LLWU_P8 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 342 Freescale Semiconductor, Inc.

LLWU_PE3 field descriptions (continued) Field Description

15.3.4 LLWU Pin Enable 4 Register (LLWU_PE4)

LLWU_PE4 contains the bit field to enable and select the edge detect type for the external wakeup input pins LLWU_P15-LLWU_P12. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_PE4 is 4007_C000h base + 3h offset = 4007_C003h Bit 7 6 5 4 3 2 1 0 Read WUPE15 WUPE14 WUPE13 WUPE12 Write Reset 0 0 0 0 0 0 0 0 LLWU_PE4 field descriptions Field Description 7–6 WUPE15 Wakeup Pin Enable for LLWU_P15 Enables and configures the edge detection for the wakeup pin. 5–4 WUPE14 Wakeup Pin Enable for LLWU_P14 Enables and configures the edge detection for the wakeup pin. 3–2 WUPE13 Wakeup Pin Enable for LLWU_P13 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 343

LLWU_PE4 field descriptions (continued) Field Description 1–0 WUPE12 Wakeup Pin Enable for LLWU_P12 Enables and configures the edge detection for the wakeup pin.

15.3.5 LLWU Module Enable Register (LLWU_ME)

LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7-MWUF0. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_ME is 4007_C000h base + 4h offset = 4007_C004h Bit 7 6 5 4 3 2 1 0 Read WUME7 WUME6 WUME5 WUME4 WUME3 WUME2 WUME1 WUME0 Write Reset 0 0 0 0 0 0 0 0 LLWU_ME field descriptions Field Description WUME7 Wakeup Module Enable for Module 7 Enables an internal module as a wakeup source input.

0 Internal module flag not used as wakeup source

1 Internal module flag used as wakeup source

Wakeup Module Enable for Module 6 Enables an internal module as a wakeup source input. Wakeup Module Enable for Module 5 Enables an internal module as a wakeup source input. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 344 Freescale Semiconductor, Inc.

LLWU_ME field descriptions (continued) Field Description Wakeup Module Enable for Module 4 Enables an internal module as a wakeup source input. Wakeup Module Enable for Module 3 Enables an internal module as a wakeup source input. Wakeup Module Enable for Module 2 Enables an internal module as a wakeup source input. Wakeup Module Enable for Module 1 Enables an internal module as a wakeup source input. Wakeup Module Enable for Module 0 Enables an internal module as a wakeup source input.

15.3.6 LLWU Flag 1 Register (LLWU_F1)

LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this will be the source causing the CPU interrupt flow. For VLLS, this will be the source causing the MCU reset flow. The external wakeup flags are read only and clearing a flag is accomplished by a write of a one to the corresponding WUFx bit. The wakeup flag (WUFx) if set will remain set if the associated WUPEx bit is cleared. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 345

Address: LLWU_F1 is 4007_C000h base + 5h offset = 4007_C005h Bit 7 6 5 4 3 2 1 0 Read WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F1 field descriptions Field Description WUF7 Wakeup Flag for LLWU_P7 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF7.

0 LLWU_P7 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P7 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P6 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF6.

0 LLWU_P6 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P6 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P5 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF5.

0 LLWU_P5 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P5 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P4 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF4.

0 LLWU_P4 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P4 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P3 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF3.

0 LLWU_P3 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P3 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P2 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF2.

0 LLWU_P2 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P2 input was a source of wakeup from LLS or VLLS mode

Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 346 Freescale Semiconductor, Inc.

LLWU_F1 field descriptions (continued) Field Description WUF1 Wakeup Flag for LLWU_P1 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF1.

0 LLWU_P1 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P1 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P0 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF0.

0 LLWU_P0 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P0 input was a source of wakeup from LLS or VLLS mode

15.3.7 LLWU Flag 2 Register (LLWU_F2)

LLWU_F2 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this will be the source causing the CPU interrupt flow. For VLLS, this will be the source causing the MCU reset flow. The external wakeup flags are read only and clearing a flag is accomplished by a write of a one to the corresponding WUFx bit. The wakeup flag (WUFx) if set will remain set if the associated WUPEx bit is cleared. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_F2 is 4007_C000h base + 6h offset = 4007_C006h Bit 7 6 5 4 3 2 1 0 Read WUF15 WUF14 WUF13 WUF12 WUF11 WUF10 WUF9 WUF8 Write w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 LLWU_F2 field descriptions Field Description WUF15 Wakeup Flag for LLWU_P15 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF15. Table continues on the next page... Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 347

LLWU_F2 field descriptions (continued) Field Description

0 LLWU_P15 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P15 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P14 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF14.

0 LLWU_P14 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P14 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P13 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF13.

0 LLWU_P13 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P13 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P12 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF12.

0 LLWU_P12 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P12 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P11 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF11.

0 LLWU_P11 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P11 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P10 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF10.

0 LLWU_P10 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P10 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P9 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF9.

0 LLWU_P9 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P9 input was a source of wakeup from LLS or VLLS mode

Wakeup Flag for LLWU_P8 Indicates that an enabled external wakeup pin was a source of exiting LLS or VLLS. To clear the flag write a one to WUF8.

0 LLWU_P8 input was not a source of wakeup from LLS or VLLS mode

1 LLWU_P8 input was a source of wakeup from LLS or VLLS mode

Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 348 Freescale Semiconductor, Inc.

15.3.8 LLWU Flag 3 Register (LLWU_F3)

LLWU_F3 contains the wakeup flags indicating which internal wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this will be the source causing the CPU interrupt flow. For VLLS, this will be the source causing the MCU reset flow. For internal peripherals that are capable of running in LLS or VLLS mode, such as RTC or CMP modules, the flag from the associated peripheral is accessible as the MWUFx bit. Clearing of the flag will need to be done in the peripheral instead of writing a one to the MWUFx bit. NOTE This register is unaffected by wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Address: LLWU_F3 is 4007_C000h base + 7h offset = 4007_C007h Bit 7 6 5 4 3 2 1 0 Read MWUF7 MWUF6 MWUF5 MWUF4 MWUF3 MWUF2 MWUF1 MWUF0 Write w1c Reset 0 0 0 0 0 0 0 0 LLWU_F3 field descriptions Field Description MWUF7 Wakeup flag for module 7 (Error Detect) Indicates that an unexpected source of wakeup was active when LLS or VLLS was entered. An immediate wakeup event was triggered and the source of the wakeup event is not known. Error handling routines should treat this source as an unknown wakeup. To clear the flag write a one to MWUF7.

0 Module 7 (Error Detect) input was not a source of wakeup from LLS or VLLS mode

1 Module 7 (Error Detect) input was a source of wakeup from LLS or VLLS mode

Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.

0 Module 6 input was not a source of wakeup from LLS or VLLS mode

1 Module 6 input was a source of wakeup from LLS or VLLS mode

Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.

0 Module 5 input was not a source of wakeup from LLS or VLLS mode

1 Module 5 input was a source of wakeup from LLS or VLLS mode

Table continues on the next page... Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 349

LLWU_F3 field descriptions (continued) Field Description MWUF4 Wakeup flag for module 4 Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.

0 Module 4 input was not a source of wakeup from LLS or VLLS mode

1 Module 4 input was a source of wakeup from LLS or VLLS mode

Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.

0 Module 3 input was not a source of wakeup from LLS or VLLS mode

1 Module 3 input was a source of wakeup from LLS or VLLS mode

Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.

0 Module 2 input was not a source of wakeup from LLS or VLLS mode

1 Module 2 input was a source of wakeup from LLS or VLLS mode

Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.

0 Module 1 input was not a source of wakeup from LLS or VLLS mode

1 Module 1 input was a source of wakeup from LLS or VLLS mode

Indicates that an enabled internal peripheral was a source of exiting LLS or VLLS. To clear the flag follow the internal peripheral flag clearing mechanism.

0 Module 0 input was not a source of wakeup from LLS or VLLS mode

1 Module 0 input was a source of wakeup from LLS or VLLS mode

15.3.9 LLWU Control and Status Register (LLWU_CS)

LLWU_CS is a status and control register that is used to enable/disable the digital filter for the external pin detect and RESET pin. NOTE ACKISO is set following wakeup from VLLS modes. FLTEP and FLTR are unaffected following wakeup from low leakage modes (exit from LLS via RESET or any exit from VLLS). Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 350 Freescale Semiconductor, Inc.

Address: LLWU_CS is 4007_C000h base + 8h offset = 4007_C008h Bit 7 6 5 4 3 2 1 0 Read ACKISO 0 FLTEP FLTR Write w1c 1 Reset 0 0 0 0 0 1 0 0 LLWU_CS field descriptions Field Description ACKISO Acknowledge Isolation Reading this bit indicates whether certain peripherals and the I/O pads are in a latched state as a result of having been in a VLLS mode. Writing one to this bit when it is set releases the I/O pads and certain peripherals to their normal run mode state.

0 Peripherals and I/O pads are in normal run state

1 Certain peripherals and I/O pads are in an isolated and latched state

6–3 Reserved This read-only field is reserved and always has the value zero. Reserved This field is reserved. FLTEP Digital Filter on External Pin Enables the digital filter for the external pin detect.

0 Filter not enabled

1 Filter enabled

Digital Filter on RESET Pin Enables the digital filter for the RESET pin during LLS and VLLS modes.

15.4 Functional description

This on-chip peripheral module is called a low leakage wake up (LLWU) module because it allows internal peripherals and external input pins to be sources of wakeup from low leakage modes. It is only operational in LLS and VLLS modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup. Choices are falling, rising or either edge (any change). When an external pin is enabled as a wakeup source the pin must be configured as an input pin. Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 351

The LLWU implements an optional 3-cycle glitch filter, based on the LPO clock, such that a detected external pin is required to stay asserted until the enabled glitch filter times out. There is also 2 additional cycles of latency due to synchronization that results in a total of 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset event when the filter function is enabled. The wakeup detect glitch filter is implemented on the "OR" of external pin inputs of all enabled external pins. There is separate reset glitch filter implemented on the RESET pin. There is no glitch filtering on the internal modules. NOTE The wakeup glitch filter should not be enabled if any of the external pin detect edge types is set for either edge. Enabling the wakeup glitch filter and selecting either edge detect on any pin results in unpredictable operation. For internal module wakeup operation, the WUMEx bit enables the respective module as a wakeup source.

15.4.1 LLS mode

While in LLS, the MCU is in a state retention mode where all registers and memory retains its contents. The I/O pins are held in their input or output state. Upon wakeup, the power management control (PMC) is re-enabled, goes through a power up sequence to full regulation and releases the logic from state retention mode. The I/O states are released. Wakeup events triggered from either an external pin input or an internal module input result in a CPU interrupt flow to begin user code execution. An LLS reset event due to RESET pin assertion causes an exit via a system reset. State retention data is lost, the I/O states return to their reset state, and the ACKISO bit is not set. The MC_SRS[WAKEUP] and MC_SRS[PIN] bits are set and the system executes a reset flow before CPU operation begins with a reset vector fetch.

15.4.2 VLLS modes

While in VLLS, much of the internal digital logic is powered down. The I/O pins are held in their input or output state. Refer to the device's Power Management chapter for powered and un-powered modules in VLLSx modes. After wakeup or reset, the PMC is re-enabled and performs a power-up sequence to full regulation. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 352 Freescale Semiconductor, Inc.

In the case of a wakeup due to external pin or internal module wakeup, the I/O states are held until software clears the ACKISO bit (by writing a 1 to it). Recovery is always via a system reset flow and the MC_SRS[WAKEUP] is set indicating the low leakage mode was active prior to the last system reset flow. An VLLS reset event due to RESET pin assertion causes an exit via a system reset. State retention data is lost, the I/O states return to their reset state, and the ACKISO bit is not set. The MC_SRS[WAKEUP] and MC_SRS[PIN] bits are set and the system executes a reset flow before CPU operation begins with a reset vector fetch.

15.4.3 Initialization

Flags associated with external input pins (WUFx) are cleared upon entry into LLS or VLLS modes. For an enabled peripheral wakeup input, the peripheral flag should be cleared by the user before entering LLS or VLLS to avoid an immediate exit from LLS or VLLS.

15.4.4 Low power mode recovery

Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU inputs" in the LLWU configuration section for a list of the sources. The wake-up flow from VLLS1,2 and 3 is through reset. The wakeup bit in the SRS registers in the Mode Controller is set indicating that the chip is recovering from a low power mode. Code execution begins; however, the I/O pins are held in their pre-low- power mode entry states, and the oscillator is disabled (even if EREFSTEN had been set before entering VLLSx). Software must clear this hold by writing a 1 to the ACKISO bit in the Control and Status register in the LLWU module. NOTE To avoid unwanted transitions on the pins, software must re- initialize the I/O pins to their pre-low-power mode entry states before releasing the hold. The oscillator cannot be re-enabled before the ACKISO bit is cleared and must be reconfigured after the hold is released. Chapter 15 Low-leakage wake-up unit (LLWU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 353

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 354 Freescale Semiconductor, Inc.

Miscellaneous Control Module (MCM)

16.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions.

16.1.1 Features

The MCM includes these distinctive features:

• Program-visible information on the platform configuration and revision
• Control and counting logic for ETB almost full

16.2 Memory Map/Register Descriptions

The memory map and register descriptions below describe the registers using byte addresses. MCM memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page E008_0008 Crossbar switch (AXBS) slave configuration (MCM_PLASC) 16 R 001Fh 16.2.1/356 Table continues on the next page... K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 355

MCM memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page E008_000A Crossbar switch (AXBS) master configuration (MCM_PLAMC) 16 R 003Fh 16.2.2/356 E008_000C SRAM arbitration and protection (MCM_SRAMAP) 32 R/W 0000_0000h 16.2.3/357 E008_0010 Interrupt status register (MCM_ISR) 32 R 0000_0000h 16.2.4/358 E008_0014 ETB counter control register (MCM_ETBCC) 32 R/W 0000_0000h 16.2.5/359 E008_0018 ETB reload register (MCM_ETBRL) 32 R/W 0000_0000h 16.2.6/360 E008_001C ETB counter value register (MCM_ETBCNT) 32 R 0000_0000h 16.2.7/361

16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)

The PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch. Address: MCM_PLASC is E008_0000h base + 8h offset = E008_0008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 ASC Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 MCM_PLASC field descriptions Field Description 15–8 Reserved This read-only field is reserved and always has the value zero. 7–0 ASC Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave input port.

0 A bus slave connection to AXBS input port n is absent

1 A bus slave connection to AXBS input port n is present

16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)

The PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: MCM_PLAMC is E008_0000h base + Ah offset = E008_000Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 AMC Write Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Memory Map/Register Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 356 Freescale Semiconductor, Inc.

MCM_PLAMC field descriptions Field Description 15–8 Reserved This read-only field is reserved and always has the value zero. 7–0 AMC Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.

0 A bus master connection to AXBS input port n is absent

1 A bus master connection to AXBS input port n is present

16.2.3 SRAM arbitration and protection (MCM_SRAMAP)

The SRAMAP register defines the arbitration and protection schemes for the two SRAM arrays. NOTE Bits 23-0 are undefined after reset. Address: MCM_SRAMAP is E008_0000h base + Ch offset = E008_000Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 SRAMLWP SRAMLAP SRAMUWP SRAMUAP Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Reserved Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_SRAMAP field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. SRAMLWP SRAM_L write protect When this bit is set, writes to SRAM_L array generates a bus error. 29–28 SRAMLAP SRAM_L arbitration priority Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_L array.

00 Round robin

Table continues on the next page... Chapter 16 Miscellaneous Control Module (MCM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 357

MCM_SRAMAP field descriptions (continued) Field Description

01 Special round robin (favors SRAM backoor accesses over the processor)

10 Fixed priority. Processor has highest, backdoor has lowest 11 Fixed priority. Backdoor has highest, processor has lowest Reserved This read-only field is reserved and always has the value zero. SRAMUWP SRAM_U write protect When this bit is set, writes to SRAM_U array generates a bus error. 25–24 SRAMUAP SRAM_U arbitration priority Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the SRAM_U array. 10 Fixed priority. Processor has highest, backdoor has lowest 11 Fixed priority. Backdoor has highest, processor has lowest 23–9 Reserved This field is reserved. 8–0 Reserved This field is reserved.

16.2.4 Interrupt status register (MCM_ISR)

Address: MCM_ISR is E008_0000h base + 10h offset = E008_0010h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 NMI IRQ 0 W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ISR field descriptions Field Description 31–4 Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Memory Map/Register Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 358 Freescale Semiconductor, Inc.

MCM_ISR field descriptions (continued) Field Description NMI Non-maskable interrupt pending If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.

0 No pending NMI

1 Due to the ETB counter expiring, an NMI is pending

If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.

0 No pending interrupt

1 Due to the ETB counter expiring, a normal interrupt is pending

This read-only field is reserved and always has the value zero.

16.2.5 ETB counter control register (MCM_ETBCC)

Address: MCM_ETBCC is E008_0000h base + 14h offset = E008_0014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 ITDIS ETDIS RLRQ RSPT CNTENW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ETBCC field descriptions Field Description 31–6 Reserved This read-only field is reserved and always has the value zero. ITDIS ITM-to-TPIU disable Disables the trace path from ITM to TPIU

0 ITM-to-TPIU trace path enabled

1 ITM-to-TPIU trace path disabled

Disables the trace path from ETM to TPIU

0 ETM-to-TPIU trace path enabled

1 ETM-to-TPIU trace path disabled

Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI interrupts were enabled and an NMI or IRQ interrupt was generated on counter expiration, setting this bit clears the pending NMI or IRQ interrupt request. Table continues on the next page... Chapter 16 Miscellaneous Control Module (MCM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 359

MCM_ETBCC field descriptions (continued) Field Description If debug halt was enabled and a debug halt request was asserted on counter expiration, setting this bit clears the debug halt request.

0 No effect

1 Clears pending debug halt, NMI, or IRQ interrupt requests

2–1 RSPT Response type

00 No response when the ETB count expires

01 Generate a normal interrupt when the ETB count expires

10 Generate an NMI when the ETB count expires

11 Generate a debug halt when the ETB count expires

Enables the ETB counter.

0 ETB counter disabled

1 ETB counter enabled

16.2.6 ETB reload register (MCM_ETBRL)

Address: MCM_ETBRL is E008_0000h base + 18h offset = E008_0018h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 RELOAD W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ETBRL field descriptions Field Description 31–11 Reserved This read-only field is reserved and always has the value zero. 10–0 RELOAD Byte count reload value Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4 value to this field results in an bus error Memory Map/Register Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 360 Freescale Semiconductor, Inc.

16.2.7 ETB counter value register (MCM_ETBCNT)

Address: MCM_ETBCNT is E008_0000h base + 1Ch offset = E008_001Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 COUNTER W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MCM_ETBCNT field descriptions Field Description 31–11 Reserved This read-only field is reserved and always has the value zero. 10–0 COUNTER Byte count counter value Indicates the current 0-mod-4 value of the counter.

16.3 Functional Description

This section describes the functional description of MCM module.

16.3.1 Interrupts

The MCM generates two interrupt requests:

• Non-maskable interrupt
• Normal interrupt

16.3.1.1 Non-maskable interrupt

The MCM's non-maskable interrupt (NMI) is generated, if:

• MCM_ISCR[ETBN] is set, which is caused by
• The ETB counter is enabled (MCM_ETBCC[CNTEN] = 1),
• The ETB count expires, and
• The response to counter expiration is an NMI (MCM_ETBCC[RSPT] = 10) Chapter 16 Miscellaneous Control Module (MCM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 361

16.3.1.2 Normal interrupt

The MCM's normal interrupt is generated if any of the following are true:

• MCM_ISCR[ETBI] is set, which is caused by
• The ETB counter is enabled (MCM_ETBCC[CNTEN] = 1),
• The ETB count expires, and
• The response to counter expiration is a normal interrupt (MCM_ETBCC[RSPT] = 01) Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 362 Freescale Semiconductor, Inc.

Crossbar Switch (AXBS)

17.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure. This structure allows all bus masters to access different bus slaves simultaneously, while providing arbitration among the bus masters when they access the same slave. A variety of bus arbitration methods and attributes may be programmed on a slave by slave basis.

17.1.1 Features

The crossbar switch includes these distinctive features:

• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• Slave arbitration attributes configured on a slave by slave basis
• 32-bit width and support for byte, 2-byte, 4-byte, and 16-byte burst transfers
• Operation at a 1-to-1 clock frequency with the bus masters
• Low-Power Park mode support K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 363

17.2 Memory Map / Register Definition

Each slave port of the crossbar switch contains configuration registers. Read- and write- transfers require two bus clock cycles. The registers can be read from and written to only in supervisor mode. Additionally, these registers can be read from or written to only by 32-bit accesses. A bus error response is returned if an unimplemented location is accessed within the crossbar switch. The slave registers also feature a bit that, when set, prevents the registers from being written. The registers remain readable, but future write attempts have no effect on the registers and are terminated with a bus error response to the master initiating the write. The core, for example, takes a bus error interrupt. NOTE This section shows the registers for all eight master and slave ports. If a master or slave is not used on this particular device, then unexpected results occur when writing to its registers. See the chip configuration details for the exact master/slave assignments for your device. AXBS memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_4000 Priority Registers Slave (AXBS_PRS0) 32 R/W 7654_3210h 17.2.1/365 4000_4010 Control Register (AXBS_CRS0) 32 R/W 0000_0000h 17.2.2/368 4000_4100 Priority Registers Slave (AXBS_PRS1) 32 R/W 7654_3210h 17.2.1/365 4000_4110 Control Register (AXBS_CRS1) 32 R/W 0000_0000h 17.2.2/368 4000_4200 Priority Registers Slave (AXBS_PRS2) 32 R/W 7654_3210h 17.2.1/365 4000_4210 Control Register (AXBS_CRS2) 32 R/W 0000_0000h 17.2.2/368 4000_4300 Priority Registers Slave (AXBS_PRS3) 32 R/W 7654_3210h 17.2.1/365 4000_4310 Control Register (AXBS_CRS3) 32 R/W 0000_0000h 17.2.2/368 4000_4400 Priority Registers Slave (AXBS_PRS4) 32 R/W 7654_3210h 17.2.1/365 4000_4410 Control Register (AXBS_CRS4) 32 R/W 0000_0000h 17.2.2/368 4000_4500 Priority Registers Slave (AXBS_PRS5) 32 R/W 7654_3210h 17.2.1/365 4000_4510 Control Register (AXBS_CRS5) 32 R/W 0000_0000h 17.2.2/368 Table continues on the next page... Memory Map / Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 364 Freescale Semiconductor, Inc.

AXBS memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_4600 Priority Registers Slave (AXBS_PRS6) 32 R/W 7654_3210h 17.2.1/365 4000_4610 Control Register (AXBS_CRS6) 32 R/W 0000_0000h 17.2.2/368 4000_4700 Priority Registers Slave (AXBS_PRS7) 32 R/W 7654_3210h 17.2.1/365 4000_4710 Control Register (AXBS_CRS7) 32 R/W 0000_0000h 17.2.2/368 4000_4800 Master General Purpose Control Register (AXBS_MGPCR0) 32 R/W 0000_0000h 17.2.3/370 4000_4900 Master General Purpose Control Register (AXBS_MGPCR1) 32 R/W 0000_0000h 17.2.3/370 4000_4A00 Master General Purpose Control Register (AXBS_MGPCR2) 32 R/W 0000_0000h 17.2.3/370 4000_4B00 Master General Purpose Control Register (AXBS_MGPCR3) 32 R/W 0000_0000h 17.2.3/370 4000_4C00 Master General Purpose Control Register (AXBS_MGPCR4) 32 R/W 0000_0000h 17.2.3/370 4000_4D00 Master General Purpose Control Register (AXBS_MGPCR5) 32 R/W 0000_0000h 17.2.3/370 4000_4E00 Master General Purpose Control Register (AXBS_MGPCR6) 32 R/W 0000_0000h 17.2.3/370 4000_4F00 Master General Purpose Control Register (AXBS_MGPCR7) 32 R/W 0000_0000h 17.2.3/370

17.2.1 Priority Registers Slave (AXBS_PRSn)

The priority registers (PRSn) set the priority of each master port on a per slave port basis and reside in each slave port. The priority register can be accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn register can only be read; attempts to write to it have no effect on PRSn and result in a bus-error response to the master initiating the write. No two available master ports may be programmed with the same priority level. Attempts to program two or more masters with the same priority level result in a bus-error response and the PRSn is not updated. NOTE The possible values for the PRSn fields depend on the number of masters available on the device. See the device's Chip Configuration details for the number of masters supported. Chapter 17 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 365

• If the device contains less than five masters, values 000– 011 are valid and writing other values results in an error.
• If the device contains n masters where n ≥ 5, values 0 to n-1 are valid and writing other values results in an error. Addresses: AXBS_PRS0 is 4000_4000h base + 0h offset = 4000_4000h AXBS_PRS1 is 4000_4000h base + 100h offset = 4000_4100h AXBS_PRS2 is 4000_4000h base + 200h offset = 4000_4200h AXBS_PRS3 is 4000_4000h base + 300h offset = 4000_4300h AXBS_PRS4 is 4000_4000h base + 400h offset = 4000_4400h AXBS_PRS5 is 4000_4000h base + 500h offset = 4000_4500h AXBS_PRS6 is 4000_4000h base + 600h offset = 4000_4600h AXBS_PRS7 is 4000_4000h base + 700h offset = 4000_4700h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 W Reset 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 AXBS_PRSn field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. 30–28 Master 7 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. Reserved This read-only field is reserved and always has the value zero. 26–24 Master 6 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Memory Map / Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 366 Freescale Semiconductor, Inc.

AXBS_PRSn field descriptions (continued) Field Description 22–20 Master 5 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. Reserved This read-only field is reserved and always has the value zero. 18–16 Master 4 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. Reserved This read-only field is reserved and always has the value zero. 14–12 Master 3 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. Reserved This read-only field is reserved and always has the value zero. 10–8 Master 2 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. Table continues on the next page... Chapter 17 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 367

AXBS_PRSn field descriptions (continued) Field Description Reserved This read-only field is reserved and always has the value zero. 6–4 Master 1 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port. Reserved This read-only field is reserved and always has the value zero. 2–0 Master 0 priority. Sets the arbitration priority for this port on the associated slave port. 000 This master has level 1, or highest, priority when accessing the slave port. 001 This master has level 2 priority when accessing the slave port. 010 This master has level 3 priority when accessing the slave port. 011 This master has level 4 priority when accessing the slave port. 100 This master has level 5 priority when accessing the slave port. 101 This master has level 6 priority when accessing the slave port. 110 This master has level 7 priority when accessing the slave port. 111 This master has level 8, or lowest, priority when accessing the slave port.

17.2.2 Control Register (AXBS_CRSn)

These registers control several features of each slave port and must be accessed using 32- bit accesses. After CRSn[RO] is set, the CRSn can only be read; attempts to write to it have no effect and result in an error response. Addresses: AXBS_CRS0 is 4000_4000h base + 10h offset = 4000_4010h AXBS_CRS1 is 4000_4000h base + 110h offset = 4000_4110h AXBS_CRS2 is 4000_4000h base + 210h offset = 4000_4210h AXBS_CRS3 is 4000_4000h base + 310h offset = 4000_4310h AXBS_CRS4 is 4000_4000h base + 410h offset = 4000_4410h AXBS_CRS5 is 4000_4000h base + 510h offset = 4000_4510h AXBS_CRS6 is 4000_4000h base + 610h offset = 4000_4610h AXBS_CRS7 is 4000_4000h base + 710h offset = 4000_4710h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RO HLP ARB PCTL PARK W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Memory Map / Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 368 Freescale Semiconductor, Inc.

AXBS_CRSn field descriptions Field Description RO Read only Forces the slave port’s CSRn and PRSn registers to be read-only. After set, only a hardware reset clears it.

0 The slave port’s registers are writeable

1 The slave port’s registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. HLP Halt low priority Sets the initial arbitration priority for low power mode requests. Setting this bit will not effect the request for low power mode from attaining highest priority once it has control of the slave ports.

0 The low power mode request has the highest priority for arbitration on this slave port

1 The low power mode request has the lowest initial priority for arbitration on this slave port

29–10 Reserved This read-only field is reserved and always has the value zero. 9–8 ARB Arbitration mode Selects the arbitration policy for the slave port.

00 Fixed priority

01 Round-robin, or rotating, priority

7–6 Reserved This read-only field is reserved and always has the value zero. 5–4 PCTL Parking control Determines the slave port’s parking control. The low-power park feature results in an overall power savings if the slave port is not saturated. However, this forces an extra latency clock when any master tries to access the slave port while not in use because it is not parked on any master.

00 When no master makes a request, the arbiter parks the slave port on the master port defined by the

01 When no master makes a request, the arbiter parks the slave port on the last master to be in control

10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all

outputs to a constant safe state This read-only field is reserved and always has the value zero. 2–0 PARK Park Determines which master port the current slave port parks on when no masters are actively making requests and the PCTL bits are cleared. NOTE: Only select master ports that are actually present on the device. If not, undefined behavior may occur.

000 Park on master port M0

Table continues on the next page... Chapter 17 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 369

AXBS_CRSn field descriptions (continued) Field Description

001 Park on master port M1

010 Park on master port M2

011 Park on master port M3

100 Park on master port M4

101 Park on master port M5

110 Reserved

111 Reserved

17.2.3 Master General Purpose Control Register (AXBS_MGPCRn)

The MGPCR controls only whether the master’s undefined length burst accesses are allowed to complete uninterrupted or whether they can be broken by requests from higher priority masters. The MGPCR can only be accessed in Supervisor mode with 32-bit accesses. Addresses: AXBS_MGPCR0 is 4000_4000h base + 800h offset = 4000_4800h AXBS_MGPCR1 is 4000_4000h base + 900h offset = 4000_4900h AXBS_MGPCR2 is 4000_4000h base + A00h offset = 4000_4A00h AXBS_MGPCR3 is 4000_4000h base + B00h offset = 4000_4B00h AXBS_MGPCR4 is 4000_4000h base + C00h offset = 4000_4C00h AXBS_MGPCR5 is 4000_4000h base + D00h offset = 4000_4D00h AXBS_MGPCR6 is 4000_4000h base + E00h offset = 4000_4E00h AXBS_MGPCR7 is 4000_4000h base + F00h offset = 4000_4F00h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 AULB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AXBS_MGPCRn field descriptions Field Description 31–3 Reserved This read-only field is reserved and always has the value zero. 2–0 AULB Arbitrates on undefined length bursts Determines whether, and when, the crossbar switch arbitrates away the slave port the master owns when the master is performing undefined length burst accesses.

000 No arbitration is allowed during an undefined length burst

001 Arbitration is allowed at any time during an undefined length burst

010 Arbitration is allowed after four beats of an undefined length burst

011 Arbitration is allowed after eight beats of an undefined length burst

100 Arbitration is allowed after 16 beats of an undefined length burst

Table continues on the next page... Memory Map / Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 370 Freescale Semiconductor, Inc.

AXBS_MGPCRn field descriptions (continued) Field Description

101 Reserved

17.3 Functional Description

17.3.1 General operation

When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. It is possible to make single-clock, or zero wait state, accesses through the crossbar. If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request. The latency in servicing the request depends on each master's priority level and the responding peripheral's access time. Because the crossbar switch appears to be just another slave to the master device, the master device has no knowledge of whether it actually owns the slave port it is targeting. While the master does not have control of the slave port it is targeting, it simply waits. A master is given control of the targeted slave port only after a previous access to a different slave port completes, regardless of its priority on the newly targeted slave port. This prevents deadlock from occurring when:

• A higher priority master has:
• An outstanding request to one slave port that has a long response time and
• A pending access to a different slave port, and
• A lower priority master is also making a request to the same slave port as the pending access of the higher priority master. After the master has control of the slave port it is targeting, the master remains in control of that slave port until it gives up the slave port by running an IDLE cycle or by leaving that slave port for its next access. The master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is running a fixed-length burst transfer it retains control of the slave port until that transfer completes. Based on MGPCR[AULB], the master either retains control of the slave port when doing undefined length incrementing burst transfers or loses the bus to a higher priority master. Chapter 17 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 371

The crossbar terminates all master IDLE transfers, as opposed to allowing the termination to come from one of the slave busses. Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. When a slave bus is being idled by the crossbar, it can park the slave port on the master port indicated by CRSn[PARK]. This is done to save the initial clock of arbitration delay that otherwise would be seen if the master had to arbitrate to gain control of the slave port. The slave port can also be put into Low Power Park mode to save power, by using CRSn[PCTL].

17.3.2 Register coherency

Because the content of the registers has a real-time effect on the operation of the crossbar, it is important to understand that any register modifications take effect as soon as the register is written. The values of the registers do not track with slave-port-related master accesses, but instead track only with slave accesses. The MGPCRx[AULB] bits are the exception to this rule. The update of these bits is only recognized when the master on that master port runs an IDLE cycle, even though the slave bus cycle to write them will have already terminated successfully. If the MGPCRx[AULB] bits are written between two burst accesses, the new AULB encodings do not take effect until an IDLE cycle is initiated by the master on that master port.

17.3.3 Arbitration

The crossbar switch supports two arbitration schemes:

• A fixed-priority comparison algorithm
• A round-robin fairness algorithm The arbitration scheme is independently programmable for each slave port.

17.3.3.1 Arbitration during undefined length bursts

Arbitration points during an undefined length burst are defined by the current master's MGPCR[AULB] field setting. When a defined length is imposed on the burst via the AULB bits, the undefined length burst is treated as a single or series of single back-to- back fixed-length burst accesses. The following figure illustrates an example: Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 372 Freescale Semiconductor, Inc.

transfer 1 2 3 4 5 6 7 8 9 10 11 12 1 beat 1 beat 12 beat burst No arbitration Arbitration allowed No arbitration No arbitration MGPCR[AULB] Figure 17-28. Undefined length burst example In this example, a master runs an undefined length burst and the MGPCR[AULB] bits indicate arbitration occurs after the fourth beat of the burst. The master runs two sequential beats and then starts what will be a 12-beat undefined length burst access to a new address within the same slave port region as the previous access. The crossbar does not allow an arbitration point until the fourth overall access, or the second beat of the second burst. At that point, all remaining accesses are open for arbitration until the master loses control of the slave port. Assume the master loses control of the slave port after the fifth beat of the second burst. After the master regains control of the slave port no arbitration point is available until after the master has run four more beats of its burst. After the fourth beat of the now continued burst, or the ninth beat of the second burst from the master's perspective, is taken, all beats of the burst are once again open for arbitration until the master loses control of the slave port. Assume the master again loses control of the slave port on the fifth beat of the third now continued burst, or the 10th beat of the second burst from the master's perspective. After the master regains control of the slave port, it is allowed to complete its final two beats of its burst without facing arbitration. Note Fixed-length burst accesses are not affected by the AULB bits. All fixed-length burst accesses lock out arbitration until the last beat of the fixed-length burst.

17.3.3.2 Fixed-priority operation

When operating in Fixed-Priority mode, each master is assigned a unique priority level in the priority registers (PRSn) . If two masters request access to a slave port, the master with the highest priority in the selected priority register gains control over the slave port. Chapter 17 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 373

When a master makes a request to a slave port, the slave port checks if the new requesting master's priority level is higher than that of the master that currently has control over the slave port, unless the slave port is in a parked state. The slave port performs an arbitration check at every clock edge to ensure that the proper master, if any, has control of the slave port. The following table describes possible scenarios based on the requesting master port: Table 17-29. How AXBS grants control of a slave port to a master When Then AXBS grants control to the requesting master Both of the following are true:

• The current master is not running a transfer.
• The new requesting master's priority level is higher than that of the current master. At the next clock edge Both of the following are true:
• The current master is running a fixed length burst transfer or a locked transfer.
• The requesting master's priority level is higher than that of the current master. At the end of the burst transfer or locked transfer The master is running an undefined length burst transfer. At the next arbitration point NOTE: Arbitration points for an undefined length burst are defined in the MGPCR for each master. The requesting master's priority level is lower than the current master. At the conclusion of one of the following cycles:
• An IDLE cycle
• A non-IDLE cycle to a location other than the current slave port

17.3.3.3 Round-robin priority operation

When operating in Round-Robin mode, each master is assigned a relative priority based on the master port number. This relative priority is compared to the master port number (ID) of the last master to perform a transfer on the slave bus. The highest priority requesting master becomes owner of the slave bus at the next transfer boundary, accounting for locked and fixed-length burst transfers. Priority is based on how far ahead the ID of the requesting master is to the ID of the last master. After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request. As an example of arbitration in Round-Robin mode, assume the crossbar is implemented with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and master 0, 4 and 5 make simultaneous requests, they are serviced in the order 4, 5, and then 0. Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 374 Freescale Semiconductor, Inc.

Parking may continue to be used in a round-robin mode, but does not affect the round- robin pointer unless the parked master actually performs a transfer. Handoff occurs to the next master in line after one cycle of arbitration. If the slave port is put into low-power park mode, the round-robin pointer is reset to point at master port 0, giving it the highest priority.

17.3.3.4 Priority assignment

Each master port needs to be assigned a unique 3-bit priority level. If an attempt is made to program multiple master ports with the same priority level within the priority registers (PRSn), the crossbar switch responds with a bus error and the registers are not updated.

17.4 Initialization/application information

No initialization is required by or for the crossbar switch. Hardware reset ensures all the register bits used by the crossbar switch are properly initialized to a valid state. Settings and priorities should be programmed to achieve maximum system performance. Chapter 17 Crossbar Switch (AXBS) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 375

Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 376 Freescale Semiconductor, Inc.

Memory Protection Unit (MPU)

18.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Memory Protection Unit (MPU) provides hardware access control for all memory references generated in the device.

18.2 Overview

The MPU concurrently monitors all system bus transactions and evaluates their appropriateness using pre-programmed region descriptors that define memory spaces and their access rights. Memory references that have sufficient access control rights are allowed to complete, while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response.

18.2.1 Block Diagram

A simplified block diagram of the MPU module is shown in the following figure. The hardware's two-dimensional connection matrix is clearly visible with the basic access evaluation macro shown as the replicated submodule block. The crossbar switch slave ports are shown on the left, the region descriptor registers in the middle, and the peripheral bus interface on the right side. The evaluation macro contains two magnitude comparators connected to the start and end address registers from each region descriptor as well as the combinational logic blocks to determine the region hit and the access protection error. For details of the access evaluation macro, see Access Evaluation Macro. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 377

Address Phase Signals Peripheral Bus MPU_EAR n MPU_EDR n Figure 18-1. MPU Block Diagram

18.2.2 Features

The MPU implements a two-dimensional hardware array of memory region descriptors and the crossbar slave ports to continuously monitor the legality of every memory reference generated by each bus master in the system. The feature set includes:

• 12 program-visible 128-bit region descriptors, accessible by four 32-bit words each
• Each region descriptor defines a modulo-32 byte space, aligned anywhere in memory
• Region sizes can vary from 32 bytes to 4 Gbytes
• Two access control permissions defined in a single descriptor word
• Masters 0–3: read, write, and execute attributes for supervisor and user accesses
• Masters 4–7: read and write attributes
• Hardware-assisted maintenance of the descriptor valid bit minimizes coherency issues Overview K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 378 Freescale Semiconductor, Inc.

• Alternate programming model view of the access control permissions word
• Priority given to granting permission over denying access for overlapping region descriptors
• Detects access protection errors if a memory reference does not hit in any memory region, or if the reference is illegal in all hit memory regions. If an access error occurs, the reference is terminated with an error response, and the MPU inhibits the bus cycle being sent to the targeted slave device.
• Error registers (per slave port) capture the last faulting address, attributes, and other information
• Global MPU enable/disable control bit

18.3 Memory Map/Register Definition

The programming model is partitioned into three groups: control/status registers, the data structure containing the region descriptors, and the alternate view of the region descriptor access control values. The programming model can only be referenced using 32-bit accesses. Attempted references using different access sizes, to undefined (reserved) addresses, or with a non- supported access type (a write to a read-only register, or a read of a write-only register) generate an error termination. The programming model can be accessed only in supervisor mode. NOTE See the chip configuration details for any chip-specific register information for this module. MPU memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D000 Control/Error Status Register (MPU_CESR) 32 R/W 0081_5101h 18.3.1/382 4000_D010 Error Address Register, Slave Port n (MPU_EAR0) 32 R Undefined 18.3.2/384 4000_D014 Error Detail Register, Slave Port n (MPU_EDR0) 32 R Undefined 18.3.3/385 4000_D018 Error Address Register, Slave Port n (MPU_EAR1) 32 R Undefined 18.3.2/384 4000_D01C Error Detail Register, Slave Port n (MPU_EDR1) 32 R Undefined 18.3.3/385 Table continues on the next page... Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 379

MPU memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D020 Error Address Register, Slave Port n (MPU_EAR2) 32 R Undefined 18.3.2/384 4000_D024 Error Detail Register, Slave Port n (MPU_EDR2) 32 R Undefined 18.3.3/385 4000_D028 Error Address Register, Slave Port n (MPU_EAR3) 32 R Undefined 18.3.2/384 4000_D02C Error Detail Register, Slave Port n (MPU_EDR3) 32 R Undefined 18.3.3/385 4000_D030 Error Address Register, Slave Port n (MPU_EAR4) 32 R Undefined 18.3.2/384 4000_D034 Error Detail Register, Slave Port n (MPU_EDR4) 32 R Undefined 18.3.3/385 4000_D400 Region Descriptor n, Word 0 (MPU_RGD0_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D404 Region Descriptor n, Word 1 (MPU_RGD0_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D408 Region Descriptor n, Word 2 (MPU_RGD0_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D40C Region Descriptor n, Word 3 (MPU_RGD0_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D410 Region Descriptor n, Word 0 (MPU_RGD1_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D414 Region Descriptor n, Word 1 (MPU_RGD1_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D418 Region Descriptor n, Word 2 (MPU_RGD1_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D41C Region Descriptor n, Word 3 (MPU_RGD1_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D420 Region Descriptor n, Word 0 (MPU_RGD2_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D424 Region Descriptor n, Word 1 (MPU_RGD2_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D428 Region Descriptor n, Word 2 (MPU_RGD2_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D42C Region Descriptor n, Word 3 (MPU_RGD2_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D430 Region Descriptor n, Word 0 (MPU_RGD3_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D434 Region Descriptor n, Word 1 (MPU_RGD3_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D438 Region Descriptor n, Word 2 (MPU_RGD3_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D43C Region Descriptor n, Word 3 (MPU_RGD3_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D440 Region Descriptor n, Word 0 (MPU_RGD4_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D444 Region Descriptor n, Word 1 (MPU_RGD4_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D448 Region Descriptor n, Word 2 (MPU_RGD4_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D44C Region Descriptor n, Word 3 (MPU_RGD4_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D450 Region Descriptor n, Word 0 (MPU_RGD5_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D454 Region Descriptor n, Word 1 (MPU_RGD5_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D458 Region Descriptor n, Word 2 (MPU_RGD5_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D45C Region Descriptor n, Word 3 (MPU_RGD5_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D460 Region Descriptor n, Word 0 (MPU_RGD6_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D464 Region Descriptor n, Word 1 (MPU_RGD6_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D468 Region Descriptor n, Word 2 (MPU_RGD6_WORD2) 32 R/W 0000_0000h 18.3.6/387 Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 380 Freescale Semiconductor, Inc.

MPU memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D46C Region Descriptor n, Word 3 (MPU_RGD6_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D470 Region Descriptor n, Word 0 (MPU_RGD7_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D474 Region Descriptor n, Word 1 (MPU_RGD7_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D478 Region Descriptor n, Word 2 (MPU_RGD7_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D47C Region Descriptor n, Word 3 (MPU_RGD7_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D480 Region Descriptor n, Word 0 (MPU_RGD8_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D484 Region Descriptor n, Word 1 (MPU_RGD8_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D488 Region Descriptor n, Word 2 (MPU_RGD8_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D48C Region Descriptor n, Word 3 (MPU_RGD8_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D490 Region Descriptor n, Word 0 (MPU_RGD9_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D494 Region Descriptor n, Word 1 (MPU_RGD9_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D498 Region Descriptor n, Word 2 (MPU_RGD9_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D49C Region Descriptor n, Word 3 (MPU_RGD9_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D4A0 Region Descriptor n, Word 0 (MPU_RGD10_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D4A4 Region Descriptor n, Word 1 (MPU_RGD10_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D4A8 Region Descriptor n, Word 2 (MPU_RGD10_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D4AC Region Descriptor n, Word 3 (MPU_RGD10_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D4B0 Region Descriptor n, Word 0 (MPU_RGD11_WORD0) 32 R/W 0000_0000h 18.3.4/386 4000_D4B4 Region Descriptor n, Word 1 (MPU_RGD11_WORD1) 32 R/W 0000_001Fh 18.3.5/387 4000_D4B8 Region Descriptor n, Word 2 (MPU_RGD11_WORD2) 32 R/W 0000_0000h 18.3.6/387 4000_D4BC Region Descriptor n, Word 3 (MPU_RGD11_WORD3) 32 R/W 0000_0000h 18.3.7/390 4000_D800 Region Descriptor Alternate Access Control n (MPU_RGDAAC0) 32 R/W 0000_0000h 18.3.8/391 4000_D804 Region Descriptor Alternate Access Control n (MPU_RGDAAC1) 32 R/W 0000_0000h 18.3.8/391 4000_D808 Region Descriptor Alternate Access Control n (MPU_RGDAAC2) 32 R/W 0000_0000h 18.3.8/391 4000_D80C Region Descriptor Alternate Access Control n (MPU_RGDAAC3) 32 R/W 0000_0000h 18.3.8/391 4000_D810 Region Descriptor Alternate Access Control n (MPU_RGDAAC4) 32 R/W 0000_0000h 18.3.8/391 4000_D814 Region Descriptor Alternate Access Control n (MPU_RGDAAC5) 32 R/W 0000_0000h 18.3.8/391 4000_D818 Region Descriptor Alternate Access Control n (MPU_RGDAAC6) 32 R/W 0000_0000h 18.3.8/391 Table continues on the next page... Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 381

MPU memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_D81C Region Descriptor Alternate Access Control n (MPU_RGDAAC7) 32 R/W 0000_0000h 18.3.8/391 4000_D820 Region Descriptor Alternate Access Control n (MPU_RGDAAC8) 32 R/W 0000_0000h 18.3.8/391 4000_D824 Region Descriptor Alternate Access Control n (MPU_RGDAAC9) 32 R/W 0000_0000h 18.3.8/391 4000_D828 Region Descriptor Alternate Access Control n (MPU_RGDAAC10) 32 R/W 0000_0000h 18.3.8/391 4000_D82C Region Descriptor Alternate Access Control n (MPU_RGDAAC11) 32 R/W 0000_0000h 18.3.8/391

18.3.1 Control/Error Status Register (MPU_CESR)

Address: MPU_CESR is 4000_D000h base + 0h offset = 4000_D000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SPERR 0 1 0 HRL NSP NRGD 0 VLDW w1c Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 MPU_CESR field descriptions Field Description 31–27 SPERR Slave port n error Indicates a captured error in EARn and EDRn. This bit is set when the hardware detects an error and records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at the exact same cycle as the write, the flag remains set. A find-first-one instruction (or equivalent) can detect the presence of a captured error. The following shows the correspondence between the bit number and slave port number:

• Bit 31 corresponds to slave port 0.
• Bit 30 corresponds to slave port 1.
• Bit 29 corresponds to slave port 2.
• Bit 28 corresponds to slave port 3.
• Bit 27 corresponds to slave port 4. 0 No error has occurred for slave port n. 1 An error has occurred for slave port n. 26–24 Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value one. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 382 Freescale Semiconductor, Inc.

MPU_CESR field descriptions (continued) Field Description 22–20 Reserved This read-only field is reserved and always has the value zero. 19–16 HRL Hardware revision level Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the functional definition of the module. 15–12 NSP Number of slave ports Specifies the number of slave ports connected to the MPU. 11–8 NRGD Number of region descriptors Indicates the number of region descriptors implemented in the MPU. 0000 8 region descriptors 0001 12 region descriptors 0010 16 region descriptors 7–1 Reserved This read-only field is reserved and always has the value zero. VLD Valid (global enable/disable for the MPU) 0 MPU is disabled. All accesses from all bus masters are allowed.

1 MPU is enabled

Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 383

18.3.2 Error Address Register, Slave Port n (MPU_EARn)

When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this read-only register and the corresponding bit in CESR[SPERR] set. Additional information about the faulting access is captured in the corresponding EDRn at the same time. This register and the corresponding EDRn contain the most recent access error; there are no hardware interlocks with CESR[SPERR], as the error registers are always loaded upon the occurrence of each protection violation. Addresses: MPU_EAR0 is 4000_D000h base + 10h offset = 4000_D010h MPU_EAR1 is 4000_D000h base + 18h offset = 4000_D018h MPU_EAR2 is 4000_D000h base + 20h offset = 4000_D020h MPU_EAR3 is 4000_D000h base + 28h offset = 4000_D028h MPU_EAR4 is 4000_D000h base + 30h offset = 4000_D030h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R EADDR W * Notes: x = Undefined at reset.• MPU_EARn field descriptions Field Description 31–0 EADDR Error address Indicates the reference address from slave port n that generated the access error Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 384 Freescale Semiconductor, Inc.

18.3.3 Error Detail Register, Slave Port n (MPU_EDRn)

When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only register and the corresponding bit in CESR[SPERR] is set. Information on the faulting address is captured in the corresponding EARn register at the same time. This register and the corresponding EARn register contain the most recent access error; there are no hardware interlocks with CESR[SPERR] as the error registers are always loaded upon the occurrence of each protection violation. Addresses: MPU_EDR0 is 4000_D000h base + 14h offset = 4000_D014h MPU_EDR1 is 4000_D000h base + 1Ch offset = 4000_D01Ch MPU_EDR2 is 4000_D000h base + 24h offset = 4000_D024h MPU_EDR3 is 4000_D000h base + 2Ch offset = 4000_D02Ch MPU_EDR4 is 4000_D000h base + 34h offset = 4000_D034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R EACD W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 EMN EATTR ERW W * Notes: x = Undefined at reset.• MPU_EDRn field descriptions Field Description 31–16 EACD Error access control detail Indicates the region descriptor with the access error. If EDRn contains a captured error and EACD is cleared, an access did not hit in any region descriptor. If only a single EACD bit is set, the protection error was caused by a single non-overlapping region descriptor. If two or more EACD bits are set, the protection error was caused by an overlapping set of region descriptors. 15–8 Reserved This read-only field is reserved and always has the value zero. 7–4 EMN Error master number Indicates the bus master that generated the access error. 3–1 EATTR Error attributes Indicates attribute information about the faulting reference. Table continues on the next page... Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 385

MPU_EDRn field descriptions (continued) Field Description NOTE: All other encodings are reserved.

000 User mode, instruction access

001 User mode, data access

010 Supervisor mode, instruction access

011 Supervisor mode, data access

Indicates the access type of the faulting reference.

0 Read

1 Write

18.3.4 Region Descriptor n, Word 0 (MPU_RGD_WORD0)

The first word of the region descriptor defines the 0-modulo-32 byte start address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). Addresses: 4000_D000h base + 400h offset + (16d × n), where n = 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SRTADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDn_WORD0 field descriptions Field Description 31–5 SRTADDR Start address Defines the most significant bits of the 0-modulo-32 byte start address of the memory region. 4–0 Reserved This read-only field is reserved and always has the value zero. Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 386 Freescale Semiconductor, Inc.

18.3.5 Region Descriptor n, Word 1 (MPU_RGD_WORD1)

The second word of the region descriptor defines the 31-modulo-32 byte end address of the memory region. Writes to this register clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). Addresses: 4000_D000h base + 404h offset + (16d × n), where n = 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ENDADDR Reserved W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 MPU_RGDn_WORD1 field descriptions Field Description 31–5 ENDADDR End address Defines the most significant bits of the 31-modulo-32 byte end address of the memory region. NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR. 4–0 Reserved This field is reserved.

18.3.6 Region Descriptor n, Word 2 (MPU_RGD_WORD2)

The third word of the region descriptor defines the access control rights of the memory region. The access control privileges depend on two broad classifications of bus masters:

• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and supervisor mode accesses.
• Bus masters 4–7 are limited to separate read and write permissions. For the privilege rights of bus masters 0–3, there are three flags associated with this function:
• Read (r) refers to accessing the referenced memory address using an operand (data) fetch
• Write (w) refers to updating the referenced memory address using a store (data) instruction
• Execute (x) refers to reading the referenced memory address using an instruction fetch Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 387

Writes to RGDn_WORD2 clear the region descriptor’s valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write to RGDAACn instead because stores to these locations do not affect the descriptor’s valid bit. Addresses: 4000_D000h base + 408h offset + (16d × n), where n = 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R M7RE M7WE M6RE M6WE M5RE M5WE M4RE M4WE Reserved M3SM M3UM Reserved M2SM [-14:1] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R M2SM [bit 0] M2UM Reserved M1SM M1UM Reserved M0SM M0UM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDn_WORD2 field descriptions Field Description M7RE Bus master 7 read enable.

0 Bus master 7 reads terminate with an access error and the read is not performed

1 Bus master 7 reads allowed

0 Bus master 7 writes terminate with an access error and the write is not performed

1 Bus master 7 writes allowed

Bus master 6 read enable.

0 Bus master 6 reads terminate with an access error and the read is not performed

1 Bus master 6 reads allowed

0 Bus master 6 writes terminate with an access error and the write is not performed

1 Bus master 6 writes allowed

Bus master 5 read enable.

0 Bus master 5 reads terminate with an access error and the read is not performed

1 Bus master 5 reads allowed

0 Bus master 5 writes terminate with an access error and the write is not performed

1 Bus master 5 writes allowed

Bus master 4 read enable. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 388 Freescale Semiconductor, Inc.

MPU_RGDn_WORD2 field descriptions (continued) Field Description

0 Bus master 4 reads terminate with an access error and the read is not performed

1 Bus master 4 reads allowed

0 Bus master 4 writes terminate with an access error and the write is not performed

1 Bus master 4 writes allowed

This field is reserved. This bit must be written with a zero. 22–21 M3SM Bus master 3 supervisor mode access control Defines the access controls for bus master 3 in supervisor mode 00 r/w/x; read, write and execute allowed 01 r/x; read and execute allowed, but no write 10 r/w; read and write allowed, but no execute

11 Same as user mode defined in M3UM

20–18 M3UM Bus master 3 user mode access control Defines the access controls for bus master 3 in user mode. M3UM consists of three independent bits, enabling read (r), write (w), and execute (x) permissions.

0 An attempted access of that mode may be terminated with an access error (if not allowed by another

descriptor) and the access not performed.

1 Allows the given access type to occur

This field is reserved. This bit must be written with a zero. 16–15 M2SM Bus master 2 supervisor mode access control See M3SM description 14–12 M2UM Bus master 2 user mode access control See M3UM description Reserved This field is reserved. This bit must be written with a zero. 10–9 M1SM Bus master 1 supervisor mode access control See M3SM description 8–6 M1UM Bus master 1 user mode access control See M3UM description Reserved This field is reserved. This bit must be written with a zero. 4–3 M0SM Bus master 0 supervisor mode access control See M3SM description 2–0 M0UM Bus master 0 user mode access control Table continues on the next page... Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 389

MPU_RGDn_WORD2 field descriptions (continued) Field Description See M3UM description

18.3.7 Region Descriptor n, Word 3 (MPU_RGD_WORD3)

The fourth word of the region descriptor contains the region descriptor’s valid bit. Addresses: 4000_D000h base + 40Ch offset + (16d × n), where n = 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 VLDW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDn_WORD3 field descriptions Field Description 31–1 Reserved This read-only field is reserved and always has the value zero. VLD Valid Signals the region descriptor is valid. Any write to RGDn_WORD0–2 clears this bit.

0 Region descriptor is invalid

1 Region descriptor is valid

Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 390 Freescale Semiconductor, Inc.

18.3.8 Region Descriptor Alternate Access Control n

(MPU_RGDAACn) Since software may adjust only the access controls within a region descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of this 32- bit entity is available. Writing to this register does not affect the descriptor’s valid bit. Addresses: 4000_D000h base + 800h offset + (4d × n), where n = 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R M7RE M7WE M6RE M6WE M5RE M5WE M4RE M4WE Reserved M3SM M3UM Reserved M2SM [-14:1] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R M2SM [bit 0] M2UM Reserved M1SM M1UM Reserved M0SM M0UM W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPU_RGDAACn field descriptions Field Description M7RE Bus master 7 read enable. Bus master 6 read enable. Bus master 5 read enable. Table continues on the next page... Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 391

MPU_RGDAACn field descriptions (continued) Field Description Bus master 4 read enable. This field is reserved. This bit must be written with a zero. 22–21 M3SM Bus master 3 supervisor mode access control Defines the access controls for bus master 3 in supervisor mode 00 r/w/x; read, write and execute allowed 01 r/x; read and execute allowed, but no write 10 r/w; read and write allowed, but no execute 20–18 M3UM Bus master 3 user mode access control Defines the access controls for bus master 3 in user mode. M3UM consists of three independent bits, enabling read (r), write (w), and execute (x) permissions. descriptor) and the access not performed. This field is reserved. This bit must be written with a zero. 16–15 M2SM Bus master 2 supervisor mode access control See M3SM description. 14–12 M2UM Bus master 2 user mode access control See M3UM description. Reserved This field is reserved. This bit must be written with a zero. 10–9 M1SM Bus master 1 supervisor mode access control See M3SM description. 8–6 M1UM Bus master 1 user mode access control See M3UM description. Reserved This field is reserved. This bit must be written with a zero. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 392 Freescale Semiconductor, Inc.

MPU_RGDAACn field descriptions (continued) Field Description 4–3 M0SM Bus master 0 supervisor mode access control See M3SM description. 2–0 M0UM Bus master 0 user mode access control See M3UM description.

18.4 Functional Description

In this section, the functional operation of the MPU is detailed, including the operation of the access evaluation macro and the handling of error-terminated bus cycles.

18.4.1 Access Evaluation Macro

The basic operation of the MPU is performed in the access evaluation macro, a hardware structure replicated in the two-dimensional connection matrix. As shown in the following figure, the access evaluation macro inputs the crossbar bus address phase signals and the contents of a region descriptor (RGDn) and performs two major functions: region hit determination and detection of an access protection violation. The following figure shows a functional block diagram. start end error ≥ ≥ RGD n MPU_EDRn Access not allowed ≥ ≤ hit_b Address (hit AND error) (no hit OR error) r,w,x Figure 18-80. MPU Access Evaluation Macro Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 393

18.4.1.1 Hit Determination

To determine if the current reference hits in the given region, two magnitude comparators are used with the region's start and end addresses. The boolean equation for this portion of the hit determination is: region_hit = ((addr[31:5] >= RGDn_Word0[SRTADDR]) & (addr[31:5] <= RGDn_Word1[ENDADDR])) & RGDn_Word3[VLD] where addr is the current reference address, RGDn_Word0[SRTADDR] and RGDn_Word1[ENDADDR] are the start and end addresses, and RGDn_Word3[VLD] is the valid bit. NOTE The MPU does not verify that ENDADDR ≥ SRTADDR.

18.4.1.2 Privilege Violation Determination

While the access evaluation macro is determining region hit, the logic is also evaluating if the current access is allowed by the permissions defined in the region descriptor. Using the master and supervisor/user mode signals, a set of effective permissions is generated from the appropriate fields in the region descriptor. The protection violation logic then evaluates the access against the effective permissions using the specification shown below. Table 18-80. Protection Violation Definition

Description

Violation?r w x Instruction fetch read — — 0 Yes, no execute permission — — 1 No, access is allowed Data read 0 — — Yes, no read permission 1 — — No, access is allowed Data write — 0 — Yes, no write permission — 1 — No, access is allowed

18.4.2 Putting It All Together and Error Terminations

For each slave port monitored, the MPU performs a reduction-AND of all the individual terms from each access evaluation macro. This expression then terminates the bus cycle with an error and reports a protection error for three conditions: Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 394 Freescale Semiconductor, Inc.

1. If the access does not hit in any region descriptor, a protection error is reported. 2. If the access hits in a single region descriptor and that region signals a protection violation, a protection error is reported. 3. If the access hits in multiple (overlapping) regions and all regions signal protection violations, a protection error is reported. As shown in the third condition, granting permission is a higher priority than denying access for overlapping regions. This approach is more flexible to system software in region descriptor assignments. For an example of the use of overlapping region descriptors, see Application Information.

18.4.3 Power Management

Disabling the MPU by clearing CESR[VLD] minimizes power dissipation. To minimize the power dissipation of an enabled MPU, invalidate unused region descriptors by clearing the associated RGDn_Word3[VLD] bits.

18.5 Initialization Information

At system startup, load the appropriate number of region descriptors, including setting RGDn_Word3[VLD]. Setting CESR[VLD] enables the module. If the system requires that all the loaded region descriptors be enabled simultaneously, first ensure that the entire MPU is disabled (CESR[VLD]=0). Note A region descriptor must be set to allow access to the MPU registers if further changes are needed.

18.6 Application Information

In an operational system, interfacing with the MPU is generally classified into the following activities: Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 395

• Creating a new memory region—Load the appropriate region descriptor into an available RGDn, using four sequential 32-bit writes. The hardware assists in the maintenance of the valid bit, so if this approach is followed, there are no coherency issues with the multi-cycle descriptor writes. (Clearing RGDn_Word3[VLD] deletes/ removes an existing memory region.)
• Altering only access privileges—To not affect the valid bit, write to the alternate version of the access control word (RGDAACn), so there are no coherency issues involved with the update. When the write completes, the memory region's access rights switch instantaneously to the new value.
• Changing a region's start and end addresses—Write a minimum of three words to the region descriptor (RGDn_Word{0,1,3}). Word 0 and 1 redefine the start and end addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most situations, all four words of the region descriptor are rewritten.
• Accessing the MPU—Allocate a region descriptor to restrict MPU access to supervisor mode from a specific master.
• Detecting an access error—The current bus cycle is terminated with an error response and EARn and EDRn capture information on the faulting reference. The error-terminated bus cycle typically initiates an error response in the originating bus master. For example, a processor core may respond with a bus error exception, while a data movement bus master may respond with an error interrupt. The processor can retrieve the captured error address and detail information simply by reading E{A,D}Rn. CESR[SPERR] signals which error registers contain captured fault data.
• Overlapping region descriptors—Applying overlapping regions often reduces the number of descriptors required for a given set of access controls. In the overlapping memory space, the protection rights of the corresponding region descriptors are logically summed together (the boolean OR operator). The following dual-core system example contains four bus masters: the two processors (CP0, CP1) and two DMA engines (DMA1, a traditional data movement engine transferring data between RAM and peripherals and DMA2, a second engine transferring data to/from the RAM only). Consider the following region descriptor assignments: Table 18-81. Overlapping Region Descriptor Example Region Description RGDn CP0 CP1 DMA1 DMA2 CP0 code 0 rwx r-- — — Flash CP1 code 1 r-- rwx — — Table continues on the next page...

Application Information

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 396 Freescale Semiconductor, Inc.

Table 18-81. Overlapping Region Descriptor Example (continued) Region Description RGDn CP0 CP1 DMA1 DMA2 CP0 data & stack 2 rw- — — — RAM CP0 → CP1 shared data 2 3 r-- r-- — — CP1 → CP0 shared data 4 CP1 data & stack 4 — rw- — — Shared DMA data 5 rw- rw- rw rw MPU 6 rw- rw- — — Peripheral spacePeripherals 7 rw- rw- rw — In this example, there are eight descriptors used to span nine regions in the three main spaces of the system memory map (flash, RAM, and peripheral space). Each region indicates the specific permissions for each of the four bus masters and this definition provides an appropriate set of shared, private and executable memory spaces. Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4. The space defined by RGD2 with no overlap is a private data and stack area that provides read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines a shared data space for passing data from CP0 to CP1 and the access controls are defined by the logical OR of the two region descriptors. Thus, CP0 has (rw- | r--) = (rw-) permissions, while CP1 has (--- | r--) = (r--) permission in this space. Both DMA engines are excluded from this shared processor data region. The overlapping spaces between RGD3 and RGD4 defines another shared data space, this one for passing data from CP1 to CP0. For this overlapping space, CP0 has (r-- | ---) = (r--) permission, while CP1 has (rw- | r--) = (rw-) permission. The non-overlapped space of RGD4 defines a private data and stack area for CP1 only. The space defined by RGD5 is a shared data region, accessible by all four bus masters. Finally, the slave peripheral space mapped onto the IPS bus is partitioned into two regions: one containing the MPU's programming model accessible only to the two processor cores and the remaining peripheral region accessible to both processors and the traditional DMA1 master. This simple example is intended to show one possible application of the capabilities of the MPU in a typical system. Chapter 18 Memory Protection Unit (MPU) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 397

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 398 Freescale Semiconductor, Inc.

Peripheral Bridge (AIPS-Lite)

19.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The peripheral bridge (AIPS-Lite) converts the crossbar switch interface to an interface to access a majority of peripherals on the device. The peripheral bridge supports up to 128 peripherals. The peripheral bridge occupies a 64 MB portion of the address space. The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals.

19.1.1 Features

Key features of the peripheral bridge are:

• Supports up to 128 peripherals
• Supports 8-, 16-, and 32-bit width peripheral slots
• Each independently configurable peripheral includes a clock enable, which allows peripherals to operate at any speed less than the system clock rate.
• Programming model provides memory protection functionality

19.1.2 General operation

The peripherals connected to the peripheral bridge are modules that contain readable/ writable control and status registers. The system masters read and write these registers through the peripheral bridge. The peripheral bridge generates module enables, the K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 399

module address, transfer attributes, byte enables, and write data as inputs to the peripherals. The peripheral bridge captures read data from the peripheral interface and drives it to the crossbar switch. The register maps of the peripherals are located on 4 KB boundaries. Each peripheral is allocated one 4 KB block of the memory map. The peripheral bridge (AIPS-Lite) memory map is illustrated as follows. Addresses Description Base + 0x000_0000 - 0x000_0FFF Module #0 Base + 0x000_1000 - 0x000_1FFF Module #1 Base + 0x007_F000 - 0x007_FFFF Module #127

19.2 Memory map/register definition

The peripheral bridge registers are 32-bit registers and can only be accessed in supervisor mode by trusted bus masters. Additionally, these registers must only be read from or written to by a 32-bit aligned access. The peripheral bridge registers are mapped into the PACR0 address space. Two system clocks are required for read accesses, and three system clocks are required for write accesses to the peripheral bridge registers. NOTE The number of fields and registers available depends on the device-specific implementation of the peripheral bridge module. See the Chip Configuration chapter for more information. AIPS memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_0000 Master Privilege Register A (AIPS0_MPRA) 32 R/W Undefined 19.2.1/401 4000_0020 Peripheral Access Control Register (AIPS0_PACRA) 32 R/W 4444_4444h 19.2.2/405 4000_0024 Peripheral Access Control Register (AIPS0_PACRB) 32 R/W 4444_4444h 19.2.2/405 4000_0028 Peripheral Access Control Register (AIPS0_PACRC) 32 R/W 4444_4444h 19.2.2/405 4000_002C Peripheral Access Control Register (AIPS0_PACRD) 32 R/W 4444_4444h 19.2.2/405 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 400 Freescale Semiconductor, Inc.

AIPS memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_0040 Peripheral Access Control Register (AIPS0_PACRE) 32 R/W Undefined 19.2.3/410 4000_0044 Peripheral Access Control Register (AIPS0_PACRF) 32 R/W Undefined 19.2.3/410 4000_0048 Peripheral Access Control Register (AIPS0_PACRG) 32 R/W Undefined 19.2.3/410 4000_004C Peripheral Access Control Register (AIPS0_PACRH) 32 R/W Undefined 19.2.3/410 4000_0050 Peripheral Access Control Register (AIPS0_PACRI) 32 R/W Undefined 19.2.3/410 4000_0054 Peripheral Access Control Register (AIPS0_PACRJ) 32 R/W Undefined 19.2.3/410 4000_0058 Peripheral Access Control Register (AIPS0_PACRK) 32 R/W Undefined 19.2.3/410 4000_005C Peripheral Access Control Register (AIPS0_PACRL) 32 R/W Undefined 19.2.3/410 4000_0060 Peripheral Access Control Register (AIPS0_PACRM) 32 R/W Undefined 19.2.3/410 4000_0064 Peripheral Access Control Register (AIPS0_PACRN) 32 R/W Undefined 19.2.3/410 4000_0068 Peripheral Access Control Register (AIPS0_PACRO) 32 R/W Undefined 19.2.3/410 4000_006C Peripheral Access Control Register (AIPS0_PACRP) 32 R/W Undefined 19.2.3/410 4008_0000 Master Privilege Register A (AIPS1_MPRA) 32 R/W Undefined 19.2.1/401 4008_0020 Peripheral Access Control Register (AIPS1_PACRA) 32 R/W 4444_4444h 19.2.2/405 4008_0024 Peripheral Access Control Register (AIPS1_PACRB) 32 R/W 4444_4444h 19.2.2/405 4008_0028 Peripheral Access Control Register (AIPS1_PACRC) 32 R/W 4444_4444h 19.2.2/405 4008_002C Peripheral Access Control Register (AIPS1_PACRD) 32 R/W 4444_4444h 19.2.2/405 4008_0040 Peripheral Access Control Register (AIPS1_PACRE) 32 R/W Undefined 19.2.3/410 4008_0044 Peripheral Access Control Register (AIPS1_PACRF) 32 R/W Undefined 19.2.3/410 4008_0048 Peripheral Access Control Register (AIPS1_PACRG) 32 R/W Undefined 19.2.3/410 4008_004C Peripheral Access Control Register (AIPS1_PACRH) 32 R/W Undefined 19.2.3/410 4008_0050 Peripheral Access Control Register (AIPS1_PACRI) 32 R/W Undefined 19.2.3/410 4008_0054 Peripheral Access Control Register (AIPS1_PACRJ) 32 R/W Undefined 19.2.3/410 4008_0058 Peripheral Access Control Register (AIPS1_PACRK) 32 R/W Undefined 19.2.3/410 4008_005C Peripheral Access Control Register (AIPS1_PACRL) 32 R/W Undefined 19.2.3/410 4008_0060 Peripheral Access Control Register (AIPS1_PACRM) 32 R/W Undefined 19.2.3/410 4008_0064 Peripheral Access Control Register (AIPS1_PACRN) 32 R/W Undefined 19.2.3/410 4008_0068 Peripheral Access Control Register (AIPS1_PACRO) 32 R/W Undefined 19.2.3/410 4008_006C Peripheral Access Control Register (AIPS1_PACRP) 32 R/W Undefined 19.2.3/410

19.2.1 Master Privilege Register A (AIPSx_MPRA)

The MPRA register specifies identical 4-bit fields defining the access-privilege level associated with a bus master in the device to the various peripherals. The register provides one field per bus master. Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 401

At reset, the default value loaded into the MPROT[7-0] fields is device-specific. See the Chip Configuration details for the value on your particular device. Accesses to registers or register fields which correspond to master or peripheral locations which are not implemented return zeros on reads, and are ignored on writes. Each master is assigned depending on its connection to the crossbar switch master ports. See your device-specific Chip Configuration details for information about the master assignments to these registers. Addresses: AIPS0_MPRA is 4000_0000h base + 0h offset = 4000_0000h AIPS1_MPRA is 4008_0000h base + 0h offset = 4008_0000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 MTR0 MTW0 MPL0 MTR1 MTW1 MPL1 MTR2 MTW2 MPL2 MTR3 MTW3 MPL3 MTR4 MTW4 MPL4 MTR5 MTW5 MPL5 0 0 W * Notes: x = Undefined at reset.• AIPSx_MPRA field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. MTR0 Master trusted for read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. MTW0 Master trusted for writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. MPL0 Master privilege level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 402 Freescale Semiconductor, Inc.

AIPSx_MPRA field descriptions (continued) Field Description MTR1 Master trusted for read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. MTW1 Master trusted for writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. MPL1 Master privilege level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. Reserved This read-only field is reserved and always has the value zero. MTR2 Master trusted for read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. MTW2 Master trusted for writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. MPL2 Master privilege level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. Reserved This read-only field is reserved and always has the value zero. MTR3 Master trusted for read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. MTW3 Master trusted for writes Determines whether the master is trusted for write accesses. Table continues on the next page... Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 403

AIPSx_MPRA field descriptions (continued) Field Description 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. MPL3 Master privilege level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. Reserved This read-only field is reserved and always has the value zero. MTR4 Master trusted for read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. MTW4 Master trusted for writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. MPL4 Master privilege level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. Reserved This read-only field is reserved and always has the value zero. MTR5 Master trusted for read Determines whether the master is trusted for read accesses. 0 This master is not trusted for read accesses. 1 This master is trusted for read accesses. MTW5 Master trusted for writes Determines whether the master is trusted for write accesses. 0 This master is not trusted for write accesses. 1 This master is trusted for write accesses. MPL5 Master privilege level Specifies how the privilege level of the master is determined. 0 Accesses from this master are forced to user-mode. 1 Accesses from this master are not forced to user-mode. 7–4 Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 404 Freescale Semiconductor, Inc.

AIPSx_MPRA field descriptions (continued) Field Description 3–0 Reserved This read-only field is reserved and always has the value zero.

19.2.2 Peripheral Access Control Register (AIPSx_PACRn)

Each of the peripherals has a four-bit PACR[0:127] field which defines the access levels supported by the given module. Eight PACR fields are grouped together to form a 32-bit PACR[A:P] register:

• PACRA-P define the access levels for the 128 peripherals The peripheral assignments to each PACR register is defined by the memory map slot that the peripherals are assigned.See the device's Memory Map details for the assignments for your particular device. NOTE The reset value of the PACRA-D registers is 0x4444_4444. The following table shows the top-level structure of the PACR registers. 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 PACR95 Table continues on the next page... Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 405

0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 Addresses: AIPS0_PACRA is 4000_0000h base + 20h offset = 4000_0020h AIPS0_PACRB is 4000_0000h base + 24h offset = 4000_0024h AIPS0_PACRC is 4000_0000h base + 28h offset = 4000_0028h AIPS0_PACRD is 4000_0000h base + 2Ch offset = 4000_002Ch AIPS1_PACRA is 4008_0000h base + 20h offset = 4008_0020h AIPS1_PACRB is 4008_0000h base + 24h offset = 4008_0024h AIPS1_PACRC is 4008_0000h base + 28h offset = 4008_0028h AIPS1_PACRD is 4008_0000h base + 2Ch offset = 4008_002Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SP0 WP0 TP0 SP1 WP1 TP1 SP2 WP2 TP2 SP3 WP3 TP3 SP4 WP4 TP4 SP5 WP5 TP5 SP6 WP6 TP6 SP7 WP7 TP7W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 AIPSx_PACRn field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. SP0 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP0 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP0 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 406 Freescale Semiconductor, Inc.

AIPSx_PACRn field descriptions (continued) Field Description Reserved This read-only field is reserved and always has the value zero. SP1 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP1 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP1 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP2 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP2 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP2 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. Table continues on the next page... Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 407

AIPSx_PACRn field descriptions (continued) Field Description 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP3 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP3 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP3 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP4 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP4 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP4 Trusted protect Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 408 Freescale Semiconductor, Inc.

AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP5 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP5 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP5 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP6 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP6 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. Table continues on the next page... Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 409

AIPSx_PACRn field descriptions (continued) Field Description TP6 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP7 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP7 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP7 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed.

19.2.3 Peripheral Access Control Register (AIPSx_PACRn)

Each of the peripherals has a four-bit PACR[0:127] field which defines the access levels supported by the given module. Eight PACR fields are grouped together to form a 32-bit PACR[A:P] register:

• PACRA-P define the access levels for the 128 peripherals The peripheral assignments to each PACR register is defined by the memory map slot that the peripherals are assigned.See the device's Memory Map details for the assignments for your particular device. Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 410 Freescale Semiconductor, Inc.

The reset value of the PACRE-P depends on your device's configuration. Addresses: 4000_0000h base + 40h offset + (4d × n), where n = 0d to 11d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 SP0 WP0 TP0 SP1 WP1 TP1 SP2 WP2 TP2 SP3 WP3 TP3 SP4 WP4 TP4 SP5 WP5 TP5 SP6 WP6 TP6 SP7 WP7 TP7W * Notes: x = Undefined at reset.• AIPSx_PACRn field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. SP0 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP0 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP0 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP1 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. Table continues on the next page... Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 411

AIPSx_PACRn field descriptions (continued) Field Description 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP1 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP1 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP2 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP2 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP2 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP3 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 412 Freescale Semiconductor, Inc.

AIPSx_PACRn field descriptions (continued) Field Description the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP3 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP3 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP4 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP4 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP4 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP5 Supervisor protect Table continues on the next page... Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 413

AIPSx_PACRn field descriptions (continued) Field Description Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP5 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP5 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. SP6 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates. 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP6 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP6 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates . 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed. Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 414 Freescale Semiconductor, Inc.

AIPSx_PACRn field descriptions (continued) Field Description SP7 Supervisor protect Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for the master must be set. If not, access terminates with an error response and no peripheral access initiates . 0 This peripheral does not require supervisor privilege level for accesses. 1 This peripheral requires supervisor privilege level for accesses. WP7 Write protect Determines whether the peripheral allows write accesss. When this bit is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. 0 This peripheral allows write accesses. 1 This peripheral is write protected. TP7 Trusted protect Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an access is attempted by an untrusted master, the access terminates with an error response and no peripheral access initiates. 0 Accesses from an untrusted master are allowed. 1 Accesses from an untrusted master are not allowed.

19.3 Functional Description

The peripheral bridge serves as an interface between the crossbar switch and the slave peripheral bus. It functions as a protocol translator. Accesses which fall within the address space of the peripheral bridge are decoded to provide individual module selects for peripheral devices on the slave bus interface.

19.3.1 Access support

Aligned and misaligned 32-bit and 16-bit accesses, as well as byte accesses are supported for 32-bit peripherals. Misaligned accesses are supported to allow memory to be placed on the slave peripheral bus. Peripheral registers must not be misaligned, although no explicit checking is performed by the peripheral bridge. All accesses are performed with a single transfer. All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted which is larger (in size) than the targeted port, an error response is generated. Chapter 19 Peripheral Bridge (AIPS-Lite) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 415

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 416 Freescale Semiconductor, Inc.

Direct memory access multiplexer (DMAMUX)

20.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter.

20.1.1 Overview

The DMA Mux routes up to 63 DMA sources (called slots) to be mapped to any of the 16 DMA channels. This is illustrated in the following figure. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 417

DMA Channel #0 Source #1 Source #2 Source #3 Always #1 DMA Channel #n Always #y Source #x Trigger #1 Trigger #z DMA Channel #1 DMAMUX Figure 20-1. DMA MUX block diagram

20.1.2 Features

The DMA channel MUX provides these features:

• 52 peripheral slots + 10 always-on slots can be routed to 16 channels.
• 16 independently selectable DMA channel routers.
• The first 4 channels additionally provide a trigger functionality.
• Each channel router can be assigned to one of the 52 possible peripheral DMA slots or to one of the 10 always-on slots.

20.1.3 Modes of operation

The following operating modes are available:

• Disabled mode Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 418 Freescale Semiconductor, Inc.

In this mode, the DMA channel is disabled. Since disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place (e.g. changing the period of a DMA trigger).

• Normal mode In this mode, a DMA source (such as DSPI transmit or DSPI receive) is routed directly to the specified DMA channel. The operation of the DMA MUX in this mode is completely transparent to the system.
• Periodic trigger mode In this mode, a DMA source may only request a DMA transfer (such as when a transmit buffer becomes empty or a receive buffer becomes full) periodically. Configuration of the period is done in the registers of the periodic interrupt timer (PIT). This mode is only available for channels 0-3.

20.2 External signal description

The DMA MUX has no external pins.

20.3 Memory map/register definition

This section provides a detailed description of all memory-mapped registers in the DMA MUX. The following table shows the memory map for the DMA MUX. All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, CHCFG0 through CHCFG3 are accessible by a 32-bit read/ write to address 'base + 0x00', but performing a 32-bit access to address 'base + 0x01' is illegal. Chapter 20 Direct memory access multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 419

(hex) Register name Width (in bits) Access Reset value Section/ page 4002_1000 Channel Configuration Register (DMAMUX_CHCFG0) 8 R/W 00h 20.3.1/420 4002_1001 Channel Configuration Register (DMAMUX_CHCFG1) 8 R/W 00h 20.3.1/420 4002_1002 Channel Configuration Register (DMAMUX_CHCFG2) 8 R/W 00h 20.3.1/420 4002_1003 Channel Configuration Register (DMAMUX_CHCFG3) 8 R/W 00h 20.3.1/420 4002_1004 Channel Configuration Register (DMAMUX_CHCFG4) 8 R/W 00h 20.3.1/420 4002_1005 Channel Configuration Register (DMAMUX_CHCFG5) 8 R/W 00h 20.3.1/420 4002_1006 Channel Configuration Register (DMAMUX_CHCFG6) 8 R/W 00h 20.3.1/420 4002_1007 Channel Configuration Register (DMAMUX_CHCFG7) 8 R/W 00h 20.3.1/420 4002_1008 Channel Configuration Register (DMAMUX_CHCFG8) 8 R/W 00h 20.3.1/420 4002_1009 Channel Configuration Register (DMAMUX_CHCFG9) 8 R/W 00h 20.3.1/420 4002_100A Channel Configuration Register (DMAMUX_CHCFG10) 8 R/W 00h 20.3.1/420 4002_100B Channel Configuration Register (DMAMUX_CHCFG11) 8 R/W 00h 20.3.1/420 4002_100C Channel Configuration Register (DMAMUX_CHCFG12) 8 R/W 00h 20.3.1/420 4002_100D Channel Configuration Register (DMAMUX_CHCFG13) 8 R/W 00h 20.3.1/420 4002_100E Channel Configuration Register (DMAMUX_CHCFG14) 8 R/W 00h 20.3.1/420 4002_100F Channel Configuration Register (DMAMUX_CHCFG15) 8 R/W 00h 20.3.1/420

20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)

Each of the DMA channels can be independently enabled/disabled and associated with one of the DMA slots (peripheral slots or always-on slots) in the system. NOTE Setting multiple CHCFG registers with the same Source value will result in unpredictable behavior. NOTE Before changing the trigger or source settings a DMA channel must be disabled via the CHCFGn[ENBL] bit. Addresses: 4002_1000h base + 0h offset + (1d × n), where n = 0d to 15d Bit 7 6 5 4 3 2 1 0 Read ENBL TRIG SOURCE Write Reset 0 0 0 0 0 0 0 0 Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 420 Freescale Semiconductor, Inc.

DMAMUX_CHCFGn field descriptions Field Description ENBL DMA Channel Enable Enables the DMA channel 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.

1 DMA channel is enabled

DMA Channel Trigger Enable Enables the periodic trigger capability for the triggered DMA channel 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. 5–0 SOURCE DMA Channel Source (slot) Specifies which DMA source, if any, is routed to a particular DMA channel. Please check your device's Chip Configuration details for further details about the peripherals and their slot numbers.

20.4 Functional description

This section provides the functional description of the DMA MUX. The primary purpose of the DMA MUX is to provide flexibility in the system's use of the available DMA channels. As such, configuration of the DMA MUX is intended to be a static procedure done during execution of the system boot code. However, if the procedure outlined in Enabling and configuring sources is followed, the configuration of the DMA MUX may be changed during the normal operation of the system. Functionally, the DMA MUX channels may be divided into two classes: Channels, which implement the normal routing functionality plus periodic triggering capability, and channels, which implement only the normal routing functionality.

20.4.1 DMA channels with periodic triggering capability

Besides the normal routing functionality, the first four channels of the DMA MUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames or packets at fixed intervals without the need for processor intervention. The trigger is generated by the periodic interrupt timer (PIT); as Chapter 20 Direct memory access multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 421

such, the configuration of the periodic triggering interval is done via configuration registers in the PIT. Please refer to Periodic Interrupt Timer chapter for more information on this topic. Note Because of the dynamic nature of the system (i.e. DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. DMA Channel #0 Trigger #2 Source #1 Source #2 Source #3 Always #1 DMA Channel #3 Always #y Trigger #4 Source #x Trigger #1 DMA Channel #1 Figure 20-19. DMA MUX triggered channels The DMA channel triggering capability allows the system to "schedule" regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen. This is illustrated in the following figure. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 422 Freescale Semiconductor, Inc.

20.4.2 DMA channels with no triggering capability

The other channels of the DMA MUX provide the normal routing functionality as described in Modes of operation. 20.4.3 "Always enabled" DMA sources In addition to the peripherals that can be used as DMA sources, there are 10 additional DMA sources that are "always enabled". Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the "always enabled" sources provide no such "throttling" of the data transfers. These sources are most useful in the following cases:

• Doing DMA transfers to/from GPIO—Moving data from/to one or more GPIO pins, either un-throttled (that is as fast as possible), or periodically (using the DMA triggering capability).
• Doing DMA transfers from memory to memory—Moving data from memory to memory, typically as fast as possible, sometimes with software activation.
• Doing DMA transfers from memory to the external bus (or vice-versa)—Similar to memory to memory transfers, this is typically done as quickly as possible.
• Any DMA transfer that requires software activation—Any DMA transfer that should be explicitly started by software. In cases where software should initiate the start of a DMA transfer, an "always enabled" DMA source can be used to provide maximum flexibility. When activating a DMA channel via software, subsequent executions of the minor loop require a new "start" event be sent. This can either be a new software activation, or a transfer request from the DMA channel MUX. The options for doing this are:
• Transfer all data in a single minor loop. By configuring the DMA to transfer all of the data in a single minor loop (that is major loop counter = 1), no re-activation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will incur on the system. For this option, the DMA channel should be disabled in the DMA channel MUX. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 424 Freescale Semiconductor, Inc.

• Use explicit software re-activation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to re-activate the channel (by writing to the DMA registers) after every minor loop. For this option, the DMA channel should be disabled in the DMA channel MUX.
• Use a "always enabled" DMA source. In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel re-activation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the re-activation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention.

20.5 Initialization/application information

This section provides instructions for initializing the DMA channel MUX.

20.5.1 Reset

The reset state of each individual bit is shown in Memory map/register definition. In summary, after reset, all channels are disabled and must be explicitly enabled before use.

20.5.2 Enabling and configuring sources

Enabling a source with periodic triggering 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point 4. Configure the corresponding timer 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set Configure source #5 transmit for use with DMA channel 2, with periodic triggering capability 1. Write 0x00 to CHCFG2 (base address + 0x02) 2. Configure channel 2 in the DMA, including enabling the channel Chapter 20 Direct memory access multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 425

1. Configure a timer for the desired trigger interval 4. Write 0xC5 to CHCFG2 (base address + 0x02) The following code example illustrates steps #1 and #4 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCONFIG2 = 0x00; *CHCONFIG2 = 0xC5; Enabling a source without periodic triggering 1. Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] is set while the CHCFG[TRIG] bit is cleared Configure source #5 Transmit for use with DMA channel 2, with no periodic triggering capability. 1. Write 0x00 to CHCFG2 (base address + 0x02) 2. Configure channel 2 in the DMA, including enabling the channel 3. Write 0x85 to CHCFG2 (base address + 0x02) The following code example illustrates steps #1 and #3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 426 Freescale Semiconductor, Inc.

volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCONFIG2 = 0x00; *CHCONFIG2 = 0x85; Disabling a source A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers. Additionally, some module specific configuration may be necessary. Please refer to the appropriate section for more details. Switching the source of a DMA channel 1. Disable the DMA channel in the DMA and re-configure the channel for the new source 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set Switch DMA channel 8 from source #5 transmit to source #7 transmit 1. In the DMA configuration registers, disable DMA channel 8 and re-configure it to handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't have triggering capability 2. Write 0x00 to CHCFG8 (base address + 0x08) 3. Write 0x87 to CHCFG8 (base address + 0x08). (In this example, setting the CHCFG[TRIG] bit would have no effect, due to the assumption that channels 8 does not support the periodic triggering functionality). The following code example illustrates steps #2 and #3 above: In File registers.h: #define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ /* Following example assumes char is 8-bits */ volatile unsigned char *CHCONFIG0 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCONFIG1 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCONFIG2 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCONFIG3 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCONFIG4 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCONFIG5 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCONFIG6 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCONFIG7 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0007); Chapter 20 Direct memory access multiplexer (DMAMUX) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 427

volatile unsigned char *CHCONFIG8 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCONFIG9 = (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCONFIG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCONFIG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCONFIG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCONFIG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCONFIG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCONFIG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCONFIG8 = 0x00; *CHCONFIG8 = 0x87; Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 428 Freescale Semiconductor, Inc.

Direct Memory Access Controller (eDMA)

21.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The hardware microarchitecture includes:

• A DMA engine that performs:
• Source- and destination-address calculations
• Data-movement operations
• Local memory containing transfer control descriptors for each of the 16 channels

21.1.1 Block diagram

This diagram illustrates the eDMA module. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 429

Descriptor (TCD) eDMA Engine Data Path eDMA Program Model/ Control n-1 To/From Crossbar Switch Channel Arbitration Address Path Read Data Write Data Address Read Data Write Data Write Address Internal Peripheral Bus eDMA Peripheral Request eDMA Done Figure 21-1. eDMA block diagram

21.1.2 Block parts

The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory. The eDMA engine is further partitioned into four submodules: Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 430 Freescale Semiconductor, Inc.

Table 21-1. eDMA engine submodules Submodule Function Address path This block implements registered versions of two channel transfer control descriptors, channel x and channel y, and manages all master bus-address calculations. All the channels provide the same functionality. This structure allows data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel activation is asserted while the first channel is active. After a channel is activated, it runs until the minor loop is completed, unless preempted by a higher priority channel. This provides a mechanism (enabled by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time another channel is blocked from execution. When any channel is selected to execute, the contents of its TCD are read from local memory and loaded into the address path channel x registers for a normal start and into channel y registers for a preemption start. After the minor loop completes execution, the address path hardware writes the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation. Data path This block implements the bus master read/write datapath. It includes 16 bytes of register storage and the necessary multiplex logic to support any required data alignment. The internal read data bus is the primary input, and the internal write data bus is the primary output. The address and data path modules directly support the 2- stage pipelined internal bus. The address path module represents the 1st stage of the bus pipeline (address phase), while the data path module implements the 2nd stage of the pipeline (data phase). Program model/channel arbitration This block implements the first section of the eDMA programming model as well as the channel arbitration logic. The programming model registers are connected to the internal peripheral bus. The eDMA peripheral request inputs and interrupt request outputs are also connected to this block (via control logic). Control This block provides all the control functions for the eDMA engine. For data transfers where the source and destination sizes are equal, the eDMA engine performs a series of source read/destination write operations until the number of bytes specified in the minor loop byte count has moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data are required for each reference of the larger size. As an example, if the source size references 16- bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. The transfer-control descriptor local memory is further partitioned into: Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 431

Table 21-2. Transfer control descriptor memory Submodule Description Memory controller This logic implements the required dual-ported controller, managing accesses from the eDMA engine as well as references from the internal peripheral bus. As noted earlier, in the event of simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is stalled. Memory array TCD storage is implemented using a single-port, synchronous RAM array.

21.1.3 Features

The eDMA is a highly-programmable data-transfer engine optimized to minimize the required intervention from the host processor. It is intended for use in applications where the data size to be transferred is statically known and not defined within the data packet itself. The eDMA module features:

• All data movement via dual-address transfers: read from source, write to destination
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 16-channel implementation that performs complex data transfers with minimal intervention from a host processor
• Internal data buffer, used as temporary storage to support 16-byte burst transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 432 Freescale Semiconductor, Inc.

• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration count
• Optional error terminations per channel and logically summed together to form one error interrupt to the interrupt controller
• Optional support for scatter/gather DMA processing
• Support for complex data structures
• Support to cancel transfers via software In the discussion of this module, n is used to reference the channel number.

21.2 Modes of operation

The eDMA operates in the following modes: Table 21-3. Modes of operation Mode Description Normal In Normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that transfers these NBYTES per service request. Each service request executes one iteration of the major loop, which transfers NBYTES of data. Debug DMA operation is configurable in Debug mode via the control register:

• If CR[EDBG] is cleared, the DMA continues to operate.
• If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a channel is active, the eDMA continues operation until the channel retires. Wait Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer completes, the device enters Wait mode.

21.3 Memory map/register definition

The eDMA's programming model is partitioned into two regions: Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 433

• The first region defines a number of registers providing control functions
• The second region corresponds to the local transfer control descriptor memory Each channel requires a 32-byte transfer control descriptor for defining the desired data movement operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 15 . Each TCDn definition is presented as 11 registers of 16 or 32 bits. Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a register are ignored. Reading or writing a reserved memory location generates a bus error. DMA memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_8000 Control Register (DMA_CR) 32 R/W 0000_0000h 21.3.1/448 4000_8004 Error Status Register (DMA_ES) 32 R 0000_0000h 21.3.2/450 4000_800C Enable Request Register (DMA_ERQ) 32 R/W 0000_0000h 21.3.3/452 4000_8014 Enable Error Interrupt Register (DMA_EEI) 32 R/W 0000_0000h 21.3.4/454 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) 8 W (always reads zero) 00h 21.3.5/456 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) 8 W (always reads zero) 00h 21.3.6/457 4000_801A Clear Enable Request Register (DMA_CERQ) 8 W (always reads zero) 00h 21.3.7/458 4000_801B Set Enable Request Register (DMA_SERQ) 8 W (always reads zero) 00h 21.3.8/459 4000_801C Clear DONE Status Bit Register (DMA_CDNE) 8 W (always reads zero) 00h 21.3.9/460 4000_801D Set START Bit Register (DMA_SSRT) 8 W (always reads zero) 00h 21.3.10/ 461 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 434 Freescale Semiconductor, Inc.

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_801E Clear Error Register (DMA_CERR) 8 W (always reads zero) 00h 21.3.11/ 462 4000_801F Clear Interrupt Request Register (DMA_CINT) 8 W (always reads zero) 00h 21.3.12/ 463 4000_8024 Interrupt Request Register (DMA_INT) 32 R/W 0000_0000h 21.3.13/ 463 4000_802C Error Register (DMA_ERR) 32 R/W 0000_0000h 21.3.14/ 466 4000_8034 Hardware Request Status Register (DMA_HRS) 32 R/W 0000_0000h 21.3.15/ 468 4000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W Undefined 21.3.16/ 470 4000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W Undefined 21.3.16/ 470 4000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W Undefined 21.3.16/ 470 4000_8103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W Undefined 21.3.16/ 470 4000_8104 Channel n Priority Register (DMA_DCHPRI7) 8 R/W Undefined 21.3.16/ 470 4000_8105 Channel n Priority Register (DMA_DCHPRI6) 8 R/W Undefined 21.3.16/ 470 4000_8106 Channel n Priority Register (DMA_DCHPRI5) 8 R/W Undefined 21.3.16/ 470 4000_8107 Channel n Priority Register (DMA_DCHPRI4) 8 R/W Undefined 21.3.16/ 470 4000_8108 Channel n Priority Register (DMA_DCHPRI11) 8 R/W Undefined 21.3.16/ 470 4000_8109 Channel n Priority Register (DMA_DCHPRI10) 8 R/W Undefined 21.3.16/ 470 4000_810A Channel n Priority Register (DMA_DCHPRI9) 8 R/W Undefined 21.3.16/ 470 4000_810B Channel n Priority Register (DMA_DCHPRI8) 8 R/W Undefined 21.3.16/ 470 4000_810C Channel n Priority Register (DMA_DCHPRI15) 8 R/W Undefined 21.3.16/ 470 4000_810D Channel n Priority Register (DMA_DCHPRI14) 8 R/W Undefined 21.3.16/ 470 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 435

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_810E Channel n Priority Register (DMA_DCHPRI13) 8 R/W Undefined 21.3.16/ 470 4000_810F Channel n Priority Register (DMA_DCHPRI12) 8 R/W Undefined 21.3.16/ 470 4000_9000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9008 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD0_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9008 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD0_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9008 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD0_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_900C TCD Last Source Address Adjustment (DMA_TCD0_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9014 TCD Signed Destination Address Offset (DMA_TCD0_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9016 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9018 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD0_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined 21.3.29/ 480 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD0_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_901E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD0_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9020 TCD Source Address (DMA_TCD1_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9024 TCD Signed Source Address Offset (DMA_TCD1_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9026 TCD Transfer Attributes (DMA_TCD1_ATTR) 16 R/W Undefined 21.3.19/ 472 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 436 Freescale Semiconductor, Inc.

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9028 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD1_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9028 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD1_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9028 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD1_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_902C TCD Last Source Address Adjustment (DMA_TCD1_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9030 TCD Destination Address (DMA_TCD1_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9034 TCD Signed Destination Address Offset (DMA_TCD1_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9036 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9036 DMA_TCD1_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9038 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD1_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_903C TCD Control and Status (DMA_TCD1_CSR) 16 R/W Undefined 21.3.29/ 480 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD1_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_903E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9040 TCD Source Address (DMA_TCD2_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9046 TCD Transfer Attributes (DMA_TCD2_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9048 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD2_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9048 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD2_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9048 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD2_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_904C TCD Last Source Address Adjustment (DMA_TCD2_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9050 TCD Destination Address (DMA_TCD2_DADDR) 32 R/W Undefined 21.3.24/ 476 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 437

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9054 TCD Signed Destination Address Offset (DMA_TCD2_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9056 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9058 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD2_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined 21.3.29/ 480 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD2_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_905E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD2_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9060 TCD Source Address (DMA_TCD3_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9064 TCD Signed Source Address Offset (DMA_TCD3_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9066 TCD Transfer Attributes (DMA_TCD3_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9068 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD3_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9068 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9068 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD3_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_906C TCD Last Source Address Adjustment (DMA_TCD3_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9074 TCD Signed Destination Address Offset (DMA_TCD3_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9076 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9078 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD3_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined 21.3.29/ 480 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 438 Freescale Semiconductor, Inc.

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD3_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_907E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9080 TCD Source Address (DMA_TCD4_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9084 TCD Signed Source Address Offset (DMA_TCD4_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9086 TCD Transfer Attributes (DMA_TCD4_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9088 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD4_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9088 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD4_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9088 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD4_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_908C TCD Last Source Address Adjustment (DMA_TCD4_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9090 TCD Destination Address (DMA_TCD4_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9094 TCD Signed Destination Address Offset (DMA_TCD4_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9096 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD4_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9096 DMA_TCD4_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9098 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD4_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_909C TCD Control and Status (DMA_TCD4_CSR) 16 R/W Undefined 21.3.29/ 480 4000_909E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD4_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_909E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_90A0 TCD Source Address (DMA_TCD5_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_90A4 TCD Signed Source Address Offset (DMA_TCD5_SOFF) 16 R/W Undefined 21.3.18/ 472 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 439

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_90A8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD5_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_90A8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_90A8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD5_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_90AC TCD Last Source Address Adjustment (DMA_TCD5_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_90B0 TCD Destination Address (DMA_TCD5_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_90B4 TCD Signed Destination Address Offset (DMA_TCD5_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_90B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD5_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_90B6 DMA_TCD5_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_90B8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD5_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_90BC TCD Control and Status (DMA_TCD5_CSR) 16 R/W Undefined 21.3.29/ 480 4000_90BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD5_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_90BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD5_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_90C0 TCD Source Address (DMA_TCD6_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_90C8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD6_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_90C8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD6_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_90C8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD6_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_90CC TCD Last Source Address Adjustment (DMA_TCD6_SLAST) 32 R/W Undefined 21.3.23/ 476 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 440 Freescale Semiconductor, Inc.

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_90D0 TCD Destination Address (DMA_TCD6_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_90D4 TCD Signed Destination Address Offset (DMA_TCD6_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_90D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD6_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_90D6 DMA_TCD6_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_90D8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD6_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_90DC TCD Control and Status (DMA_TCD6_CSR) 16 R/W Undefined 21.3.29/ 480 4000_90DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD6_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_90DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_90E0 TCD Source Address (DMA_TCD7_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_90E4 TCD Signed Source Address Offset (DMA_TCD7_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_90E6 TCD Transfer Attributes (DMA_TCD7_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_90E8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD7_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_90E8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD7_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_90E8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD7_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_90EC TCD Last Source Address Adjustment (DMA_TCD7_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_90F0 TCD Destination Address (DMA_TCD7_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_90F4 TCD Signed Destination Address Offset (DMA_TCD7_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_90F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_90F6 DMA_TCD7_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_90F8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD7_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 441

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_90FC TCD Control and Status (DMA_TCD7_CSR) 16 R/W Undefined 21.3.29/ 480 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD7_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_90FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD7_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9100 TCD Source Address (DMA_TCD8_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9104 TCD Signed Source Address Offset (DMA_TCD8_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9106 TCD Transfer Attributes (DMA_TCD8_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9108 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD8_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9108 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD8_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9108 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD8_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_910C TCD Last Source Address Adjustment (DMA_TCD8_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9110 TCD Destination Address (DMA_TCD8_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9114 TCD Signed Destination Address Offset (DMA_TCD8_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9116 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD8_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9116 DMA_TCD8_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9118 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD8_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_911C TCD Control and Status (DMA_TCD8_CSR) 16 R/W Undefined 21.3.29/ 480 4000_911E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD8_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_911E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD8_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9120 TCD Source Address (DMA_TCD9_SADDR) 32 R/W Undefined 21.3.17/ 471 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 442 Freescale Semiconductor, Inc.

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9124 TCD Signed Source Address Offset (DMA_TCD9_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9126 TCD Transfer Attributes (DMA_TCD9_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9128 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD9_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9128 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD9_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9128 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD9_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_912C TCD Last Source Address Adjustment (DMA_TCD9_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9130 TCD Destination Address (DMA_TCD9_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9134 TCD Signed Destination Address Offset (DMA_TCD9_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9136 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD9_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9136 DMA_TCD9_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9138 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD9_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_913C TCD Control and Status (DMA_TCD9_CSR) 16 R/W Undefined 21.3.29/ 480 4000_913E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD9_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_913E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD9_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9140 TCD Source Address (DMA_TCD10_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9144 TCD Signed Source Address Offset (DMA_TCD10_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9146 TCD Transfer Attributes (DMA_TCD10_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9148 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD10_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9148 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD10_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9148 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD10_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 443

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_914C TCD Last Source Address Adjustment (DMA_TCD10_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9150 TCD Destination Address (DMA_TCD10_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9154 TCD Signed Destination Address Offset (DMA_TCD10_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9156 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD10_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9156 DMA_TCD10_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9158 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD10_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_915C TCD Control and Status (DMA_TCD10_CSR) 16 R/W Undefined 21.3.29/ 480 4000_915E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD10_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_915E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD10_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9160 TCD Source Address (DMA_TCD11_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9164 TCD Signed Source Address Offset (DMA_TCD11_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9166 TCD Transfer Attributes (DMA_TCD11_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9168 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD11_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9168 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD11_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9168 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD11_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_916C TCD Last Source Address Adjustment (DMA_TCD11_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9170 TCD Destination Address (DMA_TCD11_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9174 TCD Signed Destination Address Offset (DMA_TCD11_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9176 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD11_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9176 DMA_TCD11_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 444 Freescale Semiconductor, Inc.

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_9178 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD11_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_917C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined 21.3.29/ 480 4000_917E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD11_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_917E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD11_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_9180 TCD Source Address (DMA_TCD12_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_9188 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD12_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_9188 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD12_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_9188 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD12_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_918C TCD Last Source Address Adjustment (DMA_TCD12_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_9190 TCD Destination Address (DMA_TCD12_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_9194 TCD Signed Destination Address Offset (DMA_TCD12_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_9196 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD12_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_9196 DMA_TCD12_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_9198 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD12_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_919C TCD Control and Status (DMA_TCD12_CSR) 16 R/W Undefined 21.3.29/ 480 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD12_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_919E TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD12_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 445

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_91A0 TCD Source Address (DMA_TCD13_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_91A6 TCD Transfer Attributes (DMA_TCD13_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_91A8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD13_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_91A8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD13_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_91A8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD13_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_91AC TCD Last Source Address Adjustment (DMA_TCD13_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_91B0 TCD Destination Address (DMA_TCD13_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_91B4 TCD Signed Destination Address Offset (DMA_TCD13_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_91B6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD13_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_91B6 DMA_TCD13_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_91B8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD13_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_91BC TCD Control and Status (DMA_TCD13_CSR) 16 R/W Undefined 21.3.29/ 480 4000_91BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD13_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_91BE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD13_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_91C0 TCD Source Address (DMA_TCD14_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_91C4 TCD Signed Source Address Offset (DMA_TCD14_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_91C6 TCD Transfer Attributes (DMA_TCD14_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_91C8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD14_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_91C8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD14_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 446 Freescale Semiconductor, Inc.

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_91C8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD14_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_91CC TCD Last Source Address Adjustment (DMA_TCD14_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_91D4 TCD Signed Destination Address Offset (DMA_TCD14_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_91D6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD14_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 4000_91D6 DMA_TCD14_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_91D8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD14_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_91DC TCD Control and Status (DMA_TCD14_CSR) 16 R/W Undefined 21.3.29/ 480 4000_91DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD14_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_91DE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD14_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483 4000_91E0 TCD Source Address (DMA_TCD15_SADDR) 32 R/W Undefined 21.3.17/ 471 4000_91E4 TCD Signed Source Address Offset (DMA_TCD15_SOFF) 16 R/W Undefined 21.3.18/ 472 4000_91E6 TCD Transfer Attributes (DMA_TCD15_ATTR) 16 R/W Undefined 21.3.19/ 472 4000_91E8 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCD15_NBYTES_MLNO) 32 R/W Undefined 21.3.20/ 473 4000_91E8 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCD15_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/ 474 4000_91E8 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (DMA_TCD15_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/ 475 4000_91EC TCD Last Source Address Adjustment (DMA_TCD15_SLAST) 32 R/W Undefined 21.3.23/ 476 4000_91F0 TCD Destination Address (DMA_TCD15_DADDR) 32 R/W Undefined 21.3.24/ 476 4000_91F4 TCD Signed Destination Address Offset (DMA_TCD15_DOFF) 16 R/W Undefined 21.3.25/ 477 4000_91F6 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD15_CITER_ELINKYES) 16 R/W Undefined 21.3.26/ 477 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 447

DMA memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4000_91F6 DMA_TCD15_CITER_ELINKNO 16 R/W Undefined 21.3.27/ 478 4000_91F8 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCD15_DLASTSGA) 32 R/W Undefined 21.3.28/ 479 4000_91FC TCD Control and Status (DMA_TCD15_CSR) 16 R/W Undefined 21.3.29/ 480 4000_91FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCD15_BITER_ELINKYES) 16 R/W Undefined 21.3.30/ 482 4000_91FE TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCD15_BITER_ELINKNO) 16 R/W Undefined 21.3.31/ 483

21.3.1 Control Register (DMA_CR)

The CR defines the basic operating configuration of the DMA. Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For fixed-priority arbitration, the highest priority channel requesting service is selected to execute. The channel priority registers assign the priorities; see the DCHPRIn registers. For round-robin arbitration, the channel priorities are ignored and channels are cycled through without regard to priority. NOTE For proper operation, writes to the CR register must be performed only when the DMA channels are inactive; that is, when TCDn_CSR[ACTIVE] bits are cleared. Address: DMA_CR is 4000_8000h base + 0h offset = 4000_8000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CX ECX EMLM CLM HALT HOE ERCA EDBG W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CR field descriptions Field Description 31–18 Reserved This read-only field is reserved and always has the value zero. CX Cancel Transfer Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 448 Freescale Semiconductor, Inc.

DMA_CR field descriptions (continued) Field Description

0 Normal operation

1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. ECX Error Cancel Transfer 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt. 15–8 Reserved This read-only field is reserved and always has the value zero. EMLM Enable Minor Loop Mapping 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. CLM Continuous Link Mode

0 A minor loop channel link made to itself goes through channel arbitration before being activated

again.

1 A minor loop channel link made to itself does not go through channel arbitration before being

activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. HALT Halt DMA Operations 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. HOE Halt On Error 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. Reserved This read-only field is reserved and always has the value zero. ERCA Enable Round Robin Channel Arbitration 0 Fixed priority arbitration is used for channel selection. 1 Round robin arbitration is used for channel selection. EDBG Enable Debug Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 449

DMA_CR field descriptions (continued) Field Description 0 When in debug mode, the DMA continues to operate. 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. Reserved This read-only field is reserved and always has the value zero.

21.3.2 Error Status Register (DMA_ES)

The ES provides information concerning the last recorded channel error. Channel errors can be caused by:

• A configuration error, that is:
• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle See the Error Reporting and Handling section for more details. Address: DMA_ES is 4000_8000h base + 4h offset = 4000_8004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R VLD 0 ECX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CPE 0 ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ES field descriptions Field Description VLD Logical OR of all ERR status bits

0 No ERR bits are set

1 At least one ERR bit is set indicating a valid error exists that has not been cleared

30–17 Reserved This read-only field is reserved and always has the value zero. ECX Transfer Cancelled

0 No cancelled transfers

1 The last recorded entry was a cancelled transfer by the error cancel transfer input

Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 450 Freescale Semiconductor, Inc.

DMA_ES field descriptions (continued) Field Description Reserved This read-only field is reserved and always has the value zero. CPE Channel Priority Error

0 No channel priority error

1 The last recorded error was a configuration error in the channel priorities. Channel priorities are not unique. 13–12 Reserved This read-only field is reserved and always has the value zero. 11–8 ERRCHN Error Channel Number or Cancelled Channel Number The channel number of the last recorded error (excluding CPE errors) or last recorded error cancelled transfer. SAE Source Address Error 0 No source address configuration error. 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. SOE Source Offset Error

0 No source offset configuration error

1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. DAE Destination Address Error

0 No destination address configuration error

1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. DOE Destination Offset Error

0 No destination offset configuration error

1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. NCE NBYTES/CITER Configuration Error

0 No NBYTES/CITER configuration error

1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER

fields.

• TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or
• TCDn_CITER[CITER] is equal to zero, or
• TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] SGE Scatter/Gather Configuration Error

0 No scatter/gather configuration error

1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 451

DMA_ES field descriptions (continued) Field Description SBE Source Bus Error

0 No source bus error

1 The last recorded error was a bus error on a source read

0 No destination bus error

1 The last recorded error was a bus error on a destination write

21.3.3 Enable Request Register (DMA_ERQ)

The ERQ register provides a bit map for the 16 implemented channels to enable the request signal for each channel. The state of any given channel enable is directly affected by writes to this register; it is also affected by writes to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable for a single channel can easily be modified without needing to perform a read-modify-write sequence to the ERQ. DMA request input signals and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. Address: DMA_ERQ is 4000_8000h base + Ch offset = 4000_800Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 ERQ15 ERQ14 ERQ13 ERQ12 ERQ11 ERQ10 ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ERQ field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. ERQ15 Enable DMA Request 15

0 The DMA request signal for the corresponding channel is disabled

1 The DMA request signal for the corresponding channel is enabled

Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 452 Freescale Semiconductor, Inc.

DMA_ERQ field descriptions (continued) Field Description ERQ13 Enable DMA Request 13 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 453

DMA_ERQ field descriptions (continued) Field Description

21.3.4 Enable Error Interrupt Register (DMA_EEI)

The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each channel. The state of any given channel’s error interrupt enable is directly affected by writes to this register; it is also affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the EEI register. The DMA error indicator and the error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted to the interrupt controller. Address: DMA_EEI is 4000_8000h base + 14h offset = 4000_8014h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI9 EEI8 EEI7 EEI6 EEI5 EEI4 EEI3 EEI2 EEI1 EEI0W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_EEI field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. EEI15 Enable Error Interrupt 15

0 The error signal for corresponding channel does not generate an error interrupt

1 The assertion of the error signal for corresponding channel generates an error interrupt request

Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 454 Freescale Semiconductor, Inc.

DMA_EEI field descriptions (continued) Field Description EEI13 Enable Error Interrupt 13 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 455

DMA_EEI field descriptions (continued) Field Description

21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)

The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI to disable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_CEEI is 4000_8000h base + 18h offset = 4000_8018h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEE 0 CEEI Reset 0 0 0 0 0 0 0 0 DMA_CEEI field descriptions Field Description NOP

1 No operation, ignore the other bits in this register

Clear All Enable Error Interrupts

0 Clear only the EEI bit specified in the CEEI field

1 Clear all bits in EEI

5–4 Reserved This field is reserved. 3–0 CEEI Clear Enable Error Interrupt Clears the corresponding bit in EEI Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 456 Freescale Semiconductor, Inc.

21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)

The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_SEEI is 4000_8000h base + 19h offset = 4000_8019h Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAEE 0 SEEI Reset 0 0 0 0 0 0 0 0 DMA_SEEI field descriptions Field Description NOP Sets All Enable Error Interrupts 0 Set only the EEI bit specified in the SEEI field.

1 Sets all bits in EEI

5–4 Reserved This field is reserved. 3–0 SEEI Set Enable Error Interrupt Sets the corresponding bit in EEI Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 457

21.3.7 Clear Enable Request Register (DMA_CERQ)

The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a global clear function, forcing the entire contents of the ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_CERQ is 4000_8000h base + 1Ah offset = 4000_801Ah Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAER 0 CERQ Reset 0 0 0 0 0 0 0 0 DMA_CERQ field descriptions Field Description NOP

0 Clear only the ERQ bit specified in the CERQ field

1 Clear all bits in ERQ

5–4 Reserved This field is reserved. 3–0 CERQ Clear Enable Request Clears the corresponding bit in ERQ Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 458 Freescale Semiconductor, Inc.

21.3.8 Set Enable Request Register (DMA_SERQ)

The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_SERQ is 4000_8000h base + 1Bh offset = 4000_801Bh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAER 0 SERQ Reset 0 0 0 0 0 0 0 0 DMA_SERQ field descriptions Field Description NOP

0 Set only the ERQ bit specified in the SERQ field

1 Set all bits in ERQ

5–4 Reserved This field is reserved. 3–0 SERQ Set enable request Sets the corresponding bit in ERQ Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 459

21.3.9 Clear DONE Status Bit Register (DMA_CDNE)

The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_CDNE is 4000_8000h base + 1Ch offset = 4000_801Ch Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CADN 0 CDNE Reset 0 0 0 0 0 0 0 0 DMA_CDNE field descriptions Field Description NOP

0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field

1 Clears all bits in TCDn_CSR[DONE]

5–4 Reserved This field is reserved. 3–0 CDNE Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 460 Freescale Semiconductor, Inc.

21.3.10 Set START Bit Register (DMA_SSRT)

The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set. Setting the SAST bit provides a global set function, forcing all START bits to be set. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_SSRT is 4000_8000h base + 1Dh offset = 4000_801Dh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP SAST 0 SSRT Reset 0 0 0 0 0 0 0 0 DMA_SSRT field descriptions Field Description NOP Set All START Bits (activates all channels)

0 Set only the TCDn_CSR[START] bit specified in the SSRT field

1 Set all bits in TCDn_CSR[START]

5–4 Reserved This field is reserved. 3–0 SSRT Set START Bit Sets the corresponding bit in TCDn_CSR[START] Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 461

21.3.11 Clear Error Register (DMA_CERR)

The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a global clear function, forcing the ERR contents to be cleared, clearing all channel error indicators. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_CERR is 4000_8000h base + 1Eh offset = 4000_801Eh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAEI 0 CERR Reset 0 0 0 0 0 0 0 0 DMA_CERR field descriptions Field Description NOP Clear All Error Indicators

0 Clear only the ERR bit specified in the CERR field

1 Clear all bits in ERR

5–4 Reserved This field is reserved. 3–0 CERR Clear Error Indicator Clears the corresponding bit in ERR Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 462 Freescale Semiconductor, Inc.

21.3.12 Clear Interrupt Request Register (DMA_CINT)

The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a global clear function, forcing the entire contents of the INT to be cleared, disabling all DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. Address: DMA_CINT is 4000_8000h base + 1Fh offset = 4000_801Fh Bit 7 6 5 4 3 2 1 0 Read 0 0 0 Write NOP CAIR 0 CINT Reset 0 0 0 0 0 0 0 0 DMA_CINT field descriptions Field Description NOP Clear All Interrupt Requests

0 Clear only the INT bit specified in the CINT field

1 Clear all bits in INT

5–4 Reserved This field is reserved. 3–0 CINT Clear Interrupt Request Clears the corresponding bit in INT

21.3.13 Interrupt Request Register (DMA_INT)

The INT register provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel. Depending on the appropriate bit setting in the transfer-control descriptors, the eDMA engine generates an interrupt on data transfer completion. The outputs of this register are directly routed to the interrupt controller (INTC). During the interrupt-service routine associated with any given channel, it is the software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the CINT register in the interrupt service routine is used for this purpose. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 463

The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding channel’s current interrupt status. The CINT register is provided so the interrupt request for a single channel can easily be cleared without the need to perform a read-modify-write sequence to the INT register. Address: DMA_INT is 4000_8000h base + 24h offset = 4000_8024h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_INT field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. INT15 Interrupt Request 15

0 The interrupt request for corresponding channel is cleared

1 The interrupt request for corresponding channel is active

Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 464 Freescale Semiconductor, Inc.

DMA_INT field descriptions (continued) Field Description Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 465

21.3.14 Error Register (DMA_ERR)

The ERR provides a bit map for the 16 channels, signaling the presence of an error for each channel. The eDMA engine signals the occurrence of an error condition by setting the appropriate bit in this register. The outputs of this register are enabled by the contents of the EEI, and then routed to the interrupt controller. During the execution of the interrupt-service routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the CERR in the interrupt-service routine is used for this purpose. The normal DMA channel completion indicators (setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request) are not affected when an error is detected. The contents of this register can also be polled because a non-zero value indicates the presence of a channel error regardless of the state of the EEI. The state of any given channel’s error indicators is affected by writes to this register; it is also affected by writes to the CERR. On writes to the ERR, a one in any bit position clears the corresponding channel’s error status. A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. Address: DMA_ERR is 4000_8000h base + 2Ch offset = 4000_802Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ERR15 ERR14 ERR13 ERR12 ERR11 ERR10 ERR9 ERR8 ERR7 ERR6 ERR5 ERR4 ERR3 ERR2 ERR1 ERR0 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_ERR field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 466 Freescale Semiconductor, Inc.

DMA_ERR field descriptions (continued) Field Description ERR15 Error In Channel 15

0 An error in the corresponding channel has not occurred

1 An error in the corresponding channel has occurred

Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 467

DMA_ERR field descriptions (continued) Field Description

21.3.15 Hardware Request Status Register (DMA_HRS)

The HRS provides a bit map for the DMA channels, signaling the presence of a hardware request for each channel. The hardware request status bits reflect the current state of the register and qualified (via the ERQ fields) DMA request signals as seen by the DMA’s arbitration logic. This view into the hardware request signals may be used for debug purposes. NOTE These bits reflect the state of the request as seen by the arbitration logic. Therefore, this status is affected by the ERQ bits. Address: DMA_HRS is 4000_8000h base + 34h offset = 4000_8034h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 HRS15 HRS14 HRS13 HRS12 HRS11 HRS10 HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 468 Freescale Semiconductor, Inc.

DMA_HRS field descriptions Field Description 31–16 Reserved This read-only field is reserved and always has the value zero. HRS15 Hardware Request Status Channel 15

0 A hardware service request for the corresponding channel is not present

1 A hardware service request for the corresponding channel is present

Hardware Request Status Channel 14 Hardware Request Status Channel 13 Hardware Request Status Channel 12 Hardware Request Status Channel 11 Hardware Request Status Channel 10 Hardware Request Status Channel 9 Hardware Request Status Channel 8 Hardware Request Status Channel 7 Hardware Request Status Channel 6 Hardware Request Status Channel 5 Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 469

DMA_HRS field descriptions (continued) Field Description HRS4 Hardware Request Status Channel 4 Hardware Request Status Channel 3 Hardware Request Status Channel 2 Hardware Request Status Channel 1 Hardware Request Status Channel 0

21.3.16 Channel n Priority Register (DMA_DCHPRIn)

When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel. The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next priority, then 2, 3, etc. Software must program the channel priorities with unique values. Otherwise, a configuration error is reported. The range of the priority value is limited to the values of 0 through 15. Addresses: 4000_8000h base + 100h offset + (1d × n), where n = 0d to 15d Bit 7 6 5 4 3 2 1 0 Read ECP DPA CHPRI Write * Notes: x = Undefined at reset.• DMA_DCHPRIn field descriptions Field Description ECP Enable Channel Preemption Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 470 Freescale Semiconductor, Inc.

DMA_DCHPRIn field descriptions (continued) Field Description

0 Channel n cannot be suspended by a higher priority channel’s service request

1 Channel n can be temporarily suspended by the service request of a higher priority channel

0 Channel n can suspend a lower priority channel

1 Channel n cannot suspend any channel, regardless of channel priority

5–4 Reserved This read-only field is reserved and always has the value zero. 3–0 CHPRI Channel n Arbitration Priority Channel priority when fixed-priority arbitration is enabled NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.

21.3.17 TCD Source Address (DMA_TCD_SADDR)

Addresses: 4000_8000h base + 1000h offset + (32d × n), where n = 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SADDR W * Notes: x = Undefined at reset.• DMA_TCDn_SADDR field descriptions Field Description 31–0 SADDR Source Address Memory address pointing to the source data. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 471

21.3.18 TCD Signed Source Address Offset (DMA_TCD_SOFF)

Addresses: 4000_8000h base + 1004h offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SOFF Write * Notes: x = Undefined at reset.• DMA_TCDn_SOFF field descriptions Field Description 15–0 SOFF Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed.

21.3.19 TCD Transfer Attributes (DMA_TCD_ATTR)

Addresses: 4000_8000h base + 1006h offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read SMOD SSIZE DMOD DSIZE Write * Notes: x = Undefined at reset.• DMA_TCDn_ATTR field descriptions Field Description 15–11 SMOD Source Address Modulo.

0 Source address modulo feature is disabled

≠0 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed or the original register value. The setting of this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 472 Freescale Semiconductor, Inc.

DMA_TCDn_ATTR field descriptions (continued) Field Description 10–8 SSIZE Source data transfer size The attempted use of a Reserved encoding causes a configuration error. 000 8-bit 001 16-bit 010 32-bit

011 Reserved

7–3 DMOD Destination Address Modulo See the SMOD definition 2–0 DSIZE Destination Data Transfer Size See the SSIZE definition

21.3.20 TCD Minor Byte Count (Minor Loop Disabled)

(DMA_TCD_NBYTES_MLNO) TCD word 2's register definition depends on the status of minor loop mapping. If minor loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as follows. If minor loop mapping is enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions for TCD word 2's register definition. Addresses: 4000_8000h base + 1008h offset + (32d × n), where n = 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R NBYTES W * Notes: x = Undefined at reset.• DMA_TCDn_NBYTES_MLNO field descriptions Field Description 31–0 NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via preemption.) After the minor count Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 473

DMA_TCDn_NBYTES_MLNO field descriptions (continued) Field Description is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. NOTE: An NBYTES value of 0x0000_0000 is interpreted as a 4 GB transfer.

21.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and

Offset Disabled) (DMA_TCD_NBYTES_MLOFFNO) TCD word 2 is defined as follows if:

• Minor loop mapping is enabled (CR[EMLM] = 1) and
• SMLOE = 0 and DMLOE = 0 If minor loop mapping is enabled and SMLOE or DMLOE is set then refer to the TCD_NBYTES_MLOFFYES register description. Addresses: 4000_8000h base + 1008h offset + (32d × n), where n = 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SMLOE DMLOE NBYTES W * Notes: x = Undefined at reset.• DMA_TCDn_NBYTES_MLOFFNO field descriptions Field Description SMLOE Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion.

0 The minor loop offset is not applied to the SADDR

1 The minor loop offset is applied to the SADDR

Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion.

0 The minor loop offset is not applied to the DADDR

1 The minor loop offset is applied to the DADDR

29–0 NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 474 Freescale Semiconductor, Inc.

DMA_TCDn_NBYTES_MLOFFNO field descriptions (continued) Field Description As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted; although, it may be stalled by using the bandwidth control field, or via preemption. After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed.

21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset

Enabled) (DMA_TCD_NBYTES_MLOFFYES) TCD word 2 is defined as follows if:

• Minor loop mapping is enabled (CR[EMLM] = 1) and
• Minor loop offset enabled (SMLOE or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared then refer to the TCD_NBYTES_MLOFFNO register description. Addresses: 4000_8000h base + 1008h offset + (32d × n), where n = 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SMLOE DMLOE MLOFF NBYTES W * Notes: x = Undefined at reset.• DMA_TCDn_NBYTES_MLOFFYES field descriptions Field Description SMLOE Source Minor Loop Offset Enable Selects whether the minor loop offset is applied to the source address upon minor loop completion.

Destination Minor Loop Offset enable Selects whether the minor loop offset is applied to the destination address upon minor loop completion. 29–10 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 475

DMA_TCDn_NBYTES_MLOFFYES field descriptions (continued) Field Description 9–0 NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via preemption.) After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed.

21.3.23 TCD Last Source Address Adjustment (DMA_TCD_SLAST)

Addresses: 4000_8000h base + 100Ch offset + (32d × n), where n = 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SLAST W * Notes: x = Undefined at reset.• DMA_TCDn_SLAST field descriptions Field Description 31–0 SLAST Last source Address Adjustment Adjustment value added to the source address at the completion of the major iteration count. This value can be applied to restore the source address to the initial value, or adjust the address to reference the next data structure.

21.3.24 TCD Destination Address (DMA_TCD_DADDR)

Addresses: 4000_8000h base + 1010h offset + (32d × n), where n = 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DADDR W * Notes: x = Undefined at reset.• Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 476 Freescale Semiconductor, Inc.

DMA_TCDn_DADDR field descriptions Field Description 31–0 DADDR Destination Address Memory address pointing to the destination data.

21.3.25 TCD Signed Destination Address Offset (DMA_TCD_DOFF)

Addresses: 4000_8000h base + 1014h offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read DOFF Write * Notes: x = Undefined at reset.• DMA_TCDn_DOFF field descriptions Field Description 15–0 DOFF Destination Address Signed offset Sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed.

21.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel

Linking Enabled) (DMA_TCD_CITER_ELINKYES) If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows. Addresses: 4000_8000h base + 1016h offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ELINK LINKCH CITER Write * Notes: x = Undefined at reset.• Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 477

DMA_TCDn_CITER_ELINKYES field descriptions Field Description ELINK Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit. Otherwise, a configuration error is reported.

0 The channel-to-channel linking is disabled

1 The channel-to-channel linking is enabled

14–13 Reserved This read-only field is reserved and always has the value zero. 12–9 LINKCH Link Channel Number If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request to the channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit. 8–0 CITER Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.

21.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel

Linking Disabled) (DMA_TCD_CITER_ELINKNO) If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as follows. Addresses: 4000_8000h base + 1016h offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ELINK CITER Write * Notes: x = Undefined at reset.• Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 478 Freescale Semiconductor, Inc.

DMA_TCDn_CITER_ELINKNO field descriptions Field Description ELINK Enable channel-to-channel linking on minor-loop complete As the channel completes the minor loop, this flag enables linking to another channel, defined by the LINKCH field. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: This bit must be equal to the BITER[ELINK] bit. Otherwise, a configuration error is reported. 14–0 CITER Current Major Iteration Count This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. It is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the CITER field from the beginning iteration count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.

21.3.28 TCD Last Destination Address Adjustment/Scatter Gather

Address (DMA_TCD_DLASTSGA) Addresses: 4000_8000h base + 1018h offset + (32d × n), where n = 0d to 15d Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R DLASTSGA W * Notes: x = Undefined at reset.• DMA_TCDn_DLASTSGA field descriptions Field Description 31–0 DLASTSGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather). If (TCDn_CSR[ESG] = 0) then

• Adjustment value added to the destination address at the completion of the major iteration count. This value can apply to restore the destination address to the initial value or adjust the address to reference the next data structure. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 479

DMA_TCDn_DLASTSGA field descriptions (continued) Field Description else

• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer control descriptor to be loaded into this channel. This channel reload is performed as the major iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a configuration error is reported.

21.3.29 TCD Control and Status (DMA_TCD_CSR)

Addresses: 4000_8000h base + 101Ch offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read BWC MAJORLINKCH DONE ACTIVE MAJORELINK ESG DREQ INTHALF INTMAJOR STARTWrite * Notes: x = Undefined at reset.• DMA_TCDn_CSR field descriptions Field Description 15–14 BWC Bandwidth Control Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch. NOTE: If the source and destination sizes are equal, this field is ignored between the first and second transfers and after the last write of each minor loop. This behavior is a side effect of reducing start-up latency.

00 No eDMA engine stalls

10 eDMA engine stalls for 4 cycles after each r/w 11 eDMA engine stalls for 8 cycles after each r/w 13–12 Reserved This read-only field is reserved and always has the value zero. 11–8 MAJORLINKCH Link Channel Number If (MAJORELINK = 0) then

• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted. else Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 480 Freescale Semiconductor, Inc.

DMA_TCDn_CSR field descriptions (continued) Field Description

• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit. DONE Channel Done This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero; The software clears it, or the hardware when the channel is activated. NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. ACTIVE Channel Active This flag signals the channel is currently in execution. It is set when channel service begins, and the eDMA clears it as the minor loop completes or if any error condition is detected. This bit resets to zero. MAJORELINK Enable channel-to-channel linking on major loop complete As the channel completes the major loop, this flag enables the linking to another channel, defined by MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.

Enable Scatter/Gather Processing As the channel completes the major loop, this flag enables scatter/gather processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. 0 The current channel’s TCD is normal format. 1 The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. DREQ Disable Request If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current major iteration count reaches zero.

0 The channel’s ERQ bit is not affected

1 The channel’s ERQ bit is cleared when the major loop is complete

Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT register when the current major iteration count reaches the halfway point. Specifically, the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is provided to support double-buffered (aka ping-pong) schemes or other types of data movement where the processor needs an early indication of the transfer’s progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead. Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 481

DMA_TCDn_CSR field descriptions (continued) Field Description

0 The half-point interrupt is disabled

1 The half-point interrupt is enabled

Enable an interrupt when major iteration count completes If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when the current major iteration count reaches zero.

0 The end-of-major loop interrupt is disabled

1 The end-of-major loop interrupt is enabled

If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution.

0 The channel is not explicitly started

1 The channel is explicitly started via a software initiated service request

21.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel

Linking Enabled) (DMA_TCD_BITER_ELINKYES) If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as follows. Addresses: 4000_8000h base + 101Eh offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ELINK LINKCH BITER Write * Notes: x = Undefined at reset.• DMA_TCDn_BITER_ELINKYES field descriptions Field Description ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking disables, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. Table continues on the next page... Memory map/register definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 482 Freescale Semiconductor, Inc.

DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description 14–13 Reserved This read-only field is reserved and always has the value zero. 12–9 LINKCH Link Channel Number If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA engine initiates a channel service request at the channel defined by these four bits by setting that channel’s TCDn_CSR[START] bit. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. 8–0 BITER Starting Major Iteration Count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.

21.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel

Linking Disabled) (DMA_TCD_BITER_ELINKNO) If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined as follows. Addresses: 4000_8000h base + 101Eh offset + (32d × n), where n = 0d to 15d Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read ELINK BITER Write * Notes: x = Undefined at reset.• DMA_TCDn_BITER_ELINKNO field descriptions Field Description ELINK Enables channel-to-channel linking on minor loop complete As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER Table continues on the next page... Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 483

DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. 14–0 BITER Starting Major Iteration Count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.

21.4 Functional description

21.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 484 Freescale Semiconductor, Inc.

Descriptor (TCD) Figure 21-289. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n. Channel activation via software and the TCDn_CSR[START] bit follows the same basic flow as peripheral requests. The eDMA request input signal is registered internally and then routed through the eDMA engine: first through the control module, then into the program model and channel arbitration. In the next cycle, the channel arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is complete, the activated channel number is sent through the address path and converted into the required address to access the local memory for TCDn. Next, the TCD memory is accessed and the required descriptor read from the local memory and loaded into the eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to minimize the time needed to fetch the activated channel descriptor and load it into the address path channel x or y registers. The following diagram illustrates the second part of the basic data flow: Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 485

Descriptor (TCD) Internal Peripheral Bus Figure 21-290. eDMA operation, part 2 The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement. The source reads are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write. This source read/destination write processing continues until the minor byte count has transferred. After the minor byte count has moved, the final phase of the basic data flow is performed. In this segment, the address path logic performs the required updates to certain fields in the appropriate TCD, e.g., SADDR, DADDR, CITER. If the major iteration count is exhausted, additional operations are performed. These include the final address adjustments and reloading of the BITER field into the CITER. Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from memory using the scatter/gather address pointer included in the descriptor (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 486 Freescale Semiconductor, Inc.

Descriptor (TCD) Internal Peripheral Bus Figure 21-291. eDMA operation, part 3

21.4.2 Error reporting and handling

Channel errors are reported in the ES register and can be caused by:

• A configuration error, which is an illegal setting in the transfer-control descriptor or an illegal priority register setting in Fixed-Arbitration mode, or
• An error termination to a bus master read or write cycle A configuration error is reported when the starting source or destination address, source or destination offsets, minor loop byte count, or the transfer size represent an inconsistent state. Each of these possible causes are detailed below:
• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer sizes. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 487

• All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively.
• In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal. All channel priority levels must be unique when fixed arbitration mode is enabled.
• If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the scatter/gather address (DLAST_SGA) is not aligned on a 32- byte boundary.
• If minor loop channel linking is enabled upon channel completion, a configuration error is reported when the link is attempted if the TCDn_CITER[E_LINK] bit does not equal the TCDn_BITER[E_LINK] bit. If enabled, all configuration error conditions, except the scatter/gather and minor-loop link errors, report as the channel activates and asserts an error interrupt request. A scatter/ gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enabled. A minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. In this case, the state of the channel's transfer control descriptor is updated by the eDMA engine with the current source address, destination address, and current iteration count at the point of the fault. When a system-bus error occurs, the channel terminates after the read or write transaction, which is already pipelined after errant access, has completed. If a bus error occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error. A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer request is recognized, the DMA engine stops processing the channel. The current read- write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of a major or minor loop, the cancel request is discarded and the channel retires normally. The error cancel transfer is the same as a cancel transfer except the ES register is updated with the cancelled channel number and ECX is set. The TCD of a cancelled channel contains the source and destination addresses of the last transfer saved in the TCD. If the channel needs to be restarted, you must re-initialize the TCD because the aforementioned fields no longer represent the original parameters. When a transfer is cancelled by the error cancel transfer mechanism, the channel number is loaded into DMA_ES[ERRCHN] and ECX and VLD are set. In addition, an error interrupt may be generated if enabled. The occurrence of any error causes the eDMA engine to stop the active channel immediately, and the appropriate channel bit in the eDMA error register is asserted. At the same time, the details of the error condition are loaded into the ES register. The major Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 488 Freescale Semiconductor, Inc.

loop complete indicators, setting the transfer control descriptor DONE flag and the possible assertion of an interrupt request, are not affected when an error is detected. After the error status has been updated, the eDMA engine continues operating by servicing the next appropriate channel. A channel that experiences an error condition is not automatically disabled. If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition.

21.4.3 Channel preemption

Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel preemption allows the executing channel’s data transfers to temporarily suspend in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. After the restored channel completes one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting service, the restored channel is suspended and the higher priority channel is serviced. Nested preemption, that is, attempting to preempt a preempting channel, is not supported. After a preempting channel begins execution, it cannot be preempted. Preemption is available only when fixed arbitration is selected. A channel’s ability to preempt another channel can be disabled by setting DCHPRIn[DPA]. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s ECP setting. This allows for a pool of low priority, large data-moving channels to be defined. These low priority channels can be configured to not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally available to a true, high priority channel.

21.4.4 Performance

This section addresses the performance of the eDMA module, focusing on two separate metrics:

• In the traditional data movement context, performance is best expressed as the peak data transfer rates achieved using the eDMA. In most implementations, this transfer rate is limited by the speed of the source and destination address spaces.
• In a second context where device-paced movement of single data values to/from peripherals is dominant, a measure of the requests that can be serviced in a fixed time is a more relevant metric. In this environment, the speed of the source and destination Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 489

address spaces remains important. However, the microarchitecture of the eDMA also factors significantly into the resulting metric.

21.4.4.1 Peak transfer rates

The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume:

• Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase
• All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states, when viewed from the system bus data phase
• All internal peripheral bus accesses are 32-bits in size This table presents a peak transfer rate comparison. Table 21-292. eDMA peak transfer rates (Mbytes/sec) System Speed, Width Internal SRAM-to- Internal SRAM 32b internal peripheral bus- to- Internal SRAM Internal SRAM-to- 32b internal peripheral bus 66.7 MHz, 32b 133.3 66.7 53.3 83.3 MHz, 32b 166.7 83.3 66.7 100.0 MHz, 32b 200.0 100.0 80.0 133.3 MHz, 32b 266.7 133.3 106.7 150.0 MHz, 32b 300.0 150.0 120.0 Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases, the transfer rate includes the time to read the source plus the time to write the destination.

21.4.4.2 Peak request rates

The second performance metric is a measure of the number of DMA requests that can be serviced in a given amount of time. For this metric, assume that the peripheral request causes the channel to move a single internal peripheral bus-mapped operand to/from internal SRAM. The same timing assumptions used in the previous example apply to this calculation. In particular, this metric also reflects the time required to activate the channel. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 490 Freescale Semiconductor, Inc.

The eDMA design supports the following hardware service request sequence: Table 21-293. Hardware service request process, cycles 1–7 Cycle Description 1 eDMA peripheral request is asserted.

2 The eDMA peripheral request is registered locally in the

eDMA module and qualified. TCDn_CSR[START] bit initiated requests start at this point with the registering of the user write to TCDn word 7. 3 Channel arbitration begins. 4 Channel arbitration completes. The transfer control descriptor local memory read is initiated. 5–6 The first two parts of the activated channel's TCD is read from the local memory. The memory width to the eDMA engine is 64 bits, so the entire descriptor can be accessed in four cycles.

7 The first system bus read cycle is initiated, as the third part of

the channel's TCD is read from the local memory. Depending on the state of the crossbar switch, arbitration at the system bus may insert an additional cycle of delay here. The exact timing from this point is a function of the response times for the channel's read and write accesses. In the case of an internal peripheral bus read and internal SRAM write, the combined data phase time is 4 cycles. For an SRAM read and internal peripheral bus write, it is 5 cycles. Table 21-294. Hardware service request process, cycles 8–17 Cycle, with internal peripheral bus read and internal SRAM write Cycle, with SRAM read and internal peripheral bus write 8–11 8–12 The last part of the TCD is read in. This cycle represents the first data phase for the read, and the address phase for the destination write. 12 13 This cycle represents the data phase of the last destination write. 13 14 The eDMA engine completes the execution of the inner minor loop and prepares to write back the required TCDn fields into the local memory. The TCDn word 7 is read and checked for channel linking or scatter/gather requests. 14 15 The appropriate fields in the first part of the TCDn are written back into the local memory. 15 16 The fields in the second part of the TCDn are written back into the local memory. This cycle coincides with the next channel arbitration cycle start. 16 17 The next channel to be activated performs the read of the first part of its TCD from the local memory. This is equivalent to Cycle 4 for the first channel's service request. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 491

Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with internal peripheral bus- to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle ? +5. The resulting peak request rate, as a function of the system frequency, is shown in the following table. Table 21-295. eDMA peak request rate (MReq/sec) System frequecy (MHz) Request rate with zero wait states Request rate with wait states 66.6 7.4 5.8 83.3 9.2 7.2 100.0 11.1 8.7 133.3 14.8 11.6 150.0 16.6 13.0 A general formula to compute the peak request rate with overlapping requests is: PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: Table 21-296. Peak request formula legend Where Represents PEAKreq Peak request rate freq System frequency entry Channel startup (4 cycles) read_ws Wait states seen during the system bus read data phase write_ws Wait states seen during the system bus write data phase xit Channel shutdown (3 cycles) For example, consider a system with the following characteristics:

• Internal SRAM can be accessed with one wait-state when viewed from the system bus data phase
• All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase
• System operates at 150 MHz For an SRAM to internal peripheral bus transfer, Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 492 Freescale Semiconductor, Inc.

PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec For an internal peripheral bus to SRAM transfer, PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate would be: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a cold start where no channel is executing and eDMA is idle are:

• 11 cycles for a software, that is, a TCD n_CSR[START] bit, request
• 12 cycles for a hardware, that is, an eDMA peripheral request signal, request Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from the internal registering of the eDMA peripheral request signals. For the peak request rate calculations above, the arbitration and request registering is absorbed in or overlaps the previous executing channel. Note When channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selection and startup. This allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for next channel selection.

21.5 Initialization/application information

The following sections discuss initialization of the eDMA and programming considerations. 21.5.1 eDMA initialization A typical initialization of the eDMA has the following sequence: 1. Write the CR register if a configuration other than the default is desired. 2. Write the channel priority levels into the DCHPRI n registers if a configuration other than the default is desired. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 493

1. Enable error interrupts in the EEI register if so desired. 4. Write the 32-byte TCD for each channel that may request service. 5. Enable any hardware service requests via the ERQ register. 6. Request channel service via either:

• Software: setting the TCD n_CSR[START] bit
• Hardware: slave device asserting its eDMA peripheral request signal After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model. The eDMA engine reads the entire TCD, including the TCD control and status fields, as shown in the following table, for the selected channel into its internal address path module. As the TCD is read, the first transfer is initiated on the internal bus unless a configuration error is detected. Transfers from the source, as defined by the source address, TCDn_SADDR, to the destination, as defined by the destination address, TCDn_DADDR, continue until the specified number of bytes (TCDn_NBYTES) are transferred. When the transfer is complete, the eDMA engine's local TCDn_SADDR, TCDn_DADDR, and TCDn_CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes, such as interrupts, major loop channel linking, and scatter/gather operations, if enabled. Table 21-297. TCD Control and Status fields TCDn_CSR field name Description START Control bit to start channel explicitly when using a software initiated DMA service (Automatically cleared by hardware) ACTIVE Status bit indicating the channel is currently in execution DONE Status bit indicating major loop completion (cleared by software when using a software initiated DMA service) D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated DMA service BWC Control bits for throttling bandwidth control of a channel E_SG Control bit to enable scatter-gather feature INT_HALF Control bit to enable interrupt when major loop is half complete INT_MAJ Control bit to enable interrupt when major loop completes Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 494 Freescale Semiconductor, Inc.

21.5.2 Programming errors

The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). For all error types other than channel priority error, the channel number causing the error is recorded in the ES register. If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again. If priority levels are not unique, when any channel requests service, a channel priority error is reported. The highest channel priority with an active request is selected, but the lowest numbered channel with that priority is selected by arbitration and executed by the eDMA engine. The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel.

21.5.3 Arbitration mode considerations

21.5.3.1 Fixed channel arbitration

In this mode, the channel service request from the highest priority channel is selected to execute.

21.5.3.2 Round-robin channel arbitration

Channels are serviced starting with the highest channel number and rotating through to the lowest channel number without regard to the channel priority levels.

21.5.4 Performing DMA transfers

21.5.4.1 Single request

To perform a simple transfer of n bytes of data with one activation, set the major loop to one (TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 496 Freescale Semiconductor, Inc.

For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a 32-bit port located at 0x2000. The address offsets are programmed in increments to match the transfer size: one byte for the source and four bytes for the destination. The final source and destination addresses are adjusted to return to their beginning values. TCDn_CITER = TCDn_BITER = 1 TCDn_NBYTES = 16 TCDn_SADDR = 0x1000 TCDn_SOFF = 1 TCDn_ATTR[SSIZE] = 0 TCDn_SLAST = -16 TCDn_DADDR = 0x2000 TCDn_DOFF = 4 TCDn_ATTR[DSIZE] = 2 TCDn_DLAST_SGA= –16 TCDn_CSR[INT_MAJ] = 1 TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized) All other TCDn fields = 0 This generates the following event sequence: 1. User write to the TCD n_CSR[START] bit requests channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCD n_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCD data from local memory to internal register file. 5. The source-to-destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 → first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. f. Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 497

h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop complete. 6. The eDMA engine writes: TCD n_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCD n_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 8. The channel retires and the eDMA goes idle or services the next channel.

21.5.4.2 Multiple requests

The following example transfers 32 bytes via two hardware requests, but is otherwise the same as the previous example. The only fields that change are the major loop iteration count and the final address offsets. The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration. After the channel's hardware requests are enabled in the ERQ register, the slave device initiates channel service requests. TCDn_CITER = TCDn_BITER = 2 TCDn_SLAST = –32 TCDn_DLAST_SGA = –32 This would generate the following sequence of events: 1. First hardware, that is, eDMA peripheral, request for channel service. 2. The channel is selected by arbitration for servicing. 3. eDMA engine writes: TCD n_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 4. eDMA engine reads: channel TCD n data from local memory to internal register file. 5. The source to destination transfers are executed as follows: a. Read byte from location 0x1000, read byte from location 0x1001, read byte from 0x1002, read byte from 0x1003. b. Write 32-bits to location 0x2000 → first iteration of the minor loop. c. Read byte from location 0x1004, read byte from location 0x1005, read byte from 0x1006, read byte from 0x1007. d. Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 498 Freescale Semiconductor, Inc.

f. Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop. 6. eDMA engine writes: TCD n_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1. 7. eDMA engine writes: TCD n_CSR[ACTIVE] = 0. 8. The channel retires → one iteration of the major loop. The eDMA goes idle or services the next channel. 9. Second hardware, that is, eDMA peripheral, requests channel service. 10. The channel is selected by arbitration for servicing. 11. eDMA engine writes: TCD n_CSR[DONE] = 0, TCDn_CSR[START] = 0, TCDn_CSR[ACTIVE] = 1. 12. eDMA engine reads: channel TCD data from local memory to internal register file. 13. The source to destination transfers are executed as follows: a. Read byte from location 0x1010, read byte from location 0x1011, read byte from 0x1012, read byte from 0x1013. b. Write 32-bits to location 0x2010 → first iteration of the minor loop. c. Read byte from location 0x1014, read byte from location 0x1015, read byte from 0x1016, read byte from 0x1017. d. Write 32-bits to location 0x2014 → second iteration of the minor loop. e. Read byte from location 0x1018, read byte from location 0x1019, read byte from 0x101A, read byte from 0x101B. f. Write 32-bits to location 0x2018 → third iteration of the minor loop. g. Read byte from location 0x101C, read byte from location 0x101D, read byte from 0x101E, read byte from 0x101F. h. Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCD n_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 499

1. eDMA engine writes: TCD n_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel.

21.5.4.3 Using the modulo feature

The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and destination in the TCD, and it specifies which lower address bits increment from their original value after the address+offset calculation. All upper address bits remain the same as in the original value. A setting of 0 for this field disables the modulo feature. The following table shows how the transfer addresses are specified based on the setting of the MOD field. Here a circular buffer is created where the address wraps to the original value while the 28 upper address bits (0x1234567x) retain their original value. In this example the source address is set to 0x12345670, the offset is set to 4 bytes and the MOD field is set to 4, allowing for a 24 byte (16-byte) size queue. Table 21-298. Modulo example Transfer Number Address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567C 5 0x12345670 6 0x12345674

21.5.5 Monitoring transfer descriptor status

21.5.5.1 Testing for minor loop completion

There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loop- Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 500 Freescale Semiconductor, Inc.

complete condition is indicated by both bits reading zero after the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration. The TCD status bits execute the following sequence for a software activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 1 0 0 Channel service request via software 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle The best method to test for minor-loop completion when using hardware, that is, peripheral, initiated service requests is to read the TCDn_CITER field and test for a change. The hardware request and acknowledge handshake signals are not visible in the programmer's model. The TCD status bits execute the following sequence for a hardware-activated channel: Stage TCDn_CSR bits State START ACTIVE DONE 1 0 0 0 Channel service request via hardware (peripheral request asserted) 2 0 1 0 Channel is executing 3a 0 0 0 Channel has completed the minor loop and is idle 3b 0 0 1 Channel has completed the major loop and is idle For both activation types, the major-loop-complete status is explicitly indicated via the TCDn_CSR[DONE] bit. The TCDn_CSR[START] bit is cleared automatically when the channel begins execution regardless of how the channel activates.

21.5.5.2 Reading the transfer descriptors of active channels

The eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTES values if read while a channel executes. The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 501

DADDR, and NBYTES, decrements to zero as the transfer progresses, can give an indication of the progress of the transfer. All other values are read back from the TCD local memory.

21.5.5.3 Checking channel preemption status

Preemption is available only when fixed arbitration is selected as the channel arbitration mode. A preemptive situation is one in which a preempt-enabled channel runs and a higher priority request becomes active. When the eDMA engine is not operating in fixed channel arbitration mode, the determination of the actively running relative priority outstanding requests become undefined. Channel priorities are treated as equal, that is, constantly rotating, when Round-Robin Arbitration mode is selected. The TCDn_CSR[ACTIVE] bit for the preempted channel remains asserted throughout the preemption. The preempted channel is temporarily suspended while the preempting channel executes one major loop iteration. If two TCDn_CSR[ACTIVE] bits are set simultaneously in the global TCD map, a higher priority channel is actively preempting a lower priority channel.

21.5.6 Dynamic programming

21.5.6.1 Dynamically changing the channel priority

The following two options are recommended for dynamically changing channel priority levels: 1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities, then switch back to Fixed Arbitration mode, 2. Disable all the channels, change the channel priorities, then enable the appropriate channels.

21.5.6.2 Dynamically changing the channel linking and scatter/gather

Dynamic channel linking and dynamic scatter/gather is the process of changing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits during channel execution. These bits are read from the TCD local memory at the end of channel execution, therefore allowing software to enable either feature during channel execution. Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 502 Freescale Semiconductor, Inc.

Because software can change the configuration during execution, a coherency sequence must be followed. Consider the scenario the user attempts to execute a dynamic channel link by enabling the TCDn_CSR[MAJOR_E_LINK] bit as the eDMA engine retires the channel. The TCDn_CSR[MAJOR_E_LINK] would be set in the programmer's model, but it would be indeterminate whether the actual link was made before the channel retired. The following coherency sequence is recommended when executing a dynamic channel link or dynamic scatter/gather request: 1. Set the TCD n_CSR[MAJOR_E_LINK] bit. 2. Read back the TCD n_CSR[MAJOR_E_LINK] bit. 3. Test the TCD n_CSR[MAJOR_E_LINK] request status. a. If the bit is set, the dynamic link attempt was successful. b. If the bit is cleared, the attempted dynamic link did not succeed, the channel was already retiring. This coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the TCD local memory controller forces the TCDn_CSR[MAJOR_E_LINK] and TCDn_CSR[E_SG] bits to zero on any writes to a TCDn after the TCDn_CSR[DONE] bit for that channel is set, indicating that the major loop is complete. Note Software must clear the TCDn_CSR[DONE] bit before writing the TCDn_CSR[MAJOR_E_LINK] or TCDn_CSR[E_SG] bits. The TCDn_CSR[DONE] bit is cleared automatically by the eDMA engine after a channel begins execution. Chapter 21 Direct Memory Access Controller (eDMA) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 503

Initialization/application information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 504 Freescale Semiconductor, Inc.

External Watchdog Monitor (EWM)

22.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits. The overflow of the watchdog counter must not occur if the software code works well and services the watchdog to re-start the actual counter. For safety, a redundant watchdog system, External Watchdog Monitor (EWM), is designed to monitor external circuits, as well as the MCU software flow. This provides a back-up mechanism to the internal watchdog that resets the MCU's CPU and peripherals. The EWM differs from the internal watchdog in that it does not reset the MCU's CPU and peripherals. The EWM if allowed to time-out, provides an independent EWM_out pin that when asserted resets or places an external circuit into a safe mode. The CPU resets the EWM counter that is logically ANDed with an external digital input pin. This pin allows an external circuit to influence the reset_out signal.

22.1.1 Features

Features of EWM module include:

• Independent LPO clock source
• Programmable time-out period specified in terms of number of EWM LPO clock cycles. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 505

• Windowed refresh option
• Provides robust check that program flow is faster than expected.
• Programmable window.
• Refresh outside window leads to assertion of EWM_out.
• Robust refresh mechanism
• Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 (EWM_service_time) peripheral bus clock cycles.
• One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode.
• One Input port, EWM_in, allows an external circuit to control the EWM_out signal.

22.1.2 Modes of Operation

This section describes the module's operating modes.

22.1.2.1 Stop Mode

When the EWM is in stop mode, the CPU services to the EWM cannot occur. On entry to stop mode, the EWM’s counter freezes. There are two possible ways to exit from Stop mode:

• On exit from stop mode through a reset, the EWM remains disabled.
• On exit from stop mode by an interrupt, the EWM is re-enabled, and the counter continues to be clocked from the same value prior to entry to stop mode. Note the following if the EWM enters the stop mode during CPU service mechanism: At the exit from stop mode by an interrupt, refresh mechanism state machine starts from the previous state which means, if first service command is written correctly and EWM enters the stop mode immediately, the next command has to be written within the next 15 (EWM_service_time) peripheral bus clocks after exiting from stop mode. User must mask all interrupts prior to executing EWM service instructions. Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 506 Freescale Semiconductor, Inc.

22.1.2.2 Wait Mode

The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes.

22.1.2.3 Debug Mode

Entry to debug mode has no effect on the EWM.

• If the EWM is enabled prior to entry of debug mode, it remains enabled.
• If the EWM is disabled prior to entry of debug mode, it remains disabled.

22.1.3 Block Diagram

This figure shows the EWM block diagram. Clock Gating Cell EWM_out EWM Out Logic EWM_out OR Low Power Clock Enable Counter Overflow CPU Reset Reset to Counter EWM refresh EWM enable Counter >Compare High Counter < Compare Low AND ~EWM_in_enable) Compare High > Counter > Compare Low1 Figure 22-1. EWM Block Diagram Chapter 22 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 507

22.2 EWM Signal Descriptions

The EWM has two external signals, as shown in the following table. Table 22-1. EWM Signal Descriptions Signal Description I/O EWM_in EWM input for safety status of external safety circuits. The polarity of EWM_in is programmable using the CTRL[ASSIN] bit. The default polarity is active-low. I EWM_out EWM reset out signal O

22.3 Memory Map/Register Definition

This section contains the module memory map and registers. EWM memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4006_1000 Control Register (EWM_CTRL) 8 R/W 00h 22.3.1/ 508 4006_1001 Service Register (EWM_SERV) 8 W (always reads zero) 00h 22.3.2/ 509 4006_1002 Compare Low Register (EWM_CMPL) 8 R/W 00h 22.3.3/ 510 4006_1003 Compare High Register (EWM_CMPH) 8 R/W FFh 22.3.4/ 510

22.3.1 Control Register (EWM_CTRL)

The CTRL register is cleared by any reset. NOTE This register can be written only once after a CPU reset. Writing this register more than once, generates a bus transfer error. EWM Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 508 Freescale Semiconductor, Inc.

Address: EWM_CTRL is 4006_1000h base + 0h offset = 4006_1000h Bit 7 6 5 4 3 2 1 0 Read 0 INEN ASSIN EWMEN Write Reset 0 0 0 0 0 0 0 0 EWM_CTRL field descriptions Field Description 7–3 Reserved This read-only field is reserved and always has the value zero. INEN Input Enable. This bit when set, enables the EWM_in port. ASSIN EWM_in's Assertion State Select. Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit inverts the assert state to a logic one. EWMEN EWM enable. This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and therefore it cannot be enabled until a reset occurs, due to the write-once nature of this bit.

22.3.2 Service Register (EWM_SERV)

The SERV register provides the interface from the CPU to the EWM module. It is write- only and reads of this register return zero. Address: EWM_SERV is 4006_1000h base + 1h offset = 4006_1001h Bit 7 6 5 4 3 2 1 0 Read 0 Write SERVICE Reset 0 0 0 0 0 0 0 0 EWM_SERV field descriptions Field Description 7–0 SERVICE The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The EWM service is illegal if either of the following conditions is true.

• The first or second data byte is not written correctly.
• The second data byte is not written within a fixed number of peripheral bus cycles of the first data byte. This fixed number of cycles is called EWM_service_time. Chapter 22 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 509

22.3.3 Compare Low Register (EWM_CMPL)

The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to service the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. Address: EWM_CMPL is 4006_1000h base + 2h offset = 4006_1002h Bit 7 6 5 4 3 2 1 0 Read COMPAREL Write Reset 0 0 0 0 0 0 0 0 EWM_CMPL field descriptions Field Description 7–0 COMPAREL To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum service time is required.

22.3.4 Compare High Register (EWM_CMPH)

The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256 clocks time, for the CPU to service the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error. NOTE The valid values for CMPH are up to 0xFE because the EWM counter never expires when CMPH = 0xFF. The expiration happens only if EWM counter is greater than CMPH. Address: EWM_CMPH is 4006_1000h base + 3h offset = 4006_1003h Bit 7 6 5 4 3 2 1 0 Read COMPAREH Write Reset 1 1 1 1 1 1 1 1 Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 510 Freescale Semiconductor, Inc.

EWM_CMPH field descriptions Field Description 7–0 COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum service time is required.

22.4 Functional Description

The following sections describe functional details of the EWM module.

22.4.1 The EWM_out Signal

The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. The EWM_out signal remains deasserted when the EWM is being regularly serviced by the CPU within the programmable service window, indicating that the application code is executed as expected. The EWM_out signal is asserted in any of the following conditions:

• Servicing the EWM when the counter value is less than CMPL value.
• If the EWM counter value reaches the CMPH value, and no EWM service has occurred.
• Servicing the EWM when the counter value is more than CMPL and less than CMPH values and EWM_in signal is asserted.
• After any reset (by the virtue of the external pull-down mechanism on the EWM_out pin) On a normal reset, the EWM_out is asserted. To deassert the EWM_out, set EWMEN bit in the CTRL register to enable the EWM. If the EWM_out signal shares its pad with a digital I/O pin, on reset this actual pad defers to being an input signal. It takes the EWM_out output condition only after you enable the EWM by the EWMEN bit in the CTRL register. When the EWM_out pin is asserted, it can only be deasserted by forcing a MCU reset. Chapter 22 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 511

EWM_out pad must be in pull down state when EWM functionality is used and when EWM is under Reset.

22.4.2 The EWM_in Signal

The EWM_in is a digital input signal that allows an external circuit to control the EWM_out signal. For example, in the application, an external circuit monitors a critical safety function, and if there is fault with this circuit's behavior, it can then actively initiate the EWM_out signal that controls the gating circuit. The EWM_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register is cleared, as after any reset. On enabling the EWM (setting the CTRL[EWMEN] bit) and enabling EWM_in functionality (setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU servicing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out pin is asserted. Note You must update the CMPH and CMPL registers prior to enabling the EWM. After enabling the EWM, the counter resets to zero, therefore providing a reasonable time after a power-on reset for the external monitoring circuit to stabilize and ensure that the EWM_in pin is deasserted.

22.4.3 EWM Counter

It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock source should be in the kHz range. The counter is reset to zero, after a CPU reset, or a EWM refresh cycle. The counter value is not accessible to the CPU.

22.4.4 EWM Compare Registers

The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be modified until another CPU reset occurs. Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 512 Freescale Semiconductor, Inc.

The EWM compare registers are used to create a service window, which is used by the CPU to service/refresh the EWM module.

• If the CPU services the EWM when the counter value lies between CMPL value and CMPH value, the counter is reset to zero. This is a legal service operation.
• If the CPU executes a EWM service/refresh action outside the legal service window, EWM_out is asserted. It is illegal to program CMPL and CMPH with same value. In this case, as soon as counter reaches (CMPL + 1), EWM_out is asserted.

22.4.5 EWM Refresh Mechanism

Other than the initial configuration of the EWM, the CPU can only access the EWM by the EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers. Therefore, three possible conditions can occur: Table 22-7. EWM Refresh Mechanisms Condition Mechanism A unique EWM service occurs when CMPL < Counter < CMPH. The software behaves as expected and the counter of the EWM is reset to zero, and EWM_out pin remains in the deasserted state. Note: EWM_in pin is also assumed to be in the deasserted state. A unique EWM service occurs when Counter < CMPL The software services the EWM and therefore resets the counter to zero and asserts the EWM_out pin (irrespective of the EWM_in pin). The EWM_out pin is expected to gate critical safety circuits. Counter value reaches CMPH prior to a unique EWM service The counter value reaches the CMPH value and no service of the EWM resets the counter to zero and assert the EWM_out pin (irrespective of the EWM_in pin). The EWM_out pin is expected to gate critical safety circuits. Any illegal service on EWM has no effect on EWM_out. Chapter 22 External Watchdog Monitor (EWM) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 513

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 514 Freescale Semiconductor, Inc.

Watchdog Timer (WDOG)

23.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Some reasons for such failures are: run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation. The watchdog monitors the operation of the system by expecting periodic communication from the software, generally known as servicing or refreshing the watchdog. If this periodic refreshing does not occur, the watchdog resets the system.

23.2 Features

The features of the Watchdog Timer (WDOG) include:

• Independent clock source input (independent from CPU/bus clock). Choice between two clock sources:
• LPO Oscillator
• External system clock
• Unlock sequence for allowing updates to write-once WDOG control/configuration bits.
• All WDOG control/configuration bits are writable once only within 256 bus clock cycles of being unlocked. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 515

• You need to always update these bits after unlocking within 256 bus clock cycles. Failure to update these bits, resets the system.
• Programmable time-out period specified in terms of number of WDOG clock cycles.
• Ability to test WDOG timer and reset with a flag indicating watchdog test.
• Quick test—Small time-out value programmed for quick test.
• Byte test—Individual bytes of timer tested one at a time.
• Read-only access to the WDOG timer—Allows dynamic check that WDOG timer is operational. NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value.
• Windowed refresh option
• Provides robust check that program flow is faster than expected.
• Programmable window.
• Refresh outside window leads to reset.
• Robust refresh mechanism
• Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus clock cycles.
• Count of WDOG resets as they occur.
• Configurable interrupt on time-out to provide debug breadcrumbs. This is followed by a reset after 256 bus clock cycles.

Features

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 516 Freescale Semiconductor, Inc.

23.3 Functional Overview

2 Writes of data within K bus clock

Disable Control/Configuration bit changes N bus clk cycles after unlocking WDOGEN = WDOG Enable WINEN = Windowed Mode Enable WDOGT = WDOG Time-out Value WDOGCLKSRC = WDOG Clock Source WDOG Test = WDOG Test Mode WAIT EN = Enable in wait mode STOP EN = Enable in stop mode Standby EN = Enable in standby mode Debug EN = Enable in debug mode SRS = System Reset Status Register R = Timer Reload WDOG reset count Alt Clock Osc WDOG Clock Selection WDOG CLK R System reset and SRS register Interrupt IRQ_RST_ EN = = 1? Invalid Unlock Seq 32-bit Timer Timer Time-out Refresh Outside Window Invalid Refresh Seq No config after unlocking No unlock after reset 0xB480 0xA602 System Bus Clock 32-bit Modulus Reg (Time-out Value) DebugEN Window_begin WDOGTEST STOPEN WAITEN WDOGT WDOG CLKSRC WINEN WDOGEN WDOG Y N Figure 23-1. WDOG Operation The preceding figure shows the operation of the watchdog. The values for N and K are:

• N = 256
• K = 20 The watchdog is a fail safe mechanism that brings the system into a known initial state in case of its failure due to CPU clock stopping or a run away condition in code execution. In its simplest form, the watchdog timer runs continuously off a clock source and expects Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 517

to be serviced periodically, failing which it resets the system. This ensures that the software is executing correctly and has not run away in an unintended direction. Software can adjust the period of servicing or the time-out value for the watchdog timer to meet the needs of the application. You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period. An attempted servicing of the watchdog outside this window results in a reset. By operating in this mode, you can get an indication of whether the code is running faster than expected. The window length is also user programmable. If a system fails to update/refresh the watchdog due to an unknown and persistent cause, it will be caught in an endless cycle of resets from the watchdog. To analyze the cause of such conditions, you can program the watchdog to first issue an interrupt, followed a little later by a reset. In the interrupt service routine, the software can analyze the system stack to aid debugging. To enhance the independence of watchdog from the system, it runs off an independent LPO oscillator clock. You can also switch over to an alternate clock source if required, through a control register bit.

23.3.1 Unlocking and Updating the Watchdog

You can unlock the write-once-only control and configuration registers for updating them. As a pre-condition, the ALLOW_UPDATE bit in the watchdog control register must be set. The actual unlock is accomplished by writing 0xC520 followed by 0xD928 within 20 bus clock cycles to a specific unlock register (WDOG_UNLOCK). This opens up an update window equal in length to the watchdog configuration time (WCT) within which you can update the configuration and control register bits. You can not update registers on the bus clock cycle immediately following the write of the unlock sequence, but one cycle later. These register bits can be modified only once after unlocking. If none of the configuration and control registers is updated within the update window, the watchdog issues a reset (or interrupt-then-reset) to the system. Trying to unlock the watchdog within the WCT time after an initial unlock, has no effect. During the update operation, the watchdog timer is not paused and keeps running in the background. After the update window closes, the watchdog timer restarts and the watchdog functions as per the new configuration. Functional Overview K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 518 Freescale Semiconductor, Inc.

The update feature is useful for applications that have an initial, non-safety critical part, where the watchdog is kept disabled or with a conveniently long time-out period. This means the application coder does not have to bother with frequently servicing the watchdog. After the critical part of the application begins, the watchdog can be reconfigured as per need. The watchdog issues a reset (or interrupt-then-reset if enabled) to the system for any of these invalid unlock sequences:

• You write any value other than 0xC520 or 0xD928 to the unlock register.
• ALLOW_UPDATE is set and you allow a gap of more than 20 bus clock cycles between the writing of the unlock sequence values. Also, an attempted refresh operation between the two writes of the unlock sequence and in the WCT time following a successful unlock, goes undetected. Also, see Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the unlock register. Note A context switch during unlocking and refreshing may lead to a watchdog reset.

23.3.2 The Watchdog Configuration Time (WCT)

To prevent unintended modification of the watchdog's control and configuration register bits, you are allowed to update them only within a period of 256 bus clock cycles after unlocking. This window period is known as the watchdog configuration time (WCT). In addition, these register bits can be modified only once after unlocking them for editing (even after reset). You must unlock the registers within WCT time after system reset, failing which the WDOG issues a reset to the system. To be more precise, you must write at least the first word of the unlocking sequence within the WCT time after reset. Once this is done, you get a further 20 bus clock cycles (the maximum allowed gap between the words of the unlock sequence) to complete the unlocking operation. Thereafter, to make sure that you do not forget to configure the watchdog, the watchdog issues a reset if none of the WDOG control and configuration registers is updated in the WCT time after unlock. After the close of this window or after the first write, these register bits are locked out from any further changes. The watchdog timer keeps running as per its default configuration through unlocking and update operations that can extend up to a maximum total of 2xWCT time + 20 bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles. Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 519

Updates in the write–once registers take effect only after the WCT window closes with the following exceptions for which changes take effect immediately:

• the stop, wait, and debug mode enable bits
• the standby mode enable bit
• the IRQ_RST_EN bit The operations of refreshing the watchdog goes undetected during the WCT.

23.3.3 Refreshing the Watchdog

A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh register. If these two values are written more than 20 bus cycles apart or if something other than these two values is written to the register, a watchdog reset (or interrupt-then- reset if enabled) is issued to the system. A valid refresh makes the watchdog timer restart on the next bus clock. Also, an attempted unlock operation, in between the two writes of the refresh sequence goes undetected. See Watchdog Operation with 8-bit access for guidelines related to 8-bit accesses to the refresh register.

23.3.4 Windowed Mode of Operation

In this mode of operation a restriction is placed on the point in time within the time-out period at which the watchdog can be refreshed. The refresh is considered valid only when the watchdog timer increments beyond a certain count as specified by the watchdog window register. This is known as refreshing the watchdog within a window of the total time-out period. If a refresh is attempted before the timer reaches the window value, the watchdog generates a reset (or interrupt-then-reset if enabled). Of course, if there is no refresh at all, the watchdog times out and generates a reset or interrupt-then-reset if enabled.

23.3.5 Watchdog Disabled Mode of Operation

When the watchdog is disabled through the WDOG_EN bit in the watchdog status and control register, the watchdog timer is reset to zero and is disabled from counting until you enable it or it is again enabled by the system reset. In this mode the watchdog timer cannot be refreshed (there is no requirement to do so while the timer is disabled). However, the watchdog still generates a reset (or interrupt-then-reset if enabled) on a Functional Overview K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 520 Freescale Semiconductor, Inc.

non-time-out exception (see Generated Resets and Interrupts). You need to unlock the watchdog before enabling it. A system reset brings the watchdog out of the disabled mode.

23.3.6 Low Power Modes of Operation

• In Wait mode, if the WDOG is enabled (WAIT_EN = 1), it can run on bus clock or low power oscillator clock (CLK_SRC = x) to generate interrupt (IRQ_RST_EN=1) followed by a reset on time-out. After reset the WDOG reset counter increments by one.
• In Stop mode where the bus clock is gated, the WDOG can run only on low power oscillator clock (CLK_SRC=0) if it is enabled in stop (STOP_EN=1). In this case, the WDOG runs to time-out twice, and then generates a reset from its backup circuitry. Therefore, if you program the watchdog to time-out after 100 ms and then enter such a stop mode, the reset will occur after 200 ms. Also, in this case no interrupt will be generated irrespective of the value of IRQ_RST_EN bit. After WDOG reset, the WDOG reset counter will also not increment.
• In Power-down mode, the watchdog is powered off.

23.3.7 Debug Modes of Operation

You can program the watchdog to disable in debug modes (through DBG_EN bit in the watchdog control register). This results in the watchdog timer pausing for the duration of the mode. Register read/writes are still allowed, which means that operations like: refresh, unlock etc. are allowed. On exit from the mode, the timer resumes its operation from the point of pausing. The entry of the system into the debug mode does not excuse it from compulsorily configuring the watchdog in the WCT time after unlock (unless the system bus clock is gated off, in which case the internal state machine pauses too). Failing to do so still results in a reset (or interrupt-then-reset, if enabled) to the system. Also, all the exception conditions that result in a reset to the system (see Generated Resets and Interrupts) are still valid in this mode. So, if an exception condition occurs and the system bus clock is on, a reset occurs (or interrupt-then-reset, if enabled). Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 521

The entry into Debug mode within WCT time after reset is treated differently. The WDOG timer is kept reset to zero and there is no need to unlock and configure it within WCT time. You must not try to refresh or unlock the WDOG in this state or unknown behavior may result. Upon exit from this mode, the WDOG timer restarts and the WDOG has to be unlocked and configured within WCT time.

23.4 Testing the Watchdog

For IEC 60730 and other safety standards, the expectation is that anything that monitors a safety function must be tested and this test is required to be fault tolerant. To test the watchdog, its main timer and its associated compare and reset logic must be tested. Towards this end, two tests are implemented for the watchdog that are described in Quick Test and Byte Test. While there is a control bit provided to put the watchdog into the test mode (functional), there is an overriding test-disable control bit which once set, disables the test mode permanently until reset. For running a particular test, first select that test. Thereafter, set a certain test mode bit to put the watchdog in the functional test mode. Setting this bit automatically switches the watchdog timer to a fast clock source. The switching of the clock source is done to achieve a faster time-out and hence a faster test. In a successful test, the timer times out after reaching the programmed time-out value and generates a system reset. Note After emerging from a reset due to a watchdog test, you must follow the mandatory steps of unlocking and configuring the watchdog. The refresh and unlock operations and interrupt are not automatically disabled in the test mode.

23.4.1 Quick Test

In this test the time-out value of watchdog timer is programmed to a very low value to achieve quick time-out. The only difference between the quick test and the normal mode of functioning of the watchdog is that the test mode bit is set for the quick test. This allows quick test of the watchdog reset mechanism. Testing the Watchdog K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 522 Freescale Semiconductor, Inc.

23.4.2 Byte Test

The byte test implements more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register. The following figure explains the splitting concept: CLK WDOG en Mod = = Timer?Test 32-bit Timer Modulus Register (Time-out Value) WDOG Reset Nth Stage Overflow Enables N + 1th Stage en en Reset Value (Hardwired) Byte Stage 4 Equality Comparison Byte 4 Byte 2 Byte 1 Byte 3 Byte Stage 3 Byte Stage 2 Byte Stage 1 Figure 23-2. Watchdog Timer Byte Splitting Each stage is an 8-bit synchronous counter followed by combinational logic that generates an overflow signal. The overflow signal acts as an enable to the N + 1th stage. In the test mode, when an individual byte, N, is tested, byte N – 1 is loaded forcefully with 0xFF, and both these bytes are allowed to run off the clock source. By doing so the overflow signal from stage N – 1 is generated immediately, enabling counter stage N. The Nth stage runs and compares with the Nth byte of the time-out value register. In this way, the byte N is also tested along with the link between it and the preceding stage. No disabled stages (except the most significant stage of the counter) are loaded with a value of 0xFF. These two testing schemes achieve the overall aim of testing the counter functioning and the compare and reset logic. Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 523

Do not enable the watchdog interrupt during these tests. If required, you must ensure that the effective time-out value is greater than WCT time. See Generated Resets and Interrupts for more details.

23.5 Backup Reset Generator

The backup reset generator generates the final reset which goes out to the system. It has a backup mechanism which takes care that in case the bus clock stops and prevents the main state machine from generating a reset exception/interrupt, the watchdog timer's time-out is separately routed out as a reset to the system. Two successive timer time-outs without an intervening system reset result in the backup reset generator routing out the time-out signal as a reset to the system.

23.6 Generated Resets and Interrupts

The watchdog generates a reset on the following events (referred to as exceptions at some places in this document):

• A watchdog time-out.
• Failure to unlock the watchdog within WCT time after system reset deassertion.
• No update of the control and configuration registers within the WCT window after unlocking. At least one of the following registers must be written to within the WCT window to avoid reset:
• WDOG_PRESCALER
• A value other than the unlock sequence or the refresh sequence is written to the unlock and/or refresh registers, respectively. Backup Reset Generator K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 524 Freescale Semiconductor, Inc.

• A gap of more than 20 bus cycles exists between the writes of two values of the unlock sequence.
• A gap of more than 20 bus cycles exists between the writes of two values of the refresh sequence. The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. The interrupt can be cleared by writing 1 to INT_FLG. The gap of WCT time between interrupt and reset means that the WDOG time-out value must be greater than WCT. Otherwise, if the interrupt was generated due to a time-out, a second consecutive time-out will occur in that WCT gap. This will trigger the backup reset generator to generate a reset to the system, prematurely ending the interrupt service routine execution. Also, the jobs like counting the number of watchdog resets would not be done.

23.7 Memory Map and Register Definition

This section consists of the memory map and register descriptions. WDOG memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4005_2000 Watchdog Status and Control Register High (WDOG_STCTRLH) 16 R/W 01D3h 23.7.1/ 526 4005_2002 Watchdog Status and Control Register Low (WDOG_STCTRLL) 16 R/W 0001h 23.7.2/ 528 4005_2004 Watchdog Time-out Value Register High (WDOG_TOVALH) 16 R/W 004Ch 23.7.3/ 528 4005_2006 Watchdog Time-out Value Register Low (WDOG_TOVALL) 16 R/W 4B4Ch 23.7.4/ 529 4005_2008 Watchdog Window Register High (WDOG_WINH) 16 R/W 0000h 23.7.5/ 529 4005_200A Watchdog Window Register Low (WDOG_WINL) 16 R/W 0010h 23.7.6/ 530 4005_200C Watchdog Refresh Register (WDOG_REFRESH) 16 R/W B480h 23.7.7/ 530 Table continues on the next page... Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 525

WDOG memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4005_200E Watchdog Unlock Register (WDOG_UNLOCK) 16 R/W D928h 23.7.8/ 530 4005_2010 Watchdog Timer Output Register High (WDOG_TMROUTH) 16 R/W 0000h 23.7.9/ 531 4005_2012 Watchdog Timer Output Register Low (WDOG_TMROUTL) 16 R/W 0000h 23.7.10/ 531 4005_2014 Watchdog Reset Count Register (WDOG_RSTCNT) 16 R/W 0000h 23.7.11/ 532 4005_2016 Watchdog Prescaler Register (WDOG_PRESC) 16 R/W 0400h 23.7.12/ 532

23.7.1 Watchdog Status and Control Register High

(WDOG_STCTRLH) Address: WDOG_STCTRLH is 4005_2000h base + 0h offset = 4005_2000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 DISTESTWDOG BYTESEL[1:0] TESTSEL TESTWDOG STNDBYEN WAITEN STOPEN DBGEN ALLOWUPDATE WINEN IRQRSTEN CLKSRC WDOGENWrite Reset 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 WDOG_STCTRLH field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. DISTESTWDOG Allows the WDOG’s functional test mode to be disabled permanently. Once set, it can only be cleared by a reset. It cannot be unlocked for editing once it is set. 0 WDOG functional test mode is not disabled. 1 WDOG functional test mode is disabled permanently until reset. 13–12 BYTESEL[1:0] This 2-bit field select the byte to be tested when the watchdog is in the byte test mode.

00 Byte 0 selected

01 Byte 1 selected

10 Byte 2 selected

11 Byte 3 selected

Selects the test to be run on the watchdog timer. Effective only if TESTWDOG is set. Table continues on the next page... Memory Map and Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 526 Freescale Semiconductor, Inc.

WDOG_STCTRLH field descriptions (continued) Field Description 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. TESTWDOG Puts the watchdog in the functional test mode. In this mode the watchdog timer and the associated compare and reset generation logic is tested for correct operation. The clock for the timer is switched from the main watchdog clock to the fast clock input for watchdog functional test. The TESTSEL bit selects the test to be run. Reserved This read-only field is reserved and always has the value zero. STNDBYEN Enables or disables WDOG in Standby mode. 0 WDOG is disabled in system Standby mode. 1 WDOG is enabled in system Standby mode. WAITEN Enables or disables WDOG in wait mode. 0 WDOG is disabled in CPU wait mode. 1 WDOG is enabled in CPU wait mode. STOPEN Enables or disables WDOG in stop mode. 0 WDOG is disabled in CPU stop mode. 1 WDOG is enabled in CPU stop mode. DBGEN Enables or disables WDOG in Debug mode. 0 WDOG is disabled in CPU Debug mode. 1 WDOG is enabled in CPU Debug mode. ALLOWUPDATE Enables updates to watchdog write once registers, after initial configuration window (WCT) closes, through unlock sequence. 0 No further updates allowed to WDOG write once registers. 1 WDOG write once registers can be unlocked for updating. WINEN Enable windowing mode. 0 Windowing mode is disabled. 1 Windowing mode is enabled. IRQRSTEN Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed to updating after WCT. 0 WDOG time-out generates reset only. 1 WDOG time-out initially generates an interrupt. After WCT time, it generates a reset. CLKSRC Selects clock source for the WDOG timer and other internal timing operations. 0 Dedicated clock source selected as WDOG clock (LPO Oscillator). 1 WDOG clock sourced from alternate clock source. WDOGEN Enables or disables the WDOG’s operation. In the disabled state, the watchdog timer is kept in the reset state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled. Table continues on the next page... Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 527

WDOG_STCTRLH field descriptions (continued) Field Description 0 WDOG is disabled. 1 WDOG is enabled.

23.7.2 Watchdog Status and Control Register Low

(WDOG_STCTRLL) Address: WDOG_STCTRLL is 4005_2000h base + 2h offset = 4005_2002h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read INTFLG Reserved Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WDOG_STCTRLL field descriptions Field Description INTFLG Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag. INTFLG = 1 results in an interrupt being issued followed by a reset, WCT time later. The interrupt can be cleared by writing 1 to this bit. It also gets cleared on a system reset. 14–0 Reserved This field is reserved. NOTE: Do not modify this bitfield value.

23.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH)

Address: WDOG_TOVALH is 4005_2000h base + 4h offset = 4005_2004h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TOVALHIGH Write Reset 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 WDOG_TOVALH field descriptions Field Description 15–0 TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock. Memory Map and Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 528 Freescale Semiconductor, Inc.

23.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)

The time-out value of the watchdog must be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain. Address: WDOG_TOVALL is 4005_2000h base + 6h offset = 4005_2006h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TOVALLOW Write Reset 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 WDOG_TOVALL field descriptions Field Description 15–0 TOVALLOW Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock.

23.7.5 Watchdog Window Register High (WDOG_WINH)

You must set the Window Register value lower than the Time-out Value Register. Address: WDOG_WINH is 4005_2000h base + 8h offset = 4005_2008h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WINHIGH Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_WINH field descriptions Field Description 15–0 WINHIGH Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the watchdog clock. In this mode the watchdog can be refreshed only when the timer has reached a value greater than or equal to this window length. A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 529

23.7.6 Watchdog Window Register Low (WDOG_WINL)

You must set the Window Register value lower than the Time-out Value Register. Address: WDOG_WINL is 4005_2000h base + Ah offset = 4005_200Ah Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WINLOW Write Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 WDOG_WINL field descriptions Field Description 15–0 WINLOW Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is defined in terms of cycles of the pre-scaled watchdog clock. In this mode, the watchdog can be refreshed only when the timer reaches a value greater than or equal to this window length value. A refresh outside this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system.

23.7.7 Watchdog Refresh Register (WDOG_REFRESH)

Address: WDOG_REFRESH is 4005_2000h base + Ch offset = 4005_200Ch Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WDOGREFRESH Write Reset 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 WDOG_REFRESH field descriptions Field Description 15–0 WDOGREFRES H Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles when written to this register, refreshes the WDOG and prevents it from resetting the system. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts and then resets the system).

23.7.8 Watchdog Unlock Register (WDOG_UNLOCK)

Address: WDOG_UNLOCK is 4005_2000h base + Eh offset = 4005_200Eh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read WDOGUNLOCK Write Reset 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 0 Memory Map and Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 530 Freescale Semiconductor, Inc.

WDOG_UNLOCK field descriptions Field Description 15–0 WDOGUNLOCK You can write the unlock sequence values to this register to make the watchdog write once registers writable again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens up a window equal in length to the WCT within which you can update the registers. Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts and then resets the system). The unlock sequence is effective only if ALLOWUPDATE is set.

23.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)

Address: WDOG_TMROUTH is 4005_2000h base + 10h offset = 4005_2010h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TIMEROUTHIGH Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_TMROUTH field descriptions Field Description 15–0 TIMEROUTHIGH Shows the value of the upper 16 bits of the watchdog timer.

23.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)

During stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the watchdog timer. After exiting stop mode, a maximum delay of 1 WDOG_CLK cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following the watchdog timer. Address: WDOG_TMROUTL is 4005_2000h base + 12h offset = 4005_2012h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read TIMEROUTLOW Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_TMROUTL field descriptions Field Description 15–0 TIMEROUTLOW Shows the value of the lower 16 bits of the watchdog timer. Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 531

23.7.11 Watchdog Reset Count Register (WDOG_RSTCNT)

Address: WDOG_RSTCNT is 4005_2000h base + 14h offset = 4005_2014h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read RSTCNT Write Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG_RSTCNT field descriptions Field Description 15–0 RSTCNT Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing 1 to the bit to be cleared, enables you to clear the contents of this register.

23.7.12 Watchdog Prescaler Register (WDOG_PRESC)

Address: WDOG_PRESC is 4005_2000h base + 16h offset = 4005_2016h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 PRESCVAL Write Reset 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 WDOG_PRESC field descriptions Field Description 15–11 Reserved This read-only field is reserved and always has the value zero. 10–8 PRESCVAL 3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK. 7–0 Reserved This read-only field is reserved and always has the value zero.

23.8 Watchdog Operation with 8-bit access

This section discusses 8-bit access considerations. Watchdog Operation with 8-bit access K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 532 Freescale Semiconductor, Inc.

23.8.1 General Guideline

When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is to access both the bytes of a register, you must try to place the two 8-bit accesses one after the other in your code.

23.8.2 Refresh and Unlock operations with 8-bit access

One exception condition that generates a reset to the system, is the write of any value other than those required for a legal refresh/update sequence to the respective refresh and unlock registers. For an 8-bit access to these registers, writing a correct value requires at least two bus clock cycles that means there is an invalid value in the registers for one cycle. Therefore, the system is reset even if the intention is to write a correct value to the refresh/unlock register. Keeping this in mind the exception condition for 8-bit accesses is slightly modified. Whereas the match for a correct value for a refresh/unlock sequence is as per the original definition, the match for an incorrect value is done byte-wise on the refresh/ unlock rather than for the whole 16-bit value. This means that if the high byte of the refresh/unlock register contains any value other than high bytes of the two values making up the sequence, it is treated as an exception condition, leading to a reset or interrupt- then-reset. The same holds true for the lower byte of the refresh or unlock register. Let us take the refresh operation that expects a write of 0xA602 followed by 0xB480 to the refresh register, as an example. Table 23-14. Refresh for 8-bit Access WDOG_REFRESH[15:8] WDOG_REFRESH[7:0] Sequence value1 or value2 match Mismatch exception Current Value 0xB4 0x80 Value2 match No Write 1 0xB4 0x02 No match No Write 2 0xA6 0x02 Value1 match No Write 3 0xB4 0x02 No match No Write 4 0xB4 0x80 Value2 match. Sequence complete. No Write 5 0x02 0x80 No match Yes As shown in the preceding table, the refresh register holds its reset value initially. Thereafter, two 8-bit accesses are performed on the register to write the first value of the refresh sequence. No mismatch exception is registered on the intermediate write, Write1. The sequence is completed by performing two more 8-bit accesses, writing in the second value of the sequence for a successful refresh. It must be noted that the match of value2 Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 533

takes place only when the complete 16-bit value is correctly written, write4. Hence, the requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is checked by measuring the gap between write2 and write4. It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock sequence remains unchanged. It is just the criterion for detecting a wrong value in these registers which has been relaxed, as explained, for 8-bit accesses. Any 16-bit access still needs to adhere to the original guidelines, mentioned in the sections Refreshing the Watchdog.

23.9 Restrictions on Watchdog Operation

This section mentions some exceptions to the watchdog operation that may not be apparent to you.

• Restriction on unlock / refresh operations—In the period between the closure of the WCT window (after unlock) and the actual reload of the watchdog timer, unlock and refresh operations need not be attempted.
• The update and reload of the watchdog timer happens two to three watchdog clocks after WCT window closes, following a successful configuration on unlock.
• Clock Switching Delay—The watchdog uses glitch free multiplexers at two places – one to choose between the LPO oscillator input and alternate clock input and the other to choose between the watchdog functional clock and fast clock input for watchdog functional test. A maximum time period of ~ 2 clock A cycles plus ~2 clock B cycles elapses from the time a switch is requested to the occurrence of the actual clock switch (clock A and B are the two input clocks to the clock mux).
• For the windowed mode, there is a two to three bus clock latency between the watchdog counter going past the window value and the same registering in the bus clock domain.
• For proper operation of the watchdog, the watchdog clock must be at least five times slower than the system bus clock at all times. An exception is the case when the watchdog clock is synchronous to the bus clock wherein the watchdog clock can be as fast as the bus clock.
• WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this means that even after the close of the WCT window, you have to wait for the synchronized system reset to deassert in the watchdog clock domain, before expecting the configuration updates to take effect. Restrictions on Watchdog Operation K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 534 Freescale Semiconductor, Inc.

• The time-out value of the watchdog should be set to a minimum of four watchdog clock cycles. This is to take into account the delay in new settings taking effect in the watchdog clock domain.
• You must take care not only to refresh the watchdog within the watchdog timer's actual time-out period, but also provide enough allowance for the time it takes for the refresh sequence to be detected by the watchdog timer, on the watchdog clock.
• Updates cannot be made in the bus clock cycle immediately following the write of the unlock sequence, but one bus clock cycle later.
• It should be ensured that the time-out value for the watchdog is always greater than 2xWCT time + 20 bus clock cycles.
• An attempted refresh operation, in between the two writes of the unlock sequence and in the WCT time following a successful unlock, will go undetected.
• Trying to unlock the watchdog within the WCT time after an initial unlock has no effect.
• The refresh and unlock operations and interrupt are not automatically disabled in the watchdog functional test mode.
• After emerging from a reset due to a watchdog functional test, you are still expected to go through the mandatory steps of unlocking and configuring the watchdog. The watchdog continues to be in its functional test mode and therefore you should pull the watchdog out of the functional test mode within WCT time of reset.
• After emerging from a reset due to a watchdog functional test, you still need to go through the mandatory steps of unlocking and configuring the watchdog.
• You must ensure that both the clock inputs to the glitchless clock multiplexers are alive during the switching of clocks. Failure to do so results in a loss of clock at their outputs.
• There is a gap of two to three watchdog clock cycles from the point that stop mode is entered to the watchdog timer actually pausing, due to synchronization. The same holds true for an exit from the stop mode, this time resulting in a two to three watchdog clock cycle delay in the timer restarting. In case the duration of the stop mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to pause.
• Consider the case when the first refresh value is written, following which the system enters stop mode (with system bus clk still on). Now, if the second refresh value is not written within 20 bus cycles of the first value, the system is reset (or interrupt- then-reset if enabled). Chapter 23 Watchdog Timer (WDOG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 535

Restrictions on Watchdog Operation K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 536 Freescale Semiconductor, Inc.

Multipurpose Clock Generator (MCG)

24.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock. The module can select either of the FLL or PLL output clocks, or either of the internal or external reference clocks as a source for the MCU system clock. The MCG operates in conjuction with a crystal oscillator, which allows an external crystal, ceramic resonator, or another external clock source to produce the external reference clock.

24.1.1 Features

Key features of the MCG module are:

• Frequency-locked loop (FLL)
• Digitally-controlled oscillator (DCO)
• DCO frequency range is programmable for up to four different frequency ranges.
• Option to program and maximize DCO output frequency for a low frequency external reference clock source.
• Option to prevent FLL from resetting its current locked frequency when switching clock modes if FLL reference frequency is not changed. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 537

• Internal or external reference clock can be used as the FLL source.
• Can be used as a clock source for other on-chip peripherals.
• Phase-locked loop (PLL)
• Voltage-controlled oscillator (VCO)
• External reference clock is used as the PLL source
• Modulo VCO frequency divider
• Phase/Frequency detector
• Integrated loop filter
• Can be used as a clock source for other on-chip peripherals.
• Internal reference clock generator
• Slow clock with nine trim bits for accuracy
• Fast clock with four trim bits
• Can be used as source clock for the FLL. In FEI mode, only the slow Internal Reference Clock (IRC) can be used as the FLL source.
• Either the slow or the fast clock can be selected as the clock source for the MCU
• Can be used as a clock source for other on-chip peripherals
• Control signals for "the MCG external reference low power oscillator clock generators are provided:
• HGO, RANGE, EREFS
• External clock from the Crystal Oscillator
• Can be used as a source for the FLL and/or the PLL.
• Can be selected as the clock source for the MCU
• External clock from the Real Time Counter (RTC)
• Can only be used as a source for the FLL.
• Can be selected as the clock source for the MCU
• External clock monitor with reset and interrupt request capability to check for external clock failure when running in FBE, PEE, BLPE, or FEE modes
• Lock detector with interrupt request capability for use with the PLL Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 538 Freescale Semiconductor, Inc.

• Internal Reference Clocks Auto Trim Machine (ATM) capability using an external clock as a reference
• Reference dividers for both the FLL and PLL are provided
• Reference dividers for the Fast Internal Reference Clock are provided
• MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip peripherals
• MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip peripherals
• MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals
• MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals. Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 539

/(24,25,26,...,55) Phase Detector Charge Pump Internal Filter VCO VCOOUT PLL Multipurpose Clock Generator (MCG) VDIV Lock Clock Monitor IRCLKEN CME / 2 PLLS LOLS LOCK Detector / 25 IREFST FLL DMX32 MCGFLLCLK Crystal Oscillator FRDIV n=0-7 / 2n Internal Reference Slow Clock Fast Clock Clock Generator PRDIV LOLIE Sync Auto Trim Machine IRCST PLLST CLKST ATMS SCTRIM SCFTRIM FCTRIM ATMST IREFSTEN OSCINIT EREFS HGO RANGE External DRS / 2 Clock Valid Peripheral BUSCLK PLLCLKEN MCGPLLCLK IRCSCLK IRCS CLKS CLKS DCO LP Filter IREFS STOP CLKS PLLCLKEN IREFS PLLS MCG Crystal Oscillator Enable Detect External Reference Clock Figure 24-1. Multipurpose Clock Generator (MCG) Block Diagram Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 540 Freescale Semiconductor, Inc.

24.1.2 Modes of Operation

There are nine modes of operation for the MCG: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG Modes of Operation.

24.2 External Signal Description

There are no MCG signals that connect off chip.

24.3 Memory Map/Register Definition

This section includes the memory map and register definition. The MCG registers can only be written to when in supervisor mode. Write accesses when in user mode will result in a bus error. Read accesses may be performed in both supervisor and user modes. MCG memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4006_4000 MCG Control 1 Register (MCG_C1) 8 R/W 04h 24.3.1/ 542 4006_4001 MCG Control 2 Register (MCG_C2) 8 R/W See section 24.3.2/ 543 4006_4002 MCG Control 3 Register (MCG_C3) 8 R/W Undefined 24.3.3/ 544 4006_4003 MCG Control 4 Register (MCG_C4) 8 R/W Undefined 24.3.4/ 545 4006_4004 MCG Control 5 Register (MCG_C5) 8 R/W 00h 24.3.5/ 546 4006_4005 MCG Control 6 Register (MCG_C6) 8 R/W 00h 24.3.6/ 548 4006_4006 MCG Status Register (MCG_S) 8 R 10h 24.3.7/ 549 4006_4008 MCG Auto Trim Control Register (MCG_ATC) 8 R/W 00h 24.3.8/ 551 4006_400A MCG Auto Trim Compare Value High Register (MCG_ATCVH) 8 R/W 00h 24.3.9/ 551 4006_400B MCG Auto Trim Compare Value Low Register (MCG_ATCVL) 8 R/W 00h 24.3.10/ 552 Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 541

24.3.1 MCG Control 1 Register (MCG_C1)

Address: MCG_C1 is 4006_4000h base + 0h offset = 4006_4000h Bit 7 6 5 4 3 2 1 0 Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset 0 0 0 0 0 1 0 0 MCG_C1 field descriptions Field Description 7–6 CLKS Clock Source Select Selects the clock source for MCGOUTCLK . 00 Encoding 0 — Output of FLL or PLL is selected (depends on PLLS control bit). 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Reserved, defaults to 00. 5–3 FRDIV FLL External Reference Divider Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases when trying to enter a FLL mode from FBE). 000 If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 001 If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 010 If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 011 If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 100 If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 101 If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 110 If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is Reserved . 111 If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is Reserved . IREFS Internal Reference Select Selects the reference clock source for the FLL. 0 External reference clock is selected. 1 The slow internal reference clock is selected. IRCLKEN Internal Reference Clock Enable Enables the internal reference clock for use as MCGIRCLK. 0 MCGIRCLK inactive. 1 MCGIRCLK active. IREFSTEN Internal Reference Stop Enable Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 542 Freescale Semiconductor, Inc.

MCG_C1 field descriptions (continued) Field Description 0 Internal reference clock is disabled in Stop mode.

1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI

modes before entering Stop mode.

24.3.2 MCG Control 2 Register (MCG_C2)

Address: MCG_C2 is 4006_4000h base + 1h offset = 4006_4001h Bit 7 6 5 4 3 2 1 0 Read 0 0 RANGE HGO EREFS LP IRCS Write Reset 0 0 0 0 0 0 0 0 MCG_C2 field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. Reserved This read-only field is reserved and always has the value zero. 5–4 RANGE Frequency Range Select Selects the frequency range for the crystal oscillator or external clock source. Refer to the Oscillator (OSC) chapter for more details and the device data sheet for the frequency ranges used. 00 Encoding 0 — Low frequency range selected for the crystal oscillator . 01 Encoding 1 — High frequency range selected for the crystal oscillator . 1X Encoding 2 — Very high frequency range selected for the crystal oscillator . HGO High Gain Oscillator Select Controls the crystal oscillator mode of operation. Refer to the Oscillator (OSC) chapter for more details. 0 Configure crystal oscillator for low-power operation. 1 Configure crystal oscillator for high-gain operation. EREFS External Reference Select Selects the source for the external reference clock. Refer to the Oscillator (OSC) chapter for more details. 0 External reference clock requested. 1 Oscillator requested. LP Low Power Select Controls whether the FLL (or PLL) is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode, LP bit has no affect. Table continues on the next page... Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 543

MCG_C2 field descriptions (continued) Field Description 0 FLL (or PLL) is not disabled in bypass modes.

1 FLL (or PLL) is disabled in bypass modes (lower power)

Internal Reference Clock Select Selects between the fast or slow internal reference clock source. 0 Slow internal reference clock selected. 1 Fast internal reference clock selected.

24.3.3 MCG Control 3 Register (MCG_C3)

Address: MCG_C3 is 4006_4000h base + 2h offset = 4006_4002h Bit 7 6 5 4 3 2 1 0 Read SCTRIM Write * Notes: x = Undefined at reset.• MCG_C3 field descriptions Field Description 7–0 SCTRIM Slow Internal Reference Clock Trim Setting SCTRIM 1 controls the slow internal reference clock frequency by controlling the slow internal reference clock period. The SCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). Increasing the binary value increases the period, and decreasing the value decreases the period. An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset this value is loaded with a factory trim value. If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. 1. A value for SCTRIM is loaded during reset from a factory programmed location . Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 544 Freescale Semiconductor, Inc.

24.3.4 MCG Control 4 Register (MCG_C4)

Reset values for DRST and DMX32 bits are 0. Address: MCG_C4 is 4006_4000h base + 3h offset = 4006_4003h Bit 7 6 5 4 3 2 1 0 Read DMX32 DRST_DRS FCTRIM SCFTRIM Write Reset 0 0 0 x* x* x* x* x* * Notes: x = Undefined at reset.• A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset.• MCG_C4 field descriptions Field Description DMX32 DCO Maximum Frequency with 32.768 kHz Reference The DMX32 bit controls whether or not the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range. NOTE: The system clocks derived from this source should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560 80-100 MHz 1 32.768 kHz 2929 96 MHz 0 DCO has a default range of 25%. 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. 6–5 DRST_DRS DCO Range Select The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The DRST field does not update immediately after a write to the DRS field due to internal synchronization between clock domains. Refer to DCO Frequency Range table for more details. 00 Encoding 0 — Low range (reset default). 01 Encoding 1 — Mid range. Table continues on the next page... Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 545

MCG_C4 field descriptions (continued) Field Description 10 Encoding 2 — Mid-high range. 11 Encoding 3 — High range. 4–1 FCTRIM Fast Internal Reference Clock Trim Setting FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference clock period. The FCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0). Increasing the binary value increases the period, and decreasing the value decreases the period. If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this register. SCFTRIM Slow Internal Reference Clock Fine Trim SCFTRIM 2 controls the smallest adjustment of the slow internal reference clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount possible. If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value from the nonvolatile memory location to this bit. 1. A value for FCTRIM is loaded during reset from a factory programmed location . 2. A value for SCFTRIM is loaded during reset from a factory programmed location .

24.3.5 MCG Control 5 Register (MCG_C5)

Address: MCG_C5 is 4006_4000h base + 4h offset = 4006_4004h Bit 7 6 5 4 3 2 1 0 Read 0 PLLCLKEN PLLSTEN PRDIV Write Reset 0 0 0 0 0 0 0 0 MCG_C5 field descriptions Field Description Reserved This read-only field is reserved and always has the value zero. PLLCLKEN PLL Clock Enable Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz range prior to setting the PLLCLKEN bit). Setting PLLCLKEN will enable the external oscillator if not already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN bit, and the external oscillator is being used as the reference clock, the OSCINIT bit should be checked to make sure it is set. Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 546 Freescale Semiconductor, Inc.

MCG_C5 field descriptions (continued) Field Description 0 MCGPLLCLK is inactive. 1 MCGPLLCLK is active. PLLSTEN PLL Stop Enable Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN =1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL Clock to run if it is written to 1. 0 MCGPLLCLK is disabled in any of the Stop modes. 1 MCGPLLCLK is enabled if system is in Normal Stop mode. 4–0 PRDIV PLL External Reference Divider Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN or PLLS), the PRDIV value must not be changed when LOCK is zero. Table 24-7. PLL External Reference Divide Factor PRDIV Divide Factor PRDIV Divide Factor PRDIV Divide Factor PRDIV Divide Factor 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserv ed 00010 3 01010 11 10010 19 11010 Reserv ed 00011 4 01011 12 10011 20 11011 Reserv ed 00100 5 01100 13 10100 21 11100 Reserv ed 00101 6 01101 14 10101 22 11101 Reserv ed 00110 7 01110 15 10110 23 11110 Reserv ed 00111 8 01111 16 10111 24 11111 Reserv ed Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 547

24.3.6 MCG Control 6 Register (MCG_C6)

Address: MCG_C6 is 4006_4000h base + 5h offset = 4006_4005h Bit 7 6 5 4 3 2 1 0 Read LOLIE PLLS CME VDIV Write Reset 0 0 0 0 0 0 0 0 MCG_C6 field descriptions Field Description LOLIE Loss of Lock Interrrupt Enable Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect when LOLS is set. 0 No interrupt request is generated on loss of lock. 1 Generate an interrupt request on loss of lock. PLLS PLL Select Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is disabled in all modes. 0 FLL is selected.

1 PLL is selected (PRDIV need to be programmed to the correct divider to generate a PLL reference

clock in the range of 2 - 4 MHz prior to setting the PLLS bit). CME Clock Monitor Enable Determines if a reset request is made following a loss of external clock indication. The CME bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the CME bit is set to a logic 1, the value of the RANGE bits in the C2 register should not be changed. CME bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. 0 External clock monitor is disabled. 1 Generate a reset request on loss of external clock. 4–0 VDIV VCO Divider Selects the amount to divide the VCO output of the PLL. The VDIV bits establish the multiplication factor (M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN or PLLS), the VDIV value must not be changed when LOCK is zero. Table 24-9. PLL VCO Divide Factor VDIV Multiply Factor VDIV Multiply Factor VDIV Multiply Factor VDIV Multiply Factor 00000 24 01000 32 10000 40 11000 48 Table continues on the next page... Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 548 Freescale Semiconductor, Inc.

MCG_C6 field descriptions (continued) Field Description Table 24-9. PLL VCO Divide Factor (continued) 00001 25 01001 33 10001 41 11001 49 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55

24.3.7 MCG Status Register (MCG_S)

Address: MCG_S is 4006_4000h base + 6h offset = 4006_4006h Bit 7 6 5 4 3 2 1 0 Read LOLS LOCK PLLST IREFST CLKST OSCINIT IRCST Write Reset 0 0 0 1 0 0 0 0 MCG_S field descriptions Field Description LOLS Loss of Lock Status This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D unl . LOLIE determines whether an interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when LOLS0 is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has no effect. 0 PLL has not lost lock since LOLS was last cleared. 1 PLL has lost lock since LOLS was last cleared. LOCK Lock Status This bit indicates whether the PLL has acquired lock. Lock detection is disabled when not operating in either PBE or PEE mode unless PLLCLKEN =1 and the MCG is not configured in BLPI or BLPE mode. Table continues on the next page... Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 549

MCG_S field descriptions (continued) Field Description While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV [4:0] bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay cleared until the PLL has reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN =0 also causes the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK bit is cleared, the MCGPLLCLK will be gated off until the LOCK bit is asserted again. 0 PLL is currently unlocked. 1 PLL is currently locked. PLLST PLL Select Status This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a write to the PLLS bit due to internal synchronization between clock domains. 0 Source of PLLS clock is FLL clock. 1 Source of PLLS clock is PLL clock. IREFST Internal Reference Status This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 Source of FLL reference clock is the external reference clock. 1 Source of FLL reference clock is the internal reference clock. 3–2 CLKST Clock Mode Status These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Encoding 0 — Output of the FLL is selected (reset default). 01 Encoding 1 — Internal reference clock is selected. 10 Encoding 2 — External reference clock is selected. 11 Encoding 3 — Output of the PLL is selected. OSCINIT OSC Initialization This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. Refer to the OSC module's detailed description for more information. IRCST Internal Reference Clock Status The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled, either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . 0 Source of internal reference clock is the slow clock (32 kHz IRC). 1 Source of internal reference clock is the fast clock (2 MHz IRC). Memory Map/Register Definition K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 550 Freescale Semiconductor, Inc.

24.3.8 MCG Auto Trim Control Register (MCG_ATC)

Address: MCG_ATC is 4006_4000h base + 8h offset = 4006_4008h Bit 7 6 5 4 3 2 1 0 Read ATME ATMS ATMF 0 Write Reset 0 0 0 0 0 0 0 0 MCG_ATC field descriptions Field Description ATME Automatic Trim Machine Enable Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing to C1, C3, C4, and ATC registers or entering Stop mode aborts the auto trim operation and clears this bit. 0 Auto Trim Machine disabled. 1 Auto Trim Machine enabled. ATMS Automatic Trim Machine Select Selects the IRCS clock for Auto Trim Test. 0 32 kHz Internal Reference Clock selected. 1 4 MHz Internal Reference Clock selected. ATMF Automatic Trim machine Fail Flag Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is enabled (ATME=1) and a write to the C1, C3, C4, and ATC registers is detected or the MCG enters into any Stop mode. A write to ATMF clears the flag. 0 Automatic Trim Machine completed normally. 1 Automatic Trim Machine failed. 4–0 Reserved This read-only field is reserved and always has the value zero.

24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)

Address: MCG_ATCVH is 4006_4000h base + Ah offset = 4006_400Ah Bit 7 6 5 4 3 2 1 0 Read ATCVH Write Reset 0 0 0 0 0 0 0 0 Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 551

MCG_ATCVH field descriptions Field Description 7–0 ATCVH ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion.

24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)

Address: MCG_ATCVL is 4006_4000h base + Bh offset = 4006_400Bh Bit 7 6 5 4 3 2 1 0 Read ATCVL Write Reset 0 0 0 0 0 0 0 0 MCG_ATCVL field descriptions Field Description 7–0 ATCVL ATM Compare Value Low Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion. Functional Description

24.4.1 MCG Mode State Diagram

The nine states of the MCG are shown in the following figure and are described in Table 24-14. The arrows indicate the permitted MCG mode transitions. 24.4 Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 552 Freescale Semiconductor, Inc.

Returns to the state that was active before the MCU entered Stop mode, unless a reset occurs while in Stop mode. Entered from any state when the MCU enters Stop mode Figure 24-12. MCG Mode State Diagram NOTE

• During exits from LLS or VLPS when the MCG is in PEE mode, the MCG will reset to PBE clock mode and the C1[CLKS] and S[CLKST] will automatically be set to 2’b10.
• If entering Normal Stop mode when the MCG is in PEE mode with C5[PLLSTEN]=0, the MCG will reset to PBE clock mode and C1[CLKS] and S[CLKST] will automatically be set to 2’b10.

24.4.1.1 MCG Modes of Operation

The MCG operates in one of the following modes. Note The MCG restricts transitions between modes. For the permitted transitions, see Figure 24-12. Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 553

Table 24-14. MCG Modes of Operation Mode Description FLL Engaged Internal (FEI) FLL engaged internal (FEI) is the default mode of operation and is entered when all the following condtions occur:

• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 1
• C6[PLLS] bit is written to 0 In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as selected by the C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency . Refer to the C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set. FLL Engaged External (FEE) FLL engaged external (FEE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 0
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz
• C6[PLLS] bit is written to 0 In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by the C1[FRDIV] and C2[RANGE]. Refer to the C4[DMX32] bit description for more details. In FEE mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set. FLL Bypassed Internal (FBI) FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 01
• C1[IREFS] bit is written to 1
• C6[PLLS] is written to 0
• C2[LP] is written to 0 In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (2 MHz IRC) internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by the C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. Refer to the C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low- power state unless C5[PLLCLKEN] is set. Table continues on the next page... Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 554 Freescale Semiconductor, Inc.

Table 24-14. MCG Modes of Operation (continued) Mode Description FLL Bypassed External (FBE) FLL bypassed external (FBE) mode is entered when all the following conditions occur:

• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 kHz to 39.0625 kHz.
• C6[PLLS] bit is written to 0
• C2[LP] is written to 0 In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock (DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a multiplication factor, as selected by the C4[DRST_DRS] and C4[DMX32] bits, times the divided external reference frequency. Refer to the C4[DMX32] bit description for more details. In FBI mode the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set. PLL Engaged External (PEE) PLL Engaged External (PEE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 0
• C6[PLLS] bit is written to 1 In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by C6[VDIV], times the external reference frequency, as specified by C5[PRDIV]. The PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low-power state. PLL Bypassed External (PBE) PLL Bypassed External (PBE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C6[PLLS] bit is written to 1
• C2[LP] bit is written to 0 In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock frequency locks to a multiplication factor, as specified by its [VDIV], times the PLL reference frequency, as specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low-power state. Table continues on the next page... Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 555

Table 24-14. MCG Modes of Operation (continued) Mode Description Bypassed Low Power Internal (BLPI)1 Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur:

• C1[CLKS] bits are written to 01
• C1[IREFS] bit is written to 1
• C6[PLLS] bit is written to 0
• C2[LP] bit is written to 1 In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1. Bypassed Low Power External (BLPE) Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur:
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C2[LP] bit is written to 1 In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is disabled and PLL is disabled even if the C5[PLLCLKEN] is set to 1. Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static except in the following case: MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1 MCGIRCLK is active in Stop mode when all the following conditions become true:
• C1[IRCLKEN] = 1
• C1[IREFSTEN] = 1 NOTE: • When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the MCG clock mode is forced to PBE clock mode, the C1[CLKS] and S[CLKST] will be configured to 2’b10 and S[LOCK] bit will be cleared without setting S[LOLS].
• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN]=0, on exit the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be configured to 2’b10 and S[LOCK] bit will clear without setting S[LOLS]. If C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG will continue to run in PEE mode. 1. If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the 4 MHz IRC clock selected (C2[IRCS]=1). Once in VLPR mode, writes to any of the MCG control registers that can cause a MCG clock mode switch to a non low power clock mode must be avoided. NOTE For the chip-specific modes of operation, refer to the power management chapter of this MCU. Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 556 Freescale Semiconductor, Inc.

24.4.1.2 MCG Mode Switching

The C1[IREFS] bit can be changed at any time, but the actual switch to the newly selected reference clocks is shown by the S[IREFST] bit. When switching between engaged internal and engaged external modes, the FLL will begin locking again after the switch is completed. The C1[CLKS] bits can also be changed at anytime, but the actual switch to the newly selected clock is shown by the S[CLKST] bits. If the newly selected clock is not available, the previous clock will remain selected. The C4[DRST_DRS] write bits can be changed at anytime except when C2[LP] bit is 1. If the C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO range within three clocks of the selected DCO clock. After switching to the new DCO, the FLL remains unlocked for several reference cycles. DCO startup time is equal to the FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The completion of the switch is shown by the C4[DRST_DRS] read bits.

24.4.2 Low Power Bit Usage

The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve power when these systems are not being used. The C4[DRST_DRS] can not be written while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing C2[LP] to 0.

24.4.3 MCG Internal Reference Clocks

This module supports two internal reference clocks with nominal frequencies of 32 kHz (slow IRC) and 4 MHz (fast IRC).

24.4.3.1 MCG Internal Reference Clock

The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on- chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is driven by either the fast internal reference clock (2 MHz IRC) or the slow internal reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming the period of its IRCS selected internal reference clock. This can be done by writing a new trim value to the C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 557

selected or by writing a new trim value to the C4[FCTRIM] bits when the fast IRC clock is selected. The internal reference clock period is proportional to the trim value written. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK frequency if the MCG is in FEI mode. Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and C1[IREFSTEN], otherwise this clock is disabled in Stop mode.

24.4.4 External Reference Clock

The MCG module can support an external reference clock in all modes. Refer to the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support. If the CME is asserted the slow internal reference clock is enabled along with the enabled external clock monitor. For the case when C6[CME]=1, a loss of clock is detected if the OSC external reference falls below a minimum frequency (floc_high or floc_low depending on C2[RANGE]). Upon detect of a loss of clock event, the MCU generates a system reset if the respective LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG generates a LOCS interrupt request.

24.4.5 MCG Fixed Frequency Clock

The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock source for other on-chip peripherals. This clock is driven by either the slow clock from the internal reference clock generator or the external reference clock from the Crystal Oscillator, divided by the FLL reference clock divider. The source of MCGFFCLK is selected by C1[IREFS]. Additionally, this clock is divided by two. This clock is synchronized to the peripheral bus clock and is only valid when it’s frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI mode. This clock is also disabled in Stop mode. The FLL reference clock must be set within the valid frequency range for the MCGFFCLK. Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 558 Freescale Semiconductor, Inc.

24.4.6 MCG PLL Clock

The MCG PLL Clock (MCGPLLCLK) is available depending on the device's configuration of the MCG module. For more details, refer to the clock distribution chapter of this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is enabled and S[LOCK] is set.

24.4.7 MCG Auto TRIM (ATM)

The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz. When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME] will remain asserted and will deassert after ATM is completed or an abort occurs. The MCG ATM is aborted if a write to any of the following control registers is detected including: C1, C3, C4, or ATC or if Stop mode is entered. If an abort occurs, ATC[ATMF] fail flag is asserted. The ATM machine uses the bus clock as the external reference clock to perform the IRC auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the reference clock used to generate the system clock is the external reference clock such as FBE clock mode. The MCG must not be configured in a clock mode where selected IRC ATM clock is used to generate the system clock. The bus clock is also required to be running with in the range of 8 - 16 MHz. To perform the ATM on the selected IRC, the ATM machine uses the successive approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock to enable a counter that counts number of ATM external clocks. At end of each trim bit, the ATM external counter value is compared to the ATCV[15:0] register value. Based on the comparison result, the ATM trim bit under test will get cleared or stay asserted. This is done until all trim bits have been tested by ATM SAR machine. Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 559

Before the ATM can be enabled, the ATM expected count needs to get derived and stored into the ATCV register. The ATCV expected count is derived based on the required target Internal Reference Clock (IRC) frequency, the frequency of the external reference clock, and using the following formula: ATCV

• Fr = Target Internal Reference Clock (IRC) Trimmed Frequency
• Fe = External Clock Frequency If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula. (128)

24.5 Initialization / Application Information

This section describes how to initialize and configure the MCG module in an application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes.

24.5.1 MCG Module Initialization Sequence

The MCG comes out of reset configured for FEI mode. The internal reference will stabilize in tirefsts microseconds before the FLL can acquire lock. As soon as the internal reference is stable, the FLL will acquire lock in tfll_acquire milliseconds.

24.5.1.1 Initializing the MCG

Because the MCG comes out of reset in FEI mode, the only MCG modes that can be directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 24-12). Reaching any of the other modes requires first configuring the MCG for one of these three intermediate modes. Care must be taken to check relevant status bits in the MCG status register reflecting all configuration changes within each mode. To change from FEI mode to FEE or FBE modes, follow this procedure: 1. Enable the external clock source by setting the appropriate bits in C2 register. Initialization / Application Information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 560 Freescale Semiconductor, Inc.

1. Write to C1 register to select the clock mode.

• If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the output of the FLL is selected as the system clock source.
• If entering FBE, clear the C1[IREFS] bit to switch to the external reference and change the C1[CLKS] bits to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode.
• The internal reference can optionally be kept running by setting the C1[IRCLKEN] bit. This is useful if the application will switch back and forth between internal and external modes. For minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. Once the proper configuration bits have been set, wait for the affected bits in the MCG status register to be changed appropriately, reflecting that the MCG has moved into the proper mode.
• If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS] was also set in step 1, wait here for S[OSCINIT] bit to become set indicating that the external clock source has finished its initialization cycles and stabilized.
• If in FEE mode, check to make sure the S[IREFST] bit is cleared before moving on.
• If in FBE mode, check to make sure the S[IREFST] bit is cleared and S[CLKST] bits have changed to 2'b10 indicating the external reference clock has been appropriately selected. Although the FLL is bypassed, it is still on in FBE mode. 4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency range.
• By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280 is desired instead, set C4[DRST_DRS] bits to 2'b01 for a DCO output frequency of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the C4[DRST_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a high- range FLL multiplier of 2560 is desired instead, set the C4[DRST_DRS] bits to 2'b11 for a DCO output frequency of 80 MHz. Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 561

• When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 MHz.
• When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz.
• When using a 32.768 kHz external reference, if the maximum mid high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72 MHz.
• When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96 MHz. 5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST_DRS] and C4[DMX32] programmed frequency. To change from FEI clock mode to FBI clock mode, follow this procedure: 1. Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is selected as the system clock source. 2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating that the internal reference clock has been appropriately selected. 3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range.
• By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set C2[IRCS] bit to 1 for a IRCS clock derived from the 4 MHz IRC source. Initialization / Application Information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 562 Freescale Semiconductor, Inc.

24.5.2 Using a 32.768 kHz Reference In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at low-range. If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 Mhz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part. The RTC 32 kHz oscillator may be used as the FLL reference clock. Refer to the SIM chapter on how this can be selected. The MCG must be in an internal clocking mode (FEI, FBI or BLPI) when the external clock selection mux is switched. The C2[RANGE] bits must be set to 2'b00 and the C1[FRDIV] bits must be set to 3'b000 to ensure this clock is divided by 1 to keep it within the allowed FLL reference clock range.

24.5.3 MCG Mode Switching

When switching between operational modes of the MCG, certain configuration bits must be changed in order to properly move from one mode to another. Each time any of these bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS]), the corresponding bits in the MCG status register (PLLST, IREFST, CLKST, IRCST, or OSCINIT) must be checked before moving on in the application software. Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV] and C5[PRDIV]) is set properly for the mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, C5[PRDIV] must be set to 5'b000 (divide-by-1) or 5'b001 (divide -by-2) in order to divide the external reference down to the required frequency between 2 and 4 MHz. In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST_DRS] bits. Writes to C4[DRST_DRS] bits will be ignored if C2[LP]=1. The table below shows MCGOUTCLK frequency calculations using C1[FRDIV], C5[PRDIV], and C6[VDIV] settings for each clock mode. Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 563

Table 24-15. MCGOUTCLK Frequency Calculation Options Clock Mode fMCGOUTCLK1 Note FEI (FLL engaged internal) (fint * F) Typical fMCGOUTCLK = 20 MHz immediately after reset. FEE (FLL engaged external) (fext / FLL_R) *F fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBE (FLL bypassed external) fext fext / FLL_R must be in the range of 31.25 kHz to 39.0625 kHz FBI (FLL bypassed internal) fint Typical fint = 32 kHz PEE (PLL engaged external) (fext / PLL_R) * M fext / PLL_R must be in the range of 2 – 4 MHz PBE (PLL bypassed external) fext fext / PLL_R must be in the range of 2 – 4 MHz BLPI (Bypassed low power internal) fint BLPE (Bypassed low power external) fext 1. FLL_R is the reference divider selected by the C1[FRDIV] bits, PLL_R is the reference divider selected by C5[PRDIV] bits, F is the FLL factor selected by C4[DRST_DRS] and C4[DMX32] bits, and M is the multiplier selected by C6[VDIV] bits. This section will include 3 mode switching examples using an 4 MHz external crystal. If using an external clock source less than 2 MHz, the MCG should not be configured for any of the PLL modes (PEE and PBE).

24.5.3.1 Example 1: Moving from FEI to PEE Mode : External Crystal

= 4 MHz, MCGOUTCLK Frequency = 48 MHz In this example, the MCG will move through the proper operational modes from FEI to PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal reference. First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, FEI must transition to FBE mode: a. C2 = 0x1C

• C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high frequency range
• C2[HGO] set to 1 to configure the crystal oscillator for high gain operation
• C2[EREFS] set to 1, because a crystal is being used b. C1 = 0x90 Initialization / Application Information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 564 Freescale Semiconductor, Inc.

• C1[CLKS] set to 2'b10 in order to select external reference clock as system clock source
• C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL
• C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator. c. Loop until S[OSCINIT] is 1, indicating the crystal selected by C2[EREFS] has been initialized.. d. Loop until S[IREFST] is 0, indicating the external reference is the current source for the reference clock e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK 2. Then configure C5[PRDIV] to generate correct PLL reference frequency. a. C5 = 0x01
• C5[PRDIV] set to 5'b001, or divide-by-2 resulting in a pll reference frequency of 4 MHz/2 = 2 MHz. 3. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to PBE mode: a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1. b. BLPE/PBE: C6 = 0x40
• C6[PLLS] set to 1, selects the PLL. At this time, with a C1[PRDIV] value of 2'b001, the PLL reference divider is 2 (see PLL External Reference Divide Factor table), resulting in a reference frequency of 4 MHz/ 2 = 2 MHz. In BLPE mode,changing the C6[PLLS] bit only prepares the MCG for PLL usage in PBE mode.
• C6[VDIV] set to 5'b0000, or multiply-by-24 because 2 MHz reference * 24 = 48 MHz. In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is disabled. Changing them only sets up the multiply value for PLL usage in PBE mode. c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to PBE mode. d. PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS clock is the PLL. Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 565

e. PBE: Then loop until S[LOCK] is set, indicating that the PLL has acquired lock. 4. Lastly, PBE mode transitions into PEE mode: a. C1 = 0x10

• C1[CLKS] set to 2'b00 in order to select the output of the PLL as the system clock source. b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to feed MCGOUTCLK in the current clock mode.
• Now, With PRDIV of divide-by-2, and C6[VDIV] of multiply-by-24, MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. Initialization / Application Information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 566 Freescale Semiconductor, Inc.

C2 = 0x1C (S[LP]=0) IN BLPE MODE ? C6 = 0x40 C2 = 0x1C START IN FEI MODE NO NO NO NO NO NO NO NO YES YES YES YES YES YES YES YES CHECK C1 = 0x90 CHECK CHECK ENTER BLPE MODE ? C2 = 0x1E (C2[LP] = 1) CHECK CHECK C1 = 0x10 CHECK CONTINUE IN PEE MODE S[PLLST] = 1? S[LOCK] = 1? S[CLKST] = %10? S[CLKST] = %11? (S[LP]=1) S[IREFST] = 0? S[OSCINIT] = 1? C5 = 0x01 (C5[VDIV] = 1) Figure 24-13. Flowchart of FEI to PEE Mode Transition using an 4 MHz crystal Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 567

24.5.3.2 Example 2: Moving from PEE to BLPI Mode: MCGOUTCLK

Frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, PEE must transition to PBE mode: a. C1 = 0x90

• C1[CLKS] set to 2'b10 in order to switch the system clock source to the external reference clock. b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is selected to feed MCGOUTCLK. 2. Then, PBE must transition either directly to FBE mode or first through BLPE mode and then to FBE mode: a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1 b. BLPE/FBE: C6 = 0x00
• C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value of 3'b010, the FLL divider is set to 128, resulting in a reference frequency of 4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 3'b010 (necessary to achieve required 31.25-39.06 kHz FLL reference frequency with an 4 MHz external source frequency), it must be changed prior to clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV] value does not matter. c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to FBE mode. d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the PLLS clock is the FLL. 3. Next, FBE mode transitions into FBI mode: a. C1 = 0x54 Initialization / Application Information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 568 Freescale Semiconductor, Inc.

• C1[CLKS] set to 2'b01 in order to switch the system clock to the internal reference clock.
• C1[IREFS] set to 1 to select the internal reference clock as the reference clock source.
• C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source. c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is selected to feed MCGOUTCLK. 4. Lastly, FBI transitions into BLPI mode. a. C2 = 0x02
• C2[LP] is 1
• C2[RANGE], C2[HGO], C2[EREFS], C1[IRCLKEN], and C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can remain set, or be cleared at this point. Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 569

C1 = 0x90 CHECK S[CLKST] = %10 ? NO NO NO NO YES C2 = 0x02 CONTINUE IN BLPI MODE YES YES CHECK S[PLLST] = 0? C1 = 0x54 CHECK S[IREFST] = 0? CHECK S[CLKST] = %01? YES NO YES (C2[LP] = 1) C6 = 0x00 IN BLPE MODE ? IN BLPE MODE ? NO YES C2 = 0x1C (C2[LP] = 0) C2 = 0x1E ENTER BLPE MODE ? (C2[LP]=1) Figure 24-14. Flowchart of PEE to BLPI Mode Transition using an 4 MHz crystal Initialization / Application Information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 570 Freescale Semiconductor, Inc.

24.5.3.3 Example 3: Moving from BLPI to FEE Mode

In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency. First, the code sequence will be described. Then a flowchart will be included which illustrates the sequence. 1. First, BLPI must transition to FBI mode. a. C2 = 0x00

• C2[LP] is 0 2. Next, FBI will transition to FEE mode. a. C2 = 0x1C
• C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high frequency range.
• C2[HGO] set to 1 to configure the crystal oscillator for high gain operation.
• C2[EREFS] set to 1, because a crystal is being used. b. C1 = 0x10
• C1[CLKS] set to 2'b00 in order to select the output of the FLL as system clock source.
• C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz / 128 = 31.25 kHz.
• C1[IREFS] cleared to 0, selecting the external reference clock. c. Loop until S[OSCINIT] is 1, indicating the crystal selected by the C2[EREFS] bit has been initialized. d. Loop until S[IREFST] is 0, indicating the external reference clock is the current source for the reference clock. e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected to feed MCGOUTCLK. f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640, MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz. g. At this point, by default, the C4[DRST_DRS] bits are set to 2'b00 and C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is desired instead, set the C4[DRST_DRS] bits to 0x01 to switch the FLL Chapter 24 Multipurpose Clock Generator (MCG) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 571

multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. C1 = 0x10 C2 = 0x00 C2 = 0x1C CHECK CHECK CHECK S[OSCINIT] = 1 ? CONTINUE IN FEE MODENO NO NO YES YES YES START IN BLPI MODE S[IREFST] = 0? S[CLKST] = %00? Figure 24-15. Flowchart of BLPI to FEE Mode Transition using an 4 MHz crystal Initialization / Application Information K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 572 Freescale Semiconductor, Inc.

Oscillator (OSC)

25.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU.

25.2 Features and Modes

Key features of the module are:

• Supports 32 kHz crystals (Low Range mode)
• Supports 3–8 MHz, 8–32 MHz crystals and resonators (High Range mode)
• Automatic Gain Control (AGC) to optimize power consumption in high frequency ranges 3–8 MHz, 8–32 MHz using low-power mode
• High gain option in frequency ranges: 32 kHz, 3–8 MHz, and 8–32 MHz
• Voltage and frequency filtering to guarantee clock frequency and stability
• Optionally external input bypass clock from EXTAL signal directly
• One clock for MCU clock system
• Two clocks for on-chip peripherals that can work in Stop modes Functional Description describes the module's operation in more detail. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 573

25.3 Block Diagram

The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock source assignments, refer to the clock distribution information of this MCU. Refer to the chip configuration chapter for the external reference clock source in this MCU. The following figure shows the block diagram of the OSC module. XTALEXTAL XTL_CLK CNT_DONE_4096 OSC_CLK_OUT Mux 4096 Counter OSC Clock Enable STOP OSC clock selection OSCERCLKERCLKEN OSCCLK Range selections Low Power config OSC32KCLK Oscillator Circuits EN Control and Decoding logic ERCLKEN EREFSTEN OSC_EN Figure 25-1. OSC Module Block Diagram

25.4 OSC Signal Descriptions

The following table shows the user-accessible signals available for the OSC module. Refer to signal multiplexing information for this MCU for more details. Block Diagram K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 574 Freescale Semiconductor, Inc.

Table 25-1. OSC Signal Descriptions Signal Description I/O EXTAL External clock/Oscillator input I XTAL Oscillator output O

25.5 External Crystal / Resonator Connections

The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (Cx, Cy) and feedback resistor (RF) are required. The following table shows all possible connections. Table 25-2. External Caystal/Resonator Connections Oscillator Mode Connections Low-frequency (32 kHz), low-power Connection 1 Low-frequency (32 kHz), high-gain Connection 2/Connection 31 High-frequency (3~32 MHz), low-power Connection 1/Connection 32,2 High-frequency (3~32 MHz), high-gain Connection 2/Connection 32 1. When the load capacitors (Cx, Cy) are greater than 30 pF, use Connection 3. 2. With the low-power mode, the oscillator has the internal feedback resistor RF. Therefore, the feedback resistor must not be externally with the Connection 3. OSC EXTAL Crystal or Resonator VSSXTAL Figure 25-2. Crystal/Ceramic Resonator Connections - Connection 1 Chapter 25 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 575

Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. OSC VSS Cx Cy RF Crystal or Resonator XTAL EXTAL Figure 25-4. Crystal/Ceramic Resonator Connections - Connection 3

25.6 External Clock Connections

In external clock mode, the pins can be connected as shown below. NOTE XTAL can be used as a GPIO when the GPIO alternate function is configured for it. External Clock Connections K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 576 Freescale Semiconductor, Inc.

Figure 25-5. External Clock Connections

25.7 Memory Map/Register Definitions

Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. OSC Memory Map/Register Definition OSC memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4006_5000 OSC Control Register (OSC_CR) 8 R/W 00h 25.71.1/ 577

25.71.1 OSC Control Register (OSC_CR)

After OSC is enabled and starts generating the clocks, the configurations such as low power and frequency range, must not be changed. Address: OSC_CR is 4006_5000h base + 0h offset = 4006_5000h Bit 7 6 5 4 3 2 1 0 Read ERCLKEN EREFSTEN SC2P SC4P SC8P SC16P Write Reset 0 0 0 0 0 0 0 0 OSC_CR field descriptions Field Description ERCLKEN External Reference Enable Enables external reference clock (OSCERCLK). Table continues on the next page... 25.7.1 Chapter 25 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 577

OSC_CR field descriptions (continued) Field Description 0 External reference clock is inactive. 1 External reference clock is enabled. Reserved This read-only field is reserved and always has the value zero. EREFSTEN External Reference Stop Enable Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode. 0 External reference clock is disabled in Stop mode. 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. Reserved This read-only field is reserved and always has the value zero. SC2P Oscillator 2 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 2 pF capacitor to the oscillator load. SC4P Oscillator 4 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 4 pF capacitor to the oscillator load. SC8P Oscillator 8 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 8 pF capacitor to the oscillator load. SC16P Oscillator 16 pF Capacitor Load Configure Configures the oscillator load. 0 Disable the selection. 1 Add 16 pF capacitor to the oscillator load.

25.8 Functional Description

This following sections provide functional details of the module. Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 578 Freescale Semiconductor, Inc.

25.8.1 OSC Module States

The states of the OSC module are shown in the following figure. The states and their transitions between each other are described in this section. Stable Off OSCCLK CNT_DONE_4096 Start-Up OSCCLK requested External Clock Mode Oscillator ON, Stable Oscillator OFF Oscillator ON, not yet stable Oscillator ON OSC_CLK_OUT = Static OSC_CLK_OUT = Static OSC_CLK_OUT = EXTAL OSC_CLK_OUT = XTL_CLK not requested Select OSC internal clock OSCCLK requested Select clock from EXTAL signal Figure 25-7. OSC Module State Diagram NOTE XTL_CLK is the clock generated internally from OSC circuits.

25.8.1.1 Off

The OSC enters the Off state when the system does not require OSC clocks. Upon entering this state, XTL_CLK is static unless OSC is configured to select the clock from the EXTAL pad by clearing the external reference clock selection bit. For details regarding the external reference clock source in this MCU, refer to the chip configuration chapter. The EXTAL and XTAL pins are also decoupled from all other oscillator circuitry in this state. The OSC module circuitry is configured to draw minimal current. Chapter 25 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 579

25.8.1.2 Oscillator Start-Up

The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized. When the oscillation amplitude becomes large enough to pass through the input buffer, XTL_CLK begins clocking the counter. When the counter reaches 4096 cycles of XTL_CLK, the oscillator is considered stable and XTL_CLK is passed to the output clock OSC_CLK_OUT.

25.8.1.3 Oscillator Stable

The OSC enters stable state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit and the counter reaches 4096 cycles of XTL_CLK (when CNT_DONE_4096 is high). In this state, the OSC module is producing a stable output clock on OSC_CLK_OUT. Its frequency is determined by the external components being used.

25.8.1.4 External Clock Mode

The OSC enters external clock state when it is enabled and external reference clock selection bit is cleared. For details regarding external reference clock source in this MCU, refer to the chip configuration chapter. In this state, the OSC module is set to buffer (with hysteresis) a clock from EXTAL onto the OSC_CLK_OUT. Its frequency is determined by the external clock being supplied.

25.8.2 OSC Module Modes

The OSC is a Pierce-type oscillator that supports external crystals or resonators operating over the frequency ranges shown in Table 25-5. These modes assume the following conditions: OSC is enabled to generate clocks (OSC_EN=1), configured to generate clocks internally (MCG_C2[EREFS] = 1), and some or one of the other peripherals (MCG, Timer, and so on) is configured to use the oscillator output clock (OSC_CLK_OUT). Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 580 Freescale Semiconductor, Inc.

Table 25-5. Oscillator Modes Mode Frequency Range Low-frequency, high-gain fosc_lo (1 kHz) up to fosc_lo (32.768 kHz) Low-frequency, low-power (VLP) High-frequency mode1, high-gain fosc_hi_1 (3 MHz) up to fosc_hi_1 (8 MHz) High-frequency mode1, low-power High-frequency mode2, high-gain fosc_hi_2 (8 MHz) up to fosc_hi_2 (32 MHz) High-frequency mode2, low-power NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, refer to the chip's Power Management details.

25.8.2.1 Low-Frequency, High-Gain Mode

In Low-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. The oscillator input buffer in this mode is single-ended. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used.

25.8.2.2 Low-Frequency, Low-Power Mode

In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. In this mode, the amplifier inputs, gain-control input, and input buffer input are all capacitively coupled for leakage tolerance (not sensitive to the DC level of EXTAL). Also in this mode, all external components except for the resonator itself are integrated, which includes the load capacitors and feeback resistor that biases EXTAL. Chapter 25 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 581

25.8.2.3 High-Frequency, High-Gain Mode

In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels. In this mode, the internal capacitors could be used.

25.8.2.4 High-Frequency, Low-Power Mode

In high-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption. As the oscillation amplitude increases, the amplifier current is reduced. This continues until a desired amplitude is achieved at steady-state. In this mode, the internal capacitors could be used, the internal feedback resistor is connected, and no external resistor should be used. The oscillator input buffer in this mode is differential. It provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.

25.8.3 Counter

The oscillator output clock (OSC_CLK_OUT) is gated off until the counter has detected 4096 cycles of its input clock (XTL_CLK). After 4096 cycles are completed, the counter passes XTL_CLK onto OSC_CLK_OUT. This counting time-out is used to guarantee output clock stability.

25.8.4 Reference Clock Pin Requirements

The OSC module requires use of both the EXTAL and XTAL pins to generate an output clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The EXTAL and XTAL pins are available for I/O. For the implementation of these pins on this device, refer to the Signal Multiplexing chapter.

25.9 Reset

There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. Reset K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 582 Freescale Semiconductor, Inc.

25.10 Low Power Modes Operation

When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software.

25.11 Interrupts

The OSC module does not generate any interrupts. Chapter 25 Oscillator (OSC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 583

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 584 Freescale Semiconductor, Inc.

26.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The RTC oscillator module provides the clock source for the RTC. The RTC oscillator module, in conjunction with an external crystal, generates a reference clock for the RTC.

26.1.1 Features and Modes

The key features of the RTC oscillator are as follows:

• Supports 32 kHz crystals with very low power
• Consists of internal feed back resistor
• Consists of internal programmable capacitors as the Cload of the oscillator
• Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description .

26.1.2 Block Diagram

The following is the block diagram of the RTC oscillator. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 585

Figure 26-1. RTC Oscillator Block Diagram

26.2 RTC Signal Descriptions

The following table shows the user-accessible signals available for the RTC oscillator. See the chip-level specification to find out which signals are actually connected to the external pins. Table 26-1. RTC Signal Descriptions Signal Description I/O EXTAL32 Oscillator Input I XTAL32 Oscillator Output O

26.2.1 EXTAL32 — Oscillator Input

This signal is the analog input of the RTC oscillator.

26.2.2 XTAL32 — Oscillator Output

This signal is the analog output of the RTC oscillator module. RTC Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 586 Freescale Semiconductor, Inc.

26.3 External Crystal Connections

The connections with a crystal is shown in the following figure. External load capacitors and feedback resistor are not required. RTC Oscillator Module EXTAL32 Crystal or Resonator XTAL32 VSS Figure 26-2. Crystal Connections

26.4 Memory Map/Register Descriptions

RTC oscillator control bits are part of the RTC registers. Refer to RTC_CR for more details.

26.5 Functional Description

As shown in Figure 26-1, the module includes an amplifier which supplies the negative resistor for the RTC oscillator. The gain of the amplifier is controlled by the amplitude detector, which optimizes the power consumption. A schmitt trigger is used to translate the sine-wave generated by this oscillator to a pulse clock out, which is a reference clock for the RTC digital core. The oscillator includes an internal feedback resistor of approximately 100 MΩ between EXTAL32 and XTAL32. In addition, there are two programmable capacitors with this oscillator, which can be used as the Cload of the oscillator. The programmable range is from 0pF to 30pF. Chapter 26 RTC Oscillator K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 587

26.6 Reset Overview

There is no reset state associated with the RTC oscillator.

26.7 Interrupts

The RTC oscillator does not generate any interrupts. Reset Overview K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 588 Freescale Semiconductor, Inc.

Flash Memory Controller (FMC)

27.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The Flash Memory Controller (FMC) is a memory acceleration unit that provides:

• an interface between the device and the dual-bank nonvolatile memory. Bank 0 consists of program flash memory, and bank 1 consists of FlexNVM.
• buffers that can accelerate flash memory and FlexNVM data transfers.

27.1.1 Overview

The Flash Memory Controller manages the interface between the device and the dual- bank flash memory. The FMC receives status information detailing the configuration of the memory and uses this information to ensure a proper interface. The following table shows the supported 8-bit, 16-bit, and 32-bit read/write operations. Flash memory type Read Write Program flash memory x —1 FlexNVM used as data flash memory x —1 FlexNVM and FlexRAM used as EEPROM x x 1. A write operation to program flash memory or to FlexNVM used as data flash memory results in a bus error. In addition, for bank 0 and bank 1, the FMC provides three separate mechanisms for accelerating the interface between the device and the flash memory. A 64-bit speculation buffer can prefetch the next 64-bit flash memory location, and both a 4-way, 8-set cache and a single-entry 64-bit buffer can store previously accessed flash memory or FlexNVM data for quick access times. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 589

27.1.2 Features

The FMC's features include:

• Interface between the device and the dual-bank flash memory and FlexMemory:
• 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM used as data flash memory.
• 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM used as EEPROM.
• For bank 0 and bank 1: Read accesses to consecutive 32-bit spaces in memory return the second read data with no wait states. The memory returns 64 bits via the 32-bit bus access.
• Crossbar master access protection for setting no access, read only access, write only access, or read/write access for each crossbar master.
• For bank 0 and bank 1: Acceleration of data transfer from program flash memory and FlexMemory to the device:
• 64-bit prefetch speculation buffer with controls for instruction/data access per master and bank
• 4-way, 8-set, 64-bit line size cache for a total of thirty-two 64-bit entries with controls for replacement algorithm and lock per way for each bank
• Single-entry buffer with enable per bank
• Invalidation control for the speculation buffer and the single-entry buffer

27.2 Modes of operation

The FMC only operates when the device accesses the flash memory or FlexMemory. In terms of device power modes, the FMC only operates in run and wait modes, including VLPR and VLPW modes. For any device power mode where the flash memory or FlexMemory cannot be accessed, the FMC is disabled.

27.3 External signal description

The FMC has no external signals. Modes of operation K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 590 Freescale Semiconductor, Inc.

Memory map and register descriptions The programming model consists of the FMC control registers and the program visible cache (data and tag/valid entries). NOTE Program the registers only while the flash controller is idle (for example, execute from RAM). Changing configuration settings while a flash access is in progress can lead to non-deterministic behavior. Table 27-2. FMC register access Registers Read access Write access Mode Length Mode Length Control registers: PFAPR, PFB0CR, PFB1CR Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 8, 16, or 32 bits Cache registers Supervisor (privileged) mode or user mode 32 bits Supervisor (privileged) mode only 32 bits NOTE Accesses to unimplemented registers within the FMC's 4 KB address space return a bus error. The cache entries, both data and tag/valid, can be read at any time. NOTE System software is required to maintain memory coherence when any segment of the flash cache is programmed. For example, all buffer data associated with the reprogrammed flash should be invalidated. Accordingly, cache program visible writes must occur after a programming or erase event is completed and before the new memory image is accessed. The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. The following table elaborates on the tag/valid and data entries. 27.4 Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 591

Table 27-3. Program visible cache registers Cache storage Based at offset Contents of 32-bit read Nomenclature Nomenclature example Tag 100h 13'h0, tag[18:6], 5'h0, valid In TAGVDWxSy, x denotes the way and y denotes the set. TAGVDW2S0 is the 13-bit tag and 1-bit valid for cache entry way 2, set 0. Data 200h Upper or lower word of data In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. DATAW1S0U represents bits [63:32] of data entry way 1, set 0, and DATAW1S0L represents bits [31:0] of data entry way 1, set 0. FMC memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F000 Flash Access Protection Register (FMC_PFAPR) 32 R/W 00F8_003Fh 27.4.1/ 597 4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR) 32 R/W 3002_001Fh 27.4.2/ 600 4001_F008 Flash Bank 1 Control Register (FMC_PFB1CR) 32 R/W 3002_001Fh 27.4.3/ 603 4001_F100 Cache Tag Storage (FMC_TAGVDW0S0) 32 R/W 0000_0000h 27.4.4/ 605 4001_F104 Cache Tag Storage (FMC_TAGVDW0S1) 32 R/W 0000_0000h 27.4.4/ 605 4001_F108 Cache Tag Storage (FMC_TAGVDW0S2) 32 R/W 0000_0000h 27.4.4/ 605 4001_F10C Cache Tag Storage (FMC_TAGVDW0S3) 32 R/W 0000_0000h 27.4.4/ 605 4001_F110 Cache Tag Storage (FMC_TAGVDW0S4) 32 R/W 0000_0000h 27.4.4/ 605 4001_F114 Cache Tag Storage (FMC_TAGVDW0S5) 32 R/W 0000_0000h 27.4.4/ 605 4001_F118 Cache Tag Storage (FMC_TAGVDW0S6) 32 R/W 0000_0000h 27.4.4/ 605 4001_F11C Cache Tag Storage (FMC_TAGVDW0S7) 32 R/W 0000_0000h 27.4.4/ 605 4001_F120 Cache Tag Storage (FMC_TAGVDW1S0) 32 R/W 0000_0000h 27.4.5/ 606 4001_F124 Cache Tag Storage (FMC_TAGVDW1S1) 32 R/W 0000_0000h 27.4.5/ 606 4001_F128 Cache Tag Storage (FMC_TAGVDW1S2) 32 R/W 0000_0000h 27.4.5/ 606 4001_F12C Cache Tag Storage (FMC_TAGVDW1S3) 32 R/W 0000_0000h 27.4.5/ 606 Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 592 Freescale Semiconductor, Inc.

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F130 Cache Tag Storage (FMC_TAGVDW1S4) 32 R/W 0000_0000h 27.4.5/ 606 4001_F134 Cache Tag Storage (FMC_TAGVDW1S5) 32 R/W 0000_0000h 27.4.5/ 606 4001_F138 Cache Tag Storage (FMC_TAGVDW1S6) 32 R/W 0000_0000h 27.4.5/ 606 4001_F13C Cache Tag Storage (FMC_TAGVDW1S7) 32 R/W 0000_0000h 27.4.5/ 606 4001_F140 Cache Tag Storage (FMC_TAGVDW2S0) 32 R/W 0000_0000h 27.4.6/ 607 4001_F144 Cache Tag Storage (FMC_TAGVDW2S1) 32 R/W 0000_0000h 27.4.6/ 607 4001_F148 Cache Tag Storage (FMC_TAGVDW2S2) 32 R/W 0000_0000h 27.4.6/ 607 4001_F14C Cache Tag Storage (FMC_TAGVDW2S3) 32 R/W 0000_0000h 27.4.6/ 607 4001_F150 Cache Tag Storage (FMC_TAGVDW2S4) 32 R/W 0000_0000h 27.4.6/ 607 4001_F154 Cache Tag Storage (FMC_TAGVDW2S5) 32 R/W 0000_0000h 27.4.6/ 607 4001_F158 Cache Tag Storage (FMC_TAGVDW2S6) 32 R/W 0000_0000h 27.4.6/ 607 4001_F15C Cache Tag Storage (FMC_TAGVDW2S7) 32 R/W 0000_0000h 27.4.6/ 607 4001_F160 Cache Tag Storage (FMC_TAGVDW3S0) 32 R/W 0000_0000h 27.4.7/ 608 4001_F164 Cache Tag Storage (FMC_TAGVDW3S1) 32 R/W 0000_0000h 27.4.7/ 608 4001_F168 Cache Tag Storage (FMC_TAGVDW3S2) 32 R/W 0000_0000h 27.4.7/ 608 4001_F16C Cache Tag Storage (FMC_TAGVDW3S3) 32 R/W 0000_0000h 27.4.7/ 608 4001_F170 Cache Tag Storage (FMC_TAGVDW3S4) 32 R/W 0000_0000h 27.4.7/ 608 4001_F174 Cache Tag Storage (FMC_TAGVDW3S5) 32 R/W 0000_0000h 27.4.7/ 608 4001_F178 Cache Tag Storage (FMC_TAGVDW3S6) 32 R/W 0000_0000h 27.4.7/ 608 4001_F17C Cache Tag Storage (FMC_TAGVDW3S7) 32 R/W 0000_0000h 27.4.7/ 608 Table continues on the next page... Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 593

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F200 Cache Data Storage (upper word) (FMC_DATAW0S0U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F204 Cache Data Storage (lower word) (FMC_DATAW0S0L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F208 Cache Data Storage (upper word) (FMC_DATAW0S1U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F20C Cache Data Storage (lower word) (FMC_DATAW0S1L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F210 Cache Data Storage (upper word) (FMC_DATAW0S2U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F214 Cache Data Storage (lower word) (FMC_DATAW0S2L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F218 Cache Data Storage (upper word) (FMC_DATAW0S3U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F21C Cache Data Storage (lower word) (FMC_DATAW0S3L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F220 Cache Data Storage (upper word) (FMC_DATAW0S4U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F224 Cache Data Storage (lower word) (FMC_DATAW0S4L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F228 Cache Data Storage (upper word) (FMC_DATAW0S5U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F22C Cache Data Storage (lower word) (FMC_DATAW0S5L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F230 Cache Data Storage (upper word) (FMC_DATAW0S6U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F234 Cache Data Storage (lower word) (FMC_DATAW0S6L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F238 Cache Data Storage (upper word) (FMC_DATAW0S7U) 32 R/W 0000_0000h 27.4.8/ 609 4001_F23C Cache Data Storage (lower word) (FMC_DATAW0S7L) 32 R/W 0000_0000h 27.4.9/ 610 4001_F240 Cache Data Storage (upper word) (FMC_DATAW1S0U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F244 Cache Data Storage (lower word) (FMC_DATAW1S0L) 32 R/W 0000_0000h 27.4.11/ 612 4001_F248 Cache Data Storage (upper word) (FMC_DATAW1S1U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F24C Cache Data Storage (lower word) (FMC_DATAW1S1L) 32 R/W 0000_0000h 27.4.11/ 612 Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 594 Freescale Semiconductor, Inc.

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F250 Cache Data Storage (upper word) (FMC_DATAW1S2U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F254 Cache Data Storage (lower word) (FMC_DATAW1S2L) 32 R/W 0000_0000h 27.4.11/ 612 4001_F258 Cache Data Storage (upper word) (FMC_DATAW1S3U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F25C Cache Data Storage (lower word) (FMC_DATAW1S3L) 32 R/W 0000_0000h 27.4.11/ 612 4001_F260 Cache Data Storage (upper word) (FMC_DATAW1S4U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F264 Cache Data Storage (lower word) (FMC_DATAW1S4L) 32 R/W 0000_0000h 27.4.11/ 612 4001_F268 Cache Data Storage (upper word) (FMC_DATAW1S5U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F26C Cache Data Storage (lower word) (FMC_DATAW1S5L) 32 R/W 0000_0000h 27.4.11/ 612 4001_F270 Cache Data Storage (upper word) (FMC_DATAW1S6U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F274 Cache Data Storage (lower word) (FMC_DATAW1S6L) 32 R/W 0000_0000h 27.4.11/ 612 4001_F278 Cache Data Storage (upper word) (FMC_DATAW1S7U) 32 R/W 0000_0000h 27.4.10/ 611 4001_F27C Cache Data Storage (lower word) (FMC_DATAW1S7L) 32 R/W 0000_0000h 27.4.11/ 612 4001_F280 Cache Data Storage (upper word) (FMC_DATAW2S0U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F284 Cache Data Storage (lower word) (FMC_DATAW2S0L) 32 R/W 0000_0000h 27.4.13/ 614 4001_F288 Cache Data Storage (upper word) (FMC_DATAW2S1U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F28C Cache Data Storage (lower word) (FMC_DATAW2S1L) 32 R/W 0000_0000h 27.4.13/ 614 4001_F290 Cache Data Storage (upper word) (FMC_DATAW2S2U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F294 Cache Data Storage (lower word) (FMC_DATAW2S2L) 32 R/W 0000_0000h 27.4.13/ 614 4001_F298 Cache Data Storage (upper word) (FMC_DATAW2S3U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F29C Cache Data Storage (lower word) (FMC_DATAW2S3L) 32 R/W 0000_0000h 27.4.13/ 614 Table continues on the next page... Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 595

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F2A0 Cache Data Storage (upper word) (FMC_DATAW2S4U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F2A4 Cache Data Storage (lower word) (FMC_DATAW2S4L) 32 R/W 0000_0000h 27.4.13/ 614 4001_F2A8 Cache Data Storage (upper word) (FMC_DATAW2S5U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F2AC Cache Data Storage (lower word) (FMC_DATAW2S5L) 32 R/W 0000_0000h 27.4.13/ 614 4001_F2B0 Cache Data Storage (upper word) (FMC_DATAW2S6U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F2B4 Cache Data Storage (lower word) (FMC_DATAW2S6L) 32 R/W 0000_0000h 27.4.13/ 614 4001_F2B8 Cache Data Storage (upper word) (FMC_DATAW2S7U) 32 R/W 0000_0000h 27.4.12/ 613 4001_F2BC Cache Data Storage (lower word) (FMC_DATAW2S7L) 32 R/W 0000_0000h 27.4.13/ 614 4001_F2C0 Cache Data Storage (upper word) (FMC_DATAW3S0U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2C4 Cache Data Storage (lower word) (FMC_DATAW3S0L) 32 R/W 0000_0000h 27.4.15/ 616 4001_F2C8 Cache Data Storage (upper word) (FMC_DATAW3S1U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2CC Cache Data Storage (lower word) (FMC_DATAW3S1L) 32 R/W 0000_0000h 27.4.15/ 616 4001_F2D0 Cache Data Storage (upper word) (FMC_DATAW3S2U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2D4 Cache Data Storage (lower word) (FMC_DATAW3S2L) 32 R/W 0000_0000h 27.4.15/ 616 4001_F2D8 Cache Data Storage (upper word) (FMC_DATAW3S3U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2DC Cache Data Storage (lower word) (FMC_DATAW3S3L) 32 R/W 0000_0000h 27.4.15/ 616 4001_F2E0 Cache Data Storage (upper word) (FMC_DATAW3S4U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2E4 Cache Data Storage (lower word) (FMC_DATAW3S4L) 32 R/W 0000_0000h 27.4.15/ 616 4001_F2E8 Cache Data Storage (upper word) (FMC_DATAW3S5U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2EC Cache Data Storage (lower word) (FMC_DATAW3S5L) 32 R/W 0000_0000h 27.4.15/ 616 Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 596 Freescale Semiconductor, Inc.

FMC memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4001_F2F0 Cache Data Storage (upper word) (FMC_DATAW3S6U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2F4 Cache Data Storage (lower word) (FMC_DATAW3S6L) 32 R/W 0000_0000h 27.4.15/ 616 4001_F2F8 Cache Data Storage (upper word) (FMC_DATAW3S7U) 32 R/W 0000_0000h 27.4.14/ 615 4001_F2FC Cache Data Storage (lower word) (FMC_DATAW3S7L) 32 R/W 0000_0000h 27.4.15/ 616

27.4.1 Flash Access Protection Register (FMC_PFAPR)

Address: FMC_PFAPR is 4001_F000h base + 0h offset = 4001_F000h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 M7PFD M6PFD M5PFD M4PFD M3PFD M2PFD M1PFD M0PFDW Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R M7AP[1:0] M6AP[1:0] M5AP[1:0] M4AP[1:0] M3AP[1:0] M2AP[1:0] M1AP[1:0] M0AP[1:0] W Reset 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 FMC_PFAPR field descriptions Field Description 31–24 Reserved This read-only field is reserved and always has the value zero. M7PFD Master 7 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. M6PFD Master 6 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Table continues on the next page... Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 597

FMC_PFAPR field descriptions (continued) Field Description 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. M5PFD Master 5 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. M4PFD Master 4 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. M3PFD Master 3 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. M2PFD Master 2 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. M1PFD Master 1 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. M0PFD Master 0 Prefetch Disable These bits control whether prefetching is enabled based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. 0 Prefetching for this master is enabled. 1 Prefetching for this master is disabled. 15–14 M7AP[1:0] Master 7 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 00 No access may be performed by this master. 01 Only read accesses may be performed by this master. Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 598 Freescale Semiconductor, Inc.

FMC_PFAPR field descriptions (continued) Field Description 10 Only write accesses may be performed by this master. 11 Both read and write accesses may be performed by this master. 13–12 M6AP[1:0] Master 6 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master.

00 No access may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

11–10 M5AP[1:0] Master 5 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 9–8 M4AP[1:0] Master 4 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 7–6 M3AP[1:0] Master 3 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 5–4 M2AP[1:0] Master 2 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 3–2 M1AP[1:0] Master 1 Access Protection Table continues on the next page... Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 599

FMC_PFAPR field descriptions (continued) Field Description This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master. 1–0 M0AP[1:0] Master 0 Access Protection This field controls whether read and write access to the flash are allowed based on the logical master number of the requesting crossbar switch master.

27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)

Address: FMC_PFB0CR is 4001_F000h base + 4h offset = 4001_F004h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R B0RWSC[3:0] CLCK_WAY[3:0] 0 0 B0MW[1:0] 0 W CINV_WAY[3:0] S_B_ INV Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 CRC[2:0] B0DCE B0ICE B0DPE B0IPE B0SEBEW Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMC_PFB0CR field descriptions Field Description 31–28 B0RWSC[3:0] Bank 0 Read Wait State Control This read-only field defines the number of wait states required to access the bank 0 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. For example, when this ratio is 4:1, the field's value is 3h. Table continues on the next page... Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 600 Freescale Semiconductor, Inc.

FMC_PFB0CR field descriptions (continued) Field Description 27–24 CLCK_WAY[3:0] Cache Lock Way x These bits determine if the given cache way is locked such that its contents will not be displaced by future misses. The bit setting definitions are for each bit in the field.

0 Cache way is unlocked and may be displaced

1 Cache way is locked and its contents are not displaced

23–20 CINV_WAY[3:0] Cache Invalidate Way x These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared. This field always reads as zero. Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System software is required to maintain memory coherency when any segment of the flash memory is programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event is completed and before the new memory image is accessed. The bit setting definitions are for each bit in the field.

0 No cache way invalidation for the corresponding cache

1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected

S_B_INV Invalidate Prefetch Speculation Buffer This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are immediately cleared. This bit always reads as zero. 0 Speculation buffer and single entry buffer are not affected. 1 Invalidate (clear) speculation buffer and single entry buffer. 18–17 B0MW[1:0] Bank 0 Memory Width This read-only field defines the width of the bank 0 memory. 00 32 bits 01 64 bits 1x Reserved Reserved This read-only field is reserved and always has the value zero. 15–8 Reserved This read-only field is reserved and always has the value zero. 7–5 CRC[2:0] Cache Replacement Control This 3-bit field defines the replacement algorithm for accesses that are cached.

000 LRU replacement algorithm per set across all four ways

010 Independent LRU with ways [0-1] for ifetches, [2-3] for data

011 Independent LRU with ways [0-2] for ifetches, [3] for data

Table continues on the next page... Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 601

FMC_PFB0CR field descriptions (continued) Field Description B0DCE Bank 0 Data Cache Enable This bit controls whether data references are loaded into the cache. 0 Do not cache data references. 1 Cache data references. B0ICE Bank 0 Instruction Cache Enable This bit controls whether instruction fetches are loaded into the cache. 0 Do not cache instruction fetches. 1 Cache instruction fetches. B0DPE Bank 0 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 Do not prefetch in response to data references. 1 Enable prefetches in response to data references. B0IPE Bank 0 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 Do not prefetch in response to instruction fetches. 1 Enable prefetches in response to instruction fetches. B0SEBE Bank 0 Single Entry Buffer Enable This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its operation is independent from bank 1's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 Single entry buffer is disabled. 1 Single entry buffer is enabled. Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 602 Freescale Semiconductor, Inc.

27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)

This register has a format similar to that for PFB0CR, except it controls the operation of flash bank 1, and the "global" cache control fields are empty. Address: FMC_PFB1CR is 4001_F000h base + 8h offset = 4001_F008h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R B1RWSC[3:0] 0 B1MW[1:0] 0 W Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 B1DCE B1ICE B1DPE B1IPE B1SEBEW Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 FMC_PFB1CR field descriptions Field Description 31–28 B1RWSC[3:0] Bank 1 Read Wait State Control This read-only field defines the number of wait states required to access the bank 1 flash memory. The relationship between the read access time of the flash array (expressed in system clock cycles) and RWSC is defined as: Access time of flash array [system clocks] = RWSC + 1 The FMC automatically calculates this value based on the ratio of the system clock speed to the flash clock speed. For example, when this ratio is 4:1, the field's value is 3h. 27–19 Reserved This read-only field is reserved and always has the value zero. 18–17 B1MW[1:0] Bank 1 Memory Width This read-only field defines the width of the bank 1 memory. 00 32 bits 01 64 bits This read-only field is reserved and always has the value zero. 15–8 Reserved This read-only field is reserved and always has the value zero. 7–5 Reserved This read-only field is reserved and always has the value zero. Table continues on the next page... Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 603

FMC_PFB1CR field descriptions (continued) Field Description B1DCE Bank 1 Data Cache Enable This bit controls whether data references are loaded into the cache. 0 Do not cache data references. 1 Cache data references. B1ICE Bank 1 Instruction Cache Enable This bit controls whether instruction fetches are loaded into the cache. 0 Do not cache instruction fetches. 1 Cache instruction fetches. B1DPE Bank 1 Data Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. 0 Do not prefetch in response to data references. 1 Enable prefetches in response to data references. B1IPE Bank 1 Instruction Prefetch Enable This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction fetches. 0 Do not prefetch in response to instruction fetches. 1 Enable prefetches in response to instruction fetches. B1SEBE Bank 1 Single Entry Buffer Enable This bit controls whether the single entry buffer is enabled in response to flash read accesses. Its operation is independent from bank 0's cache. A high-to-low transition of this enable forces the page buffer to be invalidated. 0 Single entry buffer is disabled. 1 Single entry buffer is enabled. Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 604 Freescale Semiconductor, Inc.

27.4.4 Cache Tag Storage (FMC_TAGVDW0Sn)

The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 0. Addresses: FMC_TAGVDW0S0 is 4001_F000h base + 100h offset = 4001_F100h FMC_TAGVDW0S1 is 4001_F000h base + 104h offset = 4001_F104h FMC_TAGVDW0S2 is 4001_F000h base + 108h offset = 4001_F108h FMC_TAGVDW0S3 is 4001_F000h base + 10Ch offset = 4001_F10Ch FMC_TAGVDW0S4 is 4001_F000h base + 110h offset = 4001_F110h FMC_TAGVDW0S5 is 4001_F000h base + 114h offset = 4001_F114h FMC_TAGVDW0S6 is 4001_F000h base + 118h offset = 4001_F118h FMC_TAGVDW0S7 is 4001_F000h base + 11Ch offset = 4001_F11Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 tag[18:6] validW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW0Sn field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This read-only field is reserved and always has the value zero. valid 1-bit valid for cache entry Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 605

27.4.5 Cache Tag Storage (FMC_TAGVDW1Sn)

The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 1. Addresses: FMC_TAGVDW1S0 is 4001_F000h base + 120h offset = 4001_F120h FMC_TAGVDW1S1 is 4001_F000h base + 124h offset = 4001_F124h FMC_TAGVDW1S2 is 4001_F000h base + 128h offset = 4001_F128h FMC_TAGVDW1S3 is 4001_F000h base + 12Ch offset = 4001_F12Ch FMC_TAGVDW1S4 is 4001_F000h base + 130h offset = 4001_F130h FMC_TAGVDW1S5 is 4001_F000h base + 134h offset = 4001_F134h FMC_TAGVDW1S6 is 4001_F000h base + 138h offset = 4001_F138h FMC_TAGVDW1S7 is 4001_F000h base + 13Ch offset = 4001_F13Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 tag[18:6] validW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW1Sn field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This read-only field is reserved and always has the value zero. valid 1-bit valid for cache entry Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 606 Freescale Semiconductor, Inc.

27.4.6 Cache Tag Storage (FMC_TAGVDW2Sn)

The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 2. Addresses: FMC_TAGVDW2S0 is 4001_F000h base + 140h offset = 4001_F140h FMC_TAGVDW2S1 is 4001_F000h base + 144h offset = 4001_F144h FMC_TAGVDW2S2 is 4001_F000h base + 148h offset = 4001_F148h FMC_TAGVDW2S3 is 4001_F000h base + 14Ch offset = 4001_F14Ch FMC_TAGVDW2S4 is 4001_F000h base + 150h offset = 4001_F150h FMC_TAGVDW2S5 is 4001_F000h base + 154h offset = 4001_F154h FMC_TAGVDW2S6 is 4001_F000h base + 158h offset = 4001_F158h FMC_TAGVDW2S7 is 4001_F000h base + 15Ch offset = 4001_F15Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 tag[18:6] validW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW2Sn field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This read-only field is reserved and always has the value zero. valid 1-bit valid for cache entry Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 607

27.4.7 Cache Tag Storage (FMC_TAGVDW3Sn)

The 32-entry cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. This section represents tag/vld information for all 8 sets (n=0-7) in way 3. Addresses: FMC_TAGVDW3S0 is 4001_F000h base + 160h offset = 4001_F160h FMC_TAGVDW3S1 is 4001_F000h base + 164h offset = 4001_F164h FMC_TAGVDW3S2 is 4001_F000h base + 168h offset = 4001_F168h FMC_TAGVDW3S3 is 4001_F000h base + 16Ch offset = 4001_F16Ch FMC_TAGVDW3S4 is 4001_F000h base + 170h offset = 4001_F170h FMC_TAGVDW3S5 is 4001_F000h base + 174h offset = 4001_F174h FMC_TAGVDW3S6 is 4001_F000h base + 178h offset = 4001_F178h FMC_TAGVDW3S7 is 4001_F000h base + 17Ch offset = 4001_F17Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 tag[18:6] validW Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_TAGVDW3Sn field descriptions Field Description 31–19 Reserved This read-only field is reserved and always has the value zero. 18–6 tag[18:6] 13-bit tag for cache entry 5–1 Reserved This read-only field is reserved and always has the value zero. valid 1-bit valid for cache entry Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 608 Freescale Semiconductor, Inc.

27.4.8 Cache Data Storage (upper word) (FMC_DATAW0SU)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 0. Addresses: FMC_DATAW0S0U is 4001_F000h base + 200h offset = 4001_F200h FMC_DATAW0S1U is 4001_F000h base + 208h offset = 4001_F208h FMC_DATAW0S2U is 4001_F000h base + 210h offset = 4001_F210h FMC_DATAW0S3U is 4001_F000h base + 218h offset = 4001_F218h FMC_DATAW0S4U is 4001_F000h base + 220h offset = 4001_F220h FMC_DATAW0S5U is 4001_F000h base + 228h offset = 4001_F228h FMC_DATAW0S6U is 4001_F000h base + 230h offset = 4001_F230h FMC_DATAW0S7U is 4001_F000h base + 238h offset = 4001_F238h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW0SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 609

27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SL)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 0. Addresses: FMC_DATAW0S0L is 4001_F000h base + 204h offset = 4001_F204h FMC_DATAW0S1L is 4001_F000h base + 20Ch offset = 4001_F20Ch FMC_DATAW0S2L is 4001_F000h base + 214h offset = 4001_F214h FMC_DATAW0S3L is 4001_F000h base + 21Ch offset = 4001_F21Ch FMC_DATAW0S4L is 4001_F000h base + 224h offset = 4001_F224h FMC_DATAW0S5L is 4001_F000h base + 22Ch offset = 4001_F22Ch FMC_DATAW0S6L is 4001_F000h base + 234h offset = 4001_F234h FMC_DATAW0S7L is 4001_F000h base + 23Ch offset = 4001_F23Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW0SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 610 Freescale Semiconductor, Inc.

27.4.10 Cache Data Storage (upper word) (FMC_DATAW1SU)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 1. Addresses: FMC_DATAW1S0U is 4001_F000h base + 240h offset = 4001_F240h FMC_DATAW1S1U is 4001_F000h base + 248h offset = 4001_F248h FMC_DATAW1S2U is 4001_F000h base + 250h offset = 4001_F250h FMC_DATAW1S3U is 4001_F000h base + 258h offset = 4001_F258h FMC_DATAW1S4U is 4001_F000h base + 260h offset = 4001_F260h FMC_DATAW1S5U is 4001_F000h base + 268h offset = 4001_F268h FMC_DATAW1S6U is 4001_F000h base + 270h offset = 4001_F270h FMC_DATAW1S7U is 4001_F000h base + 278h offset = 4001_F278h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 611

27.4.11 Cache Data Storage (lower word) (FMC_DATAW1SL)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 1. Addresses: FMC_DATAW1S0L is 4001_F000h base + 244h offset = 4001_F244h FMC_DATAW1S1L is 4001_F000h base + 24Ch offset = 4001_F24Ch FMC_DATAW1S2L is 4001_F000h base + 254h offset = 4001_F254h FMC_DATAW1S3L is 4001_F000h base + 25Ch offset = 4001_F25Ch FMC_DATAW1S4L is 4001_F000h base + 264h offset = 4001_F264h FMC_DATAW1S5L is 4001_F000h base + 26Ch offset = 4001_F26Ch FMC_DATAW1S6L is 4001_F000h base + 274h offset = 4001_F274h FMC_DATAW1S7L is 4001_F000h base + 27Ch offset = 4001_F27Ch Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW1SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 612 Freescale Semiconductor, Inc.

27.4.12 Cache Data Storage (upper word) (FMC_DATAW2SU)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 2. Addresses: FMC_DATAW2S0U is 4001_F000h base + 280h offset = 4001_F280h FMC_DATAW2S1U is 4001_F000h base + 288h offset = 4001_F288h FMC_DATAW2S2U is 4001_F000h base + 290h offset = 4001_F290h FMC_DATAW2S3U is 4001_F000h base + 298h offset = 4001_F298h FMC_DATAW2S4U is 4001_F000h base + 2A0h offset = 4001_F2A0h FMC_DATAW2S5U is 4001_F000h base + 2A8h offset = 4001_F2A8h FMC_DATAW2S6U is 4001_F000h base + 2B0h offset = 4001_F2B0h FMC_DATAW2S7U is 4001_F000h base + 2B8h offset = 4001_F2B8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 613

27.4.13 Cache Data Storage (lower word) (FMC_DATAW2SL)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 2. Addresses: FMC_DATAW2S0L is 4001_F000h base + 284h offset = 4001_F284h FMC_DATAW2S1L is 4001_F000h base + 28Ch offset = 4001_F28Ch FMC_DATAW2S2L is 4001_F000h base + 294h offset = 4001_F294h FMC_DATAW2S3L is 4001_F000h base + 29Ch offset = 4001_F29Ch FMC_DATAW2S4L is 4001_F000h base + 2A4h offset = 4001_F2A4h FMC_DATAW2S5L is 4001_F000h base + 2ACh offset = 4001_F2ACh FMC_DATAW2S6L is 4001_F000h base + 2B4h offset = 4001_F2B4h FMC_DATAW2S7L is 4001_F000h base + 2BCh offset = 4001_F2BCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW2SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry Memory map and register descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 614 Freescale Semiconductor, Inc.

27.4.14 Cache Data Storage (upper word) (FMC_DATAW3SU)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the upper word (bits [63:32]) of all 8 sets (n=0-7) in way 3. Addresses: FMC_DATAW3S0U is 4001_F000h base + 2C0h offset = 4001_F2C0h FMC_DATAW3S1U is 4001_F000h base + 2C8h offset = 4001_F2C8h FMC_DATAW3S2U is 4001_F000h base + 2D0h offset = 4001_F2D0h FMC_DATAW3S3U is 4001_F000h base + 2D8h offset = 4001_F2D8h FMC_DATAW3S4U is 4001_F000h base + 2E0h offset = 4001_F2E0h FMC_DATAW3S5U is 4001_F000h base + 2E8h offset = 4001_F2E8h FMC_DATAW3S6U is 4001_F000h base + 2F0h offset = 4001_F2F0h FMC_DATAW3S7U is 4001_F000h base + 2F8h offset = 4001_F2F8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[63:32] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnU field descriptions Field Description 31–0 data[63:32] Bits [63:32] of data entry Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 615

27.4.15 Cache Data Storage (lower word) (FMC_DATAW3SL)

The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x denotes the way, y denotes the set, and U and L represent upper and lower word, respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets (n=0-7) in way 3. Addresses: FMC_DATAW3S0L is 4001_F000h base + 2C4h offset = 4001_F2C4h FMC_DATAW3S1L is 4001_F000h base + 2CCh offset = 4001_F2CCh FMC_DATAW3S2L is 4001_F000h base + 2D4h offset = 4001_F2D4h FMC_DATAW3S3L is 4001_F000h base + 2DCh offset = 4001_F2DCh FMC_DATAW3S4L is 4001_F000h base + 2E4h offset = 4001_F2E4h FMC_DATAW3S5L is 4001_F000h base + 2ECh offset = 4001_F2ECh FMC_DATAW3S6L is 4001_F000h base + 2F4h offset = 4001_F2F4h FMC_DATAW3S7L is 4001_F000h base + 2FCh offset = 4001_F2FCh Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R data[31:0] W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FMC_DATAW3SnL field descriptions Field Description 31–0 data[31:0] Bits [31:0] of data entry

27.5 Functional description

The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between the device and the flash memory and FlexMemory, the FMC can be used to restrict access from crossbar switch masters and customize the cache and buffers to provide single-cycle system-clock data-access times. Whenever a hit occurs for the prefetch speculation buffer, the cache, or the single-entry buffer, the requested data is transferred within a single system clock. Upon system reset, the FMC is configured to provide a significant level of buffering for transfers from the flash memory or FlexMemory:

• Crossbar masters 0, 1, 2 have read access to bank 0 and bank 1. Functional description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 616 Freescale Semiconductor, Inc.

• These masters have write access to a portion of bank 1 when FlexNVM is used with FlexRAM as EEPROM.
• For bank 0 and bank 1:
• Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2.
• The cache is configured for least recently used (LRU) replacement for all four ways.
• The cache is configured for data or instruction replacement.
• The single-entry buffer is enabled. Though the default configuration provides a high degree of flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. When reconfiguring the FMC for custom use cases, do not program the FMC's control registers while the flash memory or FlexMemory is being accessed. Instead, change the control registers with a routine executing from RAM in supervisor mode. The FMC's cache and buffering controls within PFB0CR and PFB1CR allow the tuning of resources to suit particular applications' needs. The cache and two buffers are each controlled individually. The register controls enable buffering and prefetching per memory bank and access type (instruction fetch or data reference). The cache also supports three types of LRU replacement algorithms:
• LRU per set across all four ways,
• LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and
• LRU with ways [0-2] for instruction fetches and way [3] for data fetches. As an application example: if both instruction fetches and data references are accessing bank 0, control is available to send instruction fetches, data references, or both to the cache or the single-entry buffer. Likewise, speculation can be enabled or disabled for either type of access. If both instruction fetches and data references are cached, the cache's way resources may be divided in several ways between the instruction fetches and data references. In another application example, the cache can be configured for replacement from bank 0, while the single-entry buffer can be enabled for bank 1 only. This configuration is ideal for applications that use bank 0 for program space and bank 1 for data space. Chapter 27 Flash Memory Controller (FMC) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 617

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 618 Freescale Semiconductor, Inc.

Flash Memory Module (FTFL)

28.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. The FTFL module includes the following accessible memory regions:

• Program flash memory for vector space and code store
• For FlexNVM devices: FlexNVM for data store and additional code store
• For FlexNVM devices: FlexRAM for high-endurance data store or traditional RAM
• For program flash only devices: Programming acceleration RAM to speed flash programming Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. The FTFL module includes a memory controller that executes commands to modify flash memory contents. An erased bit reads '1' and a programmed bit reads '0'. The programming operation is unidirectional; it can only move bits from the '1' state (erased) to the '0' state (programmed). Only the erase operation restores bits from '0' to '1'; bits cannot be programmed from a '0' to a '1'. CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 619

The standard shipping condition for flash memory is erased with security disabled. Data loss over time may occur due to degradation of the erased ('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved.

28.1.1 Features

The FTFL module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device.

28.1.1.1 Program Flash Memory Features

• Sector size of 2 Kbytes
• Program flash protection scheme prevents accidental program or erase of stored data
• Automated, built-in, program and erase algorithms with verify
• Section programming for faster bulk programming times
• For devices containing only program flash memory: Read access to one logical program flash block is possible while programming or erasing data in the other logical program flash block
• For devices containing FlexNVM memory: Read access to program flash memory possible while programming or erasing data in the data flash memory or FlexRAM

28.1.1.2 FlexNVM Memory Features

When FlexNVM is partitioned for data flash memory (on devices that contain FlexNVM memory):

• Sector size of 2 Kbytes
• Protection scheme prevents accidental program or erase of stored data
• Automated, built-in program and erase algorithms with verify Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 620 Freescale Semiconductor, Inc.

• Section programming for faster bulk programming times
• Read access to data flash memory possible while programming or erasing data in the program flash memory

28.1.1.3 Program Acceleration RAM Features

• For devices with only program flash memory: RAM to support section programming

28.1.1.4 FlexRAM Features

For devices with FlexNVM memory:

• Memory that can be used as traditional RAM or as high-endurance EEPROM storage
• Up to 4 Kbytes of FlexRAM configured for EEPROM or traditional RAM operations
• When configured for EEPROM:
• Protection scheme prevents accidental program or erase of data written for EEPROM
• Built-in hardware emulation scheme to automate EEPROM record maintenance functions
• Programmable EEPROM data set size and FlexNVM partition code facilitating EEPROM memory endurance trade-offs
• Supports FlexRAM aligned writes of 1, 2, or 4 bytes at a time
• Read access to FlexRAM possible while programming or erasing data in the program or data flash memory
• When configured for traditional RAM:
• Read and write access possible to the FlexRAM while programming or erasing data in the program or data flash memory

28.1.1.5 Other FTFL Module Features

• Internal high-voltage supply generator for flash memory program and erase operations Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 621

• Optional interrupt generation upon flash command completion
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents

28.1.2 Block Diagram

The block diagram of the FTFL module is shown in the following figure. For devices with FlexNVM feature: FlexNVM FlexRAM Program flash EEPROM backup To MCU's flash controller Interrupt Control registers Status registersRegister access Data flash Memory controller Figure 28-1. FTFL Block Diagram For devices that contain only program flash: Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 622 Freescale Semiconductor, Inc.

To MCU's flash controller Interrupt Control registers Status registersRegister access Memory controller Figure 28-2. FTFL Block Diagram

28.1.3 Glossary

Command write sequence — A series of MCU writes to the Flash FCCOB register group that initiates and controls the execution of Flash algorithms that are built into the FTFL module. Data flash memory — Partitioned from the FlexNVM block, the data flash memory provides nonvolatile storage for user data, boot code, and additional code store. Data flash sector — The data flash sector is the smallest portion of the data flash memory that can be erased. EEPROM — Using a built-in filing system, the FTFL module emulates the characteristics of an EEPROM by effectively providing a high-endurance, byte-writeable (program and erase) NVM. EEPROM backup data header — The EEPROM backup data header is comprised of a 32-bit field found in EEPROM backup data memory which contains information used by the EEPROM filing system to determine the status of a specific EEPROM backup flash sector. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 623

EEPROM backup data record — The EEPROM backup data record is comprised of a 2-bit status field, a 14-bit address field, and a 16-bit data field found in EEPROM backup data memory which is used by the EEPROM filing system. If the status field indicates a record is valid, the data field is mirrored in the FlexRAM at a location determined by the address field. EEPROM backup data memory — Partitioned from the FlexNVM block, EEPROM backup data memory provides nonvolatile storage for the EEPROM filing system representing data written to the FlexRAM requiring highest endurance. EEPROM backup data sector — The EEPROM backup data sector contains one EEPROM backup data header and up to 255 EEPROM backup data records, which are used by the EEPROM filing system. Endurance — The number of times that a flash memory location can be erased and reprogrammed. FCCOB (Flash Common Command Object) — A group of flash registers that are used to pass command, address, data, and any associated parameters to the memory controller in the FTFL module. Flash block — A macro within the FTFL module which provides the nonvolatile memory storage. FlexMemory — FTFL configuration that supports data flash, EEPROM, and FlexRAM. FlexNVM Block — The FlexNVM block can be configured to be used as data flash memory, EEPROM backup flash memory, or a combination of both. FlexRAM — The FlexRAM refers to a RAM, dedicated to the FTFL module, that can be configured to store EEPROM data or as traditional RAM. When configured for EEPROM, valid writes to the FlexRAM generate new EEPROM backup data records stored in the EEPROM backup flash memory. FTFL Module — All flash blocks plus a flash management unit providing high-level control and an interface to MCU buses. IFR — Nonvolatile information register found in each flash block, separate from the main memory array. NVM — Nonvolatile memory. A memory technology that maintains stored data during power-off. The flash array is an NVM using NOR-type flash memory technology. NVM Normal Mode — An NVM mode that provides basic user access to FTFL resources. The CPU or other bus masters initiate flash program and erase operations (or other FTFL commands) using writes to the FCCOB register group in the FTFL module. Introduction K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 624 Freescale Semiconductor, Inc.

NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the FTFL module. A reduced FTFL command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used. Phrase — 64 bits of data with an aligned phrase having byte-address[2:0] = 000. Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00. Word — 16 bits of data with an aligned word having byte-address[0] = 0. Program flash — The program flash memory provides nonvolatile storage for vectors and code store. Program flash Sector — The smallest portion of the program flash memory (consecutive addresses) that can be erased. Retention — The length of time that data can be kept in the NVM without experiencing errors upon readout. Since erased (1) states are subject to degradation just like programmed (0) states, the data retention limit may be reached from the last erase operation (not from the programming time). RWW— Read-While-Write. The ability to simultaneously read from one memory resource while commanded operations are active in another memory resource. Section Program Buffer — Lower half of the programming acceleration FlexRAM allocated for storing large amounts of data for programming via the Program Section command. Secure — An MCU state conveyed to the FTFL module as described in the Chip Configuration details for this device. In the secure state, reading and changing NVM contents is restricted.

28.2 External Signal Description

The FTFL module contains no signals that connect off-chip.

28.3 Memory Map and Registers

This section describes the memory map and registers for the FTFL module. Data read from unimplemented memory space in the FTFL module is undefined. Writes to unimplemented or reserved memory space (registers) in the FTFL module are ignored. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 625

28.3.1 Flash Configuration Field Description

The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the FTFL module. Flash Configuration Field Byte Address Size (Bytes) Field Description 0x0_0400 - 0x0_0407 8 Backdoor Comparison Key. Refer to Verify Backdoor Access Key Command and Unsecuring the Chip Using Backdoor Key Access. 0x0_0408 - 0x0_040B 4 Program flash protection bytes. Refer to the description of the Program Flash Protection Registers (FPROT0-3). 0x0_040F 1 Program flash only devices: Reserved FlexNVM devices: Data flash protection byte. Refer to the description of the Data Flash Protection Register (FDPROT). 0x0_040E 1 Program flash only devices: Reserved FlexNVM devices: EEPROM protection byte. Refer to the description of the EEPROM Protection Register (FEPROT). 0x0_040D 1 Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT). 0x0_040C 1 Flash security byte. Refer to the description of the Flash Security Register (FSEC).

28.3.2 Program Flash IFR Map

The program flash IFR is nonvolatile information memory that can be read freely, but the user has no erase and limited program capabilities (see the Read Once, Program Once, and Read Resource commands in Read Once Command, Program Once Command and Read Resource Command). The contents of the program flash IFR are summarized in the following table and further described in the subsequent paragraphs. For devices that only contain program flash, the program flash IFR is located within the program flash 0 memory block. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 626 Freescale Semiconductor, Inc.

Address Range Size (Bytes) Field Description 0x00 – 0xBF 192 Reserved 0xC0 – 0xFF 64 Program Once Field

28.3.2.1 Program Once Field

The Program Once Field in the program flash IFR provides 64 bytes of user data storage separate from the program flash main array. The user can program the Program Once Field one time only as there is no program flash IFR erase mechanism available to the user. The Program Once Field can be read any number of times. This section of the program flash IFR is accessed in 4-Byte records using the Read Once and Program Once commands (see Read Once Command and Program Once Command).

28.3.3 Data Flash IFR Map

The following only applies to devices with FlexNVM. The data flash IFR is a 256 byte nonvolatile information memory that can be read and erased, but the user has limited program capabilities in the data flash IFR (see the Program Partition command in Program Partition Command, the Erase All Blocks command in Erase All Blocks Command, and the Read Resource command in Read Resource Command). The contents of the data flash IFR are summarized in the following table and further described in the subsequent paragraphs. Address Range Size (Bytes) Field Description 0x00 – 0xFB, 0xFE – 0xFF 254 Reserved 0xFD 1 EEPROM data set size 0xFC 1 FlexNVM partition code

28.3.3.1 EEPROM Data Set Size

The EEPROM data set size byte in the data flash IFR supplies information which determines the amount of FlexRAM used in each of the available EEPROM subsystems. To program the EEESPLIT and EEESIZE values, see the Program Partition command described in Program Partition Command. Table 28-1. EEPROM Data Set Size Data flash IFR: 0x00FD 7 6 5 4 3 2 1 0 Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 627

Table 28-1. EEPROM Data Set Size (continued) 1 1 EEESPLIT EEESIZE = Unimplemented or Reserved Table 28-2. EEPROM Data Set Size Field Description Field Description 7-6 Reserved This read-only bitfield is reserved and must always be written as one. 5-4 EEESPLIT EEPROM Split Factor — Determines the relative sizes of the two EEPROM subsystems. ‘00’ = Subsystem A: EEESIZE*1/8, subsystem B: EEESIZE*7/8 ‘01’ = Subsystem A: EEESIZE*1/4, subsystem B: EEESIZE*3/4 ‘10’ = Subsystem A: EEESIZE*1/2, subsystem B: EEESIZE*1/2 ‘11’ = Subsystem A: EEESIZE*1/2, subsystem B: EEESIZE*1/2 3-0 EEESIZE EEPROM Size — Encoding of the total available FlexRAM for EEPROM use. NOTE: EEESIZE must be 0 bytes (1111b) when the FlexNVM partition code (FlexNVM Partition Code) is set to 'No EEPROM'. '0000' = Reserved '0001' = Reserved '0010' = 4,096 Bytes '0011' = 2,048 Bytes '0100' = 1,024 Bytes '0101' = 512 Bytes '0110' = 256 Bytes '0111' = 128 Bytes '1000' = 64 Bytes '1001' = 32 Bytes '1010' = Reserved '1011' = Reserved '1100' = Reserved '1101' = Reserved '1110' = Reserved '1111' = 0 Bytes

28.3.3.2 FlexNVM Partition Code

The FlexNVM Partition Code byte in the data flash IFR supplies a code which specifies how to split the FlexNVM block between data flash memory and EEPROM backup memory supporting EEPROM functions. To program the DEPART value, see the Program Partition command described in Program Partition Command. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 628 Freescale Semiconductor, Inc.

Table 28-3. FlexNVM Partition Code Data Flash IFR: 0x00FC 7 6 5 4 3 2 1 0 1 1 1 1 DEPART = Unimplemented or Reserved Table 28-4. FlexNVM Partition Code Field Description Field Description 7-4 Reserved This read-only bitfield is reserved and must always be written as one. 3-0 DEPART FlexNVM Partition Code — Encoding of the data flash / EEPROM backup split within the FlexNVM memory block. FlexNVM memory not partitioned for data flash will be used to store EEPROM records. DEPART Data flash (KByte) EEPROM backup (KByte) 0000 256 0

0001 Reserved Reserved

0010 Reserved Reserved

0111 Reserved Reserved

1001 Reserved Reserved

1010 Reserved Reserved

1111 Reserved Reserved

28.3.4 Register Descriptions

The FTFL module contains a set of memory-mapped control and status registers. NOTE While a command is running (FSTAT[CCIF]=0), register writes are not accepted to any register except FCNFG and FSTAT. The no-write rule is relaxed during the start-up reset Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 629

sequence, prior to the initial rise of CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). FTFL memory map Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4002_0000 Flash Status Register (FTFL_FSTAT) 8 R/W 00h 28.34.1/ 631 4002_0001 Flash Configuration Register (FTFL_FCNFG) 8 R/W 00h 28.34.2/ 632 4002_0002 Flash Security Register (FTFL_FSEC) 8 R Undefined 28.34.3/ 634 4002_0003 Flash Option Register (FTFL_FOPT) 8 R Undefined 28.34.4/ 636 4002_0004 Flash Common Command Object Registers (FTFL_FCCOB3) 8 R/W 00h 28.34.5/ 637 4002_0005 Flash Common Command Object Registers (FTFL_FCCOB2) 8 R/W 00h 28.34.5/ 637 4002_0006 Flash Common Command Object Registers (FTFL_FCCOB1) 8 R/W 00h 28.34.5/ 637 4002_0007 Flash Common Command Object Registers (FTFL_FCCOB0) 8 R/W 00h 28.34.5/ 637 4002_0008 Flash Common Command Object Registers (FTFL_FCCOB7) 8 R/W 00h 28.34.5/ 637 4002_0009 Flash Common Command Object Registers (FTFL_FCCOB6) 8 R/W 00h 28.34.5/ 637 4002_000A Flash Common Command Object Registers (FTFL_FCCOB5) 8 R/W 00h 28.34.5/ 637 4002_000B Flash Common Command Object Registers (FTFL_FCCOB4) 8 R/W 00h 28.34.5/ 637 4002_000C Flash Common Command Object Registers (FTFL_FCCOBB) 8 R/W 00h 28.34.5/ 637 4002_000D Flash Common Command Object Registers (FTFL_FCCOBA) 8 R/W 00h 28.34.5/ 637 4002_000E Flash Common Command Object Registers (FTFL_FCCOB9) 8 R/W 00h 28.34.5/ 637 4002_000F Flash Common Command Object Registers (FTFL_FCCOB8) 8 R/W 00h 28.34.5/ 637 Table continues on the next page... Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 630 Freescale Semiconductor, Inc.

FTFL memory map (continued) Absolute address (hex) Register name Width (in bits) Access Reset value Section/ page 4002_0010 Program Flash Protection Registers (FTFL_FPROT3) 8 R/W Undefined 28.34.6/ 638 4002_0011 Program Flash Protection Registers (FTFL_FPROT2) 8 R/W Undefined 28.34.6/ 638 4002_0012 Program Flash Protection Registers (FTFL_FPROT1) 8 R/W Undefined 28.34.6/ 638 4002_0013 Program Flash Protection Registers (FTFL_FPROT0) 8 R/W Undefined 28.34.6/ 638 4002_0016 EEPROM Protection Register (FTFL_FEPROT) 8 R/W Undefined 28.34.7/ 639 4002_0017 Data Flash Protection Register (FTFL_FDPROT) 8 R/W Undefined 28.34.8/ 641

28.34.1 Flash Status Register (FTFL_FSTAT)

The FSTAT register reports the operational status of the FTFL module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. NOTE When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of any more commands until the flag is cleared (by writing a one to it). Address: FTFL_FSTAT is 4002_0000h base + 0h offset = 4002_0000h Bit 7 6 5 4 3 2 1 0 Read CCIF RDCOLERR ACCERR FPVIOL 0 MGSTAT0 Write w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 FTFL_FSTAT field descriptions Field Description CCIF Command Complete Interrupt Flag The CCIF flag indicates that a FTFL command or EEPROM file system operation has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low until command completion or command violation. The CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE, and CCIF stays low until the EEPROM file system has created the associated EEPROM data record. Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 631

FTFL_FSTAT field descriptions (continued) Field Description The CCIF bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization sequence. Depending on how quickly the read occurs after reset release, the user may or may not see the 0 hardware reset value.

0 FTFL command or EEPROM file system operation in progress

1 FTFL command or EEPROM file system operation has completed

FTFL Read Collision Error Flag The RDCOLERR error bit indicates that the MCU attempted a read from an FTFL resource that was being manipulated by an FTFL command (CCIF=0). Any simultaneous access is detected as a collision error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect.

0 No collision error detected

1 Collision error detected

The ACCERR error bit indicates an illegal access has occurred to an FTFL resource caused by a violation of the command write sequence or issuing an illegal FTFL command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit has no effect.

0 No access error detected

1 Access error detected

Flash Protection Violation Flag The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area of program flash or data flash memory during a command write sequence or a write was attempted to a protected area of the FlexRAM while enabled for EEPROM . While FPVIOL is set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect.

0 No protection violation detected

1 Protection violation detected

3–1 Reserved This read-only field is reserved and always has the value zero. MGSTAT0 Memory Controller Command Completion Status Flag The MGSTAT0 status flag is set if an error is detected during execution of an FTFL command or during the flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the other error flags in this register. The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution when CCIF=1 and before the next command has been launched. At some point during the execution of "command-N+1," the previous result is discarded and any previous error is cleared.

28.34.2 Flash Configuration Register (FTFL_FCNFG)

This register provides information on the current functional state of the FTFL module. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 632 Freescale Semiconductor, Inc.

The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. SWAP, PFLSH, RAMRDY , and EEERDY are read-only status bits . The unassigned bits read as noted and are not writable. The reset values for the SWAP, PFLSH, RAMRDY , and EEERDY bits are determined during the reset sequence. Address: FTFL_FCNFG is 4002_0000h base + 1h offset = 4002_0001h Bit 7 6 5 4 3 2 1 0 Read CCIE RDCOLLIE ERSAREQ ERSSUSP SWAP PFLSH RAMRDY EEERDY Write Reset 0 0 0 0 0 0 0 0 FTFL_FCNFG field descriptions Field Description CCIE Command Complete Interrupt Enable The CCIE bit controls interrupt generation when an FTFL command completes.

0 Command complete interrupt disabled

1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. RDCOLLIE Read Collision Error Interrupt Enable The RDCOLLIE bit controls interrupt generation when an FTFL read collision error occurs.

0 Read collision error interrupt disabled

1 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFL read collision error is detected (see the description of FSTAT[RDCOLERR]). ERSAREQ Erase All Request This bit issues a request to the memory controller to execute the Erase All Blocks command and release security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip Configuration details on how to request this command. The ERSAREQ bit sets when an erase all request is triggered external to the FTFL and CCIF is set (no command is currently being executed). ERSAREQ is cleared by the FTFL when the operation completes.

0 No request or request complete

1 Request to:

1. run the Erase All Blocks command, 2. verify the erased state, 3. program the security byte in the Flash Configuration Field to the unsecure state, and 4. release MCU security by setting the FSEC[SEC] field to the unsecure state. ERSSUSP Erase Suspend The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is executing.

0 No suspend requested

1 Suspend the current Erase Flash Sector command execution. SWAP Swap Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 633

FTFL_FCNFG field descriptions (continued) Field Description For program flash only configurations, the SWAP flag indicates which physical program flash block is located at relative address 0x0000. The state of the SWAP flag is set by the FTFL during the reset sequence . See the Swap Control command section for information on swap management.

0 Physical program flash 0 is located at relative address 0x0000

1 If the PFLSH flag is set, physical program flash 1 is located at relative address 0x0000. If the PFLSH flag is not set, physical program flash 0 is located at relative address 0x0000 PFLSH FTFL configuration

0 For devices with FlexNVM: FTFL configured for FlexMemory that supports data flash and/or

EEPROM For devices with program flash only: Reserved

1 For devices with FlexNVM: Reserved For devices with program flash only: FTFL configured for

program flash only, without support for data flash and/or EEPROM RAMRDY RAM Ready This flag indicates the current status of the FlexRAM /programming acceleration RAM . For devices with FlexNVM: The state of the RAMRDY flag is normally controlled by the Set FlexRAM Function command. During the reset sequence, the RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and is set if the FlexNVM block is not partitioned for EEPROM. The RAMRDY flag is cleared if the Program Partition command is run to partition the FlexNVM block for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks command or execution of the erase-all operation triggered external to the FTFL . For devices without FlexNVM: This bit should always be set. 0 For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available.

1 For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do

not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available. EEERDY For devices with FlexNVM: This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access. For devices without FlexNVM: This field is reserved. 0 For devices with FlexNVM: FlexRAM is not available for EEPROM operation.

1 For devices with FlexNVM: FlexRAM is available for EEPROM operations where:

• reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and
• writes to the FlexRAM clear EEERDY and launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup.

28.34.3 Flash Security Register (FTFL_FSEC)

This read-only register holds all bits associated with the security of the MCU and FTFL module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory. The Flash basis for the values is signified by X in the reset value. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 634 Freescale Semiconductor, Inc.

Address: FTFL_FSEC is 4002_0000h base + 2h offset = 4002_0002h Bit 7 6 5 4 3 2 1 0 Read KEYEN MEEN FSLACC SEC Write * Notes: x = Undefined at reset.• FTFL_FSEC field descriptions Field Description 7–6 KEYEN Backdoor Key Security Enable These bits enable and disable backdoor key access to the FTFL module.

00 Backdoor key access disabled

01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)

10 Backdoor key access enabled

11 Backdoor key access disabled

5–4 MEEN Mass Erase Enable Bits Enables and disables mass erase capability of the FTFL module. The state of the MEEN bits is only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does not matter.

00 Mass erase is enabled

01 Mass erase is enabled

10 Mass erase is disabled

11 Mass erase is enabled

3–2 FSLACC Freescale Failure Analysis Access Code These bits enable or disable access to the flash memory contents during returned part failure analysis at Freescale. When SEC is secure and FSLACC is denied, access to the program flash contents is denied and any failure analysis performed by Freescale factory test must begin with a full erase to unsecure the part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), Freescale factory testing has visibility of the current flash contents. The state of the FSLACC bits is only relevant when the SEC bits are set to secure. When the SEC field is set to unsecure, the FSLACC setting does not matter.

00 Freescale factory access granted

01 Freescale factory access denied

10 Freescale factory access denied

11 Freescale factory access granted

1–0 SEC Flash Security These bits define the security state of the MCU. In the secure state, the MCU limits access to FTFL module resources. The limitations are defined per device and are detailed in the Chip Configuration details. If the FTFL module is unsecured using backdoor key access, the SEC bits are forced to 10b.

00 MCU security status is secure

01 MCU security status is secure

Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 635

FTFL_FSEC field descriptions (continued) Field Description 10 MCU security status is unsecure (The standard shipping condition of the FTFL is unsecure.)

11 MCU security status is secure

28.34.4 Flash Option Register (FTFL_FOPT)

The flash option register allows the MCU to customize its operations by examining the state of these read-only bits, which are loaded from NVM at reset. The function of the bits is defined in the device's Chip Configuration details. All bits in the register are read-only . During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. Address: FTFL_FOPT is 4002_0000h base + 3h offset = 4002_0003h Bit 7 6 5 4 3 2 1 0 Read OPT Write * Notes: x = Undefined at reset.• FTFL_FOPT field descriptions Field Description 7–0 OPT Nonvolatile Option These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 636 Freescale Semiconductor, Inc.

28.34.5 Flash Common Command Object Registers

(FTFL_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB. Addresses: 4002_0000h base + 4h offset + (1d × n), where n = 0d to 11d Bit 7 6 5 4 3 2 1 0 Read CCOBn Write Reset 0 0 0 0 0 0 0 0 FTFL_FCCOBn field descriptions Field Description 7–0 CCOBn The FCCOB register provides a command code and relevant parameters to the memory controller. The individual registers that compose the FCCOB data set can be written in any order, but you must provide all needed values, which vary from command to command. First, set up all required FCCOB fields and then initiate the command’s execution by writing a 1 to the FSTAT[CCIF] bit. This clears the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed by the user until the command completes (CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded only after the current command completes. Some commands return information to the FCCOB registers. Any values returned to FCCOB are available for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a generic FTFL command format. The first FCCOB register, FCCOB0, always contains the command code. This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific FTFL command, typically an address and/or data values. NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the byte number). This number is a reference to the FCCOB register name and is not the register address. FCCOB Number Typical Command Parameter Contents [7:0]

0 FCMD (a code that defines the FTFL command)

1 Flash address [23:16]

2 Flash address [15:8]

3 Flash address [7:0]

4 Data Byte 0

5 Data Byte 1

6 Data Byte 2

7 Data Byte 3

8 Data Byte 4

9 Data Byte 5

Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 637

FTFL_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] A Data Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access : The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number. The FCCOB register group may be read and written as individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).

28.34.6 Program Flash Protection Registers (FTFL_FPROTn)

The FPROT registers define which logical program flash regions are protected from program and erase operations. Protected flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any FTFL command. Unprotected regions can be changed by program and erase operations. The four FPROT registers allow 32 protectable regions. Each bit protects a 1/32 region of the program flash memory. The bitfields are defined in each register as follows: Program flash protection register Program flash protection bits FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset sequence, the FPROT registers are loaded with the contents of the program flash protection bytes in the Flash Configuration Field as indicated in the following table. Program flash protection register Flash Configuration Field offset address FPROT0 0x0008 FPROT1 0x0009 FPROT2 0x000A FPROT3 0x000B To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration Field. Then, reprogram the program flash protection byte. Memory Map and Registers K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 638 Freescale Semiconductor, Inc.

Addresses: FTFL_FPROT3 is 4002_0000h base + 10h offset = 4002_0010h FTFL_FPROT2 is 4002_0000h base + 11h offset = 4002_0011h FTFL_FPROT1 is 4002_0000h base + 12h offset = 4002_0012h FTFL_FPROT0 is 4002_0000h base + 13h offset = 4002_0013h Bit 7 6 5 4 3 2 1 0 Read PROT Write * Notes: x = Undefined at reset.• FTFL_FPROTn field descriptions Field Description 7–0 PROT Program Flash Region Protect Each program flash region can be protected from program and erase operations by setting the associated PROT bit. In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory can be protected, but currently protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored . In NVM Special mode: All bits of FPROT are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: The user must never write to any FPROT register while a command is running (CCIF=0). Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. Each bit in the 32-bit protection register represents 1/32 of the total program flash . 0 Program flash region is protected.

1 Program flash region is not protected

28.34.7 EEPROM Protection Register (FTFL_FEPROT)

For devices with FlexNVM: The FEPROT register defines which EEPROM regions of the FlexRAM are protected against program and erase operations. Protected EEPROM regions cannot have their content changed by writing to it. Unprotected regions can be changed by writing to the FlexRAM. For devices with program flash only: This register is reserved and not used. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 639

Address: FTFL_FEPROT is 4002_0000h base + 16h offset = 4002_0016h Bit 7 6 5 4 3 2 1 0 Read EPROT Write * Notes: x = Undefined at reset.• FTFL_FEPROT field descriptions Field Description 7–0 EPROT EEPROM Region Protect For devices with program flash only: Reserved For devices with FlexNVM: Individual EEPROM regions can be protected from alteration by setting the associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is set to data flash only. When the FlexNVM Partition Code is set to data flash and EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal mode: The protection can only be increased. This means that currently-unprotected memory can be protected, but currently-protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored . In NVM Special mode : All bits of the FEPROT register are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: Never write to the FEPROT register while a command is running (CCIF=0). Reset: During the reset sequence, the FEPROT register is loaded with the contents of the FlexRAM protection byte in the Flash Configuration Field located in program flash. The flash basis for the reset values is signified by X in the register diagram. To change the EEPROM protection that will be loaded during the reset sequence, the sector of program flash that contains the Flash Configuration Field must be unprotected; then the EEPROM protection byte must be erased and reprogrammed. Trying to alter data by writing to any protected area in the EEPROM results in a protection violation error and sets the FPVIOL bit in the FSTAT register.

0 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is

1 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 640 Freescale Semiconductor, Inc.

28.34.8 Data Flash Protection Register (FTFL_FDPROT)

The FDPROT register defines which data flash regions are protected against program and erase operations. Protected Flash regions cannot have their content changed; that is, these regions cannot be programmed and cannot be erased by any FTFL command. Unprotected regions can be changed by both program and erase operations. Address: FTFL_FDPROT is 4002_0000h base + 17h offset = 4002_0017h Bit 7 6 5 4 3 2 1 0 Read DPROT Write * Notes: x = Undefined at reset.• FTFL_FDPROT field descriptions Field Description 7–0 DPROT Data Flash Region Protect Individual data flash regions can be protected from program and erase operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of the partitioned data flash memory space. The granularity of data flash protection cannot be less than the data flash sector size. If an unused DPROT bit is set, the Erase all Blocks command does not execute and the FSTAT[FPVIOL] flag is set. In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory can be protected but currently protected memory cannot be unprotected. Since unprotected regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit basis. Those FDPROT bits with 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are ignored . In NVM Special mode: All bits of the FDPROT register are writable without restriction. Unprotected areas can be protected and protected areas can be unprotected. Restriction: The user must never write to the FDPROT register while a command is running (CCIF=0). Reset: During the reset sequence, the FDPROT register is loaded with the contents of the data flash protection byte in the Flash Configuration Field located in program flash memory. The flash basis for the reset values is signified by X in the register diagram. To change the data flash protection that will be loaded during the reset sequence, unprotect the sector of program flash that contains the Flash Configuration Field. Then, erase and reprogram the data flash protection byte. Trying to alter data with the program and erase commands in any protected area in the data flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of the data flash memory (see the Erase Flash Block command description) is not possible if the data flash memory contains any protected region or if the FlexNVM block has been partitioned for EEPROM.

0 Data Flash region is protected

1 Data Flash region is not protected

Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 641

28.4 Functional Description

The following sections describe functional details of the FTFL module.

28.4.1 Program Flash Memory Swap

For devices that only contain program flash memory: The user can configure the logical memory map of the program flash space such that either of the two physical program flash blocks can exist at relative address 0x0000. This swap feature enables the lower half of the logical program flash space to be operational while the upper half is being updated for future use. The Swap Control command handles swapping the two logical P-Flash memory blocks within the memory map. See Swap Control Command for details.

28.4.2 Flash Protection

Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers:

• FPROT n — Four registers that protect 32 regions of the program flash memory as shown in the following figure Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 Program flash size / 32 FPROT3[PROT0] 0x0_0000 FPROT3[PROT1] FPROT3[PROT2] FPROT3[PROT3] FPROT0[PROT29] FPROT0[PROT31] FPROT0[PROT30] Program flash Last program flash address Figure 28-27. Program flash protection Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 642 Freescale Semiconductor, Inc.

• FDPROT —
• For 2 n data flash sizes, protects eight regions of the data flash memory as shown in the following figure Data flash size / 8 DPROT0 0x0_0000 DPROT1 DPROT2 DPROT3 DPROT5 DPROT7 DPROT6 FlexNVM Last data flash address Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 Data flash size / 8 DPROT4 EEPROM backup EEPROM backup size (DEPART) Last FlexNVM address Figure 28-28. Data flash protection
• For the non-2 n data flash sizes (192KB and 224KB), the protection granularity is 32KB. Therefore, for 192KB data flash size, only the DPROT[5:0] bits are used, and for 224KB data flash size, only the DPROT[6:0] bits are used. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 643

28.4.3 FlexNVM Description

This section describes the FlexNVM memory. This section does not apply for devices that contain only program flash memory.

28.4.3.1 FlexNVM Block Partitioning for FlexRAM

The user can configure the FlexNVM block as either:

• Basic data flash,
• EEPROM flash records to support the built-in EEPROM feature, or
• A combination of both. The user's FlexNVM configuration choice is specified using the Program Partition command described in Program Partition Command. CAUTION While different partitions of the FlexNVM block are available, the intention is that a single partition choice is used throughout the entire lifetime of a given application. The FlexNVM partition code choices affect the endurance and data retention characteristics of the device.

28.4.3.2 EEPROM User Perspective

The EEPROM system is shown in the following figure. File system handler User access (effective EEPROM) FlexRAM EEPROM backup with 1KByte erase sectors Figure 28-31. Top Level EEPROM Architecture To handle varying customer requirements, the FlexRAM and FlexNVM blocks can be split into partitions as shown in the figure below. 1. EEPROM partition (EEESIZE) — The amount of FlexRAM used for EEPROM can be set from 0 Bytes (no EEPROM) to the maximum FlexRAM size (see Table 28-2). The remainder of the FlexRAM is not accessible while the FlexRAM is Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 645

configured for EEPROM (see Set FlexRAM Function Command). The EEPROM partition grows upward from the bottom of the FlexRAM address space. 2. Data flash partition (DEPART) — The amount of FlexNVM memory used for data flash can be programmed from 0 bytes (all of the FlexNVM block is available for EEPROM backup) to the maximum size of the FlexNVM block (see Table 28-4). 3. FlexNVM EEPROM partition — The amount of FlexNVM memory used for EEPROM backup, which is equal to the FlexNVM block size minus the data flash memory partition size. The EEPROM backup size must be at least 16 times the EEPROM partition size in FlexRAM. 4. EEPROM split factor (EEESPLIT) — The FlexRAM partitioned for EEPROM can be divided into two subsystems, each backed by half of the partitioned EEPROM backup. One subsystem (A) is 1/8, 1/4, or 1/2 of the partitioned FlexRAM with the remainder belonging to the other subsystem (B). The partition information (EEESIZE, DEPART, EEESPLIT) is stored in the data flash IFR and is programmed using the Program Partition command (see Program Partition Command). Typically, the Program Partition command is executed only once in the lifetime of the device. Data flash memory is useful for applications that need to quickly store large amounts of data or store data that is static. The EEPROM partition in FlexRAM is useful for storing smaller amounts of data that will be changed often. The EEPROM partition in FlexRAM can be further sub-divided to provide subsystems, each backed by the same amount of EEPROM backup with subsystem A having higher endurance if the split factor is 1/8 or 1/4. Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 646 Freescale Semiconductor, Inc.

Size of EEPROM partition A = EEESIZE x EEESPLIT Data flash 0 and 1 interleaved Data flash 0 EEPROM partition B EEPROM backup A EEESPLIT = 1/8, 1/4, or 1/2 Figure 28-32. FlexRAM to FlexNVM Memory Mapping with 2 Sub-systems

28.4.3.3 EEPROM Implementation Overview

Out of reset with the FSTAT[CCIF] bit clear, the partition settings (EEESIZE, DEPART, EEESPLIT) are read from the data flash IFR and the EEPROM file system is initialized accordingly. The EEPROM file system locates all valid EEPROM data records in EEPROM backup and copies the newest data to FlexRAM. The FSTAT[CCIF] and FCNFG[EEERDY] bits are set after data from all valid EEPROM data records is copied to the FlexRAM. After the CCIF bit is set, the FlexRAM is available for read or write access. When configured for EEPROM use, writes to an unprotected location in FlexRAM invokes the EEPROM file system to program a new EEPROM data record in the EEPROM backup memory in a round-robin fashion. As needed, the EEPROM file system identifies the EEPROM backup sector that is being erased for future use and partially erases that EEPROM backup sector. After a write to the FlexRAM, the FlexRAM is not accessible until the FSTAT[CCIF] bit is set. The FCNFG[EEERDY] bit will also be set. If enabled, the interrupt associated with the FSTAT[CCIF] bit can be used to determine when the FlexRAM is available for read or write access. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 647

After a sector in EEPROM backup is full of EEPROM data records, EEPROM data records from the sector holding the oldest data are gradually copied over to a previously- erased EEPROM backup sector. When the sector copy completes, the EEPROM backup sector holding the oldest data is tagged for erase.

28.4.3.4 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFL to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = × Write_efficiency × nEEPROM – 2 × EEESPLIT × EEESIZEEEESPLIT × EEESIZEnvmcycd where

• Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)
• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with Program Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• n nvmcycd — data flash cycling endurance Functional Description K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 648 Freescale Semiconductor, Inc.

Figure 28-33. EEPROM backup writes to FlexRAM

28.4.4 Interrupts

The FTFL module can generate interrupt requests to the MCU upon the occurrence of various FTFL events. These interrupt events and their associated status and control bits are shown in the following table. Table 28-30. FTFL Interrupt Sources FTFL Event Readable Status Bit Interrupt Enable Bit FTFL Command Complete FSTAT[CCIF] FCNFG[CCIE] FTFL Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] Note Vector addresses and their relative interrupt priority are determined at the MCU level. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 649

Flash Operation in Low-Power Modes

28.4.5.1 Wait Mode

When the MCU enters wait mode, the FTFL module is not affected. The FTFL module can recover the MCU from wait via the command complete interrupt (see Interrupts).

28.4.5.2 Stop Mode

When the MCU requests stop mode, if an FTFL command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode. CAUTION The MCU should never enter stop mode while any FTFL command is running (CCIF = 0). NOTE While the MCU is in very-low-power modes (VLPR, VLPW, VLPS), the FTFL module does not accept flash commands.

28.4.6 Functional Modes of Operation

The FTFL module has two operating modes: NVM Normal and NVM Special. The operating mode affects the command set availability (see Table 28-31). Refer to the Chip Configuration details of this device for how to activate each mode.

28.4.7 Flash Reads and Ignored Writes

The FTFL module requires only the flash address to execute a flash memory read. MCU read access is available to all flash blocks. The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block while any command is processing within that block. The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the FSTAT[RDCOLERR] bit). 28.4.5 Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 650 Freescale Semiconductor, Inc.

28.4.8 Read While Write (RWW)

The following simultaneous accesses are allowed for devices with FlexNVM:

• The user may read from the program flash memory while commands (typically program and erase operations) are active in the data flash and FlexRAM memory space.
• The MCU can fetch instructions from program flash during both data flash program and erase operations and while EEPROM backup data is maintained by the EEPROM commands.
• Conversely, the user may read from data flash and FlexRAM while program and erase commands are executing on the program flash.
• When configured as traditional RAM, writes to the FlexRAM are allowed during program and data flash operations. Simultaneous data flash operations and FlexRAM writes, when FlexRAM is used for EEPROM, are not possible. The following simultaneous accesses are allowed for devices with program flash only:
• The user may read from one logical program flash memory space while commands (typically program and erase operations) are active in the other logical program flash memory space. Simultaneous operations are further discussed in Allowed Simultaneous Flash Operations.

28.4.9 Flash Program and Erase

All flash functions except read require the user to setup and launch an FTFL command through a series of peripheral bus writes. The user cannot initiate any further FTFL commands until notified that the current command has completed. The FTFL command structure and operation are detailed in FTFL Command Operations.

28.4.10 FTFL Command Operations

FTFL command operations are typically used to modify flash memory contents. The next sections describe: Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 651

• The command write sequence used to set FTFL command parameters and launch execution
• A description of all FTFL commands available

28.4.10.1 Command Write Sequence

FTFL commands are specified using a command write sequence illustrated in Figure 28-34. The FTFL module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed. If CCIF is zero, the previous command execution is still active, a new command write sequence cannot be started, and all writes to the FCCOB registers are ignored.

28.4.10.1.1 Load the FCCOB Registers

The user must load the FCCOB registers with all parameters required by the desired FTFL command. The individual registers that make up the FCCOB data set can be written in any order.

28.4.10.1.2 Launch the Command by Clearing CCIF

Once all relevant command parameters have been loaded, the user launches the command by clearing the FSTAT[CCIF] bit by writing a '1' to it. The CCIF flag remains zero until the FTFL command completes. The FSTAT register contains a blocking mechanism, which prevents a new command from launching (can't clear CCIF) if the previous command resulted in an access error (FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error scenarios, two writes to FSTAT are required to initiate the next command: the first write clears the error flags, the second write clears CCIF.

28.4.10.1.3 Command Execution and Error Reporting

The command processing has several steps: 1. The FTFL reads the command code and performs a series of parameter checks and protection checks, if applicable, which are unique to each command. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 652 Freescale Semiconductor, Inc.

If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, access errors suggest that the command was not set-up with valid parameters in the FCCOB register group. Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set. Command processing never proceeds to execution when the parameter or protection step fails. Instead, command processing is terminated after setting the FSTAT[CCIF] bit. 2. If the parameter and protection checks pass, the command proceeds to execution. Run-time errors, such as failure to erase verify, may occur during the execution phase. Run-time errors are reported in the FSTAT[MGSTAT0] bit. A command may have access errors, protection errors, and run-time errors, but the run-time errors are not seen until all access and protection errors have been corrected. 3. Command execution results, if applicalbe, are reported back to the user via the FCCOB and FSTAT registers. 4. The FTFL sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 653

Clear the CCIF to launch the command Write 0x80 to FSTAT register Clear the old errors Access Error and Protection Violation Check FCCOB ACCERR/ FPVIOL Set? EXIT Write to the FCCOB registers to load the required command parameter. More Parameters? Availability Check Results from previous command Read: FSTAT register Write 0x30 to FSTAT register no yes no yes Previous command complete? no CCIF = ‘1’? yes START Figure 28-34. Generic FTFL Command Write Sequence Flowchart

28.4.10.2 FTFL Commands

The following table summarizes the function of all FTFL commands. If the program flash, data flash, or FlexRAM column is marked with an 'X', the FTFL command is relevant to that particular memory resource. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 654 Freescale Semiconductor, Inc.

(Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x00 Read 1s Block × × × Verify that a program flash or data flash block is erased. FlexNVM block must not be partitioned for EEPROM. 0x01 Read 1s Section × × × Verify that a given number of program flash or data flash locations from a starting address are erased. 0x02 Program Check × × × Tests previously- programmed locations at margin read levels. 0x03 Read Resource IFR IFR IFR Read 4 bytes from program flash IFR, data flash IFR, or version ID. 0x06 Program Longword × × × Program 4 bytes in a program flash block or a data flash block. 0x08 Erase Flash Block × × × Erase a program flash block or data flash block. An erase of any flash block is only possible when unprotected. FlexNVM block must not be partitioned for EEPROM. 0x09 Erase Flash Sector × × × Erase all bytes in a program flash or data flash sector. Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 655

(Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x0B Program Section × × × × Program data from the Section Program Buffer to a program flash or data flash block. 0x40 Read 1s All Blocks × × × Verify that all program flash, data flash blocks, EEPROM backup data records, and data flash IFR are erased then release MCU security. 0x41 Read Once IFR Read 4 bytes of a dedicated 64 byte field in the program flash 0 IFR. 0x43 Program Once IFR One-time program of 4 bytes of a dedicated 64- byte field in the program flash 0 IFR. Table continues on the next page... Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 656 Freescale Semiconductor, Inc.

(Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x44 Erase All Blocks × × × × Erase all program flash blocks, program flash 1 IFR, data flash blocks, FlexRAM, EEPROM backup data records, and data flash IFR. Then, verify- erase and release MCU security. NOTE: An erase is only possible when all memory locations are unprotected. 0x45 Verify Backdoor Access Key × × Release MCU security after comparing a set of user-supplied security keys to those stored in the program flash. 0x46 Swap Control × × Handles swap- related activities 0x80 Program Partition IFR × Program the FlexNVM Partition Code and EEPROM Data Set Size into the data flash IFR. Format all EEPROM backup data sectors allocated for EEPROM. Initialize the FlexRAM. Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 657

(Devices with only program flash) Data flash (Devices with FlexNVM) FlexRAM (Devices with FlexNVM) Function 0x81 Set FlexRAM Function x × Switches FlexRAM function between RAM and EEPROM. When switching to EEPROM, FlexNVM is not available while valid data records are being copied from EEPROM backup to FlexRAM.

28.4.10.3 FTFL Commands by Mode

The following table shows the FTFL commands that can be executed in each flash operating mode. Table 28-31. FTFL Commands by Mode FCMD Command NVM Normal NVM Special Unsecure Secure MEEN=10 Unsecure Secure MEEN=10 0x00 Read 1s Block × × × × — — 0x01 Read 1s Section × × × × — — 0x02 Program Check × × × × — — 0x03 Read Resource × × × × — — 0x06 Program Longword × × × × — — 0x08 Erase Flash Block × × × × — — 0x09 Erase Flash Sector × × × × — — 0x0B Program Section × × × × — — 0x40 Read 1s All Blocks × × × × × — 0x44 Erase All Blocks × × × × × — 0x45 Verify Backdoor Access Table continues on the next page... Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 658 Freescale Semiconductor, Inc.

Table 28-31. FTFL Commands by Mode (continued) FCMD Command NVM Normal NVM Special Unsecure Secure MEEN=10 Unsecure Secure MEEN=10 0x80 Program Partition × × × × — — 0x81 Set FlexRAM Function × × × × — —

28.4.10.4 Allowed Simultaneous Flash Operations

Only the operations marked 'OK' in the following table are permitted to run simultaneously on the program flash, data flash, and FlexRAM memories. Some operations cannot be executed simultaneously because certain hardware resources are shared by the memories. The priority has been placed on permitting program flash reads while program and erase operations execute on the FlexNVM and FlexRAM. This provides read (program flash) while write (FlexNVM, FlexRAM) functionality. For devices containing FlexNVM: Table 28-32. Allowed Simultaneous Memory Operations Program Flash Data Flash FlexRAM Read Program Sector Erase Read Program Sector Erase Read E-Write1 R-Write2 Program flash Read — OK OK OK Program — OK OK OK3 Sector Erase — OK OK OK Data flash Read OK OK — Program OK — OK OK Sector Erase OK — OK OK FlexRAM Read OK OK OK OK — E-Write1 OK — R-Write2 OK OK OK OK — 1. When FlexRAM configured for EEPROM (writes are effectively multi-cycle operations). 2. When FlexRAM configured as traditional RAM (writes are single-cycle operations). 3. When FlexRAM configured as traditional RAM, writes to the RAM are ignored while the Program Section command is active (CCIF = 0). For devices containing program flash only: Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 659

Table 28-33. Allowed Simultaneous Memory Operations Program Flash 0 Program Flash 1 Read Program Sector Erase Read Program Sector Erase Program flash 0 Read — OK OK Program — OK Sector Erase — OK Program flash 1 Read OK OK — Program OK — Sector Erase OK —

28.4.11 Margin Read Commands

The Read-1s commands (Read 1s All Blocks, Read 1s Block, and Read 1s Section) and the Program Check command have a margin choice parameter that allows the user to apply non-standard read reference levels to the program flash and data flash array reads performed by these commands. Using the preset 'user' and 'factory' margin levels, these commands perform their associated read operations at tighter tolerances than a 'normal' read. These non-standard read levels are applied only during the command execution. All simple (uncommanded) flash array reads to the MCU always use the standard, un- margined, read reference level. Only the 'normal' read level should be employed during normal flash usage. The non- standard, 'user' and 'factory' margin levels should be employed only in special cases. They can be used during special diagnostic routines to gain confidence that the device is not suffering from the end-of-life data loss customary of flash memory devices. Erased ('1') and programmed ('0') bit states can degrade due to elapsed time and data cycling (number of times a bit is erased and re-programmed). The lifetime of the erased states is relative to the last erase operation. The lifetime of the programmed states is measured from the last program time. The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. The 'user' margin is a small delta to the normal read reference level. 'User' margin levels can be employed to check that flash memory contents have adequate margin for normal level read operations. If unexpected read results are encountered when checking flash memory contents at the 'user' margin levels, loss of information might soon occur during 'normal' readout. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 660 Freescale Semiconductor, Inc.

The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria that should only be attempted immediately (or very soon) after completion of an erase or program command, early in the cycling life. 'Factory' margin levels can be used to check that flash memory contents have adequate margin for long-term data retention at the normal level setting. If unexpected results are encountered when checking flash memory contents at 'factory' margin levels, the flash memory contents should be erased and reprogrammed. CAUTION Factory margin levels must only be used during verify of the initial factory programming.

28.4.12 FTFL Command Description

This section describes all FTFL commands that can be launched by a command write sequence. The FTFL sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur:

• There is an unrecognized command code in the FCCOB FCMD field.
• There is an error in a FCCOB field for the specific commands. Refer to the error handling table provided for each command. Ensure that the ACCERR and FPVIOL bits in the FSTAT register are cleared prior to starting the command write sequence. As described in Launch the Command by Clearing CCIF, a new command cannot be launched while these error flags are set. Do not attempt to read a flash block while the FTFL is running a command (CCIF = 0) on that same block. The FTFL may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. When required by the command, address bit 23 selects between:
• program flash 0 (=0) block
• (for devices with FlexNVM) data flash (=1) block
• (for devices with program flash only) program flash 1 (=1) block CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 661

28.4.12.1 Read 1s Block Command

The Read 1s Block command checks to see if an entire program flash or data flash block has been erased to the specified margin level. The FCCOB flash address bits determine which logical block is erase-verified. Table 28-34. Read 1s Block Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x00 (RD1BLK)

1 Flash address [23:16] in the flash block to be verified

2 Flash address [15:8] in the flash block to be verified

3 Flash address [7:0]1 in the flash block to be verified

4 Read-1 Margin Choice

1. Must be longword aligned (Flash address [1:0] = 00). After clearing CCIF to launch the Read 1s Block command, the FTFL sets the read margin for 1s according to Table 28-35 and then reads all locations within the selected program flash or data flash block. When the data flash is targeted, DEPART must be set for no EEPROM, else the Read 1s Block command aborts setting the FSTAT[ACCERR] bit. If the FTFL fails to read all 1s (i.e. the flash block is not fully erased), the FSTAT[MGSTAT0] bit is set. The CCIF flag sets after the Read 1s Block operation has completed. Table 28-35. Margin Level Choices for Read 1s Block Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Table 28-36. Read 1s Block Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Program flash is selected and the address is out of program flash range FSTAT[ACCERR] Data flash is selected and the address is out of data flash range FSTAT[ACCERR] Data flash is selected with EEPROM enabled FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 662 Freescale Semiconductor, Inc.

28.4.12.2 Read 1s Section Command

The Read 1s Section command checks if a section of program flash or data flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of phrases to be verified. Table 28-37. Read 1s Section Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x01 (RD1SEC)

1 Flash address [23:16] of the first phrase to be verified

2 Flash address [15:8] of the first phrase to be verified

3 Flash address [7:0]1 of the first phrase to be verified

4 Number of phrases to be verified [15:8]

5 Number of phrases to be verified [7:0]

6 Read-1 Margin Choice

1. Must be phrase aligned (Flash address [2:0] = 000). Upon clearing CCIF to launch the Read 1s Section command, the FTFL sets the read margin for 1s according to Table 28-38 and then reads all locations within the specified section of flash memory. If the FTFL fails to read all 1s (i.e. the flash section is not erased), the FSTAT(MGSTAT0) bit is set. The CCIF flag sets after the Read 1s Section operation completes. Table 28-38. Margin Level Choices for Read 1s Section Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Table 28-39. Read 1s Section Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin code is supplied FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not phrase aligned FSTAT[ACCERR] The requested section crosses a Flash block boundary FSTAT[ACCERR] The requested number of phrases is zero FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 663

28.4.12.3 Program Check Command

The Program Check command tests a previously programmed program flash or data flash longword to see if it reads correctly at the specified margin level. Table 28-40. Program Check Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x02 (PGMCHK)

3 Flash address [7:0]1

4 Margin Choice

8 Byte 0 expected data

9 Byte 1 expected data

1. Must be longword aligned (Flash address [1:0] = 00). Upon clearing CCIF to launch the Program Check command, the FTFL sets the read margin for 1s according to Table 28-41, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the MGSTAT0 bit is set. The FTFL then sets the read margin for 0s, re-reads, and compares again. If the comparison at margin-0 fails, the MGSTAT0 bit is set. The CCIF flag is set after the Program Check operation completes. The supplied address must be longword aligned (the lowest two bits of the byte address must be 00):

• Byte 0 data is expected at the supplied address ('start'),
• Byte 1 data is expected at byte address start + 0b01,
• Byte 2 data is expected at byte address start + 0b10, and
• Byte 3 data is expected at byte address start + 0b11. NOTE See the description of margin reads, Margin Read Commands Table 28-41. Margin Level Choices for Program Check Read Margin Choice Margin Level Description 0x01 Read at 'User' margin-1 and 'User' margin-0 0x02 Read at 'Factory' margin-1 and 'Factory' margin-0 Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 664 Freescale Semiconductor, Inc.

Table 28-42. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] An invalid margin choice is supplied FSTAT[ACCERR] Either of the margin reads does not match the expected data FSTAT[MGSTAT0]

28.4.12.4 Read Resource Command

The Read Resource command allows the user to read data from special-purpose memory resources located within the FTFL module. The special-purpose memory resources available include program flash IFR space, data flash IFR space, and the Version ID field. Each resource is assigned a select code as shown in Table 28-44. Table 28-43. Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x03 (RDRSRC)

4 Read Data [31:24]

5 Read Data [23:16]

6 Read Data [15:8]

7 Read Data [7:0]

8 Resource Select Code (see Table 28-44)

1. Must be longword aligned (Flash address [1:0] = 00). Table 28-44. Read Resource Select Codes Resource Select Code1 Description Resource Size Local Address Range 0x00 IFR 256 Bytes 0x0000 - 0x00FF 0x012 Version ID 8 Bytes 0x0000 - 0x0007 1. Flash address [23] selects between program flash (=0) and data flash (=1) resources. 2. Located in program flash 0 reserved space; Flash address [23] = 0 Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 665

After clearing CCIF to launch the Read Resource command, four consecutive bytes are read from the selected resource at the provided relative address and stored in the FCCOB register. The CCIF flag sets after the Read Resource operation completes. The Read Resource command exits with an access error if an invalid resource code is provided or if the address for the applicable area is out-of-range. Table 28-45. Read Resource Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid resource code is entered FSTAT[ACCERR] Flash address is out-of-range for the targeted resource. FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR]

28.4.12.5 Program Longword Command

The Program Longword command programs four previously-erased bytes in the program flash memory or in the data flash memory using an embedded algorithm. CAUTION A Flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a Flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. Table 28-46. Program Longword Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x06 (PGM4)

4 Byte 0 program value

5 Byte 1 program value

6 Byte 2 program value

7 Byte 3 program value

1. Must be longword aligned (Flash address [1:0] = 00). Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 666 Freescale Semiconductor, Inc.

Upon clearing CCIF to launch the Program Longword command, the FTFL programs the data bytes into the flash using the supplied address. The swap indicator address in each program flash block is implicitly protected from programming. The targeted flash locations must be currently unprotected (see the description of the FPROT and FDPROT registers) to permit execution of the Program Longword operation. The programming operation is unidirectional. It can only move NVM bits from the erased state ('1') to the programmed state ('0'). Erased bits that fail to program to the '0' state are flagged as errors in MGSTAT0. The CCIF flag is set after the Program Longword operation completes. The supplied address must be longword aligned (flash address [1:0] = 00):

• Byte 0 data is written to the supplied address ('start'),
• Byte 1 data is programmed to byte address start+0b01,
• Byte 2 data is programmed to byte address start+0b10, and
• Byte 3 data is programmed to byte address start+0b11. Table 28-47. Program Longword Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Flash address points to a protected area FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0]

28.4.12.6 Erase Flash Block Command

The Erase Flash Block operation erases all addresses in a single program flash or data flash block. Table 28-48. Erase Flash Block Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x08 (ERSBLK)

1 Flash address [23:16] in the flash block to be erased

2 Flash address [15:8] in the flash block to be erased

3 Flash address [7:0]1 in the flash block to be erased

1. Must be longword aligned (Flash address [1:0] = 00). Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 667

Upon clearing CCIF to launch the Erase Flash Block command, the FTFL erases the main array of the selected flash block and verifies that it is erased. When the data flash is targeted, DEPART must be set for no EEPROM (see Table 28-4) else the Erase Flash Block command aborts setting the FSTAT[ACCERR] bit. The Erase Flash Block command aborts and sets the FSTAT[FPVIOL] bit if any region within the block is protected (see the description of the FPROT and FDPROT registers). The swap indicator address in each program flash block is implicitly protected from block erase unless the swap system is in the UPDATE or UPDATE-ERASED state and the program flash block being erased is the non-active block. If the erase verify fails, the MGSTAT0 bit in FSTAT is set. The CCIF flag will set after the Erase Flash Block operation has completed. Table 28-49. Erase Flash Block Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Program flash is selected and the address is out of program flash range FSTAT[ACCERR] Data flash is selected and the address is out of data flash range FSTAT[ACCERR] Data flash is selected with EEPROM enabled FSTAT[ACCERR] Flash address is not longword aligned FSTAT[ACCERR] Any area of the selected flash block is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0]

28.4.12.7 Erase Flash Sector Command

The Erase Flash Sector operation erases all addresses in a Flash sector. Table 28-50. Erase Flash Sector Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x09 (ERSSCR)

1 Flash address [23:16] in the flash sector to be erased

2 Flash address [15:8] in the flash sector to be erased

3 Flash address [7:0]1 in the flash sector to be erased

1. Must be phrase aligned (flash address [2:0] = 000). After clearing CCIF to launch the Erase Flash Sector command, the FTFL erases the selected program flash or data flash sector and then verifies that it is erased. The Erase Flash Sector command aborts if the selected sector is protected (see the description of the FPROT and FDPROT registers). The swap indicator address in each program flash block is implicitly protected from sector erase unless the swap system is in the UPDATE or UPDATE-ERASED state and the program flash sector containing the swap indicator Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 668 Freescale Semiconductor, Inc.

address being erased is the non-active block. If the erase-verify fails the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase Flash Sector operation completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] bit and Figure 28-35). Table 28-51. Erase Flash Sector Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid Flash address is supplied FSTAT[ACCERR] Flash address is not phrase aligned FSTAT[ACCERR] The selected program flash or data flash sector is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0]

28.4.12.7.1 Suspending an Erase Flash Sector Operation

To suspend an Erase Flash Sector operation set the FCNFG[ERSSUSP] bit (see Flash Configuration Field Description) when CCIF is clear and the CCOB command field holds the code for the Erase Flash Sector command. During the Erase Flash Sector operation (see Erase Flash Sector Command), the FTFL samples the state of the ERSSUSP bit at convenient points. If the FTFL detects that the ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the FTFL sets CCIF. While ERSSUSP is set, all writes to FTFL registers are ignored except for writes to the FSTAT and FCNFG registers. If an Erase Flash Sector operation effectively completes before the FTFL detects that a suspend request has been made, the FTFL clears the ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been successfully suspended, the FTFL sets CCIF and leaves the ERSSUSP bit set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of a suspend request before the FTFL has acknowledged it.

28.4.12.7.2 Resuming a Suspended Erase Flash Sector Operation

If the ERSSUSP bit is still set when CCIF is cleared to launch the next command, the previous Erase Flash Sector operation resumes. The FTFL acknowledges the request to resume a suspended operation by clearing the ERSSUSP bit. A new suspend request can then be made by setting ERSSUSP. A single Erase Flash Sector operation can be suspended and resumed multiple times. There is a minimum elapsed time limit between the request to resume the Erase Flash Sector operation (CCIF is cleared) and the request to suspend the operation again (ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash Sector operation will eventually complete. If the minimum period is continually violated, Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 669

i.e. the suspend requests come repeatedly and too quickly, no forward progress is made by the Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely without completing the erase.

28.4.12.7.3 Aborting a Suspended Erase Flash Sector Operation

The user may choose to abort a suspended Erase Flash Sector operation by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch. When a suspended operation is aborted, the FTFL starts the new command using the new FCCOB contents. While FCNFG[ERSSUSP] is set, a write to the FlexRAM while FCNFG[EEERDY] is set clears ERSSUSP and aborts the suspended operation. The FlexRAM write operation is executed by the FTFL. Note Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 670 Freescale Semiconductor, Inc.

Clear SUSPACK = 0 ERSSCR Command (Write FCCOB) Launch/Resume Command (Clear CCIF) CCIF = 1? Request Suspend (Set ERSSUSP) Interrupt? CCIF = 1? Service Interrupt (Read Flash) ERSSUSP=0? Next Command (Write FCCOB) Clear ERSSUSP Enter with CCIF = 1 Resume ERSSCR No Memory Controller Command Processing SUSPACK=1 Clear ERSSUSP Execute Yes DONE? No ERSSUSP=1? Save Erase Algo Set CCIF No Yes Start New Resume Erase? No, Abort User Cmd Interrupt/Suspend Set SUSPACK = 1 ERSSCR Suspended Command Initiation Yes No Yes Yes ERSSCR Completed ERSSCR Suspended ERSSUSP=1 ERSSUSP: Bit in FCNFG register SUSPACK: Internal Suspend Acknowledge No Yes Yes No Yes No ERSSCR Completed ERSSUSP=0 Figure 28-35. Suspend and Resume of Erase Flash Sector Operation Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 671

28.4.12.8 Program Section Command

The Program Section operation programs the data found in the section program buffer to previously erased locations in the flash memory using an embedded algorithm. Data is preloaded into the section program buffer by writing to the FlexRAM while it is set to function as traditional RAM (see Flash Sector Programming). The section program buffer is limited to the lower half of the RAM. Data written to the upper half of the RAM is ignored and may be overwritten during Program Section command execution. CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device. Table 28-52. Program Section Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x0B (PGMSEC)

4 Number of phrases to program [15:8]

5 Number of phrases to program [7:0]

1. Must be phrase aligned (Flash address [2:0] = 000). After clearing CCIF to launch the Program Section command, the FTFL blocks access to the programming acceleration RAM (program flash only devices) or FlexRAM (FlexNVM devices) and programs the data residing in the section program buffer into the flash memory starting at the flash address provided. The starting address must be unprotected (see the description of the FPROT and FDPROT registers) to permit execution of the Program Section operation. The swap indicator address in each program flash block is implicitly protected from erase. If the swap indicator address is encountered during the Program Section operation, it is bypassed without setting FPVIOL and the contents are not programmed. Programming, which is not allowed to cross a flash sector boundary, continues until all requested phrases have been programmed. The Program Section command also verifies that after programming, all bits requested to be programmed are programmed. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 672 Freescale Semiconductor, Inc.

After the Program Section operation completes, the CCIF flag is set and normal access to the FlexRAM is restored. The contents of the section program buffer may be changed by the Program Section operation. Table 28-53. Program Section Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Flash address is not phrase aligned FSTAT[ACCERR] The requested section crosses a program flash sector boundary FSTAT[ACCERR] The requested number of phrases is zero FSTAT[ACCERR] The space required to store data for the requested number of phrases is more than half the size of the programming acceleration RAM (program flash only devices) or FlexRAM (FlexNVM devices) FSTAT[ACCERR] The FlexRAM is not set to function as a traditional RAM, i.e. set if RAMRDY=0 FSTAT[ACCERR] The flash address falls in a protected area FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0]

28.4.12.8.1 Flash Sector Programming

The process of programming an entire flash sector using the Program Section command is as follows: 1. If required, execute the Set FlexRAM Function command to make the FlexRAM available as traditional RAM and initialize the FlexRAM to all ones. 2. Launch the Erase Flash Sector command to erase the flash sector to be programmed. 3. Beginning with the starting address of the programming acceleration RAM (program flash only devices) or FlexRAM (FlexNVM devices), sequentially write enough data to the RAM to fill an entire flash sector. This area of the RAM serves as the section program buffer. NOTE In step 1, the section program buffer was initialized to all ones, the erased state of the flash memory. The section program buffer can be written to while the operation launched in step 2 is executing, i.e. while CCIF = 0. 4. Execute the Program Section command to program the contents of the section program buffer into the selected flash sector. 5. If a flash sector is larger than half the FlexRAM, repeat steps 3 and 4 until the sector is completely programmed. 6. To program additional flash sectors, repeat steps 2 through 4. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 673

1. To restore EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available as EEPROM.

28.4.12.9 Read 1s All Blocks Command

The Read 1s All Blocks command checks if the program flash blocks, data flash blocks, EEPROM backup records, and data flash IFR have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e. all data reads as '1'. Table 28-54. Read 1s All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x40 (RD1ALL)

1 Read-1 Margin Choice

After clearing CCIF to launch the Read 1s All Blocks command, the FTFL :

• sets the read margin for 1s according to Table 28-55,
• checks the contents of the program flash, data flash, EEPROM backup records, and data flash IFR are in the erased state. If the FTFL confirms that these memory resources are erased, security is released by setting the FSEC[SEC] field to the unsecure state. The security byte in the flash configuration field (see Flash Configuration Field Description) remains unaffected by the Read 1s All Blocks command. If the read fails, i.e. all memory resources are not in the fully erased state, the FSTAT[MGSTAT0] bit is set. The EEERDY and RAMRDY bits are clear during the Read 1s All Blocks operation and are restored at the end of the Read 1s All Blocks operation. The CCIF flag sets after the Read 1s All Blocks operation has completed. Table 28-55. Margin Level Choices for Read 1s All Blocks Read Margin Choice Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Table 28-56. Read 1s All Blocks Command Error Handling Error Condition Error Bit An invalid margin choice is specified FSTAT[ACCERR] Table continues on the next page... Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 674 Freescale Semiconductor, Inc.

Table 28-56. Read 1s All Blocks Command Error Handling (continued) Error Condition Error Bit Read-1s fails FSTAT[MGSTAT0]

28.4.12.10 Read Once Command

The Read Once command provides read access to a reserved 64-byte field located in the program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to this field is via 16 records, each 4 bytes long. The Read Once field is programmed using the Program Once command described in Program Once Command. Table 28-57. Read Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x41 (RDONCE)

1 Read Once record index (0x00 - 0x0F)

2 Not used

3 Not used

4 Read Once byte 0 value

5 Read Once byte 1 value

6 Read Once byte 2 value

7 Read Once byte 3 value

After clearing CCIF to launch the Read Once command, a 4-byte Read Once record is read from the program flash IFR and stored in the FCCOB register. The CCIF flag is set after the Read Once operation completes. Valid record index values for the Read Once command range from 0x00 to 0x0F. During execution of the Read Once command, any attempt to read addresses within the program flash block containing this 64-byte field returns invalid data. The Read Once command can be executed any number of times. Table 28-58. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 675

28.4.12.11 Program Once Command

The Program Once command enables programming to a reserved 64-byte field in the program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to the Program Once field is via 16 records, each 4 bytes long. The Program Once field can be read using the Read Once command (see Read Once Command) or using the Read Resource command (see Read Resource Command). Each Program Once record can be programmed only once since the program flash 0 IFR cannot be erased. Table 28-59. Program Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x43 (PGMONCE)

1 Program Once record index (0x00 - 0x0F)

4 Program Once Byte 0 value

5 Program Once Byte 1 value

6 Program Once Byte 2 value

7 Program Once Byte 3 value

After clearing CCIF to launch the Program Once command, the FTFL first verifies that the selected record is erased. If erased, then the selected record is programmed using the values provided. The Program Once command also verifies that the programmed values read back correctly. The CCIF flag is set after the Program Once operation has completed. The reserved program flash 0 IFR location accessed by the Program Once command cannot be erased and any attempt to program one of these records when the existing value is not Fs (erased) is not allowed. Valid record index values for the Program Once command range from 0x00 to 0x0F. During execution of the Program Once command, any attempt to read addresses within program flash 0 returns invalid data. Table 28-60. Program Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] The requested record has already been programmed to a non-FFFF value1 FSTAT[ACCERR] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 1. If a Program Once record is initially programmed to 0xFFFF_FFFF, the Program Once command is allowed to execute again on that same record. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 676 Freescale Semiconductor, Inc.

28.4.12.12 Erase All Blocks Command

The Erase All Blocks operation erases all flash memory, initializes the FlexRAM, verifies all memory contents, and releases MCU security. Table 28-61. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the FTFL erases all program flash memory, program flash 1 IFR space, data flash memory, data flash IFR space, EEPROM backup memory, and FlexRAM, then verifies that all are erased. If the FTFL verifies that all flash memories and the FlexRAM were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state and the FCNFG[RAMRDY] bit is set. The Erase All Blocks command aborts if any flash or FlexRAM region is protected. The swap indicator address in each program flash block is not implicitly protected from the Erase All Blocks operation. The security byte and all other contents of the flash configuration field (see Flash Configuration Field Description) are erased by the Erase All Blocks command. If the erase-verify fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase All Blocks operation completes. Table 28-62. Erase All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Any region of the program flash memory, data flash memory, or FlexRAM is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0]

28.4.12.12.1 Triggering an Erase All External to the FTFL

The functionality of the Erase All Blocks command is also available in an uncommanded fashion outside of the flash memory. Refer to the device's Chip Configuration details for information on this functionality. Before invoking the external erase all function, the FSTAT[ACCERR and PVIOL] flags must be cleared and the FCCOB0 register must not contain 0x44. When invoked, the erase-all function erases all program flash memory, program flash 1 IFR space, data flash memory, data flash IFR space, EEPROM backup, and FlexRAM regardless of the protection settings or if the swap system has been initialized. If the post-erase verify passes, the routine then releases security by setting the FSEC[SEC] field register to the Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 677

unsecure state and the FCNFG[RAMRDY] bit sets. The security byte in the Flash Configuration Field is also programmed to the unsecure state. The status of the erase-all request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is cleared once the operation completes and the normal FSTAT error reporting is available as described in Erase All Blocks Command.

28.4.12.13 Verify Backdoor Access Key Command

The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see FTFL Commands by Mode). Execution of the Verify Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The Verify Backdoor Access Key command releases security if user-supplied keys in the FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash Configuration Field (see Flash Configuration Field Description). The column labelled Flash Configuration Field offset address shows the location of the matching byte in the Flash Configuration Field. Table 28-63. Verify Backdoor Access Key Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] Flash Configuration Field Offset Address 0 0x45 (VFYKEY) 1-3 Not Used

4 Key Byte 0 0x0_0000

5 Key Byte 1 0x0_0001

6 Key Byte 2 0x0_0002

7 Key Byte 3 0x0_0003

8 Key Byte 4 0x0_0004

9 Key Byte 5 0x0_0005

A Key Byte 6 0x0_0006 B Key Byte 7 0x0_0007 After clearing CCIF to launch the Verify Backdoor Access Key command, the FTFL checks the FSEC[KEYEN] bits to verify that this command is enabled. If not enabled, the FTFL sets the FSTAT[ACCERR] bit and terminates. If the command is enabled, the FTFL compares the key provided in FCCOB to the backdoor comparison key in the Flash Configuration Field. If the backdoor keys match, the FSEC[SEC] field is changed to the unsecure state and security is released. If the backdoor keys do not match, security is not released and all future attempts to execute the Verify Backdoor Access Key command are immediately aborted and the FSTAT[ACCERR] bit is (again) set to 1 until a reset of the Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 678 Freescale Semiconductor, Inc.

FTFL module occurs. If the entire 8-byte key is all zeros or all ones, the Verify Backdoor Access Key command fails with an access error. The CCIF flag is set after the Verify Backdoor Access Key operation completes. Table 28-64. Verify Backdoor Access Key Command Error Handling Error Condition Error Bit The supplied key is all-0s or all-Fs FSTAT[ACCERR] An incorrect backdoor key is supplied FSTAT[ACCERR] Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down reset FSTAT[ACCERR]

28.4.12.14 Swap Control Command

The Swap Control command handles specific activities associated with swapping the two logical program flash memory blocks within the memory map. Table 28-65. Swap Control Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x46 (SWAP)

3 Flash address [7:0] 1

Swap Control Code: 0x01 - Initialize Swap System 0x02 - Set Swap in Update State 0x04 - Set Swap in Complete State 0x08 - Report Swap Status Returned values Current Swap State: 0x00 - Uninitialized 0x01 - Ready 0x02 - Update 0x03 - Update-Erased 0x04 - Complete Current Swap Block Status: 0x00 - Program flash block 0 at 0x0_0000 0x01 - Program flash block 1 at 0x0_0000 Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 679

Table 28-65. Swap Control Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] Next Swap Block Status (after any reset): 0x00 - Program flash block 0 at 0x0_0000 0X01 - Program flash block 1 at 0x0_0000 1. Must be phrase-aligned (Flash address [2:0] = 000). Upon clearing CCIF to launch the Swap Control command, the FTFL will handle swap- related activities based on the swap control code provided in FCCOB4 as follows:

• 0x01 (Initialize Swap System to UPDATE-ERASED State) - After verifying that the current swap state is UNINITIALIZED and that the flash address provided is in Program flash block 0 but not in the Flash Configuration Field, the flash address (shifted with bits[2:0] removed) will be programmed into the IFR Swap Field found in program flash 1 IFR. After the swap indicator address has been programmed into the IFR Swap Field, the swap enable word will be programmed to 0x0000. After the swap enable word has been programmed, the swap indicator, located within the Program flash block 0 address provided, will be programmed to 0xFF00.
• 0x02 (Progress Swap to UPDATE State) - After verifying that the current swap state is READY and that the flash address provided matches the one stored in the IFR Swap Field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0xFF00.
• 0x04 (Progress Swap to COMPLETE State) - After verifying that the current swap state is UPDATE-ERASED and that the flash address provided matches the one stored in the IFR Swap Field, the swap indicator located within bits [15:0] of the flash address in the currently active program flash block will be programmed to 0x0000. Before executing with this swap control code, the user must erase the non- active swap indicator using the Erase Flash Block or Erase Flash Sector commands and update the application code or data as needed. The non-active swap indicator will be checked at the erase verify level and if the check fails, the current swap state will be changed to UPDATE with ACCERR set.
• 0x08 (Report Swap System Status) - After verifying that the flash address provided matches the one stored in the IFR Swap Field, the status of the swap system will be reported as follows:
• FCCOB5 (Current Swap State) - indicates the current swap state based on the status of the swap enable word and the swap indicators. If the MGSTAT0 flag is set after command completion, the swap state returned was not successfully transitioned from and the appropriate swap command code must be attempted again. If the current swap state is UPDATE and the non-active swap indicator is 0xFFFF, the current swap state is changed to UPDATE-ERASED. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 680 Freescale Semiconductor, Inc.

• FCCOB6 (Current Swap Block Status) - indicates which program flash block is currently located at relative flash address 0x0_0000.
• FCCOB7 (Next Swap Block Status) - indicates which program flash block will be located at relative flash address 0x0_0000 after the next reset of the FTFL module. NOTE It is recommended that the user execute the Swap Control command to report swap status (code 0x08) after any reset to determine if issues with the swap system were detected during the swap state determination procedure. NOTE It is recommended that the user write 0xFF to FCCOB5, FCCOB6, and FCCOB7 since the Swap Control command will not always return the swap state and status fields when an ACCERR is detected. The swap indicators are implicitly protected from being programmed during Program Longword or Program Section command operations and are implicitly unprotected during Swap Control command operations. The swap indicators are implicitly protected from being erased during Erase Flash Block and Erase Flash Sector command operations unless the swap indicator being erased is in the non-active program flash block and the swap system is in the UPDATE or UPDATE-ERASED state. Once the swap system has been initialized, the Erase All Blocks command can be used to uninitialize the swap system. Table 28-66. Swap Control Command Error Handling Error Condition Swap Control Code Error Bit Command not available in current mode/security1 All FSTAT[ACCERR] Flash address is not in program flash block 0 All FSTAT[ACCERR] Flash address is in the Flash Configuration Field All FSTAT[ACCERR] Flash address is not phrase aligned All FSTAT[ACCERR] Flash address does not match the swap indicator address in the IFR 2, 4 FSTAT[ACCERR] Swap initialize requested when swap system is not in the uninitialized state 1 FSTAT[ACCERR] Swap update requested when swap system is not in the ready state 2 FSTAT[ACCERR] Swap complete requested when swap system is not in the update-erased state 4 FSTAT[ACCERR] An undefined swap control code is provided - FSTAT[ACCERR] Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 681

Table 28-66. Swap Control Command Error Handling (continued) Error Condition Swap Control Code Error Bit Any errors have been encountered during the swap determination and program-verify operations 1, 2, 4 FSTAT[MGSTAT0] Any brownouts were detected during the swap determination procedure 8 FSTAT[MGSTAT0] 1. Returned fields will not be updated, i.e. no swap state or status reporting Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 682 Freescale Semiconductor, Inc.

Block0 Active States Block1 Active States Ready0 Update0 Complete0 Ready1 UpErs1 Complete1 0xFFFF 0x0000 0xFF00 0x0000 0x0000 0xFFFF 0x0000 0xFFFF 0xFFFF 0xFF00 0xFFFF 0x0000 Swap State Indicator0 Indicator1 Legend Swap Control Code UpErs0 0xFF00 0xFFFF Update1 0x0000 0xFF00 Erase: ERSBLK or ERSSCR commands Reset: POR, VLLSx exit, warm/system reset Uninitialized0 0xFFFF 0xFFFF Figure 28-36. Valid Swap State Sequencing Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 683

Table 28-67. Swap State Report Mapping Case Swap Enable Field1 Swap Indicator Swap Indicator Swap State2 State Code MGST AT0 Active Block 1 0xFFFF - - Uninitialized 0 0 0 2 0x0000 0xFF00 0x0000 Update 2 0 0 3 0x0000 0xFF00- 0xFFFF Update-Erased 3 0 0 4 0x0000 0x0000 0xFFFF3 Complete4 4 0 0 5 0x0000 0x0000 0xFFFF Ready5 1 0 1 6 0x0000 0x0000 0xFF00 Update 2 0 1 7 0x0000 0xFFFF 0xFF00 Update-Erased 3 0 1 8 0x0000 0xFFFF3 0x0000 Complete4 4 0 1 9 0x0000 0xFFFF 0x0000 Ready5 1 0 0 10 0xXXXX - - Uninitialized 0 1 0 11 0x0000 0xFFFF 0xFFFF Uninitialized 0 1 0 12 0x0000 0xFFXX 0xFFFF Ready 1 1 0 13 0x0000 0xFFXX 0x0000 Ready 1 1 0 146 0x0000 0xXXXX 0x0000 Ready 1 1 0 156 0x0000 0xFFFF 0xFFXX Ready 1 1 1 16 0x0000 0x0000 0xFFXX Ready 1 1 1 176 0x0000 0x0000 0xXXXX Ready 1 1 1 18 0x0000 0xFF00 0xFFFF7 Update 2 1 0 19 0x0000 0xFF00 0xXXXX Update 2 1 0 20 0x0000 0xFF(00) 0xFFXX Update 2 1 0 216 0x0000 0x0000 0x0000 Update 2 1 0 226 0x0000 0xXXXX 0xXXXX Update 2 1 0 23 0x0000 0xFFFF7 0xFF00 Update 2 1 1 24 0x0000 0xXXXX 0xFF00 Update 2 1 1 25 0x0000 0xFFXX 0xFF(00) Update 2 1 1 26 0x0000 0xXX00 0xFFFF Update-Erased 3 1 0 27 0x0000 0xXXXX 0xFFFF Update-Erased 3 1 0 28 0x0000 0xFFFF 0xXX00 Update-Erased 3 1 1 29 0x0000 0xFFFF 0xXXXX Update-Erased 3 1 1 1. 0xXXXX, 0xFFXX, 0xXX00 indicates a non-valid value was read; 0xFF(00) indicates more 0’s than other indicator (if same number of 0’s, then swap system defaults to block 0 active) 2. Cases 10-29 due to brownout (abort) detected during program or erase steps related to swap 3. Must read 0xFFFF with erase verify level before transition to Complete allowed 4. No reset since successful Swap Complete execution 5. Reset after successful Swap Complete execution 6. Not a valid case 7. Fails to read 0xFFFF at erase verify level Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 684 Freescale Semiconductor, Inc.

28.4.12.14.1 Swap State Determination

During the reset sequence, the state of the swap system is determined by evaluating the IFR Swap Field in the program flash 1 IFR and the swap indicators located in each of the program flash blocks at the swap indicator address stored in the IFR Swap Field. Table 28-68. Program Flash 1 IFR Swap Field Address Range Size (Bytes) Field Description 0x00 – 0x01 2 Swap Enable Word 0x02 – 0x03 2 Swap Indicator Address 0x04 – 0xFF 252 Reserved

28.4.12.15 Program Partition Command

The Program Partition command prepares the FlexNVM block for use as data flash, EEPROM backup, or a combination of both and initializes the FlexRAM. The Program Partition command must not be launched from flash memory, since flash memory resources are not accessible during Program Partition command execution. CAUTION While different partitions of the FlexNVM are available, the intention is that a single partition choice is used throughout the entire lifetime of a given application. The FlexNVM Partition Code choices affect the endurance and data retention characteristics of the device. Table 28-69. Program Partition Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x80 (PGMPART)

1 Not Used

4 EEPROM Data Size Code1

5 FlexNVM Partition Code2

1. See Table 28-70 and EEPROM Data Set Size 2. See Table 28-71 and Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 685

Table 28-70. Valid EEPROM Data Set Size Codes EEPROM Data Size Code (FCCOB4)1 EEPROM Data Set Size (Bytes) Subsystem A + BFCCOB4[EEESPLIT] FCCOB4[EEESIZE] 11 0xF 02 00 0x9 4 + 28 01 0x9 8 + 24 10 0x9 16 + 16 11 0x9 16 + 16 00 0x8 8 + 56 01 0x8 16 + 48 10 0x8 32 + 32 11 0x8 32 + 32 00 0x7 16 + 112 01 0x7 32 + 96 10 0x7 64 + 64 11 0x7 64 + 64 00 0x6 32 + 224 01 0x6 64 + 192 10 0x6 128 + 128 11 0x6 128 + 128 00 0x5 64 + 448 01 0x5 128 + 384 10 0x5 256 + 256 11 0x5 256 + 256 00 0x4 128 + 896 01 0x4 256 + 768 10 0x4 512 + 512 11 0x4 512 + 512 00 0x3 256 + 1,792 01 0x3 512 + 1,536 10 0x3 1,024 + 1,024 11 0x3 1,024 + 1,024 00 0x2 512 + 3,584 01 0x2 1,024 + 3,072 10 0x2 2,048 + 2,048 11 0x2 2,048 + 2,048 1. FCCOB4[7:6] = 00 2. EEPROM Data Set Size must be set to 0 bytes when the FlexNVM Partition Code is set for no EEPROM. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 686 Freescale Semiconductor, Inc.

Table 28-71. Valid FlexNVM Partition Codes FlexNVM Partition Code (FCCOB5[DEPART])1 Data flash Size (Kbytes) EEPROM backup Size (Kbytes) 0000 256 0 0011 224 32 0100 192 64 0101 128 128 0110 0 256 1000 0 256 1011 32 224 1100 64 192 1101 128 128 1110 256 0 1. FCCOB5[7:4] = 0000 After clearing CCIF to launch the Program Partition command, the FTFL first verifies that the EEPROM Data Size Code and FlexNVM Partition Code in the data flash IFR are erased. If erased, the Program Partition command erases the contents of the FlexNVM memory. If the FlexNVM is to be partitioned for EEPROM backup, the allocated EEPROM backup sectors are formatted for EEPROM use. Finally, the partition codes are programmed into the data flash IFR using the values provided. The Program Partition command also verifies that the partition codes read back correctly after programming. If the FlexNVM is partitioned for EEPROM, the allocated EEPROM backup sectors are formatted for EEPROM use. The CCIF flag is set after the Program Partition operation completes. Prior to launching the Program Partition command, the data flash IFR must be in an erased state, which can be accomplished by executing the Erase All Blocks command or by an external request (see Erase All Blocks Command). The EEPROM Data Size Code and FlexNVM Partition Code are read using the Read Resource command (see Read Resource Command). Table 28-72. Program Partition Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] The EEPROM data size and FlexNVM partition code bytes are not initially 0xFFFF FSTAT[ACCERR] Invalid EEPROM Data Size Code is entered (see Table 28-70 for valid codes) FSTAT[ACCERR] Invalid FlexNVM Partition Code is entered (see Table 28-71 for valid codes) FSTAT[ACCERR] FlexNVM Partition Code = full data flash (no EEPROM) and EEPROM Data Size Code allocates FlexRAM for EEPROM FSTAT[ACCERR] Table continues on the next page... Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 687

Table 28-72. Program Partition Command Error Handling (continued) Error Condition Error Bit FlexNVM Partition Code allocates space for EEPROM backup, but EEPROM Data Size Code allocates no FlexRAM for EEPROM FSTAT[ACCERR] FCCOB4[7:6] != 00 FSTAT[ACCERR] FCCOB5[7:4] != 0000 FSTAT[ACCERR] Any errors have been encountered during the verify operation FSTAT[MGSTAT0]

28.4.12.16 Set FlexRAM Function Command

The Set FlexRAM Function command changes the function of the FlexRAM:

• When not partitioned for EEPROM, the FlexRAM is typically used as traditional RAM.
• When partitioned for EEPROM, the FlexRAM is typically used to store EEPROM data. Table 28-73. Set FlexRAM Function Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0 0x81 (SETRAM) FlexRAM Function Control Code (see Table 28-74) Table 28-74. FlexRAM Function Control FlexRAM Function Control Code Action 0xFF Make FlexRAM available as RAM:
• Clear the FCNFG[EEERDY] and FCNFG[RAMRDY] flags
• Write a background of ones to all FlexRAM locations
• Set the FCNFG[RAMRDY] flag 0x00 Make FlexRAM available for EEPROM:
• Clear the FCNFG[EEERDY] and FCNFG[RAMRDY] flags
• Write a background of ones to all FlexRAM locations
• Copy-down existing EEPROM data to FlexRAM
• Set the FCNFG[EEERDY] flag After clearing CCIF to launch the Set FlexRAM Function command, the FTFL sets the function of the FlexRAM based on the FlexRAM Function Control Code. When making the FlexRAM available as traditional RAM, the FTFL clears the FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of the entire FlexRAM with a background pattern of all ones, and sets the FCNFG[RAMRDY] flag. The state of the FEPROT register does not prevent the FlexRAM from being overwritten. Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 688 Freescale Semiconductor, Inc.

When the FlexRAM is set to function as a RAM, normal read and write accesses to the FlexRAM are available. When large sections of flash memory need to be programmed, e.g. during factory programming, the FlexRAM can be used as the Section Program Buffer for the Program Section command (see Program Section Command). When making the FlexRAM available for EEPROM, the FTFL clears the FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of the FlexRAM allocated for EEPROM with a background pattern of all ones, and copies the existing EEPROM data from the EEPROM backup record space to the FlexRAM. After completion of the EEPROM copy-down, the FCNFG[EEERDY] flag is set. When the FlexRAM is set to function as EEPROM, normal read and write access to the FlexRAM is available, but writes to the FlexRAM also invoke EEPROM activity. Table 28-75. Set FlexRAM Function Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] FlexRAM Function Control Code is not defined FSTAT[ACCERR] FlexRAM Function Control Code is set to make the FlexRAM available for EEPROM, but FlexNVM is not partitioned for EEPROM FSTAT[ACCERR]

28.4.13 Security

The FTFL module provides security information to the MCU based on contents of the FSEC security register. The MCU then limits access to FTFL resources as defined in the device's Chip Configuration details. During reset, the FTFL module initializes the FSEC register using data read from the security byte of the Flash Configuration Field (see Flash Configuration Field Description). The following fields are available in the FSEC register. The settings are described in the Flash Security Register (FTFL_FSEC) details. Table 28-76. FSEC register fields FSEC field Description KEYEN Backdoor Key Access MEEN Mass Erase Capability FSLACC Freescale Factory Access SEC MCU security Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 689

28.4.13.1 FTFL Access by Mode and Security

The following table summarizes how access to the FTFL module is affected by security and operating mode. Table 28-77. FTFL Access Summary Operating Mode Chip Security State Unsecure Secure NVM Normal Full command set NVM Special Full command set Only the Erase All Blocks and Read 1s All Blocks commands.

28.4.13.2 Changing the Security State

The security state out of reset can be permanently changed by programming the security byte of the flash configuration field. This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected. If the flash security byte is successfully programmed, its new value takes affect after the next chip reset.

28.4.13.2.1 Unsecuring the Chip Using Backdoor Key Access

The chip can be unsecured by using the backdoor key access feature, which requires knowledge of the contents of the 8-byte backdoor key value stored in the Flash Configuration Field (see Flash Configuration Field Description). If the FSEC[KEYEN] bits are in the enabled state, the Verify Backdoor Access Key command (see Verify Backdoor Access Key Command) can be run; it allows the user to present prospective keys for comparison to the stored keys. If the keys match, the FSEC[SEC] bits are changed to unsecure the chip. The entire 8-byte key cannot be all 0s or all 1s; that is, 0000_0000_0000_0000h and FFFF_FFFF_FFFF_FFFFh are not accepted by the Verify Backdoor Access Key command as valid comparison values. While the Verify Backdoor Access Key command is active, program flash memory is not available for read access and returns invalid data. The user code stored in the program flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN bits are in the enabled state, the chip can be unsecured by the following backdoor key access sequence: Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 690 Freescale Semiconductor, Inc.

1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Verify Backdoor Access Key Command 2. If the Verify Backdoor Access Key command is successful, the chip is unsecured and the FSEC[SEC] bits are forced to the unsecure state An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command. A reset of the chip is the only method to re-enable the Verify Backdoor Access Key command when a comparison fails. After the backdoor keys have been correctly matched, the chip is unsecured by changing the FSEC[SEC] bits. A successful execution of the Verify Backdoor Access Key command changes the security in the FSEC register only. It does not alter the security byte or the keys stored in the Flash Configuration Field (Flash Configuration Field Description). After the next reset of the chip, the security state of the FTFL module reverts back to the flash security byte in the Flash Configuration Field. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the program flash protection registers. If the backdoor keys successfully match, the unsecured chip has full control of the contents of the Flash Configuration Field. The chip may erase the sector containing the Flash Configuration Field and reprogram the flash security byte to the unsecure state and change the backdoor keys to any desired value.

28.4.14 Reset Sequence

On each system reset the FTFL module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FDPROT, FEPROT, FOPT, and FSEC registers and the FCNFG[SWAP, PFLSH, RAMRDY, EEERDY] bits. CCIF is cleared throughout the reset sequence. The FTFL module holds off all CPU access for a portion of the reset sequence. Flash reads are possible when the hold is removed. Completion of the reset sequence is marked by setting CCIF which enables flash user commands. If a reset occurs while any FTFL command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. Chapter 28 Flash Memory Module (FTFL) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 691

Flash Operation in Low-Power Modes K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 692 Freescale Semiconductor, Inc.

External Bus Interface (FlexBus)

29.1 Introduction

For the chip-specific implementation details of this module's instances see the chip configuration chapter. This chapter describes external bus data transfer operations and error conditions. It describes transfers initiated by the core processor (or any other bus master) and includes detailed timing diagrams showing the interaction of signals in supported bus operations.

29.1.1 Overview

A multi-function external bus interface called the FlexBus interface controller is provided on the device with basic functionality of interfacing to slave-only devices. It can be directly connected to the following asynchronous or synchronous devices with little or no additional circuitry:

• External ROMs
• Flash memories
• Programmable logic devices
• Other simple target (slave) devices For asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has up to six general purpose chip-selects, FB_CS[5:0]. The actual number of chip selects available depends upon the device and its pin configuration. K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 693

29.1.2 Features

Key FlexBus features include:

• Six independent, user-programmable chip-select signals ( FB_CS[5:0]) that can interface with external SRAM, PROM, EPROM, EEPROM, flash, and other peripherals
• 8-, 16-, and 32-bit port sizes with configuration for multiplexed or non-multiplexed address and data buses
• 8-bit, 16-bit, 32-bit, and 16-byte transfers
• Programmable burst- and burst-inhibited transfers selectable for each chip select and transfer direction
• Programmable address-setup time with respect to the assertion of chip select
• Programmable address-hold time with respect to the negation of chip select and transfer direction
• Extended address latch enable option helps with glueless connections to synchronous and asynchronous memory devices

29.1.3 Modes of Operation

The external interface is a configurable multiplexed bus set to one of the following modes:

• Multiplexed 32-bit address and 32-bit data
• Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16- bit data)
• Multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit data)
• Non-multiplexed 32-bit address and 32-bit data busses

29.2 Signal Descriptions

This section describes the external signals involved in data-transfer operations. NOTE Not all of the following signals may be available on a particular device. See the Chip Configuration details for information on which signals are available. Signal Descriptions K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 694 Freescale Semiconductor, Inc.

Table 29-1. FlexBus Signal Summary Signal Description I/O FB_A[31:0] In a non-multiplexed configuration, this is the address bus. O FB_D[31:0]/ FB_AD[31:0] In a non-multiplexed configuration, this is the data bus. In a multiplexed configuration this bus is the address/data bus, FB_AD[31:0]. In non- multiplexed and multiplexed configurations, during the first cycle, this bus drives the upper address byte, addr[31:24]. I/O FB_CS[5:0] General purpose chip-selects. The actual number of chip selects available depends upon the device and its pin configuration. O FB_BE_31_24 FB_BE_23_16 FB_BE_15_8 FB_BE_7_0 Byte enables O FB_OE Output enable O FB_R/W Read/write. 1 = Read, 0 = Write O FB_TS Transfer start O FB_ALE Address latch enable (an inverse of FB_TS) O FB_TSIZ[1:0] Transfer size O FB_TBST Burst transfer indicator O FB_TA Transfer acknowledge I FB_CLK FlexBus clock output O

29.2.1 Address and Data Buses (FB_An, FB_Dn, FB_ADn)

In non-multiplexed mode, the FB_A[31:0] and FB_D[31:0] buses carry the address and data, respectively. The number of byte lanes carrying the data is determined by the port size associated with the matching chip select. In multiplexed mode, the FB_AD[31:0] bus carries the address and data. The full 32-bit address is driven on the first clock of a bus cycle (address phase). Following the first clock, the data is driven on the bus (data phase). During the data phase, the address continues driving on the pins not used for data. For example, in 16-bit mode the lower address continues driving on FB_AD[15:0] and in 8-bit mode the lower address continues driving on FB_AD[23:0]. Chapter 29 External Bus Interface (FlexBus) K60 Sub-Family Reference Manual, Rev. 6, Nov 2011 Freescale Semiconductor, Inc. 695

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