MK5027DIP

MK5027 STMICROELECTRONICS | Alldatasheet

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FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE COMPLETE LEVEL 2 IMPLEMENTATION COMPATIBLE WITH 1988 CCITT, AT&T, ANSI, AND BELLCORE SIGNALLING SYS- TEM NUMBER 7 LINK LEVEL PROTOCOLS

52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN

COMPATIBLE WITH THE SGS-THOMSON X.25 CHIP (MK5025) AND NEARLY PIN-FOR- PIN COMPATIBLE WITH THE SGS-THOM- SON VLANCE CHIP (MK5032) BUFFER MANAGEMENT INCLUDES: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes. ON CHIP DMA CONTROL WITH PROGRAM- MABLE BURST LENGTH SELECTABLE BEC OR PCR RETRANSMIS- SION METHODS, INCLUDING FORCED RE- TRANSMISSION FOR PCR HANDLES ALL 7 SS7 TIMERS HANDLES ALL SS7 FRAME FORMATTING: - Zero bit insert and delete - FCS generation and detection - Frame delimiting with flags PROGRAMMABLE MINIMUM SIGNAL UNIT SPACING (number of flags between SU’s) HANDLES ALL SEQUENCING AND LINK CONTROL SELECTABLE FCS OF 16 OR 32 BITS. TESTING FACILITIES: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test ALL INPUTS AND OUTPUTS ARE TTL COM- PATIBLE PROGRAMMABLE FOR FULL OR HALF DU- PLEX OPERATION

DESCRIPTION

The SGS-THOMSON Signalling System #7 Sig- nalling Link Controller (MK5027) is a VLSI semi- conductor device which provides a complete link control function conforming to the 1988 CCITT version of SS7. This includes frame formatting, transparency (so called ”bit-stufling”), error recov- ery by two types of retransmission, error monitor- ing, sequence number control, link status con- trol, and FISU generation. One of the outstanding features of the MK5027 is its buffer management which includes on-chip DMA. This feature allows users to handlq multiple packets of receive and transmit data at a time. (A conventional data link- control chip plus a separate DMA chip would han- dle data for only a single block at a time.) The MK5027 may be used with any of several popular 16 and 8 bit microprocessors, such as 68000, 6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc. DIP48 PLCC52 VSS-GND DAL07 DAL06 DAL05 DAL04 DAL03 DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO, BYTE, BUSREL BMI, BUSAKO HOLD, BUSRQ ALE, AS CS ADR READY RESET VSS-GND 24 HLDA

25 TCLK

DSR, CTS TD SYSCLK RCLK DTR, RTS VCC (+5V) DAL08 DAL09 DAL10 DAL11 DAL12 DAL13 DAL14 DAL15 A16 A17 M K H Figure 1:Pin Connection.

Table 1:Pin Description. LEGEND: I Input only O Output only IO Input/Output 3S 3-State OD Open Drain (no internal pull-up) Signal Name Pin(s) Type Descriplion DAL<15:00> 2-9 40-47 IO/3S The time multiplexed Data Address bus. During the address portion of a memory transfer, DALe15:00 contains the lower 16 bits of the memory address. During the data portion of a memory transfer, DAL<15:00> contains the read or write data, depending on the type of transfer. READ 10 IO/3S READ indicates the type of operation that the bus controller is performing during a bus transaction. READ is driven by the MK5027 only while it is the BUS MASTER. READ is valid during the entire bus transaction and is tristated at all other times. MK5027 as a Bus Slave: READ = HIGH - Data is placed on the DAL lines by the chip. READ = LOW - Data is taken off the DAL lines by the chip. MK5027 as a Bus Master: READ = HIGH - Data is taken off the DAL lines by the chip. READ = LOW - Data is placed on the DAL lines by the chip. INTR 11 O/OD INTERRUPT is an attention interrupt line that indicates that one or more of the following CSR0 status flags is set: MISS, MERR, RINT, TINT or PINT. INTERRUPT is enabled by CSR0<0.9>, INEA = 1. DALI 12 O/3S DAL IN is an external bus transceiver control line. DALI is driven by the MK5027 only while it is the BUS MASTER. DALI is asserted by the MK5027 when | ads from the DAL lines during the data portion of a READ transfer. DALI is not asserted during a WRITE transfer. DALO 13 O/3S DAL OUT is an external bus transceiver control line. DALO is driven by the MK5027 only while it is the BUS MASTER. DALO is asserted by the MK5027 when it drives the DAL lines during the address portion of a READ transfer or for the duration of a WRITE transfer. DAS 14 IO/3S DATA STROBE defines the data portio,n of a transaction. By definition, data is stable and valid at the low to high transition of DAS. This signal is driven by the MK5027 while it is the BUS MASTER. During the BUS SLAVE operation, this pin is used as an input. At all other times the signal is tristated. BMO BYTE BUSREL 15 IO/3S I/O pins 15 and 16 are programmable through CSR4. If bit 06 of CSR4 is set to a one, pin 15 becomes input BUSREL and is used by the host to signal the MK5027 to terminate a DMA burst after the current bus transfer has completed. If bit 06 is clear the pin 15 is an output and behaves as described below for pin 16. Note:Pin out shown is for 48 pin dip. MK5027

Table 1:Pin Description (continued) Signal Name Pin(s) Type Descriplion BM1 BUSAKO 16 O/3S Pins 15 and 16 are programmable though bit 00 of CSR4 (BCON). If CSR4<00> BCON = 0, I/O PIN 15 = BMO (O/3S) I/O PIN 16 = BM1 (O/3S) BYTE MASK<1:0> indicates the byte(s) on the DAL to be read or written during this bus transaction. MK5027 drives these lines only as a Bus Master. MK5027 ignores the BM lines when it is a Bus Slave. Byte selection is done as outlined in the following table. BM1 BM0 TYPE OF TRANSFER LOW LOW ENTIRE WORD LOW HIGH UPPER BYTE (DAL<15:08>) HIGH LOW LOWER BYTE (DAL<07:00>) HIGH HIGH NONE If CSR4<00>BCON = 1, I/O PIN 15 = BYTE (O/3S) I/O PIN 16 = BUSAKO(O) Byte selection is done using the BYTE line and DAL<00> latched during the address portion of the bus transaction. MK5027 drives BYTE only a Bus Master and ignores it when a Bus Slave. Byte selection is done as outlined in the following table. BYTE DAL<00> TYPE OF TRANSFER LOW LOW ENTIRE WORD LOW HIGH ILLEGAL CONDITION HIGH LOW LOWER BYTE HIGH HIGH UPPER BYTE BUSAKOis a bus request daisy chain output. If MK5027 is not requesting the bus and it receives HLDA, BUSAKOwill be driven low. If MK5027 is requesting the bus when it receives HLDA, BUSAKOwill remain high. Note: All transfers are entire word unless the MK5027 is configured for 8 bit operation. HOLD BUSRQ 17 IO/OD Pins 17 is configured through bit 0 of CSR4. If CSR4<00> BCON = 0, I/O PIN 17 = HOLD HOLD request is asserted by MK5027 when it requires a DMA cycle, if HLDA is inactive, regardless of the previous state of the HOLD pin. HOLD is held low for the entire ensuing bus transaction. If CSR4<00> BCON = 1, I/O PIN 17 = BUSRQ BUSRQ is asserted by MK5027 when it requires a DMA cycle if the prior state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held low for the entire ensuing bus transaction. ALE AS 18 O/3S The active level of ADDRESS STROBE is programmable through CSR4. The address portion of a bus transfer occurs while this signal is at its asserted level. This signal is driven by MK5027 while it is the BUS MASTER. At all other times, the signal is tristated. If CSR4<01> ACON = 0, I/O PIN 18 = ALE ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define the address portion of the transfer and remains low during the data portion. If CSR4<01> ACON = 1, I/O PIN 18 = AS As AS, the signal pulses low during the address portion of the bus transfer. The low to high transition of AScan be used by a slave device to strobe the address into a register. AS is effectively the inversion of ALE. HLDA 19 I HOLD AKNOWLEDGE is the response to HOLD. When HLDA is low in response to MK5027’s assertion of HOLD, the MK5027 is the Bus Master. HLDA should be desasserted ONLY after HOLD has been released by the MK5027. MK5027

Table 1:Pin Description (continued) Signal Name Pin(s) Type Descriplion CS 20 I CHIP SELECT indicates, when low, that the MK5027 is the slave device for the data transfer.CS must be valid througout the enture transaction. ADR 21 I ADDRESS selects the Register Address Port or the Register Data Port. It must be valid throughout the data portion of the transfer and is only used by the chip when CS is low. ADR PORT LOW REGISTER DATA PORT HIGH REGISTER ADDRESS PORT READY 22 IO/OD When the MK5027 is a Bus Master, READY is an asynchronous acknowledgement from the bus memory that memory will accept data in a WRITE cycle or that memory has put data on the DAL lines in a READ cycle. As a bus Slave, the MK5027 asserts READY when it has put data on the DAL lines during a READ cycle or is about to take data from the DAL lines during WRITE cycle. READY is a response to DAS and it will be released after DAS or CS is negated. RESET 23 I RESET is the Bus signal that will cause MK5027 to cease operation, clear its internal logic and enter an idle state with the Power Off bit of CSR0 set. TCLK 25 I TRANSMIT CLOCK. A 1x clock input for transmitter timing. TD changes on the falling edge of TCLK. The frequency of TCLK may not be greater than the frequency of SYSCLK. DTR RTS 26 IO DATA TERMINAL READY, REQUEST TO SEND. Modem control pin. Pin 26 is configurable through CSR5. This pin can be programmed to behave as output RTS or as programmable IO pin DTR. If configured as RTS, the MK5027 will assert this pin if it has data to send and throughout the transmission of a signal unit. RCLK 27 I RECEIVE CLOCK. A 1x clock input for receiver timing. RD is sampled on the rising edge of RCLK. The frequency of RCLK may not be greater than the frequency of SYSCLK. SYSCLK 28 I SYSTEM CLOCK. System clock used for internal timing of the MK5027. SYSCLK should be a square wave, of frequency up to 10MHz. TD 29 O TRANSMIT DATA. Transmit serial data output. DSR CTS 30 IO DATA SET READY, CLEAR TO SEND. Modem Control Pin. Pin 30 is configurable through CSR5. This pin can be programmed to behave as input CTS or as programmable IO pin DSR. If configured as CTS, the MK5027 will transmit all ones while CTS is high. RD 31 I RECEIVE DATA. Received serial data input. A<23:16> 32-39 O/3S Address bits <23:16> used in conjunction with DAL <15:00> to produce a 24 bit address. MK5027 drives these lines only as a Bus Master. A23-A20 may be driven continuously as described in the CSR4<7> BAEN bit. VSS-GND 1, 24 Ground Pins VCC 48 Power Supply Pin +5.0 VDC ± 5% MK5027

Figure 2:Possible System Configuration for the MK5027. MK5027

The SGS-THOMSON Signalling System #7 Sig- nalling Link Controller (MK5027) device is a VLSI product intended for data communication applica- tions requiring SS7 link level control. The MK5027 will perform all frame formatting, such as: frame delimiting with flags, FCS generation and detec- tion. It will also perform all error recovery and link control. The MK5027 also includes a buffer man- agement mechanism that allow the user to trans- mit and/or receive multiple MSU’s. Contained in the buffer management is an on-chip dual chan- nel DMA: one channel for receive and one chan- nel for transmit. The MK5027 handles error recov- ery and link status signalling. The MK5027 is intended to be used with any popular 16 or 8 bit microprocessor. Possible sys- tem configuration for the MK5027 is shown in Fig- ure 2. The MK5027 will move multiple blocks of receive and transmit data directly into and out of memory through the host’s bus. An I/O accelera- tion processor in Figure 2 is recommended, but not required. DALI DALO HLDA HOLD ALE, AS BM0 BM1 DAS READ INTR ADRREADY DTR, RTS DSR, CTS CS FIRMWARE ROM MICRO CONTROLLER TIMERSDMA CONTROLLER CONTROL / STATUS REGISTERS 0 - 5 SYSCLK INTERNAL BUS RECEIVER FIFO TRANSMITTER FIFO RECEIVER TRANSMITTER LOOPBACK TEST RD RCLK TCLK TD VSS - GND RESET VCC DAL <15:00> A <23:16> Figure 3:MK5027 Simplified Block Diagram. MK5027

All signal pins on the MK5027 are TTL compat- ible. This has the advantage of making the MK5027 in- dependent of the physical interface. As shown in Figure 2. Iine drivers and receivers are used for electrical- connection to the physical layer. SERIAL INTERFACE The MK5027 provides two separate serial chan- nels: one for received data and one for transmit- ted data. These serial channels are completely separate and may be run at different clock fre- quencies The receiver is responsible for recogniz- ing frame boundries. removal of inserted zeroes (for transparency) and checking the incoming FCS. Signal units with in correct FCS values are discarded. The receiver also parallelizes the in- coming data which is placed into the receive data buffers within the receive descriptor ring The transmitter is responsible for framing and serializ- ing the data frames placed in the transmit de- scriptor ring. The transmitter calculates the FCS of the outgoing data and appends it to the data The transmitter generates flag sequences for in- ter-signal unit fill, at least two flags are transmit- ted between adjacent signal units. The FCS cal- culations for both directions of serial data optionally follow either the 16 bit CRC CCITT or the 32-bit CRC 32 algorithms FCS generation and checking can also be optionally disabled if neces- sary. MICROPROCESSOR INTERFACE The MK5027 contains a dual channel DMA on chip to handle data transfers to and from the host mem- ory. All access to the initialization block and descriptor rings is handled in this way The ad- dress bus is 24 bits wide and does not use any segmentation or paging methods. Data transfers can optionally be 8 and 16 bit operations. this al- lows easy interfacing with both 8 and 16 bit proc- essors DMA transfers can be up to 1. 8 or an un- limited number of words per transfer under program control During bus slave operation the MK5027 allows access to its 6 control/status reg- isters which are used to monitor and control the chip. These registers are used to control link pro- cedures, configure interface options, control and monitor interrupt status. and more. Bus slave mode also allows both 8 and 16 bit accesses. BUFFER MANAGEMENT The basic organization of the buffer management is a circular queue of tasks in memory called de- scriptor rings. There are separate rings to de- scribe the transmit and receive operations. Up to 128 buffers may be queued-up on a descriptor ring awaiting execution by the MK5027 The de- scriptor ring has a segment assigned to each buffer. Each segment holds a pointer for the start- ing address of the buffer. and holds a value for the length of the buffer in bytes. Each segment also contains two control bits called OWNA and OWNB, which denote whether the MK5027. the HOST. or the l/O ACCELERA- TION PROCESSOR (if present) ”owns” the buff- er. For transmit. when the MK5027 owns the buff- er. the MK5027 is allowed and commanded to transmit the buffer When the MK5027 does not own the buffer, it will not transmit that buffer. For receive. when the MK5027 owns a buffer. it may place received data into that buffer. Conversely. when the MK5027 does not own a receive buff- er, it will not place received data in that buffer. The MK5027 buffer management mechanism will handly signal units which are longer than the length of an individual buffer. This is done by a chaining method which utilizes multiple buffers. The MK5027 tests the next segment in the de- scriptor ring in a ”look ahead” manner. If the packet is too long for one buffer, the next buffer- will be used after filling the first buffer: that is, ”chained”. The MK5027 will then ”look ahead” to the next buffer, and chain that buffer if necessary, and so on The operational parameters for the buffer management are defined by the user in the initialization block The parameters defined include the basic mode of operation. the number of entries for the transmitter and receiver descrip- tor rings. etc. MK5027

N BUFFER BUFFER TRANSMIT BUFFER BUFFER M BUFFER BUFFER RECEIVE BUFFER CSR 2, CSR3 POINTER TO INITIALIZATI ON BLOCK INITIALIZATI ON BLOCK MODE TIMER VALUES RX DESCRIPTOR TX DESCRIPTOR POINTER POINTER FRAME ADDRESS FIELDS STATUS BUFFER ADDRESS STATUS BUFFER ERROR COUNTERS XID/TEST TRANSMIT DESCRIPTOR POINTER XID/TEST RECEIVE DESCRIPTOR POINTER RECEIVE BUFFER TRANSMIT BUFFER XID/TEST XID/TEST Figure 4:MK5027 Buffer Management. MK5027

SIGNALLING UNIT REPERTOIRE The signal unit repertoire of the MK5027 is shown in Table 1. This set conforms to the 1988 CCITT specification for level 2 of Signalling System #7. The definitions for the symbols for the frame types are: Name Definition F FSN BSN FIB BIB LI X SIO SIF SF FCS Flag Sequence Forward Sequence Number Backward Sequences Number Forward Indicator Bit Backward Indicator Bit Lenght Indicator Programmed As Zeroes Signalling Information Octet Service Information Field Satus Field Frame Check Sequence Table 1:MK5027 Signal Unit Repertoire. MK5027

MK5027 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Temperature under Bias –25 °C to +100°C Storage Temperature –65°C to +150°C Voltage on Any Pin with Respect to Ground –0.5V to VCC +0.5V Power Dissipation 0.50W Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the above device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability. DC CHARACTERISTICS TA=0 °Ct o7 0°C, VCC = +5V±5 percent unless otherwise specified. Symbol Parameter Min. Typ. Max. Units VIL -0.5 +0.8 V VIH +2.0 V CC +0.5 V VOL @ IOL = 3.2 mA +0.5 V VOH @ IOH= -0.4 mA +2.4 V IIL @ VIN = 0.4 to VCC +10 mA ICC @ TSCT = 100 ns 50 µA CAPACITANCE f = 1MHz Symbol Parameter Min. Typ. Max. Units C IN Capacitance on Input pins 10 pF C OUT Capacitance on Output Pins 10 pF C IO Capacitance on I/O pins 20 pF AC TIMING SPECIFICATIONS TA =0 °Ct o7 0°C, VCC = +5V±5 percent, unless otherwise specified. No Signal Symbol Parameter Test Condition Min. Typ. Max. Units

1 SYSCLK T SCT SYSCLK period 100 20000 ns

2 SYSCLK T SCL SYSCLK low time 45 ns

3 SYSCLK T SCH SYSCLK high time 45 ns

4 SYSCLK T SCR Rise time of SYSCLK 0 8 ns

5 SYSCLK T SCF Fall time of SYSCLK 0 8 ns

6 TCLK T TCT TCLK period 140 ns

7 TCLK T TCL TCLK low time 63 ns

8 TCLK T TCH TCLK high time 63 ns

9 TCLK T TCR Rise time of TCLK CL = 50 pF 0 8 ns

10 TCLK T TCF Fall time of TCLK 0 8 ns

11 TD T TDP TD data propagation delay after the

CL = 50 pF 40 ns

12 TD T TDH TD data hold time after the falling edge

AC TIMING SPECIFICATIONS (Continued) TA =0 °Ct o7 0°C, VCC = +5V±5 percent, unless otherwise specified. No Signal Symbol Parameter Test Conditions Min. Typ. Max. Units

13 RCLK T RCT RCLK period 140 ns

14 RCLK T RCH RCLK high time 63 ns

15 RCLK T RCL RCLK low time 63 ns

16 RCLK T RCR Rise time of RCLK 0 8 ns

17 RCLK T RCF Fall time of RCLK 0 8 ns

18 RD T RDR RD data rise time 0 8 ns

19 RD T RDF RD data fall time 0 8 ns

20 RD T RDH RD hold time after rising edge of

21 RD T RDS RD setup time prior to rising edge of

22 A/DAL T DOFF Bus Master driver disable after rising

23 A/DAL T DON Bus Master driver enable after falling

TSCT = 100ns 0 200 ns

24 HLDA T HHA Delay to falling edge of HLDA from

falling edge of HOLD (Bus Master) 0n s

25 RESET T RW RESET pulse width 30 ns

26 A/DAL T CYCLE Read/write, address/data Cycle Time TSCT = 100ns 600 ns

27 A T XAS Address setup time to falling edge

28 A T XAH Address hold time after the rising

29 DAL T AS Address setup time to falling edge

30 DAL T AH Address hold time after the falling

31 DAL T RDAS Data setup time to the falling edge

of DAS (Bus Master read) 55 ns

32 DAL T RDAH Data hold time after the rising edge

of DAS (bus master read) 0n s

33 DAL T DDAS Data setup time to the falling edge of

DAS (bus master write) 0n s

34 DAL T WDS Data setup time to the rising edge of

DAS (bus master write) 250 ns

35 DAL T WDH Data hold time to the rising edge of

DAS (bus slave write) 35 ns

36 DAL T SRDH Data hold time after the rising edge

of DAS (bus slave read) TSCT = 100ns 0 35 ns

37 DAL T SWDH Data hold time after the rising edge

of DAS (bus slave write) 0n s

38 DAL T SWDS Data setup time to the falling edge of

DAS (bus slave write) 0n s

39 ALE T ALEW ALE width high 110 ns

40 ALE T DSW Delay from rising edge od DAS to

41 DAS T DSW DAS width low 200 ns

AC TIMING SPECIFICATIONS (Continued) TA =0 °Ct o7 0°C, VCC = +5V±5 percent, unless otherwise specified. No Signal Symbol Parameter Test Conditions Min. Typ. Max. Units

42 DAS T ADAS Delay from the falling edge of ALE to

43 DAS T RIDF Delay from the rising edge of DALO

to the falling edge of DAS (bus master read) 35 ns

44 DAS T

RDYS Delay from the falling edge of READY to the falling edge of DAS TARYD = 300ns TSCT = 100ns 120 200 ns

45 DALI T ROIF Delay from the rising edge of DALO

to the falling edge of DALI (bus master read) 70 ns

46 DALI T RIS DALI setup time to the rising edge of

DAS (bus master read) 150 ns

47 DALI T RIH DALI hold time after the rising edge

of DAS (bus master read) 0n s

48 DALI T RIOF Delay from the rising edge of DALI

to the falling edge of DALO (bus master read) 70 ns

49 DALO T OS DALO setup time to the falling edge

of ALE (bus master read) 110 ns

50 DALO T ROH DALO hold time after the falling

edge of ALE (bus master read) 35 ns

51 DALO T WDSI Delay from the rising edge of DAS to

the rising edge of DALO (bus master write) 50 ns

52 CS T

CSH CS hold time after the rising edge of DAS (bus slave) 0n s

53 CS T CSS CS setup time to the falling edge of

DAS (bus slave) 0n s

54 ADR T SAH ADR hold time after the rising edge

of DAS (bus slave) 0n s

55 ADR T SAS ADR setup time to the falling edge of

DAS (bus slave) 0n s

56 READY T ARYD Delay from the falling edge of ALE to

the falling edge of READY to Insure a Minimum Bus Cycle Time (600ns) T SCT = 100ns 150 ns

57 READY T SRDS Data setup time to the falling edge of

READY (bus slave read) 75 ns

58 READY T RDYH READY hold time after the rising

edge of DAS (bus master) 0n s

59 READY T SRYH READY hold time after the rising

edge of DAS (bus slave) TSCT = 100ns 0 35 ns

60 READY T RSH READ hold time after rhe rising edge

of DAS (bus slave) 0n s

61 READ T SRS READ setup time after rhe rising

edge of DAS (bus slave) 0n s

62 READY T RDYD Delay from falling edge of DAS to

falling edge of READY (bus slave) TSCT = 100ns 200 ns MK5027

Figure 7:MK5027 Bus Master Timing Diagram (read). Note:The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. MK5027

Figure 8:MK5027 Bus Master Timing Diagram (write). Note:The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. MK5027

DIP48 PACKAGE MECHANICAL DATA DIM. mm inch a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 D 62.74 2.470 E 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 58.42 2.300 F 14.1 0.555 I 4.445 0.175 L 3.3 0.130 MK5027

PLCC52 PACKAGE MECHANICAL DATA DIM. mm inch A 4.20 5.08 0.165 0.20 A1 0.51 0.020 A3 2.29 3.30 0.090 0.13 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 C 0.25 0.01 D 19.94 20.19 0.785 0.795 D1 19.05 19.20 0.750 0.756 D2 17.53 18.54 0.690 0.730 D3 15.24 0.60 E 19.94 20.19 0.785 0.795 E1 19.05 19.20 0.750 0.756 E2 17.53 18.54 0.690 0.730 E3 15.24 0.60 e 1.27 0.05 L 0.64 0.025 L1 1.53 0.060 M 1.07 1.22 0.042 0.048 M1 1.07 1.42 0.042 0.056 MK5027

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.  1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. MK5027