MK5025

MK5025 STMICROELECTRONICS | Alldatasheet

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Mi 7929237 0045393 387 MBSGTH 7 7) SGS-THOMSON MICROELECTROMICS MK5025 CCITT X.25 LINK LEVEL CONTROLLER PRELIMINARY DATA = CMOS = FULLY COMPATIBLE WITH BOTH 8-BIT OR 16-BIT SYSTEMS e = SYSTEM CLOCK RATE TO 10MHz « : = DATE RATE UP TO 7Mbps, WITH A 64-BYTE KK FIFO IN EACH DIRECTION = COMPLETE DATA LINK LAYER IMPLEMEN- ! TATION = COMPATIBLE WITH X.25 LAPB, ISDN LAPD, X.32, AND X.75 LINK LEVEL PROTOCOLS cpiPas Pioos2 = 48-PIN DIP NEARLY PIN-FOR-PIN COM- (Order codes at the end of the datasheet) PATIBLE WITH THE LANCE CHIP (MK7990) = BUFFER MANAGEMENT INCLUDES : initialization block . = Separate recelve and transmit rings Figure 1 : MK5025 Dual in Line Pin Configuration. ~ variable descriptor ring and window size = ONCHIP DMA CONTROL WITH PROGRAMM- ABLE BURST LENGTH = SELECTABLE SINGLE OR EXTENDED CON- oon “oP Nec TROL FIELD oavor 2 rb omtos = PROGRAMMABLE 1 BYTE OR 2 BYTES AD oavos 3 «spi oatos DRESS FIELD AND GLOBAL ADDRESS: ALS 4 45) DALIO = TRANSPARENT MODE WITH OR WITHOUT aioe fs caf oaun ADDRESS FILTERING ALLOWS DISABLING naios 6 cap oar X.25 PROCESSING FOR CUSTOMIZED AP- omar ah oats PLICATIONS = HANDLES ALL HDLC (ADCCP) FRAME FOR- ous fe aif oaute MATTING : aLoo cop) oaurs - Zero bit insert and delete READ (10 339 are - FCS generation and detection NTR Qn 36p) 17 = frame delimiters by flags ode a = FIVE PROGRAMMABLE TIMER/COUNTERS «S025 11, T3, TP, N1, N2 DADO 13 sep aio = HANDLES ALL_ERROR RECOVERY, SE- bas 14 asp 420 QUENCING, AND S AND U FRAME CONTROL SMOrayTE/BUSREL 15 sap arr = SELECTABLE FCS OF 16 OR 32 BITS BM /BUSARO (16 aaplaze = DATA LINK SERVICES : FOTOBUSRG d 17 sep aaa = compatible with LAPD data Ink senoes oes apr - ibe wi i ic _ _ «= TESTING FACILITIES = uu bee 30 OSR.CTS ~ built-in self test facility tS 20 29H) 10 | loopback medes aor tf 21 20h srscux = ALL INPUTS AND OUTPUTS ARE TTL COM- READY 22 ap Re PATIBLE RESET th 23 asf) ore. RTS = PROGRAMMABLE FOR FULL OR HALF DU no 24 och rae PLEX OPERATION = PROGRAMMABLE MINIMUM FRAME SPAC- ING ON TRANSMIT (flags between frames) August999t 339

MK5025 WM 7929237 0045394 216 MMBSGTH GENERAL DESCRIPTION Figure 2 : MK5025 Chip Carrier Pin Configuration. The SGS-THOMSON X.25 Link Level Controller (MK5025) is a VLSI semiconductor device which ailieviliai provides a complete link level data communication gs ves control conforming to the 1984 CCITT version of PO ee "sh oun X.25. This includes frame formatting, transparency cee de oh one (so-called “bit-stuffing’), error recovery by retrans- once do cb ous mission, sequence number control, U_(unnum- cao Shae bered) frame control, and S (supervisory) frame mm dus sper control. The MK5025 also supports X.32 (XID), ati axso2s chas X.75, and ISDN LAPD. The MK5025 may be used ode spa with any of several popular 16 and 8 bit micropro- | ssmeneissna die mba cessors, such as 68000, 6800, 28000, 280, LSI-11, xe fo np aa 8086, 8088, 8080, etc. ee da pea mS Gy ao ws om mse nw PAO BESERZYEERS&S BES*EEES*S PIN DESCRIPTIONS DAL <07 : 00> (InpuVOutput ; 3-State). The time lines during the data portion of a READ transfer. multiplexed Data/Address bus. During the address. DALI is not asserted during a WRITE transfer. portion of the memory transfer, DAL <07 :00>con- ALO (Output ; 3-State). DAL OUT is an external tains the lower 8 bits of the memory address. During bys transceiver control line, DALO is driven by the the data portion of the memory address. During the K5025 only while it is the BUS MASTER, DALO is, data portion of a memory transfer, DAL <07 : 00> asserted by MK5025 when it driven the DAL lines contains the read or write data, depending on the uring the data portion of a READ transfer or for the type of transfer. duration of a WRITE transfer. READ (Input/Output ; 3-State). READ indicates the aS (Input/Oulput ; 3-State). DATA STROBE ‘ype of operation that the bus controller is perfor. defines the data portion of a bus transaction. By de- ming during a bus transaction. READ is driven by inition datais stable and valid at the low to high tran- the MK5025 only while it is the BUS MASTER. sition of DAS. This signal is driven by the MK5025 READ is valid during the entire bus transaction and Whiletis the BUS MASTER, During Bus Slave oper. is tristated by the MK5025 at all other times. ations, this pinis used as an input. Atallother times - MKS025 as a Bus Slave the signal is trstated. READ = HIGH - Datais placed on the DAL Ii eee | a bythe chip, onthe DAL IINeS MO, BYTE, BUSREL (Input/Output ; 3-State). VO | READ = LOW- taken off the DAL li pins 15 (16) and 16 (18) are programmable through bythe chi. Of tne DAL IINES CSRA. If bit 06 of CSR4 is set to a one, pin 15 (16) _ MK5025 as a Bus Master becomes input BUSREL and is used by the host to READ ~ HIGH Data is taken off the DAL lines _signal the MK5025 to terminate a DMA burst atter by the chip. the current bus transfer has completed. If bit 06 is READ = LOW- Data is placed on the DAL lines __learthe pin 15 (16) is the output BMO, and behaves by the chip. as described below for pin 16 (18). INTR (Output ; Open Drain). INTERRUPT is an at- BM1, BUSAKO (Output ; 3-State). Pin 15 (16) and tention interrupt line that indicates that one or more _ 16 (18) are programmable through bit 00 of CSR4 of the following CSRO status flags is set: MISS, (8CON). MERR, ROR, TUR, RINT, TINT OR PINT. INTER- If CSR4 <00> BCON =0, RUPT is enabled by CSRO<09>, INEA=1. VO Pin 15 (16) = BMO (Output ; 3-State) DALI (Output ; 3-State). DAL IN is an external bus VO Pin 16 (18) = BM1 (Output ; 3-State) transceiver control line. DALI is driven by the BYTE MASK <1 : O> Indicates the byte(s) on the MK5025 only while itis the BUS MASTER. DALIis DAL to be read or written during this bus transition. asserted by MK5025 when it reads from the DAL 2140 J i 2 Se 340 ——E~“eee aaa... eee

@™ 7929237 0045395 152 MESGTH MK5025 PIN DESCRIPTIONS (continued) MK5025 drives these lines only as a Bus Master. _nal is at its asserted level. This signal is driven by MK5025 ignores the BM lines when itisaBus Slave. _ the MK5025 while itis the BUS MASTER. At all other Byte selection is done as outlined in the following __ times, the signal is tristated. table : = Bui BMO wCOPIN 8 eo) Le LOW LOW Entire Word ; LOW HIGH Upper Byte (DAL <15: 08>) Address Latch Enable is used to demuttiplex the HIGH LOW Lower Byte (DAL <07:00>) DAL lines and define the address portion of the HIGH HIGH — None transfer. As ALE, the signal transitions from high to low during the address portion of the transfer and lf CSR4 <00> BCON = 1, VO Pin 16 (16) = BYTE (Output ;3-State) remains low during the data portion. VO Pin 16 (18) = BUSAKO (Output) If CSR4 <00> ACON = 1, Byte selection is done using the BYTE line and VO Pin 18 (20) = AS DAL <00> latched during the address portion of he As AS, the signal pulses low during the address por- bus transaction. MK5025 drives BYTE only as aBus tion of the bus transfer. The low to high transition of Master and ignores it when a Bus Slave. Byte se- A can be used by a slave device to strobe the ad- lection is done as outlined in the following table : dress into a register BYTE DAL <00> : LOW LOW Entire Word HLDA. Hold Acknowledge (Input). Hold Acknowl- LOW HIGH __llegal Condition edge is the response to HOLD. When HLDA is low HIGH LOW Lower Byte in response to MK5025's assertion of HOLD, the HIGH HIGH Upper Byte MK5025 is the Bus Master. HLDA should be disas- BUSAKO is a bus request daisy chain output. if §aited ONLY alter HOLD has been released by MK5025 is not requesting the bus and itreceives <*>» . HLDA, BUSAKO will be driven low.lf MK5025 isre- CS. Chip Select (Input). Chip Select indicates, questing the bus when it receives HLDA, BUSAKO ~— When low, that the MK5026 is the slave device for will remain high. the data transfer. CS must be valid throughout the HOLD, BUSRG (Input/Output ; Open Drain), Pre transaction. Pin 17 (19) is contigured through bit 0 of CSR4. ADR Address (input) Address selects the Regis: _ ter Address Port or the Register Data Port. It must ese Oe be valid throughout the data portion of the transfer NO (19) = and is only used by the chip when CS is low. HOLD request is asserted by MK5025 when it re- ADR PORT quires a DMA cycle regardless of the previous state LOW Register Data Port of the HOLD pin. HOLD is held low for the entire en- HIGH Register Address Port surge us transaction. READY (Input/Output ; Open Drain). When the 'CSR4 <00> BCON = 1__ MK5025 is a Bus Master, READY is an asynchron- VO Pin 17 (19) = BUSRO ous acknowledgement from the bus memory that BUSRQ is asserted by the MK5025 when itrequires memory will accept data in a WRITE cycle or that a DMA cycle if the prior state of the BUSRQ pin was memory has put data on the DAL lines in a READ high, BUSRQ is held low for the entire ensuring bus cycle. transaction. As a Bus Slave, the MK5025 asserts READY when ALE, AS. Address Latch Enable, Address Strobe _ithas put data on the DAL lines during a READ cycle (Output ; 3-State). The active level of Address or is about to take data from the DAL lines during a Strobe is programmable through CSR4. The ad- — WRITE cycle. READY is a response to DAS and it dress portion of a bus transfer occurs while this sig- _will be negated after DAS is negated. J ‘3/40 i 8 341

MK5025 me 7929237? 0045396 099 MSGTH PIN DESCRIPTIONS (continued) RESET (Input). RESET is the Bus signal that will DSR, CTS. Data Set Ready, Clear to Send cause MK5025 to cease operation, clear itsinternal (Input/Output). Modem Control Pin. Pin 30 (33) is logic and enter an idle state with the STOP bit of configurable through CSRS. This pin can be pro- CSRO set. grammed to behave as input CTS or as programm- TELK. Transmit Clock (input).A 1X clock inputfor able LOpin DSR, Itconigured as CTS, the MKBO25 transmitter timing. TD changes on the falling edge _Will transmit all 1's while CTS is high. of TCLK. The frequency of TCLK may be up to RD. Receive Data (Input). Received serial data 7Mbps. input. DTR, RTS. Data Terminal Ready, Request to Send _A<23: 16> (Output ;3-State). Address bits <23: 16> y, Req (InpuvOutput). Modem Control Pin. Pin 26 (29) is _usedin conjunction with DAL <15 : 00> to produce a configurable through CSRS. This pin can be pro- 24-bit address. MK5025 drives these lines only as a grammedto behave as outputRTSoras programm- Bus Master. able /O in DTA. configured as RTS, the MK5025 DAL <1 : 08> (InpuvOutput ; 3-State). The time will assert this pin if it has data to send and muttipiexed Data/Address bus. For 16-bit operations, throughout transmission of a frame. DAL <15 : 08> behaves similar to DAL <07 : 00> RCLK. Receive Clock (Input). A 1X clock input for above for the high byte of data or the middle byte of receiver timing. RD is sampled on the rising edge ofthe 24-bit address. For 8-bit operations, FCLK. The frequency of RCLK may be up to 7MHz. DAL <15_: 08> behaves similar to A <23 : 16> for SYSCLK. System Clock (Input). Used for internal __ the middle byte of the 24-bit address only. timing of the MK5025. SYSCLK should bea square sg, Digital circuit ground pi wave, and be greater than S00KHz and less than VSS: Digital circult ground pins. tOMrE Voc. Main power supply pin (SV + 5%). TD. Transmit Data (Output). Transmit serial data output. OPERATIONAL DESCRIPTION The SGS-THOMSON X.25 Link Controller from the Host. The /O acceleration processor in (MK5025) device isa VLSIproduct intendedfordata Figure 3 is recommended, but not required. communication applications requiring X.25 link level ; ; control (LAPB). The MK5025 will perform all frame All signal pins on the MK5025 independent of the formating, such as frame delimiting with flags, FCS Physical interface. As shown in Figure 3, line drivers generation and detection, as well as zero-bit inser-___Nd receivers are used for electrical connection to tion and delection for transparency. The MK5025 _ the physical layer. also includes a buffer management mechanism that The M5025 is mode up of functional blocks shown allows the user to transmit and/or receive multiple in Figure 4 and the MK5025 is made up of functional Packets. Contained in the buffer management is 29 —_igcks shown in Figure 4 and described in the fol- on-chip dual channel DMA: one channel forreceive _jawing paragraphs. and one channel for transmit. The MK5025 handles all supervisory (S) and unnumbered (U) frames as Microcontroller. shown in table 2 and table 3. aaiate The microcontroller is the brain of the MK5028. It The MK5025 is intended to be used with any popu- controls all of the other blocks and contains most of lar 16 or 8 bit microprocessor. A possible system the protocol processing. All frame content process- configuration for the MK5025 is shown in Figure 3. _ ing as well as S and U frame processing and gener- ‘The MK5025 will move multiple blocks of receive ation is performed by the microcontroller. All and transmit data directly into and out of memory _ primitive processing and generation is also done through the Host's bus. An 1/O acceleration proces-__here. The microcode ROM contains the control pro- sor can be used to off-load Network Level software gram for the microcontroller. A emcees

M8 7929237 004539? T25 MSGTH MK5025 OPERATIONAL DESCRIPTION (continued) Figure 3 : Possible System Configuration for the MK5025. HOST PROCESSOR (68000, 8086, 28000, ETC) 16-BIT DATA BUS INCLUDING 24-BIT ADDRESS ANO BUS CONTROL MEMORY LAYER 3 (MULTIPLE ————] 1/0 PROCESSOR DATA BLOCKS) “OPTIONAL” I otr.| osr,] —_| - 1 Rrs | cts alo TeLK] TO} | LINE ORIVERS LINE DRIVERS AND RECEIVERS AND RECEIVERS “OPTIONAL” ELECTRICAL VO 1 (SUCH AS RS-232C.RS-423, 1 RS~422,V 35) DATA COMM. CONNECTOR (SUCH AS RS-232C,RS-449,V.35) ‘vooors eg scs-rtomson SY7 iarcrouscrnowics 3

MK5025 ME 7929237 0045398 9b] MESGTH OPERATIONAL DESCRIPTION (continued) Figure 4 : Simplified Block Diagram. ; a ele 2/G)6/e) 3/8} mom |e} 8) RENE CI lf : Fs] i: [rar ua o— | = | LI « ves-ono | = | [a reset a na. ox ro m [comer] The MK5025 can interface with the host bus intwo _ the MK5025 allows access to its 6 controlstatus reg- ways : either as bus master or as a bus peripheral. _isters which are used to monitor and control the chip. The MK5025 contains a dual channel DMA on chip These registers are used to control link procedures, to handle data transfers to and from the host mem- —_ configure interface options, control and monitor in- ory. All access to the initialization block and descrip- _terrupt status, and more. Bus slave mode also tor rings is handled in this way. The address but is __allows both 8 and 16-bit accesses. 24 bits wide and does not use any segmentation or paging methods. Data transfers can optionally be 8 DMA Controller. and 16 bit operations, this allows easy interfacing The MK5025 has an on-chip DMA Controller circuit. with both 8 and 16 bit processors. DMA transferscan This allows it to access memory without requiring be up to 1, 8 or an unlimited number of words per- host software intervention. Whenever the MK5025 transfer under program control. In bus slave mode _requires access to the host memory it will negotiate 6/40 . —— yy S6s:THomson __ 344

M@@ 792923? 0045399 878 MESGTH MK5025 | OPERATIONAL DESCRIPTION (continued) | for mastership of the bus. Upon gaining control of the ation and checking can also be optionally disabled bus the MK5025 will begin transferringdatatoorfrom _ if defined. memory. The MK5025 will perform memory transfers . ‘ i until either it has nothing more to transfer, it has Receiver. Serial receive data comes into the Re- "reached its DMA burst limit (user programmable), or Celver (figure 4). The Receiver is responsible for : the BUSREL pin is driven low. In any case itwillcom- _1. Leading and trailing flag detection. plete all bus transfers before releasing bus master- 9. Deletion of in ship back to the host. f, during a memory transfer, > Deletion of zeroes inserted for transparency. the memory does not respond within 256 SCLK 3: Detection of idle and abort sequences. cycles, the MK5025 will release ownership ofthebus __4. Detection of good and bad FCS (Frame Check immediately and the MERR bit will be set in CSRO. Sequence). ‘The DMA burst limit can be programmed by the user itoring Rece through CSR4. In 16 bit mode th limit can be set to 5. Monitoring ver FIFO status. 1 word, 8 words, or unlimited word transfers. In bit _ 6: Detection of Receiver-Over-Run. mode, it can be set to 2 bytes, 16 bytes, or unlimited 7. Odd byte detection. If frames are received that byte transfers. For high speed data lines have an odd number of bytes in the informa- (ie. > 1Mbps) a burst limit of 8 words, 16 bytes or un- tion field, the last byte of the frame is said to be limited is suggested to allow maximum throughput. an odd byte. The byte ordering of the DMA transfers canbe pro- _8. Detection of non-octet aligned frames, such grammed to account for differences in processor frames are treated as invalid frames. architectures or host programming languages. Byte : on . ordering can be programmed seperately for data Transmitter. The Transmitter is responsible for and control information. Data information is defined _1. Serialization of outgoing data as all contents of data buffers ; control information —_ 2. Generating and appending the FCS, is defined as anything else in the shared memory © Generating and appending the F space (i.e. initialization block, descriptors, etc). For 3. Generation of interframe time-fill as either flags more information see "Control and Status Regis- or idle. ter 4" description. 4. Zero bit insertion for transparency. Serial Interface. 5. Transmitter-Under-Run detection. The MK5025 provides two seperate serial chan- _ 6. Transmission of odd byte. nels ; one for received data and one for transmitted 7. RTS/CTS Control data. These serial channels are completely sep- erate and may be run at different clock frequencies Frame Check Sequence. The FCS on the trans- up to 7MHz. The receiver is responsible for recog- _mitter or receiver may be either 16 bit or 32 bit, and nizing frame boundaries, removalotinserted zeroes _is user selectable. For full duplex operation, both the (for transparency), and checking the incoming FCS. __receiver and transmitter have individual FCS com- Frames with incorrect FCS values are discarded. _putation circuits. The characteristics of the FCS are : The receiver also parallelizes the incoming data. Transmitted Polarity : inverted which is placed into the receive data buffers within _ Transmitted Order : High Order Bit First the receive descriptor ring. The receiver alsorecog- - Pre-set Value : All 1's nizes link idle and frame abort sequences. The — - Polynominal 16 bit : X16 + X12+X5 +1 transmitter is responsible for framing and serializing Remainder 16 bit (if received correctly) : the data frames placed in the transmit descriptor high order bit > 0001 1101 0000 1111 ring. The transmitter calculates the FCS of the out- - Polynomial 32 bit going data and appends it to the data. The transmit X32 + X26 + X23 + X22 + X16 + X12 4 X11 + ter generates flag sequences for interframe fill, at X10 +X8+X7+X54+X4+X2+X41 least two flags are transmitted between adjacent © . Remainder 32 bit (if received correctly) : frames. The FCS calculations for both directions of high order bit + 1100 0111 0000 0100 serial data optionally follow either the 16-bit CRC- 1101 1101 0111 1011 CCITT or the 32-bit CRC-32 algorithms. FCS gener- 7140 ‘SGS-THOM! IO 5 s:20ms00 345

MK5025 mm 7929237 0045400 34T MMSGTH OPERATIONAL DESCRIPTION (continued) read or write to these registers like any other bus Receive FIFO. The Receive FIFO buffers the data__slave. The contents of these registers are listed in received by the receiver. This performs two major the Control and Status Registers section and the functions. First. it resynchronizes the data from the _bus signal timing is described in figures 9 and 10. receive clock to the system clock. Second, it allows the microcontroller time to finish whatever it may be Buffer Management doing before it has to process the received data. The basic organization of the buffer management is The receive FIFO holds the data from the receiver Circular queue of tasks in memory called descrip- without interrupting the microcontroller until it con- 10" rings. There are separate rings to descnbe the tains enough data to reach the watermark level. This _tfansmit and receive operations. Up to 128 buffers watermark level can be programmed in CSR4 to Tay be queued-up on a descriptor ring awaiting ex- ‘cour when the FIFO contains at least 2 bytes; 18 @cuttion by the MK5025. The descriptor ring has a ormorebytes :34 ormorebytes :or50ormore bytes. Segment assigned to each butter. Each segment This programmability, along with the programmable holds a pointer for the starting address of the buff- burst length of the DMA controller, enables the user _&" and holds a value for the length of the butfer in to define how often and for how long the MK5025 Words (16 bits). must use the host bus. For more information, See Each segment also cdntains two control bits called Control and Status Register 4 description. OWNA and OWNB, which denote whether the For example, if the watermark levelis set at34 bytes MK5025, the HOST, or the /O ACCELERATION and the burst length is limited to 8 word transfers at Processor (if present) “owns” the buffer. For trans- a time, the MK5025 will request control of the host __mit, when the MK5025 owns the buffer, the MK5025 busas soon as 34 bytes are received and again after _is allowed and commanded to transmit the .butfer. every 16 subsequent bytes. When the MK5025 does not own the butter, it will Transmit FIFO. The Transmit FIFO butfersthedata transmit that buffer. For receive, when the tobe transmitted by the MK5025. This also performs MK5025 owns a buffer, it may place received data two major functions. First, it resynchronizes thedata _into that butfer. Conversely, when the Mk5025 does from the system clock to the transmit clock, Second, NOt own a receive buffer, it will nat place received it allows the microcontroller and DMA controller to. ata in that butfer. read data from the host's memory buffers inbursts; The MK5025 buffer management mechanism will making both the MK5025 and the host bus more ef- handle frames which are longer than the length of ficient an individual buffer. This is done by a chaining The transmit FIFO has a watermark scheme simi- method which utilizes multiple buffers. The MK5025 lar to the one described for the receive FIFO tests the next segment in the descriptor ring in a above. The transmit FIFO will not interrupt the “look ahead” manner. If the packet is too long for microcontroller for service until it empties enough —_one buffer, the next buffer will be used after filling to reach the watermark level. The watermark can _ the first buffer ; that is, “chained”. The MK50285 will be programmed in CSR4 as: any space available, _then “look ahead” to the next buffer, and chain that 18 bytes of space available, 34 bytes of space buffer if necessary, andsoon. available, or 50 bytes of space available. The ut "y transmission of data however, will begin as soon The operational parameters for the buffer manage- as the FIFO has al least word of data ment are defined by the user in the initialization Bus Slave Circuitry block. The parameters defined include the basic The MK5025 contains a bank of internal con- mode of operation, the number of entries for the trol/status registers (CSRO-5) which can be ac- transmitter and receiver descriptor rings, frame Ad- cessed by the host as a peripheral. The host can dress field, and etc. 8/40 1 | Se ___ 5 gggmomsom eal

@@ 7929237 OO45401 286 MESGTH MK5025 OPERATIONAL DESCRIPTION (continued) Figure 5 : Butter Management Organization. eceIve BUFFERS cena, ona — a al ec | DESCRIFTOR © DUrren SiaTUS ~ “aurren nooness _ furren sae _ BUFFER WS COUNT DESCRIPTOR + . as Telos no Secor [er sees] {TRANSMIT DESCRIPTOR RINGS. "TRANSMIT BUFFER THOTEST Teaver a Torres neceve — SURFER Stars _ ~surren soness [error counrens_| turrem msc count an : XID/TEST RECEIVE hd — a surren The Initialization Block. Chip initialization informa- B. Frame Address Values. tion is located in a block of memory called the Initial- ization Block. The Initialization Block consists of 28 © Timer Preset Values. contiguous words of memory starting on a word _D. Location and size of Receive and Transmit De- boundary. This memory is assembled by the HOST soriptor Rings. or VO acceleration processor, and is accessed by ; MK5025 during initialization. The Initialization Block ©: Location and size of XID/TEST Butters, is comprised of F. Location of status buffer. A, Mode of Operation. G, Error Counters. ee OPF=E|ses-romson SY7 imcnosacracancs 347

MK5025 Me 7929237 0045402 lle MESGTH OPERATIONAL DESCRIPTION (continued) The Circular Queue. The basic organization of the method which utilizes multiple buffers. The MK5025 butfer management is a circular queue of tasks in _ tests the next segment in the descriptor ring in a memory called descriptor rings. There are separate "look ahead” manner. If the frames are too long for rings to describe the transmit and receive oper- one buffer, the next buffer will be used after filing ations, Up to 128 buffers may be queued-up on a_—_ (or transmitting) the first buffer ; that is, "chained! descriptor ring awaiting execution by the MK5025. ‘The M5025 will then “look ahead” to the next butt- The descriptorringhas a segment assignedto each __er, and chain that buffer it necessary, and so on. buffer. Each segment holds a pointer for the start: . The operational parameters for the buffer manage- ing address of the buffer, and holds a value forthe ment are defined by the user in the initialization length of the buffer in bytes block. The parameters defined include the basic Each segment also contains two control bits called mode of operation, the number of entries for the OWNA and OWNB, which denote whether the transmitter and receiver descriptor rings, frame Ad- MK5025, the HOST, or the VO ACCELERATION dress field, and etc. The starting address for the In- PROCESSOR (if present) ‘owns" the buffer. For _itialization, IADR, is defined in the CSR2 and CSR3 transmit, when the MK5025 owns the buffer, the registers inside the MK5025. M5025 is allowed and commanded to transmit the Frame Format. The frame form h buffer. When the MK5025 doos not own the buffer, Hemod Cena inion ech at oti ote it wll not transmit that buffer. For receive, when the programmable number of leading flag. patterns MK5025 owns a buffer, it may place received data (91114110), an address field, a control field, an in- into that butfer. Conversely, when the MK5025 does formation field (not in all frames), an FCS of either not own a receive butter, it wll not place received —+6.gr 32 bits, and a tailing flag pattern. The num. Gata in that buffer. ber of leading flags is programmable through the The MK5025 buffer management mechanism will — Mode Register in the Initialization Block. Received handle frames which are longer than the length of frames may have only one flag between adjacent an individual buffer. This is done by a chaining frames. B-dits 8 ane Bné an 16/32 8 Tansmited Fist Table 1 : Frame Types Symbols Definit : Jefinitions. The Command/Response Repertoire. The com- me Types Symbols ons. mandiresponse repertoire of the MK5025 is shown [Name _[Detinition in tables 2 and 3. This set conforms to the ISDN [I information ame LAPD, which is a super-set of X.25 Link Level. The Ul lUnrumbered Information MK5025 will process the S and U frames shown in [BR Receiver Ready table 1 andwillhandle the A and Cfieldsfor all land |ISC_——_—Disconnect Ul frames. |RNR Receiver Not Ready UA lUnnumbered Acknoledge REJ [Reject FRMR Frame Reject SABM [Set Asynchronous Balance Mode IDM Disconnect Mode xID Exchange Identification TEST |Link Test frame foo GS-THOMSON G7 SeScnietonet 348

: @™ 7929237 0045403 059 MBSGTH MK5025 OPERATIONAL DESCRIPTION (continued) Table 2 : Command/Response Repertoire - Module 8 Operation. [Format [ Commana [Resp [Encoding fo a GS [information Transfer | tf NS) PNA [Supervisory RR RR 1 0 0 0 PF « NR Oo RNR RNR 1 0 4 0 PF © NR) = | REJ REJ 1 0 0 1 PF «© NA) 3 |} Unnumbered SABM 1 1 4 1 PFO 4 0 0 om 1 1 4 1 F 0 0 0 XID (1) XI) | 1 1 1 1 PR 1 0 14 ul(1) ul (1) 1 1 0 0 PF 0 0 0 Disc 1 4 0 0 P 0 1 0 UA 4 4 0 0 F 4 4 0 FRMR 1 1 4 0 F 0 0 14 Test(2)| TesT(2)} 1 1 0 0 PF 1 1 14 Table 3 : Command/Response Repertoire - Modulo 128 Operation. | informationtraster | 1 | 0 NS) | Pea] Supervisory RR RR 1 0 0 0 0 0 0 0 |PF NR) RNR RNR 1 0 1 0 0 0 0 oO |P NR) REJ REJ 1 0 0 1 0 0 0 0 |PF NA Unaumbered SABME 1 1 1 1 PF 1 4 0 DM 1 1 4 1 F 0 0 0 XID (1) xip()) | 1 1 4 1 PRE 1 0 4 ul(i) ui) | 1 1 0 0 PF 0 0 O DISC 1 1 0 0 P 0 1 0 UA 1 1° 0 0 F 1 4 0 FAMR | t 7 1 0 F 0 0 1 Test(2)] TeSt(2)| 11 0 0 PF 1 Ot 4 Notes: 1. XID and Ul frames can be individually enabled for compatibility with X.32 and LAPD respectively. 2. TEST frames are enabled with XID frames. 3. N(S) = Transmitter Send sequence number 4. N(R) = Transmitier Receive sequence number 5. P/F = Poll bit when issued as a command. Final bit when issued as a response. Protocol. The MK5025 contains a full implementa- XID and TEST frames are available for use in X.32. tion of the 1984 CCITT X.25 data link layer. It allows The interface between the MK5025 and the host both basic and extended control fields, variable win- (layer 3) conforms to both the {SO data link services dow sizes, and user-defined counter and timer standard and the ISDN LAPD data link services values. Extended addressing and UI frames are op- standard. tionally available for use in ISDN LAPD applications. 11740 —_ i SGS-THOMSON “YY jmicnoe. ecmowics 349

MK5025 mm 7929237 OO4S4O4 TIS MESGTH PROGRAMMING SPECIFICATIONS This section defines the Control and Status Regis- _Bit <06 : 04>. They are reserved and must be writ- ters and the memory data structures required topro- _ten as zeroes. gram the MKS025. Bit <03 : 01>, CSR <2: O>. CSR address select bits Control and Status Registers. is ReadMrite. Selects the CSR to be accessed There are six Control and Status Registers (CSR's) _through the RDP RAP is cleared by Bus Reset. resident within MK5025. The CSR's are accessed CSRe2 : 0> CSR Selected through two bus addressable ports, an address port 0 CSRO (RAP), and a data port (RDP). Thus the MK5025, 1 csRi needs only two address locations in the system 2 csR2 memory or /O map. 8 one Accessing the Control and Status Registers. 5 CSRS The CSR's are read (or written) in a two-step oper- , ation. The address of the CSR is written into the ad- ‘Bit 00, HBYTE. Determines which byte is ad- Gress port (RAP) during a bus slave transaction, essed for 8-bit operation. If set, the high byte of During a subsequent bus slave transaction, thedata _the register referred to by CSR <2 : 0> is addressed, being read from (or written into) the data port (RDP) _ otherwise the low byte is addressed. This bitis only is read from (or written into) the CSR selected in the meaningful for 8-bit operation and must be written RAP. Once written, the address in RAP remains un- @8 zero if BMB = 0. HBYTE is Read/Write and changed until rewritten. A control /O pin (ADR) is _“!eared on Bus Reset. provided to distinguish the address port from the Register Data Port (RDP) oat Oot BORT rLLLrroeoecvcceee 432109876 HIGH Register Address Port (RAP) SE raLen I ERE REE A EE LOW Register Data Port (RDP) Register Address Port (RAP) CSR DATA yr 11770000080 0000 titi saa2 soo e765 4 921 0. Bit <15 : 00>, CSR DATA. Writing data to the RDP TT T Ti dn loads data into the CSR selected by RAP. Reading ololelololojmjololo| <s> jy, thedata from ROP reads the data from the CSR se- e}o) ( it \\T) lected in RAP. Li db bo titel Control and Status Register 0 (CSRO) Bit <15 : 08>. They are reserved and must be writ, RAP <3: 1>=0 ten as zeroes. 114441 0000000000 Bit 07, BM8. When set, places chip into 8-bit mode. s4a2roo98 76543210 CSR's, Init Block and data transfers are all 8-bit trans- T TIA fers, this provides compatibility with 8-bit micropro- al§ TIrixlx ninfeltiofuls We cessors. When clear, all transfers are 16-bit mjolx|x/olole/t/Ris/r{R|NiN W/o transfers. This bit mustbe set to the same value each jel l minialayats TIT time itis written, changing this bit during normal oper- ation will achieve unexpected results. BM8 is Read/Write and cleared on Bus Reset. 12/40 5 hyp SHSM 350

i i M™ 7929237 OO4S4OS 92) MBSGTH MK5025 ' PROGRAMMING SPECIFICATIONS (continued) ; Bit 15, TRANSMIT DEMAND, when set, Bit 11, TRANSMITTER ON indicates that ‘DMD. causes MK5025 to access the TXON. the transmitter ring access is en- Transmit Descriptor Ring without abled. TXON is set as the START waiting for the transmit polltime in- primitive is issued if the DTX bit is tervalto elapse. TDMD need not be 0" or afterward as DTX is cleared. ; set fo transmit a frame, it merely TXON is cleared upon recognition : hastens MK5025's response to a of DTX being set, by issuing a Transmit Descriptor Ring entry in- STOP primitive in CSR1, or by a 7 sertion by the host. TDMD is Bus RESET. If TXON is clear, the WRITE WITH ONE ONLY and host may modify the Transmit De- cleared by the MK5025 afer it is scriptor Ring entries regardless of used. Itmayreadasa"1" fora short the state of the OWNA bits. TXON time after it is written because the is READ ONLY ; writing this bit has MKS5025 may have been busy no effect. when TOMD was set. It is also Bit 10, RECEIVER ON indicates that the cleared by Bus RESET. Writing a = RXON, receiver ring access is enabled 0° in this bit has no effect. RXON is set as the START primi- Bit 14, STOP, when set, indicates that tive is issued if the DRX bit is "0" or STOP, MK5025 is operating in the afterward as DRX is cleared. STOPPED phase of operation. All RXON js cleared upon recognition external activity is disabled and in- of DRX being set, by sending a temal logic is reset. MK5025 re- STOP primitive in CSR1, or by a mains inactive except for primitive Bus RESET. If RXON is clear, the processing until a START primitive host may modify the Receive De- is issued. STOP IS READ ONLY scriptor Ring entries regardless of and set by Bus RESET or a STOP the state of the OWNA bits. RXON primitive. Writing to this bit has no is READ ONLY ; writing this bit has effect. no effect. Bit 13, Transmitter Ring Disable prevents Bit 09, INTERRUPT ENABLE allows the DTX. the MK5025 from further access to IEA. INTR VO pin to be driven low when the Transmitter Descriptor Ring. the Interrupt Flag is set. If INEA = 1 No transmissions are attempted the INTR /O pin will be low if after finishing transmission of any CSRO-<08> INTRis set. If INEA = 0 frame in transmission at the time of the INTR V/O pin will be high, re- DTX being set. DTX is gardless of the state of the Interrupt READWRITE. TXON acknow- Flag. INEA is READWRITE, setby ledges changesto DTX, see below. writing a "1" into this bit and is Bit 12, Receiver Ring Disable prevents cleared by writing a “0” into this bit DRX the MK5025 from further acoess to or by Bus RESET or by issuing a the Receiver Descriptor Ring. No STOP primitive. received frames are accepted after Bit 08, INTERRUPT FLAG indicates that finishing reception of any frame in INTR. one or more of the following inter- reception at the time of DRX being rupt causing conditions has oc- set. If DRX is set while a data link cured ; MISS, MERR, RINT, TINT, is established the MK5025 will go PINT, TUR or ROR. If INEA= 1 and into the local busy condition and will INTR = 1 the INTR LO pin will be send a RNR response frame to the low. INTR is READ ONLY, writing remote station. Upon clearing DRX this bit has no effect. INTR is the MK5025 will send a RR re- cleared as the specific interrupting sponse frame. DRX is. condition bits are cleared. INTR is READWRITE. RXON_ acknow- also cleared by Bus RESET or by ledges changes to DRX, see issuing a STOP primitive. below. Br SSionson re

MK5025 WM 7929237 OO4S4Ob 868 MSGTH PROGRAMMING SPECIFICATIONS (continued) Bit 07, MEMORY ERROR sets when also cleared by Bus RESET or by MERR. MK5025 is the Bus Master and has issuing a STOP primitive. not received READY within 256 Bit os, PRIMITIVE INTERRUPT is set SYSCLKs (25.6 usec @ 10MH2) pT, after the chip updates the primitive after asserting the address on the register to issue a provider primitive DAL lines. When a Memory Error is or to indicate a User Primitive Error detected, the receiver and trans- Condition. See CSR1<15> UERR. mitter are tured off and an inter- When PINT is set, an interrupt is Tupt_is generated if INEA = 1 generated if INEA = 1. PINT is MERR is READ/CLEAR ONLY and READ/CLEAR ONLY andis set by is set by the chip and cleared by M5025 and cleared by writing 2 writing a "1" into the bit. Writing a "into the bit. Writing a"0" has no "0" has no effect. It is cleared by effect. It is also cleared by Bus Bus RESET or by issuing a STOP RESET or byissuing a STOP primi- primitive. tive. Bit 06, MISSED PACKET is set when the Bit 92, TRANSMITTER INTERRUPT is MISS. receiver loses a packet because it TNT, set after the chip updates an entry does not own a receive butter, indi- in the Transmit descriptor Ring cating loss of a frame. When MISS. This occurs when a transmitted is set, an interrupt will be generated frame has been acknowledged by TINEA = 1. MISS is READ/CLEAR the remote station. When TINT is ONLY and is set by the MK5025 set, an interrupt is generated if and cleared by writing a"1" into the INEA = 1. TINT is READ/CLEAR bit. Writing a "0" has no effect. Itis ONLY and is set by MK5025 and also cleared by Bus RESET or by cleared by writing a"1" into the bit. issuing a STOP primitive. Writing a "0" has no effect. Itis also Bit 05, RECEIVER OVERRUN indicates cleared by Bus RESET or by is- ROR. that the Receiver FIFO was full suing a STOP primitive. when the receiver was ready 10 Bit Ot, RECEIVER INTERRUPT is set input data to the Receiver FIFO. Rint. after MK5025 updates an entry in The frame being received is lost but the Receive Descriptor Ring. This isrecoverable according tothe Link ‘occurs when the MK5025 has re- Level protocol. When ROR is set, ceived a correct frame from the an_ interrupt is generated if remote station. When RINT is set, INEA = 1. ROR is READ/CLEAR an interrupt is generated if INEA = ONLY and is set by MK5025 and 1. RINT is READ/CLEAR ONLY cleared by writing a "1" into the bit. and is set by MK5025 and cleared Writing a*0" has no effect. Itis also by writing a "1" into the bit. Writing cleared by Bus RESET or by is- a "0" has no effect. Its cleared by suing a STOP primitive. Bus RESET or by issuing a STOP Bit 04, TRANSMITTER UNDERRUN indi- primitive. TUR. cates that the Mic5026 has abarted Bit 00. Reserved. This bit is READ ONLY. a frame since data was late from memory. This condition is reached Control and Status Register 1 (CSR1) when the transmitter and transmit. RAP <3: 1>=1 ter FIFO both become empty while transmitting aframe. When TURis }} 1} }12 e929 92900 set, an interrupt is generated if rurul T ple lel or INEA = 1. TUR is READ/CLEAR ral Pyere! | am | ONLY and is set by the MK5025 ayy pap urn Joly iA pe | and cleared by writing a"1" into the al { ,|s| iB e | bit. Writing a “0” has no effect. Itis LLitise itt | alobigd 14/40 . _ i rn SS 352

— MM 7929237 OO45407 7T4 MMSGTH MK5025 | PROGRAMMING SPECIFICATIONS (Continued) 1 Bit 15, USER PRIMITIVE ERROR is set flags. Issuring a Start ‘ UERR. by the MK5025 when a primitive primitive with UPARM = + will issued by the user is in conflict put the MK5025 directly into with the current status of the link. the Information Transfer i UERR is READ/CLEAR ONLY phase, just as if it had and is set by MK5025. and received UA in response to cleared bywritig a *1" into the bit. SABM. Valid only in Writing a "0" in this bit has no STOPPED Mode, or effect. It is also cleared by Bus Transparent Mode. RESET. 2 Init Request - instructs MK5025 Bit14, USER PRIMITIVE AVAILABLE is to read the initialization block. UAV. set by the user after a primitive Valid only in STOPPED Mode has been placed in UPRIM. It is and Disconnected Phase. This cleared by the MK5028 after the should be performed prior to the primitive has been processed. start primitive after a bus reset This bit is also cleared by a Bus or powerup, RESET. 3 Trans - Instructs MK5025 to Bit <13: 12>, UPARM is written by the host in enter the Transparent phase UPARM. conjunction with the user of operation. Data frames are primitives in UPRIM. This user transmitted and received out parameter field provides for the of the descriptor rings but no information to the MK5025 protocol processing is done. concerning the corresponding Address and Control Fields user primitive, For connect and are not prepended to the reset primitives this field frames, but FCS processing determines what the MK5025 will works normally. If the PROM do with frames in the transmit bit is set in CSR2 then no descriptor ring that have been address filtering is performed previously sent but not ‘on received frames. aknowledged. If UPARM = 0, Transparent Mode may be these frames will be resent when exited only with a stop the new link is established. If primitive or by bus reset. UPARM = 1, these frames are their OWNA bits are cleared, N , ’ , link status into the STATUS releasing ownership back to the butter. Valid only if INIT host. For all other primitives this ner Wy field should be written with zeroes, primitive has previously been unless otherwise indicated. Issued. Bit<11:08>, USER PRIMITIVE is written by 5 Sel Test Request; Instructs UPRIM. the user to control the MK5025 per ) link procedures. The following Valid only in STOPPED values are valid: Mode, See page 31/40 for self-test procedure.

0 Stop - Instructs MK5025 to go

into. STPPED Modo. All ink Ses Oe atompt te activi is terminated and the establish a logical link with the outputs “a bev Al DMA remote site. Valid only in ‘ I} Disconnected Phase. activity ceases. 1 StartInstructs. MK5025 to exit Misiones raat nramed STOPPED Mode and enter a ee wit the seat it the Disconnected Phase. Vaid only. in. Disconnected Descriptor Rings are reset. Phase ehor receiving 4 Transmitter begins outputting Connect indlation primitive. —— SS es

MK5025 M@@ 792923? 0045408 630 MESGTH PROGRAMMING SPECIFICATIONS (continued)

8 Reset Request - Ifa logical link 13 TEST Response - Requests

has been established, instructs MK5025 to send a TEST re- MK5025 to attempt to reset the sponse to the remote site. Data current logical link with the in the XID/TEST transmit butter remote site (sends SABM/E). In is used for the data field. Valid Transparent Mode or Discon- only after receiving a TEST in- nected Phase, __ instructs dication primitive. MK5025 to start the T1 timer. 14 Disconnect Request - Requests

9 Reset Response - If a logical MK5025 to disconnect the cur-

link has been established, indi- rent logical link, Invalid in cates willingness to reset cur- STOPPED Mode. A DM re- rent logical link with remote site sponse with the F bit clear will (valid only after receiving a be sentif the linkis currently dis- Reset Indication primitive.) in connected. Transparent Mode or Discon- it 97, PROVIDER PRIMITIVE LOST is nected Phase, __ instructs pLosT. set by MK5025 when a provider MKS5028 to stop the T1 timer. primitive cannot be issued because

10 XID Request - Requests the PAV bit is still set from the pre-

MK5025 to send an XID com- vious provider primitive. PLOST is mando the remote site. Data in cleared when PAV is cleared and the XID/TEST Transmit bufteris by a Bus RESET. Writing to this bit used for the Data Field. Invalid has no effect. in STOPPED Mode. Bit 06, PROVIDER PRIMITIVE AVAIL- 11 XID Response - Requests PAV. ABLE is set by the MK5025 when MK5025 to send an XID te- a new provider primitive has been sponse to the remote site. Data placed in PPRIM. PPRIM is in the XID/TEST Transmit But- READ/CLEAR ONLY andis set by fer is used for the Data Field. the chip and cleared by writing a"1" Valid only after receiving an XID to the bit or by Bus RESET. Indication primitive. Bit <05:04>, PROVIDER PARAMETER pro- 12 TEST Request - Requests PPARM. vides additional information about MK5025 to send a TEST com- the reason for the receipt of a dis- mand to the remote site. Datain connect, reset or error indication the XID/TEST Transmit Buffer 7 primitive. This field is undefined for is used for the Data Field. In- other provider primitives. Parame- valid in STOPPED Mode. ters are as follows : PPARM Indication Confirmation Indication Indication oO Remotely UA or DM Remotely, Unsolicited Initiated F = 1Recvd Initiated OM/F = 0 Recvd 1 ‘SABM DISC Timer Recovery Timeout Timeout Timeout

2 FRMR Sent then DISC FRMR Sent then FRMR

or DM Received SABME Recvd Received T3 Timeout

3 T3 Timeout Unsolicited UA or F bit

16/40 . sep ge rong 354

: MB 7929237 OO45409 57? MBSGTH MK5025 PROGRAMMING SPECIFICATIONS (continued) ; Bit <03:00>, PROVIDER PRIMITIVE is written Data Field of the XID command : PPRIM. by MK5025 to inform the user of is located in the XID/TEST Re- 1 link control conditions. Valid Pro- ceive Buffer. | vider Primitives are as follows : 11 XID Confirmation - Indicates the : 2 InitConfirmation - Indicates that receipt of an XID response. The ‘ the initialization has completed. Data field of the XID response is ‘ 4 Error Indication - Indicates an located in the XID/TEST Re- error condition has occurred ceive Buffer. during the Information Transfer 12 TEST Indication - Indicates the phase of operation that requires receipt of a TEST command. instruction by the Host for re- The Data Field of the TEST covery. See PPARM for specific command is located in the error conditions. Either a Reset XID/TEST Receive buffer. Request or Disconnect Re- 13 TEST Confirmation - Indicates quest primitive should be is- the receipt of a TEST response. sued in UPAIM after receiving The Data field of the TEST re- an Error Indication primitive. sponse is located in the 5 Remote Busy Indication - Indi- XID/TEST Receive Buffer. cates change in Remote Busy 14 Disconnect Indication - Indi- status. PPARM = 0 indicates re- cates a request by the remote ceipt_ of RNR - Remote Busy. site to disconnect the current PPARM = 1 indicates Remote logical link or the refusal of a no longer busy - RR received. previous Connect or Reset Re- This primitive is only issued if quest. The chip is now in the RBSY = 1. RBSY (bit 15 of Disconnected Phase. IADR + 16) is set by the Host in 15 Disconnect Confirmation - Indi- the Init block. cates the completion of a pre-

6 Connect Indication - Indicates viously requested link discon

an attempt by the remote site to nection, establish a logical link. Appro- priate user responses are Con- Control and Status Register 2 (CSR2) nect Response or Disconnect pap <3: 15-2 Request.

7 Connect Confirmation - Indi- tirartr1egoegeooo0o000

cates the success of a previous Ss s2rose7esse sare Connect Request by the user. A 2 5 | y * ‘ logical link is now established. 3lslolelo ADR <23:18>

8 Reset Indication - Ifa logieal link 3lelm| le

has been established, indicates E an attempt by the remote siteto Bit <15: 14>, Reserved, must be written as ze- reset the current logicallink. Ap- Toes. propriate user responses are Reset Response or Disconnect Bit 13, Setting this bit disables the sending Request. In Transparent Mode, FRMRD. of FRMR frames (used for LAPD ap- or-Disconnected Phase, indi- plications) ; otherwise the MK5025 cates expiry of timer T1. behaves as specified for X.25. This 9 Reset Confirmation - Indicates bitis READ/WRITE. the success of aprevious Reset it 12, If this bit is set, the T3 timer is rec- Request by the user. The.cur- T293E, ‘onfigured to behave as specified rent logical link has now been for LAPD T203 timer ; otherwise it reset. behaves as specified for X.25. This 10 XID Indication - Indicates the re- bit is READ/WRITE. ceipt of an XID command. The SF SSIS ee

MK5025 mM 7929237 0045410 299 MBSGTH PROGRAMMING SPECIFICATIONS (continued) Bit 11, X.75 mode is enabled if this bit is Bit <15:10> Reserved, must be written as ze- X75E. set to 1 ; otherwise X.25 mode is Toes. enabled. This bitis READ/WRITE. — Bit <09: 08>, These bits define the FIFO water- Bit 10, Address filtering is disabled for FWM. marks. FIFO watermarks prevent PROM. transparent mode, if this bit is set. the MK5025 from performing DMA All uncorrupted incoming frames transfers to/from the data butters are placed in the Receive Descrip- until the FIFOs contain a minimum tor Ring. This bit is READ/WRITE. amount of data or space for data. Should be set only in Trans Mode. For receive data, data will only be ; transferred to the data buffers after Bit 09, UI frames are recognized only if the FIFO has at least N 16-bit UIE. this bit is set. If UIE = 0 all received words or an end of frame has been Ul frames will not be recognized. reached. Conversely, for transmit This bit is READ/WRITE. data, data will only be transferred F from the data buffers when the Bit 08, XID frames are recognized only if h XIDE. this bitis set. If XIDE = Oall received ea roe eochegaeat XID frames will not be recognized. one is of data. N isdefined as fol- This bit is READ/WRITE. FWM 0 N Bit <07: 00>, Thehigh order 8 bits of the address 14 tword IADR. of the first word (lowest address) in 10° 9 words the Initialization Block. IADR must 01 17 words be written by the Host prior to is- 00 25 words suing an INIT primitive. * Suggested Setting Control and Status Register 3 (CSR3) Bito7, This bit should be written as "0" for BAEN. standard operation as described in RAP <3: 1>=3 the timing diagrams in figures 7 and 8 of this manual. If this bit is set, the sha atoseresesere upper 4 adress its (A <2 20>) Tan an Be will be available at the time m ; isasserted, and are nevertristated. IADR < 15:00 > ° | This facilitates use in multiple bus systems to identify which bus is Phititttreritits being requested. BIT <15: 00>, Theloworder 16bitsoftheaddress _Bit 06, If this_bit is set, pin 15 becomes IADR. of the first word (lowest address) in BUSR. input BUSREL. If this bit is clear the Initialization Block. Must be pin 15 is either BMO or BYTE de- written by the Host prior to issuing pending on bit 00. For more infor- an INIT primitive. The Initialization mation see the description for pin Block must be on an even byte 15 earlier in this document. BUSR boundary. is READWRITE and cleared on Control and Status Register 4 (CRS4). CRS4 Leaehinegia allows redefinition of the bus master interface. Bit 05, This bit determines the byte orde- BSWPC. ring of all "non-data” DMA trans- RAP <3: 1>=4 fers. "Non-data” DMA. transfers refers to any DMA transters thatac- bidstioseressszio cess memory other than the data "DOOM OG buffers themselves. This includes ulsfu 1{sjele the Initialization Block, Descriptors, A PMle|s|wir :|wlolo and Status Buffer. It has no effect NIA) ETS op RININ on data DMA transfers. BSWPC allows MK5025 to operate with 18/40 {yy scs:THomson SY iccrornscrcrics 356

— @@ 7929237 0045411 125 MESGTH MK5025 memory organizations that have BCON is READWRITE and : bits <07 : 00> ar even addresses cleared by Bus RESET. with bits <15 : 08> at odd ad- BCON PIN16 PIN15 PIN17 dresses or vice versa. 0 _BMi_ BMO HOLD With BSWPC = 1: 1 BUSAKO BYTE BUSRQ Address Control and Status Register 5 (CSR5).CSRS fa- x0 cllitates control and monitoring of modem controls. XX1 [B_see 15] This memory organization is used RAP <3: 1>=5 with the LSI 11 andthe 8086 micro- +iar11e000000000 processors. 5432108876543210 With BYTE SWAP = 0: Ty aT Aa > ‘Address T Xx0 [Bae 15] RUTGUBBDDpSREAL wer Coe lhe! is memory organization is used with the 68000 and Z8000 micro- Bit <15:05>. Reserved, must be written as ze- processors. BSWP is Read/Write roes. and cleared by BUS RESET. Bit4, RTSICTS ENABLE is a Bit<04:03>, This field determines the RTSEN. READMWRITE bit used to BURST. maximum — number of — data configure pins 26 and 30. If this transfers performed each time bit is set pin 26 (DTR) becomes control of the host bus is obtained. RTS and _pin 30 (DSR) becomes BURST is READMWRITE and CTS. RTS is driven low cleared on Bus RESET. whenever the MKS5025 has data BURST <1 : > 8 bit Mode 16 bit Mode to transmit and_kept low during 00 2bytes 1 word transmission. RTS will be driven 10° 16 bytes — Bwords high after the closing flag of a 1 uniinited unlimited frame transmitted if either no * Suggested Setting other frames are in the FIFO or if the minimum frame spacing is Bit 02, This bit determines the byte orde- higher than 2 (see Mode BSWPD. ring of all data DMA transfers. Data Register). The MK5025 will not transfers are those to or from adata begin transmission_and TD will buffer. BSWPD has no effect on remain HIGH if CTS is high. Bit non-data transfers. The effect of RTSEN should not be set when BSWPD on data transfers is the operating in Internal Loopback same as that of BSWPC on non- mode. data transfers (see above). For it 3, DTR DIRECTION is a READ/ most applications, including most DTRD. WRITE bit usedto control the direc- 68000 based systems, this bit tion of the DTR pin. If OTRD = 0, should be set. the DTR pin becomes an input pin Bit o1, ALE CONTROL defines the asser- and the DTA bit reflects the current ACON. tive state of Pin 18 when MK5025 value of the pin ; if DTRD = 1, the is a Bus Master. ACON is DTR pin is an output pin controlled READ/WRITE and cleared by Bus by the DTR bit below. RESET. Bit2, DSR DIRECTION is a READ/ ACON Pin 18 Asserted DSRD. WRITE bit usedto control the direc- O ALE High tion of the DSR pin. If DSRD = 0,

1 AS Low the DSR pin becomes an input pin

Bit 00, BYTE CONTROL redefines the and the DSR bit reflects the current BCON. Byte Mask and Hold /O pins. value of the pin ; if DSRD = 1, the DSR pin is an output pin controlled by the DSR bit below. ep scs-tomson KO SY microc.scmewre 357

MK5025 M 7929237 OO4S41e Ob1 MSGTH Bit 1, DATA TERMINAL READY is used ten to this bit appears on the DSR DTR. to control or observe the DTR VO pin pin depending on the value of — tnitializati DTRD. It OTRD = 0, this bt — [nitlalization Block - becomes READONLY and always _MKS025 initialization includes the reading of the in- equals the current value of the DTR __ ialization block in memory to obtain the operating pin. If DTRD = 1, this bit becomes Parameters. READMRITE and any value writ- The Initialization Block is read by MK5025 when re- ten to this bit appears on the DTR ceiving an INIT primitive. During normal initialization pin. the INIT should be sent prior to sending a START Bito. DATASET READY is usedtocon- Primitive. The user may re-issue the INIT primitive DSR. trol or observe the DSR /Opinde- _alter a START, but received frames may be lost if pending on the value of DSRD. It Fe is not taken. An INIT cannot be issued while a DSRD—O, this bit becomes READ __ink is connected ; MK5025 will reject such an at- ONLY and always equals the cur- tempt. rent value of the DSR pin. if — Except for the Error Counters and XID/TEST De- DSRD = 1, this bit becomes scriptor OWNA bits, the MK5025 will not write into READ/WRITE and any value writ- the Initialization Block. Figure 6 : Initialization Block. LOCAL STATION ADDRESS IADR+02 REMOTE STATION ADDRESS IADR+04 Nt IADR +06 N2 + SCALER IADR+08 TP TIMER IADR+14 RLEN-RDRA <23:16> IADR+16 RORA <15:00> IADR+18 TLENTDRA <23:16> 1ADR+20 XID/TEST TRANSMIT IADR+24 DESCRIPTOR XID/TEST RECEIVE \\ADR+32 DESCRIPTOR ‘STATUS BUFFER ADDRESS IADR +40 IADR+44 HIGHER ADOR: Six ERROR COUNTERS thru — IADR+55 9 Sr 358

| MM 7929237 OOWSY13 TTS MMSGTH MK5025 "Mode Register. The Mode Register allows alter- Bit 10, Extended Control Force is useful ation of the MK5025's operating parameters. EXTCF. only in transparent mode oper- : ation. If set along with EXTC, the , LLLsEseegecoogoe receiver will assume the control oe eT eetelele field to be two octets long regard- J Kialalalxlelele less of the first two bits of the con- mescao> |T/Tlc|T|T/FIF/ S| teack trol field. See EXTC below. EVALELSVATS TS) S| <29> Bit 09, Extended Address Force is useful EXTAF. only in transparent mode oper- Bit <15:11>, Minimum Frame Spacing defines ation. If set along with EXTA, the MFS <4 :0>, the minimum number of flag se- receiver will assume the address quences transmitted between ad- field to be two octets long regard- jacent frames transmitted by the less of the first bit of the address. MK5025. This only affects frames See EXTA below. transmitted by the MK5025 and Bit 08, Address and control field extraction does not restrict the spacing of | DACE. are disabled when DACE is set. frames received by the MK5025. Address and control fields are When using RTS/CTS control this treated as normal data. DACE field defines the number of flags must be written as "0" for normal transmitted at the beginning of the operation in non-transparent frame after CTS is driven low mode. (minus one for the trailing flag). See git g7, Extended Control Field is enabled following table for encoding of this ExT ¢! when EXTC = 1. The control fields field of all S and | frames become two [__NumberofFiags | MFS<4:0>_~+| octets inlength, instead of one. The 7 1 numbering for | frames becomes 2 0 modulo 128, instead of modulo 8. 4 2 The control field of U frames re- 6 4 mains one octet in length. fa id Bito6, Extended address is enabled when 12 5 EXTA. EXTA = 1. The length of address 14 1" fields is determined by the first bit 16 22 of the address. If the first bit is set 18 2 then the address field is 1 octet 20 Fd long otherwise it is 2 octets. 24 7 Bit 05, Disable Receiver FCS. When 26 15 DRFCS. DRFCS =0, the receiver will extract 26 3 and check the FCS field at the end Ed 3 of each frame. When DRFCS = 1, 34 24 the receiver continues to extract 36 7 the last 16 or 32 bits of each frame, 38 3 depending on FCSS, but no check 40 8 is performed to determine whether a 3 the FCS is correct. 46 23 Bito4, Disable Transmitter FCS. When 48 14 DTFCS. DTFCS = 0, the transmitter will 60 29 generate and append the FCS to & ee each frame. When DTFCS = 1, the Se 10 FCS logic is disabled, and no FCS 38 20 is generated with transmitted 60 8 frames. 62 16 Gy Scs:tomson HO SY/ iacronsciowcs 359

MK5025 mm 7929237 0045414 934 MMSGTH Setting DTFCS =1 is usefulinloop- back. Combination of Silent and back testing for checking the ability Clockless loopbacks. Receive data of the receiver to detect an incor- is driven internally by transmit data, rect FCS. transmit and receive clocks are Bit 03, FCS Select. When FCSS = 1, 216 driven by SYSCLK divided by 8. TD FCss. bit FCS is selected otherwise a 32 bin is forced to all ones bit FCS is used. Station Addresses. The Local and Remote station . addresses may be either one or two octets accord- Bit <2: 00>, Loopback Control puts the ing to the EXTA control bit described in the MODE LBACK. MKS025 into one of several loop- register. If extended address mode is selected bit 0 back configurations. - should be set to a zero for adherence to LBACKO. Normal operation. No ADCCP/HDLC. If extended address mode is not loopback. selected, the command and response frame ad- LBACK4. Simple loopback. Re- dresses should be located in the lower order byte of ceive data and clock are driven in- __their respective fields. When operating in Loopback ternally by transmit data and clock. mode, Station addresses must be the same. LBACKS. Clockless loopback. Re- Timers. There are 5 independent counter-timers. ceive data is driven internally by The lower 8 bits of IADR + 08 are used as a scaler transmit data. Transmit and re- for T1, T3, and TP. The scaler is driven by a clock ceive clocks are driven bySYSCLK whichis 1/32 of SYSCLK. N1 is a 16 bit counter and divided by 8 is used to count the number of bytes in an Hrame. LBACKE. Silent loopback. Same —_N2is an 8 bit counter. as 3 simple poopback with TD pin The Host will write the period of N1, N2, T1, T3, and rorced to al ones. TP into the Initialization Block. LBACK7. Silent Clockless loop- into the Inalization Bloc 17171 1100800000000 64321098765 4321 0 TUT?ETITITe IADR + 06 COUNTER Ni IADR + 08 COUNTER N2 IADR + 10 IADR + 12 TIMER T3 IADR + 14 TIMER TP zo __ gj ses-swowso 360

Me 7929237 OO4S4IS 870 MSGTH MK5025 Ni. MAXIMUM FRAME LENGTH. This a frame in the transmit descriptor field must contain the two's com- ring is made until TP expires. At TP plement of one less than the maxi- expiration all transmit frames in the mum allowable frame length, in transmit descriptor ring will be sent. ; bytes. Any frame received that ex- This field must contain the two's : ceeds this count will be discarded. complement of the period of timer N2. MAXIMUM RETRANSMISSION TP. COUNT. This fieldmustcontainthe Receive Descriptor Ring Pointer two's complement of one less than tiartatoooeve000. the maximum number of retrans- S432; o9e76 64 3240 missions that will be made follow- 5| ing the expiration of T1. hon + 98 Blo 0 0] — RoRAqza16> SCALER. TIMER PRESCALER. Timers Tt, Y =a 73, and TP are scaled by this num- ber. The prescaler incremented on + 8 oma 15.00% ° once every 32 system clock pulses. I! n When itreaches zero the timers are , incremented and the prescaler is Bit 15. Reserved, must be written as a reset. This field is interpreted as the zero. two's complement of the prescaler ‘Bit <14: 125, RECEIVE RING LENGTH is the period. Note : a prescale value of | RLEN. number of entries in the Receive one gives the smallest amount of Ring expressed as a power of two. same twes he latest (gees [-—FLEN [Number of Entries | ses), Zero gives the largest (8224 clock pulses). fy NA T. RETRANSMISSION TIMER. Link 5 : control frames will be retransmitted 3 3 upon the expiration of the Tt timer : i if the appropriate response is not 5 32 received, These frames will be re- Ps ee transmitted up to N2 (see above) 7 128 times, at which time the link will be - disconnected or reset by MK5025 Bi 2 Setting this bit enables the gener- " ‘i ation of the Remote Busy Indica- according to the X.25 protocol. This tion primitive (PPRIM = 5) field must contain the two's com- pr , i" whenever there is a change in the plement of the period of timer T1. Parrott Bucy statu The scaled (see SCALER) value of y Ti should be made large enough Bit <10: 08>. Reserved, must be written as ze- to allow the remote station to re- oes. ceive the contro!frameandsendits — Bit<07:00>/ RECEIVE DESCRIPTOR RING response. <15:00>, ADDRESS is the base address of 73. LINK IDLE TIMER. The link idle timer RDRA. (lowest address) of the Receive determines the amount of link idle Descriptor Ring. The Receive Ring time necessary to consider the link must be aligned on a word bound- disconnected. This field must contain ary. the two's complement of the period Transmit Descriptor Ring Pointer of timer T3. T3 is disabled (but not 7203) if CSRS RTSEN = 1 or if the Poaprosesesasery MKB5025 is in transparent mode. tery : TP. TRANSMIT POLLING TIMER. won. 20 o| nex Jo! two rorAczase> This scaled timer determines the ; fame pols Uness TOMB. eee ie Inless ID (see aor + <1500> CSRO) is set or a frame is received 9“ *” | Tomei ae ° ‘on the link, no attempt to transmit LLititttiot 1 361

MK5025 @™ 7929237 OO4S4Ib 707 MESGTH Bit 15. Reserved, must be written as a Status Buffer Address Bit <14: 12>, TRANSIT RING LENGTH is the fyi TLEN. number of entires in the Transmit Ring expressed as a power oftwo. “on # fej i oe a] aanczowe Bit 11. Reserved, must be written as a t bE bE Het zero. WADA + 42 SBA< 1500 > ° Bit <10: 08>, TRANSMIT WINDOW is the a TWD. window size of the Transmitter as . shown in the following table. Bit <15: 08>. Reserved, must be written as ze- TWD is the maximum number of oes, 1 frames which may be Bit<07:00>/ STATUS BUFFER ADDRESS transmitted without. = an. <15:00>, —_ points to. a7 word buffer into which acknowledgement. TWD is not SBA. link status information is placed allowed to be greater than 127. upon the issuance of the STAT primitive by the HOST. The con- | _TLEN __|_—_Mumber of Entries tents of the Status Buffer are de- 0 1 scribed later in this document. The 1 2 Status Buffer must begin on a word 2 4 boundary. 3 8 Error Counters. Six locations in the initialization é 8 butfer are reserved for use as error counters which = oa the MK5025 will increment. These are intended for 5 18 use of the Host CPU for statistical analysis. The MK5025 will only increment the counters ; itis up to [two] Window Sie +] ~=«CM user to clear an preset these counters. The error counters are : | —arre=o [erTe=7] ewonv ADDRESS EAROR COUNTER o NA 1 IADR + 44 Bad frames received i 1 3 - Bad FCS

3 Q A - Non-Octet Aligned

1 4 31 IADR + 46 Number of FRMR 5 5 63 frames received 6 6 127 IADR + 48 Number of T1 timeouts 7 7 127 IADR + 50 Number of REJ Bit <07 :00>/ TRANSMIT DESCRIPTOR RING frames received <15:00>, ADDRESS is the base address of IADR + 52 Number of REJ TDRA. (lowest address) of the Transmit frames transmitted Descriptor Ring. The Transmit 1ADR + 54 Frames shorter than Ring must be aligned on a word minimum length received boundary. ; Receive and Transmit Descriptor Rings. Each XID/TEST Descriptors. The XID/TEST Descriptors descriptor ring in memory is a 4 word entry. The fol contain pointers to the buffers used to receive and [owing is the format of the receive and transmit de- transmit XID and TEST frames, as well as the buff- _scriptors. er lengths. The exact format of these descriptors can - be seen below under Receive and Transmit Mess- Receive Message Descriptor 0 (RMDO) age Descriptor Entry descriptions. They reused == 1 1 1 1110000000000 the same as other descriptors except thatnodata «$4 3210887654321 0 chaining is allowed. sfeTuye[aya rrrrr tlelr alate ala _ cl jtitit (24/40 -THOMSO! a br SSHOmson — 362

M@@ 7929237 OO4S41L7 b43 MESGTH MK5025 Bit 15, When this bit is a zero either the of the Initialization Block. Other- OWNA. HOST or the I/O ACCELERATION wise it matched the value in the PROCESSOR owns this descrip- Remote Address field. tor. When this bit is a one the git og Valid only for Ul, XID and TEST MIKS025 owns this descriptor. The PF, frames. RPF equals the state of the chip clears the OWNA bit after fill Por F bit for the reevd frame. ing the buff inted to by the de- soriptor entry providedithe received Bit <07: 00>, The High Order 8 address bits of frame had a good FCS, N(y, and RBADR. the buffer pointed to by this de- Nis), The Host sets the OWNA bit scriptor. This field is written by the after emptying the buffer. Once the Host and unchanged by MK5025. MK5025, Host, or I/O acceleration Receive Message Descriptor 1 (RMD1) processor has relinquishedowner- yy 1110000000000 ship of a buffer, itmaynotchange 5 43 2109876549210 any field in the four words that com- TTT prise the descriptor entry. Bit 14, This bit determines whether the RBADR<15:00> ° OWNB. HOST or the SLAVE PROCES- SOR owns the buffer when OWNA isa zero. The MK5025 never uses Bit <15: 00>, The low order 16address bits of the this bit. This bit is provided to faci. RBADR. receive buffer pointed to by this de- tate use of an /O acceleration pro- seriptor. RBADR is written by the cessor. Host CPU and unchanged by Bit 13, Start of Long Frame indicates that MKS5026, The receive buffers must SLF. this is the first buffer used by be word aligned. MK5025 forthis frame. tisusedfor Receive Message Descriptor 2 (RMD2) data chaining butters. SLFissetby 444411 0000000000 the Ch oF , s4a2109876543210 te :A "Long Frame"isanyframe | TT TT which needs data chaining. Usually this will be an I frame, but it could BENT <15:00> ° also be a Ul or FRMR frame. Bit 12, End of Long Frame indicates that ELF. this the last bufferusedby MK5025 Bit <15: 00>, Buffer Byte Count is the length of for this frame. It is used for data. BCNT. the buffer pointed to by this de- chaining buffers. If both SLF and scriptor expressed in two's comple- ELF were set the frame would fit ment. This field is written to by the into one butfer and no data chain- Host and unchanged by MK5025. ing would be required. ELF is set Buffer size must be even. by the MK5025. Receive Message Descriptor 3 (RMD3) Bit 11, Ul Frame Received indicates that sk gg a oo UR. a U! frame has been received and a0 is stored in this buffer. se ye Bit 10, FRMR Received indicates that the FRMRR. Hield of a FRMR is stored in the MONT <15:00> buffer referenced by this Message Descriptor. Bit 09, Valid only forframes received while _Bit<15: 00>, Message Byte Count is the length, RADR. in Transparent Mode with address MCNT. inbytes, of the contents of the buft- filtering enabled. RADR indicates er expressed in two’s complement. which of the 2 programmable ad- it ELF = 0, MCNT will equal the dresses the frame matched. It set, two's complement of BCNT since the received address field matched the MK5025 will fill a butter before the value in the Local Address field chaining to the next descriptor. [jy s6s:THomson HO 4 tacnoascvscecs 363

MK5025 @® 79292397 OO4S4LS S&T MBSGTH Transmit Message Descriptor 0 (TMD0) frame. This bit must also be set for ° anything transmitted while the Saaz tossresa sate MK5025 is in Transparent Mode sfe|t{t] [x T Bit 10, Transmit Interrupt Disable. If this bit byejuliy oe TINTD is set, no transmit interrupt is FlF|t " oy) TBADR<23:16> generated when ownership of this ol | | f descriptor is released back to the + host. This allows users to limit the Bit 15, When this bit is a zero either the number of transmit interrupts. OWNA. HOST or the SLAVE PROCES- Bitog Reserved, must be written as ze- SOR owns this descriptor. When toes this bit is a one the MK5025 owns ; this descriptor. The hostshould set. Bit, Transmit P/F bit instructs the the OWNA bit after filling the buffer XPF. MKS5025 to send the corresponding pointed to by the deecrptor entry. frame with a particular value for the The MK5025 releases the descrip. PYF bit. This bit should equal the tor after transmitting the buffer and desired value of the transmitted receiving the proper acknow- P/F bit. This bit is valid only for Ul, ledgement from the remote station. XID and TEST frames and should Atter the MK5025, Host, or I/O ac- be written with zero otherwise. celeration processor has relin- Bit<07:00>, The High Order 8 address bits of quished ownership of a buffer, it © TBADR. the buffer pointed to by this de- may not change any field in the four scriptor. This field is written by the words that comprise the descriptor Host and unchanged by MK5025. entry. Transmit Message Descriptor 1 (TMD1) Bit 14, This bit determines whether the OWNB. HOSTorthe VOACCELERATION {3331 333 3 eee 3 kG PROCESSOR owns the butfer when OWNA is a zero. The MK5025 never uses thisbit. This bit TBADA <15:00> ° is provided to facilitate use of an/O acceleration processor. ttt t Bit 13, Start of Long Frame indicates that Bit <15: 00>, The Low Order 16 address bits of SLF. this is the first buffer used by | TBADR. the buffer pointed to by this de- MK5025 for this frame. itis used for scriptor. TBADR is written by the data chaining buffers. SLF is set by Host and unchanged by MK5025. the Host. The least significant bit is zero Note : "Long Frame" is any frame since the descriptor must be word which needs data chaining. Usually aligned. this will be an | frame, but it could Transmit Message Descriptor 2 (TMD2} also be a UI frame or others. 9 ptor 2 (TMD2) Bit 12,ELF, End of Long Frame indicates that 2333} 3 oe oe ee 8 this the last butfer used by MK5025 for this frame. It is used for data chaining buffers. If both SLF and BONT<15:00> ° ELF were set the frame would fit into one buffer and no data chain- ing would be required. ELF is set Bit <15: 00>, Buffer Byte Count is the usable ¥ 7 BCNT. length, in bytes, of the buffer Bit 11, Transmit a UI frame indicates that a pointed to by this descriptor in two's Tul. Ulframeis to be transmitted from the complement. This field is not used transmit buffer instead of a normal | by the MK5025, gomo e scs-tHomson SY iacroziscrnemcs 364

| Mm 2929237 OO4S4R9 4ib MMESGTH —___ M5025 ‘Transmit Message Descriptor 3 (TMD3) Bit <15 : 00>, Message byte count is the length, +tt1tt1eee0000000 MCNT. in bytes, of the contents of the butt- 5439210987654 3210 er associated with this descriptor TYTITTTTTrTrt | expressed as a two's complement. MONT <15:00> | : Jiititiits Status Buffer ri4tt10000000000 s432109876543210 Tr TTI ‘SBA + 00 wo Ms) SBA + 02 Loca! Stato Remote State wv om fm ws | arn SeA + 08 CURAD <15:00> SBA +10 Unuses ‘cuRXD <20:16 > SBA +12 URXD <15:00> Littitittittit vn). Current value of the Receive Count 2 REJ sent state Variable. 0 < V(r) < 7 for non-ex- 3 nee bri state cted stat tend 1 0< VN) < 1274 jormal Disconnected state tended control: 0 < Vt) $ 127 for 5 SABMIE sent for link . , connection Vis). Current value of the Transmit 6 ERMA sont state Count Variable. 0 <= V(s) = 7 for 7 SABMIE sent for link reset non-extended control ; 0 = V(s) 8 Error Indication issued = 127 for extended control. Remote State. Current state of remote station. C ¥ local station. Value Description ‘oral Siete Value Description Q Normal Data Transter state

0 Normal Data Transfer state 1 Remote Busy state

1 Local Busy state

MK5025 Mm 7929237 OO45420 138 MBSGTH Phase. Current phase of operation descriptor for the next transmit Value Description buffer to be transmitted. =1 Stopped Mode ,

0 Iteration Transfer phase Data Link Services

4 Disconnected phase ‘The MK5025 is consistent with the ISO Data Link

2 Resetting ph: aes

3 Transparent Data Transfer Service Definition in providing services to the HOST. phase The following section is a brief description of this in- VA). Current valueof Transmit Acknowl ‘terface. ‘edge Count. Thisfield containsthe _Alll link oriented services are provided through the value of the N(r) ofthe mostrecent- —_ exchange of Data Link Service Primitives. These lyreceived Sor frame. The modu- _ primitives provide services to the HOST. Each primi- lo difference between V(A) and tive falls into one of the following categories : V(s) determines the number of out- 1. Link Establishment (Connection) standing I frames that have not 2. Link Resetting been acknowledged by the remote 3. Link Disconnection Station. 4, Data Transfer CURRD Current Receive Descriptor. This A primitive is also one of the following types : <23:00>. pointer indicates the positionofthe FY "Request 9 lype descriptor for the next receive buff- 2) Response erto be filled. 3. Indication CURRXD Current Transmit Descriptor. This 4. Confirmation <23:00>. pointer indicates the position of the. Figure 7 : Examples of Confirmed Data Link Services. wea station _____neware stanon HIGHER LAYER in DATA LK Laver! [7 oar unc caver [ “Wicnen waver | | | | i | ] Sete mouse | ' ] | ; | | peyton | | voy nesPonse | | <e I |_west ! ee ee | connect COMER — ] 1 | | | | | ° i excomee! poe | | TOMES neovesr 1 | | ] eet 1 | one 1 | oo! | ee ! ! \\ —“# au [i oe 366

Me 7929237? 0045421 074 MMSGTH MK5025 Requests and Responses are issued by the HOST 2. Setup Initialization Block and Descriptor Rings and Indications and Confirmations are issued by the and load the address of the initialization block MK5025. in CSR's 2 and 3. ‘A Request will be issued by the HOST when a ser- 3. Issue the INIT primitive through CSR1 instruct- vice is required. An Indication will be issued by the ing the MK5025 to read the initialization block MK5025 when the remote system is attempting to information. change the data link status. A Response is issued 4. Wait for INIT Confirmation primitive from the by the HOST when receiving an indication for acon- MKS5025. firmed service. A confirmation is issued by the 5. Issue the START Primitive through CSR1 to 3 MK5025 when the remote system has responded to enable the MK5025 for link operation. a previously requested service. 6. Enable interrupts in CSRO if desired. In the MK5025, primitives are exchanged two ways: Active Link Setup. The following procedures through the CSR1 and through the OWN bits in the Should be followed to actively establish a link : descriptor rings. Connection, disconnection, and 1. Issue the Connect Request primitive through link reset primitives are exchanged through CSR1 CSR1. The MK5025 will attempt to establish a Data transfer primitives are handled transparently logical link. , by the OWN bit handshaking in the Descriptor 2. wae ( a Connect Confirm primitive from the Rings - «iv ie voceh Nine additional primitives have been included in the 3. Ia Connect Confirm primitive is received, @ M5025 to handle services not mentioned in the 4. Ifa Disconnect Indication primitive is received, ISO Data Link Service detition. These primitives the MK5025 has been unable to establish a i link. Th ill be in the PPARM fic if STOP - Disables the MK5025 from link oper- 16m 7he reason willbe in the ‘eld ol ation. MK5025 transmits 1's. : INIT - Instructs the MK5026 to read the initializ- Passive Link Setup. The following procedures ation block. should be followed to passively establish a link : START - Enables the MK5025 for link oper- 1. Issue a Disconnect Request primitive. A DM ation. MK5025 starts sending flags. frame with F bit clear will be sent to the remote TRANS - Enables the MK5025 for transparent station requesting link setup. This step is op- operation. MK5025 starts sending flags. tional. . STAT - instructs the MK5025 to write chip 2. Wait for a Connect Indication primitive from the status in the status buffer. MKS5025. “or oe STEST - Instructs the MK5025 to perform an 3. If a Connect Indication primitive is received, internal self test. issue a Connect Response primitive to indi- ERROR - Indicates the occurence of a link cate willingness to establish the link. The link error requiring higher level action. is now established. ae XID - Confirmed exchange of identification (op- 4. If no Connect Indication primitive is received, tional). the remote site is not trying to actively setup a TEST - Provides a full remote loopback test fa- link. cility (optional). Refusing Link Setup. The following procedure For examples of the use of primitives, see the sec- Should be followed when refusing Ink estab tion on detailed it ed low. Ishment : ion Programming procedures below. 4. A Connect Indication will be received indicat- Detailed Programming Procedures ing a request by the remote station to estab- Initialization. The following procedures should be lish a link followed to initialize the MK5025 : 2. Issue a Disconnect Request to refuse the link 1. Setup bus control information in CSR4. establishment request. a GS-THOMSON 29140 367

MK5025 @ 7929237 OO45422 TOO MMSGTH Sending Data. The following procedure should be 2. it able to reset, issue a reset response to indi- followed to send a data frame : cate willingness to reset the link. 1. Wait for OWNA bit of current transmit descrip- 3. If unable to reset, issue a Disconnect Request tor to be cleared, if not already. to disconnect the link 2. Fill buffer associated with current transmit de- scriptor with data to be sent, or set descriptor Receiving FRMR Frame. The following procedure buffer address to any already filled buffer. should be followed when receiving a FRMR : 3. Repeat steps 1 and 2 for next buffer if chain- «1 An Error Indication will be received from ingis necessary, setting SL ELF and MCNT MK8025 indicating an error condition. PPARM appropriately. willindicate a FRMR frame has been received. 4, Set the OWNA bit for each descriptor used. The Iield of the FRMR has been placed inthe 5. Goon to next descriptor, these OWNA bits will next Receive Descriptor. be cleared when the data has been sucess- 2.1 able to reset, issue a Reset Request to fully sent and acknowledged. In Transparent MK5025 and wait for either a Reset Indication Mode, OWNA bits are cleared immediately or a Disconnect indication as described above after frame transmission. for Link Reset. a 3. Itunable to reset, issue a Disconnect Request Receiving Data. The following procedure shouldbe to disconnect the current link. Link setup pro- followed when receiving a data frame : Cedures should now be performedto re-estab. 1. Make sure that the OWNA bit of the current re- isha link ceive descriptor is clear 2. Read dataout of buffer associated with current. Exchanging Identification. The following proce- receive descriptor. dure should be followed to exchange identification 3. Set the OWNA bit of current descriptor. with the remote : 4.1F ELF bit of current descriptor is clear, go on 1. XIDE in CSRS must be set prior to any identi- to next descriptor and repeat above steps ap- fication exchange. pending data from each buffer until a descrip- 2.Place identification information in the tor with the ELF bit set is reached. XID/TEST Transmit Butfer. Link Disconnection. The following procedure 3. Issue an XID Request primitive, should be followed to disconnect an established 4-{f an XID Confirm primitive ie received, the fink: identcaion exchange has been performed 1. Issue the Disconnect Request primitive to the and the remote response is located in the MK5025. The MK5025 will disconnect the link XID/TEST receive buffer. ; 2. A Disconnect Confirmation will be issued after 5.11 a Disconnect Indication is received, the successful disconnection. identification exchange was unsuccessful. Link Reset. The following procedure should be fol Receiving an Identification Request. The follow- lowed to reset an established link : ing procedure should be performed when receiving t.Issue_a Reset Request primitive to the a request for identification : MK5025, 1.An XID Indication primitive will be received 2. Wait for a Reset Confirm primitive from the from the MK5025 to indicate the request for MK5025. identification. The remote identification infor- 3. Ifa Reset Confirm primitive is received, the link mation will be locatedin the XID/TEST receive has been reset. buffer. 4.If a Disconnect Indication is received, the 2. To respond, place identification information in MK5025 was unable to reset and has discon- the XID/TEST send buffer and issue an XID nected. The reason for failure is in the PPARM Response primitive. field of CSR1. Link connection procedures 3. To refuse, issue a Disconnect Request primi- must now be performed to re-establish the link. tive. Receiving Link Reset. The following procedure Note : An XID Indication will only be issued ifthe shouldbe folowed when receiving a request for ink XIDE bit in CSRB has been set. Otherwise, all reset : identification requests will automatically be re- 1.A Reset Indication will be received from the fused and XID frames will not be recognized. M5025 indicating the remote station has re- quested a link resetting. 30/40 ' — fy S88-THOMSON 368

— MM 7929237 0045423 947 MSGTH MK5025 Disabling the MK5025. The following procedure 5. After the PAV bit is set, read CSR1. The suc- should be followed to disable the MK5025 : cess oF failure of the test is indicated in the | 1. Issue the STOP primitive. This will disable the PPRIM and PPARM fields as follows : MK5025 from receiving or transmitting. The PPARM PPRIM RESULT TD pin will be held high while the MK5025 is. 0 0 Passed self test in stopped mode. The STOP bit in CSRO will 1 1 Failed the reset test of bbe set and interrupts disabled. Ifa link is cur- the seff test : rently established, data may be lost. 1 2 Failed self test in the . Re-enabling the MK5025. The same procedure micro controller RAM 1 should be followed for re-enabling the MK5025 as 1 3 Failed self test in {was used to initialize upon power-up. If the Initializ- the ALU ation Block and the hardware configuration have not 1 4 Heres set test in hi 1and2 changed then steps 1 and 2 may be omitted 1 5 hetimers ctimthe MK5025 Internal Self Test. The MK5025 contains tranemitter and/or an easy to use internal built-in self test designed to recelver test, with a high fault coverage, all of the major 1 6 Failed self test in the blocks of the device except for the DMA controller. CSRs and/or bus master It is suggested that a loopback test also be per- Otherwise failed device. formed to more completely test the DMA controller. 6. If the PAV bit is not set within 75 msec The following procedure should be followed to ex- (SYSCLK = 10MHz), the MK5025 is unable to ecute intemal self test respond to the Self Test Request and will not +. Reset the device using the RESET pin. complete it successtully. 2. Set bit 04 of CSR4. . 7 If the self test passes, then it may be immediately 5. teeue a Self Test Request request through —_re.executed by clearing the PAV bit in CSR1 and : then proceding from step 3, otherwise re-execu- 4. Poll CSA1, waiting for the PAV bitin CSR to fon should proceed rom step 1. be set by the MK5025: MK5025 Software Identification. The MK502X family of devices provide a means of identifing the device type by using the following procedure. After completing steps 1 and 2 of above listed procedure for Self Test, issue the Self Test Re- guest primitve (UPRIM ~ 5) with UPARM = 3. he chip will then return a PPRIM of 5 (7 for the MK5027, 9 for the MK5029, etc.) to identify the device type. . 31/40

9 SSS TT OS

MKS025 Os MM 7929237 0045424 883 MMSGTH ELECTRICAL SPECIFICATION ABSOLUTE MAXIMUM RATINGS [Symbol Parameter | value | uni | [5 | Tota Doves over Osspaten | os | w] Note : Siresses above those listed under “Absolute Maximum Ratings" may cause pormanant damago to tho device. This ie a strese rating only and functional operation ofthe device al these or any other condition above thase ingicated inthe operational sections of this specification isnot implied. Exposure to absolute maximum rating Conditions for extended periods may aifect device reliability, DC CHARACTERISTICS (T, = 0°C to 70°C, Voc = + 5V + 5%, unless otherwise specified) [Symbol[ Conditions mins | typ. | Max. [unit] ve) = 05 tee fe A Ce: [pes |v Wo @ baa Oana - ee ee | @Vn= 0-4 t0 Veo _ — [fio Ta] co _| Tsor = 100ns = [so [ [ma] CAPACITANCE (Frequency = 1MHz) [ Symbol | Conditions Min. | Max. | Unit | [Gt [Gown [to A AC TIMING SPECIFICATIONS (Tx = 0°C to 70°C, Vee = + SV + 5%, unless otherwise specified). rr] stone [mont | __rarametw condone | ee | ME | S| [+ [syscux] Toor [svscuK period TT t00 | 2000 | [2 [sysctk| Ts | S¥SCLK iow time ee ee a jo erect Teas SYSOLK righ time rs ee | Rise time of SYSCLK re ee

5 SS0iR Tae Fall time of SYSCLK | o {| ya |

TOK | Trer | TOK period [| Texk Ls-|-—-—] [e [ook | tren | Tecknighme | | |] | [2 [TeLK | Trea | Rise time of TCLK a 8 [10[7otK | Tice | Fall time of TOLK oc [pe ft | TD data propagation delay after the falling pass P of] | edge of TCLK [fr | te | TD data hold time after the falling edge of ee ee | TCLK - 32/40, Sg gg ogy

@@ 7929237 GO4SkesS 717 MESGTH MK5025 AC TIMING SPECIFICATIONS (T, = 0°C to 70°C, Vee = + 5V + 5%, unless otherwise specified) Test Typ. Conditions ns. [ie] ROR | Tor | RORPoea SSCSC~sSC‘CSC*iL O'] Cd 15|_RCLK Tacu__| ACLK Low Time _ [18|RGIK | Tren | Rise Tine of GK [fs Fal Tine of AGKK [fs] | [48RD RO Data Rise Time a ee [19[ RO | Thor _| RD Data Fatt Time a [20] RD | Taow _| RD Hold Time after Rising Edge of RCLK [|

24 Taos | RD setup Time Prior to Rising Edge of 30

22| A/ADL Toorr Bus Master Driver Disable after Rising 50 Edge of HOLD j ADAL | Toon | Bus Master Driver Enable after Falling [Tscr = 100nS 200 Edge of HLDA | 24] HLDA Tua | Delay to Falling Edge of HLDA from } Falling Edge of HOLD (bus master) | RESET | Taw | ReseTPusewin || go | [26] DAL | Terese | Roedwito, Adresstaia Gye Tine [Tuer = 10008] ooo | [|_|

27 Tras Address Setup Time to Falling Edge of

A A Tyan | Address Hold Time after the Rising Edge of DAS. | DAL Tas _ | Address Setup Time to the Falling Edge of 75 ALE DAL Tan Address Hold Time after the Falling Edge of ALE DAL Tross Data Setup Time to the Rising Edge of DAS (bus maaster read) 32] DAL Troms | Data Hold Time after the Rising Edge of DAS (bus master read) 33] DAL Tooas Data Setup Time to the Falling Edge of DAS (bus masterwrite) DAL | Twos | Data Setup Time to the Rising Edge of i DAS (bus master write) DAL | TWDH | Data Hold Time after the Rising Edge ot | 35 DAS (bus mater write) DAL TSRDH | Data Hold Time after the Rising Edge of | Tscr = 100nS} DAS (bus slave read) 37] DAL | TSWDH | Data Hold Time after the Rising Edge of DAS (bus slave write) 38] DAL TSWDS | Data Setup Time to the Falling Edge of DAS (bus siave write) [ge] Ale | TALEW [ALE wit nigh ee OF stcs-tomson HO SY imcnoessmomes 371

MK5025 mm 7929237 OO4S42b bSb MMSGTH AC TIMING SPECIFICATIONS (T, = 0°C to 70°C, Vec = + 5V + 5%, unless otherwise specified). ° Test Min. | Typ. Ne. [ signa | ‘Symbol Parameter Conditions ne ne ALE Toate | Delay from rising edge of DAS to the rising 70 edge of ALE [2t| BAS | Toa [OAS wimiow |_| a0) |

42 DAS Taoas Delay from the falling edge of ALE to the 80 |

_ falling edge of DAS . { _ 43! DAS Taps} Delay from the rising edge of DALO to the 35 falling edge of DAS (Bus master read)

44 DAS Troys Delay trom the failing edge of READY to Tanyo = 300nS 200

the rising edge of DAS Tscr = 100nS 45, DALI Troe | Delay from the rising edge of DALO to the 70 | | falling edge of DALI (Bus master read) | 46 | BAL Tris | DALI setup time to the rising edge of DAS. 150 L_! (Bus master read) 1a7] DAU Tan | DALI hold time after the rising edge of | DAS (Bus master read) DALI Tror | Delay from the rising edge of DALI to the 70 falling edge of DALO (Bus master read) 49| DALO Tos | DALO setup time to the falling edge of | ALE (Bus master read) 50 | DALO Tron | DALO hold time after the falling edge of 35 { ALE (Bus master read) DALO | Twos | Delay from rising edge of DAS to the rising edge of DALO (bus master write) cs Tesh | CS hold time after the rising edge of DAS (bus slave) 53] CS Tess __| CS setup time to the falling edge of DAS. (bus slave)

54 Tsay | ADR hold time after the rising edge of

DAS (bus slave) Tsag | ADR setup time to the falling edge of DAS (bus slave) READY | Taavo | Delay from the falling edge of ALE to the | Tscr = 100nS 150 | falling edge of READY to insure a minimum bus cycle (600nS) 57| READY | Tseos | Data setup time to the falling edge of 75 READY (bus slave read) READY | Trom | READY hold time after the rising edge of DAS (bus master) READY | Tsayy | READY hold time after the rising edge of | Tscr = 100nS 35 DAS (bus slave) READ Tea | HEAD hold time after the rising edge of DAS (bus slave) _ READ | Tors | READ setup time to the falling edge of DAS (bus slave) READY | Troyo | Delay from falling edge of DAS to faling | Tscr = 100nS 200 ‘edge of READY (bus slave read) 34i40 L577 SSs:THomson _ ‘YY imicnoascmomes 372

MK5025 M@@ 7929237 0045428 425 MSGTH Figure 10 : Bus Master Timing Diagram (Read) Siw awe ae eae t i ' i 1 fl | oas HOLD 23. 22 LDA iN nies pf es pas ——— 4 oALO _ Po 8M0.1 ‘Note : The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device returns READY. 374

M@® 7929237 0045429 365 MSGTH MK5025 Figure 11 : Bus Master Timing Diagram (Write). 0 02000000 $0000 ee Fa FOG — ; aoa N ae oe, ® “ s EADY OUI |e ie wo 3s ALOIS, v) ‘ADORESS My, __ Data ‘our hb — fo. ALO oar | ReaD amon Note : The Bus Master cycle time wil increase from a minimum of 600ns in 100ns steps untl the slave device returns READY.

MK5025 W@® 792923? 0045430 087 BESGTH Figure 12: MK5025 Bus Slave Timing Diagram (Read). . . as - : ae 1117 i ons i ‘READY | | “ 376

— @@ 7929237 0045431 TL3 MSGTH MK5025 Figure 13: MK5025 Bus Slave Timing Diagram (Write). . . ca4 : 2 OS ReaD je oo W 377

MK5025 M™ 7929237 0045432 IST MESGTH ORDER CODES [renee [GO| suse rel SE [ | [ mKsozsp-1072 | x.25 | 7Mevs | tomHz | orcto70°c | cpipaa6oo.mi | LKso2sa-1oo2 [| 7wis [tome | orcto70"e | Pucca Note: CDIP = Ceramic Multlayer DIP, PLCC = Plastic leaded Chip carrier, PDIP = Plastic DIP MK | 5025 N io_| 02 Test, Marking, Rev Speed grade MK502510/02 Package Type i P: CERAMICS IDEBRAZE Q: PLCC Devce family and Po number identification 5025 = X, 25 1 _ -. SGS-THOMSON prefix MK5021Q10/0 Serial COM Controller, Frame Relay MK5027P 10/0 CCS#7 MK5027Q10/0 CCS#7

00 SGS-THOMSON __