MK48Z09B-10

MK48Z08 STMICROELECTRONICS | Alldatasheet

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S2— D MM 7929237 0038370 656 MBSGTH T-46-23-12 STA 7] SGS-THOMSON MK48Z08,18 ® MICROELECTRONICS MK48Z09,19 SG S-THOMSON CMOS 8K x 8 ZEROPOWER SRAM ® INTEGRATED ULTRA LOW POWER SRAM, - FOWER-FAIL CONTROL CIRCUIT AND BAT: aN Y. _ ® UNLIMITED WRITE-CYCLES. = READ-CYCLE TIME EQUALS WRITE-CYCLE t TIME. = PREDICTED WORST CASE BATTERY LIFE OF 28 \\ 11 YEARS @ 70°C. = PIN AND FUNCTION COMPATIBLE WITH 1 JEDEC STANDARD 8K X 8 SRAMS. = AUTOMATIC POWER-FAIL CHIP DESE- PHDIP26 WITH BATTERY TOP HAT (B) LECTMVRITE PROTECTION. . *® CHOICE OF TWO WRITE PROTECT VOLT- AGES : Figure 1. Pin Connections —MK48Z08/09 - 4.50V< Vprp < 4.75V —MK48Z18/19 - 4.20V< Vprp < 4.50V neg:® 260 Vec DESCRIPTION “as eh nc The MK48Z08/18/09/19 ZEROPOWER™ RAM a6 4 25 fl AB combines an 8K x 8 full CMOS SRAM and a long as Ys 24 flag life lithium carbon mono-fluoride battery in a single aa qe 23 fan plastic DIP package. The MK48Z08/18/09/19 is a A3 7 wKaszos 27 fl G Non Volatile, pin and function equivalent to any Az qs MKka8z18 21H Alo JEDEC standard 8K x 8 SRAM. It also easily fits aids 2ohe into many EPROM and EEPROM sockets, provid- a0 q 10 19 f 07 ing the non-volatility of the PROMs without any 290 qx 18 006 requirement for special write timing, or limitations par g 12 17 f 005 on the number of writes that can be performed. oa2 q 5 16 f pos In addition, the MK48Z08/18/09/19 has its own Guo 4 18 f 003 Power-fail Detect circuit, The circuit deselects the vacones device whenever Vcc is below tolerance, providing ahigh degree of data security in the midst of — ie y unpredictable system operations brought on by writ 26 p Yoo low Voc. ane aee ards 26 f Ea PIN NAMES a6 as has ASS 24D ag neds ap att

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Figure 2. Block Diagram

1 UTHIUM 8K xB KF a0-a12

1 AND _

1 SWITCHING Ww

S G6 S-THOMSON MK48Z08,18,09,19 SeE D MB 7929237 0038372 429 MSGTH T-46-23-12 ABSOLUTE MAXIMUM RATINGS ‘Symbol "Parameter Ce - | Po | Total Power Dissipation 40 Ww our Output Current per Pin ee mA Voo ‘Voltage on any Pin Relative to GND 0.3 to +7.0 v Tera | Ambient Storage (Voc Off) Temperature "40 to 85 “C = “Ta | Ambient Operating Temperature ~ 0t070 a ‘Stresses greater than those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. Tis isa stress rating only Tatimpied Exposure fa abeaue mass ata conasens Wr eters porass ote ray Shea ease ON Speciation & CAUTION : Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode. RECOMMENDED DC OPERATING CONDITIONS (0°C < Ta < 70°C) Parameter Min. Max. Unit [Notes | Veo | Supply Voltage (MK48Z18/19) [4s es 1 ‘Supply Voltage o | 0 v 1 Vie Logic "1" Voltage All Inputs 22 | Veo +0.3V v 1 [Ve [Lesie "0" Votage At inputs | 3 | os v : 12 | DC ELECTRICAL CHARACTERISTICS (O°C < Ta $ +70°C; Voc min $ Voc $ Voc max) ~ Symbol Parameter Min. =| Max. [unit | Notes ‘Average Voc Power Supply Current ~ | 80,125 [om | 36 TTL Standby Current (E = Viv or Eo = Vi) [3 a lu | Input Leakage Current (Any Input) as 1 [| ~ | 5s | Output Leakage Current 7 5 5 Vox | Output Logic "1" Voltage (lout = —1.0mA) 24 801

MK48Z08,18,09,19 SG S-THOMSON 1-46-23-12 ACTESTCoNDITIONS SCE D MB 7929237 0038373 3b5 MBSGTP ‘Transition Times Sns Input and Output Timing : Lev Reference Levels OUTPUT LOAD DIAGRAM MK48Z08-70 MK48Z08,18,09,19 +5V +5V ohms ohms Dut Dut | u . To 1K 30pF * i = + 10pF ohms’ ‘ohms i} cones vpogoe23 CAPACITANCE (Ta = 25°C) es [es [emir nA 00) Notes : 1. All voltages referenced to GND. 2. Negative spikes of -1.0 vot allowed for up to 10ns once per Cycte. 3. lecr measured with outputs open. 4. ImAtypcal 5. Measured wth Vec 2 Vi GND and outpus deselected. 6. 80MA@ 100ns, & 125mA @ 70ns. 7. Effective capacitance calculated from the equation C = lAvAV with AV = 3 volts and power supply at 5.0V. 8. Measured wih outputs deselected. a 802

Figure 3. Power Down/Up Timing T-46-23-

MK48208,18.09.19 7 OMSON 12 See D mM 7929237 0038375 138 MESGTH READ MODE Hf Chip Enable or Output Enable access times ae li i t tr the The MK48Z08/18/09/1 91s in the Read Mode when- OF Cap Eat Acres Time (tas) or at Output ever W (Write Enable) is high, Ex(Chip Enable 1) is Enable Access Time (tata). The state of the eight low, and Eo(Chip Enable 2) is high (MK48Z09/19). three-state Data I/O signals is controlled by Chip The device architecture allows ripple-through ac- Enable and Output Enable. if the Outputs are cess of data from eight of 65,536 locations in the activated before tavav, the data lines will be driven Static storage array. Thus, the unique address spe- to an indeterminate state until tavav. If the Address cified by the 13 Address Inputs defines which on@ inputs are changed while Chip Enable and Output Of the 8,192 bytes of data is to be accessed. Valid Enable remain low, output data will remain valid for data wi be avalabl atthe Data VO pins within Guiut Hold trom Address (txcx) But wil go In tavay after the last address input signal is stable, in i A . providing that the Chip Enable'and Gutput Enable t2"™inate until the next Address Access. access times are satisfied. ‘AC ELECTRICAL CHARACTERISTICS (Read Cycle) (0°C < Ta < 470°C; Voc mins Voc $ Voomax) ara _ wins [Max | bans | ax | [eo [einewereoume fw [pe fp | [iss oostasionaies fe |e | texoz | Chip Enable 2 to Q High-Z [| fe | | 62 . 804

Figure 4. Read Timing n’ 1 (Address Access) T-46-23-12 Figure 5. Read Timing n° 2

57 S¢S:THOMSON me

MK48208,18,09,19 __ sar ) Mm 7929237 0038377 TOO MBSGTH WRITE MODE initiation of another read or write cycle. Data-in voi , must be valid t jor to the end of write and The MK48Z08/18/09/19is inthe Write Mode when- ‘Must Be valid tovwa prior to the ever Write Enable and Chip Enable are active. The G is « Don't Care in the Witte Mode and start ofa write is referenced tothe later occurring Because G is Don't Cave in the Write Mode a falling edge of W or E1 or ring edge of E2 alow on wil return the outputs to Ht eeberal (MK48Z09/19). A write is terminated by the earlier Jon ated. at On W i dk oie th can wuts fising edge of W or Es, or the falling edge of Ez jmplementeg. A Tow on wil cisable the ups (MK48Z09/19). The addresses must be held valid waz after W goes low. Take care to avoid by throughout the cycle. E; or W must return high or perating . Ee low for minimum of te1Hax or tea.ax prior to the S G S-THOMSON AC ELECTRICAL CHARACTERISTICS (Write Cycle) (0°C <Ta< 470°C; Voc min $ Vec < Vc max) [ symot | parm “wxaez0e70 | mKsezoio | | | — Tiaioas Sctpmewwiw | o | fe | fm ‘to Chip Enable Active i tavezH ns | } teres _| Write Recover rom Chip het —pet m | 2 cc i [tm [Address vaiswoWrign fo | fo Pe Coe [merce pee |_ tus [chip Enable Actvto ee ee End of Write [ter [enctiewaims Dw |e) Notes : 1. ina W Controlled Cycle. 2. ina, Ee Controlled Cycle. a2 . ee 896

Figure 6. Write Control Write Cycle Timing Figure 7. Chip Enable Control Write Cycle Timing

57 SSs:THoMson one

MK48Z08,18,09,19 MM 7929237 0038379 883 WESGTH 1-46-23-12 S G S-THOMSON SeE D DATA RETENTION MODE PHEUIGIING STORAGE LIFE With Voc applied, the MK48Z08/18/09/19 operates _Figure 8 ilustrates how temperature affects Storage as a conventional BYTEWIDE™ Static RAM. _Life of the MK48Z08/18/09/19 battery. The life of the Should the supply voltage decay, the RAM will battery is controlled by temperature and is virtually automatically power-fail deselect, write protecting —_ unaffected by leakage currents drawn by the itself when Voc falls within the Vero(max), — MK48Z08/18/09/19. Vero(min) window. Storage Life predictions presented in Figure 8 are Note : Amid-write cycle power failure may corrupt extrapolated from temperature accelerated fe-test data at the currently addressed location, but does. data collected in over 100 milion device hours of not jeopardize the rest of the RAM’s content. At continuing bare cell and encapsulated call battery voltages below Vpro(Min), the user canbe assured _ testing by SGS-THOMSON. Obviously, temperature the memory will be in a write protected state, accelerated testing cannot identify non-temperature provided the Vcc fall time is not less than tr. The dependent failure mechanisms. However, in view of MK48Z08/18/09/19 may respond to transient the fact that no random cell failures have been noise spikes that reach into the deselect window if _ recorded in any of SGS-THOMSON's on going bat- this should occur during the time the device is tery testing since it began in 1982, we believe the sampling Vcc. Therefore decoupling of the power chance of such failure mechanisms surfacing is ex- supply lines is recommended. tremely smal. For the purpose ofthe testing, a col The power switching circuit connects external Vcc _failure is defined as the inability of a cell stabilized at to the RAM and disconnects the battery when Vcc 25°C to produce a 2.4 volt closed-circuit voltage rises above Vso. Normal RAM operation can re- _@Cfoss a 250K load resistance. sume trec after Voc exceeds Verp(max). Caution A Special Note : The summary presented in Figure should be taken to keep E1 high (MK48Z08/18) or 8 represents a conservative analysis of the data Ez low (MK48Z09/19) as Vcc rises past Verp(min) presently available. While SGS-THOMSON is most as some systems may perform inadvertent write likely in possession of the largest collection of cycles after Vcc rises but before normal system _battery life data of this kind in the world, the resutts operation begins. presented should not be considered absolute or final ; they can be expected to change as yet more POWER FAIL INTERRUPT data’ becomes available. We believe that future : read points of life test presently under way and Vee te etre oaeer fal eee tenet one improvements in the battery technology itself will Mics8Z09/19 an interrupts immediately generated. resultina continuing improvement of these figures. ‘An intemal clock provides a delay no less than 10us Two end of life curves are presented in Figure 8. but no greater than 40 us before automatically They are labeled "Average" (tsox) and (tix). deselecting the MK48Z09/19.The INT pin is anopen ‘These terms relate to the probability that a given drain output and requires an extemal pullup resistor. number of failures will have accumulated by a particular point in ime. for example, expected PREDICTING BACK-UP SYSTEM LIFE Ite at 70°C, ie al lesue, Figure 8 incosiss tht a particular MK48Z08/18/09/19 has a 1% chance of did a oxpented tovultanatey Cone to ar oed for Raving a battery falure 11 years into its lite and a one of two reasons : either because it has been 90% chance of failure at the 20 year mark. Con- Gischarged while providing current to an-external versely, given asample of devices, 1% of them can load ; orbecause the effects of aging render the celi_ 9 @xPected to experience a battery failure within useless before it can actually be discharged. Fortu- 't years 50% af them can be expected to experi- nately, these two effects are virtually unrelated, al- &"0® @ failure within 20 years. lowing discharge, or Capacity Consumption, and the The ti, figure represents the practical onset of wear effects of aging, or Storage Life, to be treated as two out, and is therefore suitable for use in what would independent but simultaneous mechanisms, theear- normally be thought of as a worst-case analysis. The lier of which defines Back-up System life. ts0% figure represents "normal" or "average" life. Itis, With Voc on, the battery is disconnected from the RAM _ therefore, accurate to say that the average device will and aging effects become the determining factor in 4st "tbo". battery life. With Voc off, leakage currents in the RAM —_Battery life is defined as beginning at the date of man- provide the only load on the Battery during battery facture. Each MK48708/18/09/19 is marked with a back-up. For the MK48208/18/09/19, the leakage cur- nine digit manufacturing date code in the form rents are so low that the Back-up System Life of the H99XXVYZZ, example: #0589231 is H -fabricated in device is simply the Storage Life of the cell. The Carroliton, TX; 9 - assembled in Muar, Malaysia; 9- Storage Life of the cell is a function of tempera- _ tested in Muar, Malaysia; 5B - lot designator; 9231 ture. - assembled in the year 1992, work week 31. 10/12 SGS-THOMSON 898

pendent upon application controlled variables, tion should be used to estimate Storage Life. Where TAs, TA2, TAN, = Time at Ambient Temperature 1, 2, etc. ment where the MK48208/18/09/19 is exposed to 70°C, for the remaining 438 hrs./yr. Figure 8. Predicted Battery Storage Life Versus Temperature

MK46206,18,08.19 sae ) mm 7929237 0038381 43) MBSGTH

ORDERING INFORMATION

Example: MK48Z08 B 70 T | T-46-23-12 ol [__seeee B PHDIP28 70 70ns- 10 100ns For a list of available options of Package and Speed refer to the Selector Guide in this Data Book or the current Memory Shortform that will be periodically up-dated. For further information or any aspect of this device, please contact our Sales Office nearest to you. 12/12 > 900