MK48T02 STMICROELECTRONICS | Alldatasheet
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S5eE D MM 7929237 0038504 74T MBSGTH T-46-23-/72 ® MICROELECTRONICS MK48T12 SG S-THOMSON CMOS 2K x 8 TIMEKEEPER SRAM = INTEGRATED ULTRA LOW POWER SRAM, - REAL TIME CLOCK, CRYSTAL, POWER-FAIL a CONTROL CIRCUIT AND BATTERY. Ko » = BYTEWIDE RAM-LIKE CLOCK ACCESS. Qe = BCD CODED YEAR, MONTH, DAY, DATE, Weert) | HOURS, MINUTES AND SECONDS. 2a Nery Lt = SOFTWARE CONTROLLED CLOCK CALIBRA- TION FOR HIGH ACCURACY APPLICATIONS. 1 =PI WORST CASE BATTERY STOR- es 11 YEARS @ 70°C. PHDIP24 WITH BATTERY TOP HAT (B) = PIN AND FUNCTION COMPATIBLE WITH JEDEC STANDARD 2K x 8 SRAMS. = AUTOMATIC POWER-FAIL CHIP DESE- Figure 1. Pin Connection LECTWRITE PROTECTION. = TWO POWER-FAIL DESELECT TRIP POINTS AVAILABLE : = —MK48T02 4.75V > VprD> 4.50V a7 qt 24 pl Yoo —MK48T12 4.50V>Vprp2 4.20V AB g 2 230 AB ASgds 220 Ag DESCRIPTION Aste an Ww The MK48T02/12 TIMEKEEPER™ RAM combines oa wee a 2K x 8 full CMOS SRAM, a BYTEWIDE™ ac- de Mesoms eRe cessible real time clock, a crystal and a long life Ald wep E lithium carbon mono-fluoride battery, all in a single aoge 17 p ba? plastic DIP package. The MK48T02/12 is a non-vo- Dao fe 16 f 006 latile pin and function equivalent to any JEDEC pat q 10 15 f 005 standard 2K x 8 SRAM, such as the 6116 or 5517. It pe2 qd: 141 pa4 also easily fits into many EPROM AND EEPROM exo dz 3h pas sockets, providing the non-volatility of the PROMs without any requirement for special write timing, or vao0s98 limitations on the number of writes that can be per- formed. Access to the clock is as simple as conventional BYTEWIDE RAM access because the RAM andthe Bn Names Clock are combined on the same die. As Figure 2 indicates, the TIMEKEEPER registers are located r in the upper eight locations of the RAM. The regis. [A*A"0 Address Inputs | ters contain, beginning at the top: year, month, date, E Chip Enable day, hours, minutes, and seconds data in 24 Hour [up Ground BCD format. Corrections for 28,29 (Leap Year),30 [GNP | Groune and 31 day months are made automatically. The | Voc 3 Volts eight location is a Control register. These registers are not the actual clock counters ; they are Br |W | Wrtenablo PORT™ read/write Static RAM memory locations. fe The MK48T02/12 includes a clock control circuit |° Cuenta ‘that, once every second, transfers the counters into DQo - DQ7 Data Inputs/Outputs February 1992 414 1023
Figure 2. Block Diagram registers are being updated at the very moment _dictable system operations brought on by low Voc. another location in the memory array is accessed.
. MK48T02, MK48T12 S2— D M@™ 7929237 00348506 $12 MBSGTH T-46-23-12 ABSOLUTE MAXIMUM RATINGS ‘Symbol Parameter | —vawe si unit | Ambient Storage (Voc Off, Oscillator Off) Temperature “40 10 +85 —efeweeeweween a Output Current Per Pin 20 mA ‘Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage 10 the dovice. This is a stress rating CAUTION:Negative undershoots below 0.3 volts are not allowed on any pin whie in Battery Back-up mode. RECOMMENDED DC OPERATING CONDITIONS (0°C < Tas 70°C) ‘Symbol Parameter Min. Max. unit | Notes i [We [seorvemeomanig esse a Vin Logic “1" Voltage All Inputs [22 | Vec+0av | v 1 DC ELECTRICAL CHARACTERISTICS (O°Cs Ta < 70°C; Voc max 2 Voc 2 Voc min) oe eos ‘Average Vec Power Supply Current | 80 mA 3 [es |Momayoreneev pm [ee emos sereycoen @2veeaa | sm [i frets inert fou Output Leakage Current 5 HA 5 | 57, S88-THOMsON sia J, imvencMRECTRORCS 1025
MK48T02, MK48T12 SG S-THONSON T-46-23-12 H see Do 7929237 0038507 459 UESGT EQUIVALENT OUTPUT LOAD DIAGRAM AC TEST CONDITIONS av Input Levels 0.6V to 2.4V Transition Times _ 5ns rene Input and Output Timing 0.8V or 22V Reference Levels DEVICE a UNDER Test a ms inetUome score Frcs = vno00730 ‘CAPACITANCE (T= 25°C) [6 lemimanansteaseg [er Notes = ° 1. Allotages elerenced to GN. 2. Negatve spies of 10 volt alowed for upto 10ns once per cyl 5. nc meeumed wth uate opon. 4. Measured with Control Bits set as follows : R= 1; W, ST, KS, FT = 0. 5. Measured with Voc> Vi2 GND and outputs deselected. 6 ffoctvecapadtance calculated rm the equation C = LAVAV with AV « 3 vos and power supply a 6. 7. Measured wth outputs dosloctnd ana 57 SGS:THoMson OFA face cc088208—©§ $A 1026
W (Write Enable) is high andE (Chip Enable) islow. Time (tcea) or atOutbut Enable Access Time (toca). access times are satisfied. will go indeterminant until the next taa . Figure 3. Read-Read-Write Timing ' Note: ‘Measured using the Output Load Diagram shown Page 4.
referenced to the latter occurring falling edge of | during power-up to protect memory after Voc . rising edge of W or E. The addresses must beheld _lizes. afterwards. contention when operating with two-wire control. Figure 4. Write-Write-Read Timing [_ tm [Oaatosting | st sy ts] fmt .
registers can be halted without disturbing the clock &*oeed + 35ppm (Parts Par Million) oscilator fre. Control Register. As long as a“1" remains in that various temperatures. registers are updated simultaneously. AHaltwill not Tee ere oe eo resants from the oscil. user can then load them with the correct day, date clock up, subtracting counts slows the clock down. Figure 5. The MK48T02/12 Register Map
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MK48T02, MK48T12~ 5cE D MM 7929237 0038511 948T MBSGTH T-46-23-12 ane second ether shortened or lengthened by 128 STOPPING AND STARTING THE OSCILLATOR oscillator cycles, that is one tick of the divide by 256 The oscillator may be stopped at any time. If the stage. If a binary 1 is loaded into the register, only device is going 10 spend a significant amount of ! the first two minutes in the 64 minute cycle will be time on the shelf, the oscillator can be turned off to Modified ; if a binary 6 is loaded, the first 12 willbe minimize current drain from the battery. The “Stop” affected, and so on. bit is the MSB of the Seconds register. Setting it to Therefore, each calibration step has the effect of a. "1" stops the oscillator. In order to make the adding or subtracting 256 oscillator cyclesforevery oscillator as stingy with current as possible, the 125,829,120 (32768 x 60 x 64) actual oscillator oscillator is designed to require an extra "kick" to cycles, that is 2,034 ppm of adjustment per calipra- begin oscillation again. The extra kick is provided tion step ; giving the user a +63.07 ppm calibration _by the Kick Start (KS) bit, the MSB of the Hours range. Assuming that the oscillators infactrunning __register. To start the oscillator, implement the fol- at exactly 32768 Hz, each of the 31 increments in lowing procedure : the Calibration byte would represent 5.35 seconds —_1. Set the Write Bit to “1" er month, which corresponds to a total range of ape 75 minutes permonth.. 9 2. Reset the Stop Bit to "0" Two methods are available for ascertaining how >: Set the Kick Start Bit to “1 much calibration agiven MK48T02/12 may require. 4. Reset the Write Bit to “0”. The first involves simply setting the clock, letting it 5, Wait 2 seconds. run for a month and comparing it to a known he Ba to"t* accurate reference (like WWV broadcasts). While © Set the Write Bit to “1". this may seem crude, it allows the designer to give 7. Reset the Kick Start Bit to “O". the end user the ability to calibrate his clock as his. Set the Correct time and date. environment may require, even after the final pro- ote it to duct ist packaged in a non-user serviceable enclo- 8. Reset the wate Bite 0". he Chacko era sure. All the designer has to do is provide a simple :Leaving et will eause the Clock to draw excossive untility that accesses the Calibration byte. The = ™™emtane wi shoren bate. utility could even be menu driven and made fool- proof. The second approach is better suited to a manu- S 6 S-THOMSON facturing environment, and involves the use of some test equipment.’ When the Frequency Test (F7) bi the seventh-most significant bt in the Day register, is set to a "1", and the oscillator is running at 32768 Hz, the LSB (DQo) of the Seconds register. Figure 6. Oscillator Frequency VS will toggle at a 512 Hz. Any deviation from 512Hz Temperature indicates the degree and direction of oscillator fre- quency shiftat the test temperature. For example, a reading of 512.00512Hz would indicate a ” a ee ee +10 ppm. (1 — (512/512.00512)) oscillator fre- * 4 — quency error, requiring a -5 (0001012) tobe |=. b— MI loaded into the Calibration Byte for correction. Note [= that setting or changing the Calibration Bytedoes |= “[—_| notaffect the Frequency Test output frequency.The | 2° rf device must be selected and addresses must be | i stable at Address 7F9 when reading the 512Hzon | 3 4 ——* | DQo. FA [TN The FT bitmustbesetusingthesamemethodused |% , a to set the clock, using the Write bit. The LSB of the é ee ee Seconds register is monitored by holding the a MK48T02/12 in an extended read of the Second oe register, without having the Read bit set. The FT bit TEMPERATURE (OEGAEES CELSIUS) MUST be reset to a “0” for normal clock operations to resume. ana : me pp sesetuomsoy 1030
S2E D MM 7929237 0038512 816 MESGTH_ MK4sT02, MK48T12 DATA RETENTION MODE Figure 7. Adjusting the Divide by 256 Pulse With Voc applied, the MK48T02/12 operatesas a ‘Train conventional BYTEWIDE static RAM. However, T-46-23-12 Voc is being constantly monitored. Should the sup- ply voltage decay, the RAM will automatically S G S-THOMSON power-fail desalect, write protecting itself when Voc falls within the Veep (max), Vero (min) window. The MK48T02 has a Vero (max) - Vero (min) window NORMAL of 4.75 volts to 4.5 volts, providing very high data security, particularly when all of the other system components are specified to 5.0 volts plus and minus 10%. The MK48T12 has a Verp (max) - Vero positive FP LIU ALS (min) window of 4.5 voltsto 4.2 volts, allowing users | cAtisRavion constrained to a 10% power supply specification to use the device. Note : A mid-write cycle power failure may corrupt vesarve [|] r M data at the currently addressed location, but does CALIBRATION not jeopardize the rest of the RAM's content. At voltages below Verp (min), the user can be assured A aamnaad the memory will be in a write protected state, provided the Vcc fall time does not exceed tr. The MK48T02/12 may respond to transient noise spikes that reach into the deselect window if they ‘should occur during the time the device is sampling Vcc. Therefore decoupling of power supply lines is recommended. PREDICTING BACK-UP SYSTEM LIFE ‘The power switching circuit connects external Vcc_—_—_The useful life of the battery in the MK48T02/12 is to the RAM and disconnects the battery when Vcc expected to ultimately come to an end for one of ee re Tt SMe esate attery voltage two reasons : either because it has been dis- 1s checked. It the voltage is too low, mal charged while providing current to an external Battory Not OK (BOR) fag willbe set. The BOK flag fad’ or because the effects of aging render the can be checked after power up. If the BOK flag is ce! useless before it can actually be discharged. set, the first write attempted will be blocked. The Fortunately, these two effects are virtually unre- - flag is automatically cleared after the frstwrite, and ated, allowing discharge, or Capacity Consump- normal RAM operation resumes. Figure 9 illus- tion and tho elfects of aging, oF Storage Life to be trates how a BOK check routine could be struc- treated as two independent but simultaneous tured. mechanisms, the earlier of which defines Back-up Normal RAM operation can resume tec after Vcc System life. exceeds Vero (max). Caution should be taken to The current drain that is responsible for Capaci keep E or W high as Vco rises past Vero (min) 5 Consumption can be reduced either by apeying some systems may perform inadvertent write Voc of tuming off the oscillator. With the oscillator cycles after Voc rises but before normal system ff, only the leakage currents required to maintain operation begins. data in the RAM are flowing. With Vcc on, the battery is disconnected from the RAM. Because the leakage currents of the MK48T02/12 are so low, they can be neglected in practical Storage Life calculations. Therefore, application of Vec or turn- ing off the oscillator can extend the effective Back- up System life. 57 8&S-THomson sia TON, c288E FRAC ££ 1031
Figure 8. Power-Down/Power-Up Timing T-46-23-12
- Allvoltages referenced to GND.
- Vero (max) to Vero (min) fll times of less tr may resut in deselectionywite protection not occuring uni 50us ator Vee passes Vivo (min).
- Vero (min) to Veo fall mes of less than trs may cause corruption of RAM data or stop the clock
S2— D M@@ 7929237 0038514 699 MSGTH — mxasto2, MKasT12 EO Ore eee MK 48TO2, MK48T12 PREDICTING STORAGE LIFE Figure 9. Checking the BOK Flag Status Figure 10 illustrates how temperature affects Stor- age Life of the MK48T02/12 battery. As long as Voc T-46-23-12 is applied or the oscillator is turned off, the life of the battery is controlled by temperature and is virtually - Unaffected by leakage currents drawn by the» © S~ THOMSON MK48T02/12. READ DATA Storage Life predictions presented in Figure 10 are AT ANY extrapolated from temperature accelerated life-test ADDRESS data collected in over 100 million device hours of continuing bare cell and encapsulated cell battery testing by SGS-THOMSON. Obviously, temperature accelerated testing cannot identify non-temperature dependent failure mechanisms. However, in view of conte ay the fact that no random cell failures have been DATA BACK recorded in any of SGS-THOMSON's on going bat- To SAME tery testing since it began in 1982, we believe the ADDRESS: chance of such failure mechanisms surfacing is ex- tremely small. For the purpose of this testing, a cell failure is defined as the inability of a cell stabilized at 25°C to produce a 2.4 volt closed-circuit voltage READ DATA across a 250K ohm load resistance. AT SAME A Special Note : The summary presented in Figure AGAIN 10 represents a conservative analysis of the data presently available. While SGS-THOMSON is most likely in possession of the largest collection of battery (BATTERY Low) life data of this kind in the world, the results presented vate NOTIFY SYSTEM should not be considered absolute or final ; they can COMPLIMENT, NO ‘OF Low be expected to change as yet more data becomes OF FIRST BATTERY (DATA MA available. We believe that future read-points of life BE CORRUPTED) tests presently under way and improvements in the ves battery technology itself will result in a continuing (BATTERY OK) improvement of these figures. WRITE ORIGINAL ‘Two end of life curves are presented in Figure 10. They prelate are labeled “Average” (tsa) and (ts). These terms SAME ADORESS relate to the probability that a given number of failures will have accumulated by a particular pointin time. If, for example, expected life at 70°C is at issue, Figure 10 indicates that a particular MK48T02/12 has a 1% chance of having a battery failure 11 years into its life and a 50% chance of failure at the 20 year mark. veaas760 Conversely, given a sample of devices, 1% of them can be expected to experience battery failure within 11 years ;50% of them can be expected to fail within 20 years. GALCULATING PREDICTED STORAGE LIFE Thetis, igure represents the practicalonsetofwear out, _As Figure 10 indicates, the predicted Storage Life ands therefore suitable for use in what would normally —_of the battery in the MK48T02/12 is a function of Tepresans rorral or average" ie, re, hoeere, temperature. r or . It is, therefore, - fn r * Because the ambient temperature profile is depen- accurate to say that the average device will ast“tsox’. Gent upon application controlled variables, only the Battery life is defined as beginning on the date of |_user can estimate predicted Storage Life in a given manufacture. Each MK48T02/12 is marked with a design. As long as ambient temperature is held nine digit manufacturing data code in the form reasonably constant, expected Storage Life can be H99XXYYZZ, example: H995B9231 is H - fabri- read directly from Figure 10. If the MK48T02/12 cated in Carrollton, TX; 9 - assembled in Muar, spends an appreciable amount of time at a variety Malaysia; 9 - tested in Muar, Malaysia; 5B - lot —_of temperatures, the following equation should be designator; 9231 - assembled in the year 1992, _used to estimate Storage Life. work week 31 . 1114 ST Se 1033
MK48T02, MK48T12 S G S-THOMSON T-46-23-12 52— D M@® 7929237 0038515 525 MESGTH Predicted Storage Lite = 1 [(TA/TTYSL] + [CTASTT)/SL] + ... + [(TA/TTYSL] Where TA, TA:, TA. = Time at Ambient Temperature 1, 2, etc. TT =Total Time = TA: + TAs +... + TAs SL, SLs, SL. = Predicted Storage Life at Temp 1, Temp 2, etc. (See Figure 10). EXAMPLE PREDICTED STORAGE LIFE CAL- CULATION A cash registerterminal operates in an environ- _(104°F), for 3650 hrs/r; and temperatures greater ment where the MK48T02/12 is exposed to tem- than 40°C, but less than 70°C (158°F), for the peratures of 30°C (86°F) or less for 4672 hrs/yr ; remaining 438 hrs/yr. temperatures greater than 25°C, but less than 40°C. = 126 yrs PREDICTING CAPACITY CONSUMPTION LIFE sumption life can be estimated by reading 0% Voc , 'y Cycle Capacity Consumption life directly from The MK48T02/12 internal cell has a nominal ca- Figure 12, and dividing by the expected Vcc Duty pacity of 39mAh. The device places a nominal Yala (i.e at 25°C with a 66% Duty Cycle, Capacity combined RAM and TIMEKEEPER load of 1.2uA — Congumption Life = 3.7/(1-.66) = 10.9 years) on the intemal battery when the clock is running spent : and the device is in Battery Back-up mode. At that If the MK48T02/12 ‘spends an appreciable amount rate, the MK48T02/12 will consume the cell's ca- Of time at a variety of temperatures, the same pactty in 32,500 hours, or about 3.7 years. But, as equation provided in the previous Storage Life Figure 11 shows, Capacity Consumption can be _ section should be used to estimate Capacity Con- spread over a much longer period of time. sumption life. Naturally, Back-up current varies with temperature. . As Figure 12 indicates, the rate of Current Con- Example consumption life calculation sumption by the MK48T02/12 with the clock run- Taking the same cash register/terminal used ear- ning in Battery Back-up mode is a function of lier, let's assume that the high and low temperature temperature. periods ae, the non-operating, Battery Back-up Because the ambient temperature profile is de- de periods, and that the register is turned on 1 pendent upon application controlled variables, only hours a day seven days per week The two Points the user can estimate consumption rates inagiven ° scterest on the curves in Figure 12 wit be tt design. As long as ambient temperature is held 29°C and the 70°C points. reasonably constant, expected Capacity Con- Reading Capacity Life values from Figure 12 ; CL: = 3.7 yrs., CL: = 3.96 yrs. 26.38 yrs. 1244 'SGS-THOMSON 1034
Figure 10. Predicted Battery Storage Life Versus Temperature
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MK48T02. MK48T12 S G S-THOMSON T-46-23-12 S52— D MW 7929237 0038517 JTS MBSGTH Figure 12. Current Consumption Life over Tem- APPLICATION NOTE :
ORDERING INFORMATION
Example: MK48T02 B 12 B PHDIP24 12 120ns 15 150ns- 20 200ns 25 250ns For a list of available options of Package and Speed refer to the Selector Guide in this Data Book or the current Memory Shortform that will be periodically up-dated. For further information or any aspect of this device, please contact our Sales Office nearest to you. 14/14 THOMSON a Ee __ 1036