MK48256 | DigiCamel IC Datasheet

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MK48256 STMICROELECTRONICS | Alldatasheet

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IST; 7 SGS-THOMSON MK48256 +» MICROELECTRONICS MK48256L 32K x 8 CMOS STATIC RAM PRELIMINARY DATA ™ BYTEWYDE™ 32K X 8 CMOS SRAM ; ™ EQUAL CYCLE/ACCESS TIMES, 100, 120NS a 7 MAX. ra - aot ™ LOW Vcc DATA RETENTION, 2 VOLTS \\ § THREE-STATE OUTPUT 28 yl i DESCRIPTION 1 Poires Pso28 ' The, MK48256 is a 256K (262,144-bi) CMOS | i RAM, organized as 32,768 words x 8 bits. Itis | 1 fabricated using SGS-THOMSON's low power | (Ordering information at the end of the data-sheet) | high performance, CMOS technology. The device features fully static operation requiring noextemal pj, i clocks or timing strobes, with equal address access. Pi Connection and cycle times. It requires a single +5V + 10%. supply, and all inputs and outputs are TTL com- | patible. } — | aw it 28 Vee Al2 2 27, WwW a7 is 265 AIS OPERATIONAL MODES Nar ares The MK48256 has a Chip Enable power down aa 76 23, att feature wich sustains an automatic standby mode. a3 7 22 G whenever Chip Enable (E) goes inactive high. An A2 |g MK4B256 95° Aig | Output Enable (G) pin provides a high speed tris- Al : ° 20! € tate control, allowing fast read/write cycles to be 1% * H achieved with the common-V/O data bus. Oper- Ao baz i ational modes are determined by device control DQ, 0 185 D6 i inputs W, G and E, as summarized in the truth da, 12 7 | Das | table. Da, = 13 16) DQ, Vss 14 15 DQ, | . PIN NAMES | AO-A14 Address Inputs a0-Da7 Data VOo7 MK48256 TRUTH TABLE 6 (08) Output Enable iH | x | x [pesetect Hiz | Standby w Write/Read Enable tlalnl Read Hz | Active

Figure 1 : MK48256 Block Diagram A Nec bd Yes now MewoRY (10) @ /DECODE “nea e (1024 «32 «8) a 250K. ot ce | bara (8)|crn | | comm 00 iB | aed coe Looe | ce | 6 | | i | Ak | w=.) q | e | z-d> l 5 ae L ra dA) LpD48256 READ MODE within tavav after the last stable address, providing The MK48256 is in the Read mode whenever Write Gis low, and E is low. If Chip Enable or Output Enable (W) is high with Output Enable (G) low, and Enable access times are not met, data access will Chip Enable (E) is active low. This provides access be measured from the limiting parameter (teLav, or to data from eight of 262,144 locations in the static ‘GLav) rather than the address. Data out may be memory array, specified by the 15 address inputs. _ indeterminate at tevax, and te.ox, but data lines will Valid data will be available at the eight Output pins always be valid at tavav. AC ELECTRICAL CHARACTERISTICS (READ CYCLE) (OC <Tas +70°C, Voc =5.V+ 10%) MK48256-100 | _MK48256-120 | 7——+ - NOTE SYMBOL PARAMETER MIN MAX | MIN MAX tavay Read Cycle Time 100 | 420 | tavav | Address Access Time 100 120 4 teLav Chip Enable Access Time 100 120 4 tcuev Output Enable Access Time 50 60 4 teax Chip Enable to Q Low-Z 10 10 "s [os | NOTES : 4. Measured with load as shown in Figure 8A, ~ . 5. Measured wit load as shown in Figure 88. 20 57 SGS-THOMSON ~ — YA. imicaoseernowce - ——

Figure 2 : Read Timing N’.1 ( Address Access) | } | tavay | Agy —\\ tavav hb t AXQX pK we HD

0 KS DATA VALID K> 7

WRITE MODE If the Output is enabled (E = low, G = low), then W The MK48256 is in the Write mode whenever the _Will return the outputs to high impedance within W and E pins are low. Either Chip Enable or W _‘tw.az0f its falling edge. Care must be taken to avoid must be inactive during Address transitions. The US contention in this type of operation. Data-in Write begins with the concurrence of Chip Enable ust be valid for town to the rising edge of Write being low with W low. Therefore, address setup Enable, or tothe rising edge of E, whichever occurs times are referenced to Write Enable and Chip __fifst, and remain valid twox . Enable as tavw., and taveL respectively, and is determined by whichever edge occurs latter. The Write cycle can be terminated by the earliest rising edge of W or Chip Enable (E). AC ELECTRICAL CHARACTERISTICS (WRITE CYCLE) AS see ey a _ } MK48256-100 | —MM48256-120 ‘SYMBOL | PARAMETER UNIT | NOTE | MIN = MAX | MIN | MAX tavay | Write Cycle Time 100 | | 120 ; tawn | Address Set-up Time to W Low o | a) taver | Address Set-up Time to E Low o | a) tavwy | address valid to W HiGh a | 85 twuwn | Write Pulse Width | 60 | 65 twiax | Address Hold After End Of Write | 5 | 5 i teen |Chip Enable Active ToEnd Of Write | 80 | 85 | sou [AdsessHosTineFomCnperse) 5 | 8 Viner lomesme |e |e ‘wwe _|W High 1G Active 8 5 {| 5 twiaz |W Low to Q High-Z 0 35 0 | 40 5 NOTE : 5. Measured with load as shown in Figure 88. ano 77 S&S-THomson - SYA. carcromucTaceice —

ABSOLUTE MAXIMUM RATINGS * SYMBOL PARAMETER VALUE UNIT Vi Voltage On Any Pin Relative to Ground 0.510 +7.0 v t Ta Ambient Operating Temperature 01070 c ra_jAmben Ceeraing Torperae i Tst6 i Storage Temperature: -65 to 150 c Po Power Dissipation 1 w lo |Output Current * 50 mA * This is a stress rating only and functional operation of the devioe at these or any other conditions above those indicated in the operation sectons of his specication isnot implied. Exposure to absolute maximum rating conditions for extended periods ol ime may atlec reabiity +f Ouput current absolute maximum rating is specified or one output ata time, not to exceed a duration of 1 second. RECOMMENDED DC OPERATING CONDITIONS (OC < Ta < 470°C) SYMBOL | PARAMETER MIN TYP MAX | UNIT — NOTE [vee [Supp vonage a | so) ss | v4 a o | eo |. |v 4 Vex | Logic “t* Voltage All Inputs 22 [vec +oav) Vv 1 Vi. Logic "0" Voltage All Inputs 03 08 v 1 DC ELECTRICAL CHARACTERISTICS (OC < Ta<+70°C) SYMBOL | PARAMETER MIN maxX | oUNIT | NOTE loc; _| Average Vee Power Supply Current 70 mA 6 Isq__| TTL Standby Current ( E= Vin) 7 | _ Mka8256 8 sa1__| CMOS Standby Current (E= Voc -0.2v) tu Input Leakage Current (Any Input) PT pA 2 ho | Quput Leakage Current 42 WA 2 Output Logic "1" Voltage ( lour =-4.0 mA) | 24 | tov 1 NOTES : 1. Al'voltages references to Ground 2, Measured with Vss < V < Vee and outputs deselected 6. lect measured with outputs open, Vcc max ;1 = min duty cycle 100% 7. E= Ve, all other inputs = dont care ;t= 0 8. Voc (max) > E >Voc-0.0, all other inputs ~ don care = 0 G57 SSS:THOMSON 710 YA. iacnoaacroeics

‘AC TEST CONDITIONS Input Levels GND to 3.0 V Transition Time 1.5 ns Input and Output Signal Timing Reference Level 1.5 Volts Ambient Temperature O°C to 70°C Veco 5.0V + 10% Note : + 5% V-bump test is employed for t avav only. Figure 8 : Output Load Diagram + 50V + 5.0V ' ; 470 ohms g 470 ohms DEVICE | ewe | UNoER UNDER Test Test 240 ohms 100pF * 240 ohms = 5pF* GND _| GND | > “INCLUDES SCOPE AND TEST JIG = | TUxerAM | ” ® | CAPACITANCE (TA = 25°C, f = 1.0 MHz) ‘Symbol Parameter Max | Unit | Note | _o Capacitance on all pins (except DQ) a 8.0 _ pr | 10 Coo Capacitance on DQ pins 100 | pF, 3,10 NOTES : 3. Output butler is deselected 10. Capacitances are sampled and not 100 % tested. Sno 57 S¢S-THomson SYM. inienosiscrnomes

Figure 9 : Plastic PDIP28 tra foee [son [oss | [| yee way (core | [a2 Jos | Joe || 73 EUR, seats { - Day fase | |734|1 430 1.470 oes i le [rao] {1626| 500 40 | finog| iis er [ew] fase | || ee ks re Ca NOTES - 1 Overall length includes 010 IN. Flash on either end of the package. Riser eam peaee SON ramen she are 43 The maximum mt shal be increased by 003 IN. When solder lead fnish is specified Figure 10 : Plastic PSO28 : on| om inches : [in [yp [in yp ae | J (Se a | foe [Ys fow [Toe Lt je pe | len foe] we || | 2 |=) mee] eo lo 81 (3) oes |ore 026 [ae [ows | [orl | (ow fer] [aus |esr | [re . ; few fom [fname | [a lI 4 7 Je [127 Now | 080M, a « inn fA [n[ives[fise [aso | [soo | helio ins im [ee Tb few [Loe NOTES : 1. Overall length and width dimensions do not include moid flash or protrusions. Mold flash or protrusions shall not exceed 006

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— 1 9/10 : E57 SES:THOMSON — — —_—

ORDERING INFORMATION

| PART NUMBER ACCESS TIME PACKAGE TYPE ‘TEMPERATURE RANGE __mwasasen-too | t00ns | 28 PIN 600 Ml Plastic DIP | 0 10 70'C / MK48256N-120 120ns, 28 PIN 600 Mil. Plastic DIP > OC to 70°C MK48256LN-100 400s 28 PIN 600 Mil. Plastic DIP OC 070°C wKaspseLNizo.)tStS*«é« oe 0 7 ” oO MK48256LN-120 1 120ns_ 28 PIN 600 Mil. Plastic DIP OC to 70C MK48256S-100 100ns 28 PIN 330 mil. PSO 0° 070°C ' MK48256S-420 120ns 28 PIN 330 mil. PSO OC to 70°C MK48256LS-100 100ns 28 PIN 330 mil. PSO OC to 70°C MK48256LS-100 120ns 28 PIN 330 mil. PSO oC to 70'C _I {nformation furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsabilty for the consequences of use of such information nor for any infringement of patents or other rights of third partes which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject 1o change without notice. This publication supersedes and replaces all informations previously ‘supplied © 1990 SGS-THOMSON Microelectronics - Printed in France - All Rights Resorved ‘SGS-THOMSON Microelectronics GROUP OF COMPANIES ‘Australia - Brazil - China - France - Hong Kong - Italy - Japan - Korea - Malaysia - Maita - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - US.A. - West Germany Printed by NTI - AGL Partenaires - Belcodene - France 10/10 7 SSS:THOMSON - SYA. cunsmam e7"nom 3s ~ ~ _

Product Information

MK48256 specifications and overview.

Summary

32K x 8 CMOS STATIC RAM

Description

32K x 8 CMOS STATIC RAM

Source title MK48256 Datasheet(PDF) - STMicroelectronics

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