MK3805

MK3805 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 8

Technical content

Features

• Packaged in 20-pin SSOP
• Pb (lead) free package
• Five outputs for each bank with one clock input
• Two separate banks of five outputs each
• Advanced, low-power, CMOS process
• Ten output clocks
• Two separate inputs
• Industrial temperature range -40° C to +85° C
• Hysteresis on all inputs Block Diagram OA0-4

5 OB0-4

BUFFER/CLOCK DRIVER FAN OUT BUFFER IDT™ BUFFER/CLOCK DRIVER 2 MK3805 REV E 051310 Pin Assignment Truth Table Pin Descriptions GND GND GND MON INB OEA OEB INA 3OA1 OA2 OB2

18 OB1

20 VCC

20 pin (150 mil) SSOP/20 pin (300mil) SOIC Inputs Outputs OEA, OEB INA, INB OAN, OBN MON LLLL LHHH HLZL HHZH Pin Number Pin Name Pin Type Pin Description 1 VCC Power Connect to +3.3 V. 2 OA0 Output Clock output. 3 OA1 Output Clock output. 4 OA2 Output Clock output. 5 GND Power Connect to ground. 6 OA3 Output Clock output. 7 OA4 Output Clock output. 8 GND Power Connect to ground. 9O E A Input Tri state output enable input (active low). 10 INA Input Clock input. 11 INB Input Clock input.

12 OEB

Input Tri state output enable input (active low). 13 MON Output Monitor output. 14 OB4 Output Clock output. 15 OB3 Output Clock output. 16 GND Power Connect to ground. 17 OB2 Output Clock output. 18 OB1 Output Clock output. 19 OB0 Output Clock output. 20 VCC Power Connect to +3.3 V.

BUFFER/CLOCK DRIVER FAN OUT BUFFER IDT™ BUFFER/CLOCK DRIVER 3 MK3805 REV E 051310 External Components The MK3805 requires a minimum number of external components for proper operation. Decoupling Capacitors Decoupling capacitors of 0.01µF must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pins as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through the signal layers. Other signal traces should be routed away from the MK3805. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK3805. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85 ° C Storage Temperature -65 to +150 ° C Junction Temperature 125 ° C Soldering Temperature 260 ° C

BUFFER/CLOCK DRIVER FAN OUT BUFFER IDT™ BUFFER/CLOCK DRIVER 4 MK3805 REV E 051310 Recommended Operation Conditions Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40° C to +85° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.13 +3.3 +3.46 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.13 3.3 3.46 V Supply Current IDD No load, OEA ,OEB GND, fo=10MHz, 50% duty cycle 3.3 mA IDD No load, OEA ,OEB GND, fo=2.5MHz, 50% duty cycle 1.8 mA Quiescent Current ICC 3 30 µA Input High Voltage V IH 2V Input Low Voltage V IL 0.8 V Output High Voltage V OH IOH = -4 mA VDD-0.4 V Output High Voltage V OH IOH = -12 mA 2.4 V Output Low Voltage V OL IOL = 12 mA 0.4 V Short Circuit Current I OS CLK output ±50 mA Input Capacitance 5 pF Nominal Output Impedance Z O 20 Ω Input Hysteresis V H 150 mV

BUFFER/CLOCK DRIVER FAN OUT BUFFER IDT™ BUFFER/CLOCK DRIVER 5 MK3805 REV E 051310 Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40° C to +85° C Parameter Symbol Conditions Min. Typ. Max. Units Skew between outputs of same package) tsk(o) CL=50 pF , RL=500Ω 0.5 ns Skew between outputs of different packages at same temp (same transition) tsk (t) CL=50 pF , RL=500Ω 0.8 ns Propagation Delay INA to OAN INB to OBN tPLH, tPHL CL=50 pF , RL=500Ω 1.5 4.5 ns Output Rise Time 0.8 V to 2.0 V tR CL=50 pF , RL=500Ω 2n s Output Fall Time 2.0 V to 0.8 V tF CL=50 pF , RL=500Ω 2n s Output Enable Time OEA to OAN, OEB to OBN CL=50 pF , RL=500Ω 1.5 6.2 ns Output Disable Time OEA to OAN, OEB to OBN CL=50 pF , RL=500Ω 1.5 5.0 ns Duty Cycle Measured at VDD/2 CL=50 pF , RL=500 Ω 45 55 % Operating Frequency CL=50 pF , RL=500 Ω 1 100 MHz

BUFFER/CLOCK DRIVER FAN OUT BUFFER IDT™ BUFFER/CLOCK DRIVER 6 MK3805 REV E 051310 Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK3805RILF MK3805RILF Tubes 20-pin SSOP -40 to +85 ° C MK3805RILFTR MK3805RILF Tape and Reel 20-pin SSOP -40 to +85 ° C INDEX AREA 1 2 D E1 E SEATING PLANE AA2 e - C - b .10 (.004) C c L *For reference only. Controlling dimensions in mm. Millimeters Inches* Symbol Min Max Min Max A 1 . 3 51 . 7 5. 0 5 3. 0 6 9 A1 0.10 0.25 .0040 .010 A2 -- 1.50 -- .059 b 0.20 0.30 0.008 0.012 C 0 . 1 80 . 2 5. 0 0 7. 0 1 0 D 8 . 5 58 . 7 5. 3 3 7. 3 4 4 E 5 . 8 06 . 2 0. 2 2 8. 2 4 4 E1 3.80 4.00 .150 .157 e 0.635 Basic 0.025 Basic L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc. www.idt.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support www.idt.com/go/clockhelp Innovate with IDT and accelerate your future networks. Contact: www.IDT.com MK3805 BUFFER/CLOCK DRIVER FAN OUT BUFFER

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