MK3732-10

MK3732-10 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 9

Technical content

Features

• Packaged in 16 pin SOIC
• Replaces a VCXO and oscillator
• Contains popular multiplier values
• Uses an inexpensive 27 MHz pullable crystal
• Includes popular audio frequencies from 27 MHz
• On-chip patented VCXO with pull range of 230 ppm ±115 ppm) minimum
• VCXO tuning voltage of 0 to 3.3 V
• Advanced, low power, sub-micron CMOS process
• Operating voltage of 3.3 V Block Diagram REF/2 Voltage Controlled Crystal Oscillator VIN 16 - 28 MHz Pullable Crystal PLL/Clock Synthesis Circuitry CLK REF S3:S0 VDD GND OE (all outputs) PDCLK3

VCXO AND MULTIPLIER VCXO AND MULTIPLIER IDT™ VCXO AND MULTIPLIER 2 MK3732-10 REV E 051310 Pin Assignment Clock Select Table VDD VDD OE VIN GND REF/2 REF GND CLK3 PDCLK3 S3 S0

16 Pin (150 mil) SOIC

S3 S2 S1 S0 Input CLK1 CLK2 CLK3 Multiplier 00001 6 - 2 8 R E F / 2 R E F 2 0 - 3 5 x 1 . 2 5 00011 6 - 2 8 R E F / 2 R E F 2 1 - 3 7 . 5 x 1 . 3 3 3 00101 6 - 2 8 R E F / 2 R E F 2 4 - 4 2 x 1 . 5 00111 6 - 2 8 R E F / 2 R E F 3 2 - 5 6 x 2 01001 6 - 2 8 R E F / 2 R E F 4 0 - 7 0 x 2 . 5 01011 6 - 2 8 R E F / 2 R E F 4 2 - 7 5 x 2 . 6 6 7 01101 6 - 2 8 R E F / 2 R E F 4 8 - 8 4 x 3

0111 T E S T

10001 6 - 2 8 R E F / 2 R E F 6 4 - 1 1 2 x 4 10011 6 - 2 8 R E F / 2 R E F 8 0 - 1 4 0 x 5 10101 6 - 2 8 R E F / 2 R E F 8 5 - 1 5 0 x 5 . 3 3 3 10111 6 - 2 7 R E F / 2 R E F 9 6 - 1 6 2 x 6 1100 2 7 1 3 . 5 2 7 1 1 . 2 8 9 N / A 1101 2 7 1 3 . 5 2 7 1 2 . 2 8 8 N / A 1110 2 7 1 3 . 5 2 7 8 . 1 9 2 N / A 1111 2 7 1 3 . 5 2 7 2 4 . 5 7 6 N / A

VCXO AND MULTIPLIER VCXO AND MULTIPLIER IDT™ VCXO AND MULTIPLIER 3 MK3732-10 REV E 051310 Pin Descriptions Pin Descriptions The MK3732-10 requires a minimum number of external components for proper operation. Decoupling Capacitors Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 2 and 5 and pins 3 and 6, as close to the MK3732-10 as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB traces between the clock outputs (CLK, pin 5) and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Quartz Crystal The MK3732-10 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section must be followed. The frequency of oscillation of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The MK3732-10 incorporates on-chip variable load capacitors that “pull” (change) the frequency of the crystal. The crystal specified for use with the MK3732-10 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF . Recommended Crystal Parameters: Initial Accuracy at 25 ° C± 2 0 p p m Temperature Stability ±30 ppm Pin Number Pin Name Pin Type Pin Description 1 XI XI Crystal connection. Connect to a pullable of 16 to 28 MHz cyrstal. 2 - 3 VDD Power Connect to +3.3 V. 4 VIN Input Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency. 5 - 6 GND Power Connect to ground. 7 S3 Input Select input #3. Selects outputs per table above. Internal pull-up resistor. 8 S2 Input Select input #2. Selects outputs per table above. Internal pull-up resistor. 9P D C L K 3 Input Power down for CLK3. 10 S0 Input Select input #0. Selects outputs per table above. Internal pull-up resistor. 11 CLK3 Output PLL output clock that is either a multiple of the input or an audio clock. See table above. 12 REF Output Buffered VCXO reference clock output. Matches crystal frequency. 13 REF/2 Output Reference clock output divided by two. 14 S1 Input Select input #1. Selects outputs per table above. Internal pull-up resistor. 15 OE Input Output enable. Tri-states outputs when low. Internal pull-up resistor. 16 X2 XO Crystal connection. Connect to a pullable 16 to 28 MHz crystal.

VCXO AND MULTIPLIER VCXO AND MULTIPLIER IDT™ VCXO AND MULTIPLIER 4 MK3732-10 REV E 051310 Aging ±20 ppm Load Capacitance 14 pf Shunt Capacitance, C0 7 pF Max C0/C1 Ratio 250 Max Equivalent Series Resistance 35 Ω Max The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the MK3732-10. There should be no via’s between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. See application note MAN05. Crystal Tuning Load Capacitors The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF . The procedure for determining the value of these capacitors can be found in application note MAN05. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK3732-10. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70 ° C Storage Temperature -65 to +150 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 ° C Power Supply Voltage (measured in respect to GND) +3.15 3.3 +3.45 V Reference crystal parameters Refer to pages 3 - 4

VCXO AND MULTIPLIER VCXO AND MULTIPLIER IDT™ VCXO AND MULTIPLIER 5 MK3732-10 REV E 051310 VDD=3.3V ±5% , Ambient temperature 0 to +70° C, unless stated otherwise VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Note 1: External crystal device must conform with Pullable Crystal Specifications listed on pages 3-4. Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.15 3.3 3.45 V Input High Voltage V IH X1 pin, clock in Non VCXO mode (VDD/2)+1 V Input Low Voltage V IL X1 pin, clock in Non VCXO mode (VDD/2)-1 V Input High Voltage V IH 2V Input Low Voltage V IL 0.8 V Output High Voltage V OH IOH = -12 mA 2.4 V Output Low Voltage V OL IOL = 12 mA 0.4 V Output High Voltage (CMOS Level) VOH IOH = -4 mA -0.5 V Operating Supply Current IDD No Load 19 mA Short Circuit Current Each output ±50 mA Input Capacitance C IN S2:S0, OE 5 pF Frequency Synthesis Error All clocks 0 ppm VIN, VCXO Control Voltage V IA 03 . 3 V Parameter Symbol Conditions Min. Typ. Max. Units Input Crystal Frequency f IN 16 27 28 MHz Output Clock Frequency f OUT 8 162 MHz Output Clock Rise Time 0.8 to 2.0V 1.5 ns Output Clock Fall Time 2.0 to 0.8V 1.5 ns Output Clock Duty Cycle at VDD/2 40 60 % Maximum Absolute Jitter ±350 ps Output pullability 0V < VI N < 3.3V, Note 1 ±115 ppm

VCXO AND MULTIPLIER VCXO AND MULTIPLIER IDT™ VCXO AND MULTIPLIER 6 MK3732-10 REV E 051310 Thermal Characteristics Marking Diagram Notes: YYWW is the last two digits of the year and the week number that the part was assembled Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 120 ° C/W θJA 1 m/s air flow 115 ° C/W θJA 3 m/s air flow 105 ° C/W Thermal Resistance Junction to Case θJC 58 ° C/W MK3732-10S YYWW

VCXO AND MULTIPLIER VCXO AND MULTIPLIER IDT™ VCXO AND MULTIPLIER 7 MK3732-10 REV E 051310 Package Outline and Package Dimensions (16 pin SOIC) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping packaging Package Temperature MK3732-10SLF MK3732-10LF Tubes 16 pin SOIC 0 to +70° C MK3732-10SLFTR MK3732-10LF Tape and Reel 16 pin SOIC 0 to +70 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 9.80 10.00 .3859 .3937 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

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