MK28FN2M0ACAU15R

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 87

Technical content

Kinetis K28F MCU Sub-Family High performance ARM® Cortex®-M4 MCU with 2 MB Flash,

1 MB SRAM, 2 USB Controllers (High-Speed and Full-

Speed), SDRAM controller, QuadSPI interface and Power Management Controller with Core Voltage Bypass. K28F extends the Kinetis Micontroller portfolio with large embedded memory, advanced external memory interfaces, performance, and peripheral integration while maintaining a high level of software compatibility with previous Kinetis devices:

• The extended memory resources include a total of 2 MB of programmable flash and 1 MB of embedded SRAM which can be used to support application needs for data logging and rich human to machine interfaces with displays
• The Power Management Controller with Core Voltage Bypass enables the use of an external PMIC to maximize the power efficiency of the system
• K28F enables memory expansion leveraging the SDRAM controller and QuadSPI interface for eXecution-In-Place (XIP) from an external Serial NOR flash
• Both the USB High-Speed and Crystal-less Full-Speed Controllers integrate a PHY to reduce BOM cost
• The integrated smart peripherals such as Low-power UARTs and Timers operate in very low-power modes to optimize battery life of the system Performance
• Up to 150 MHz ARM Cortex-M4 based core with DSP instructions and Single Precision Floating Point unit (FPU) Memories and memory expansion
• 2 MB dual bank program flash and 1 MB SRAM
• 8 KB I/D + 8 KB System cache
• 32-bit external bus interface (FlexBus)
• 32-bit SDRAM controller
• Dual QuadSPI interface with eXecution-In-Place (XIP)
• supports SDR and DDR serial flash and octal configurations
• 32 KB Boot ROM with built-in bootloader System and Clocks
• 32-ch Asynchronous DMA
• Multiple low-power modes
• Memory protection unit with multi-master protection
• 3 to 32 MHz main crystal oscillator
• 32 kHz low power crystal oscillator
• 48 MHz internal reference
• Hardware and Software Watchdogs Human-machine interface
• Up to 120 General-purpose input/output (GPIOs) Analog modules
• Power Management Control (PMC) with Core Voltage Bypass
• One 16-bit SAR ADCs, two 6-bit DAC and one 12-bit DAC
• Two analog comparators (CMP) containing a 6-bit DAC and programmable reference input
• 1.2 V Voltage reference Timers
• One 4-ch 32-bit Periodic interrupt timer
• Two 16-bit low-power timer PWM modules
• Two 8-ch motor control/general purpose/PWM timers
• Two 2-ch quadrature decoder/general purpose timers
• Real-time clock with independent 3.6 V power domain
• Programmable delay block Operating Characteristics
• Temperature range (ambient): -40 to 105°C (BGA) Temperature range (ambient):-40 to 85°C (WLCSP)
• V DD Voltage/Flash write voltage range:1.71 V–3.6 V MK28FN2M0ACAU15R MK28FN2M0AVMI15

169 MAPBGA (MI)

9 x 9 x 1.28 mm Pitch 0.65 mm

210 WLCSP (AU)

6.9 mm x 6.9 x 0.6 mm Pitch 0.4 mm NXP Semiconductors K28P210M150SF5V2 Data Sheet: Technical Data Rev. 0, 08/2017 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

• Hardware random-number generator
• Memory Mapped Crypto Acceleration Unit(MMCAU): DES, 3-DES, AES, SHA-1, SHA-256 and MD5 accelerator
• Cyclic Redundancy Check (CRC) Target Applications
• Wearables
• Low-end graphic display system
• Cost-optimized multi-standard wireless smart home hubs
• Home Automation devices
• Consumer accessories
• V DD_CORE: 1.17 V–1.47 V
• Independent V DDIO_E (QuadSPI):1.71 V–3.6 V
• Independent V BAT (RTC): 1.71 V–3.6 V
• I/O Voltage range (V DD): 1.71 V–3.6 V Communication interfaces
• Two USB controllers:Crystal-less Full-/low-speed + transceiver Host and Device; High-/Full-/low-speed + PHY Host and Device
• Secure Digital Host Controller (SDHC)
• Two I2S modules, four I2C modules and five Low- Power UART modules
• Four SPI modules (SPI3 supports more than 40 Mbps)
• 32-ch Programmable module (FlexIO) to emulate various serial, parallel or custom interfaces Ordering Information 1 Part Number Embedded Memory Package Type Maximum number of I\\O'sFlash SRAM MK28FN2M0AVMI15 2 MB 1 MB 169 MAPBGA 120 MK28FN2M0ACAU15R 2 MB 1 MB 210 WLCSP 120 1. To confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. Device Revision Number Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN] 3N96T 0011 0011 Related Resources Type Description Resource Fact Sheet The Fact Sheet gives overview of the product key features and its uses. K2x Fact Sheet Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K28P210M150SF5RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. This document Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_K_3N96T1 Package drawing Package dimensions are provided in package drawings. • MAPBGA 169-pin: 98ASA00628D1
• WLCSP 210-pin: 98ASA01002D 1 1. To find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

256 KByte

8 Kbyte

48 MHz

4 MHzPLL FLLDMA

512 KByte

4 KByte

Figure 1. K28F Block Diagram

1.4.1 Recommended Power-On-Reset (POR)

2.2.6 Electromagnetic Compatibility (EMC)

3.6.1 USB Voltage Regulator electrical specifications..61

3.6.2 USB Full Speed Transceiver and High Speed

3.6.4 DSPI switching specifications (limited voltage

3.6.5 DSPI switching specifications (full voltage

5.2 Recommended connection for unused analog and

8.4 Relationship between ratings and operating

4 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level (for V-temp variant) — 3 — 1 MSL Moisture sensitivity level (for C-temp variant) — 1 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current maximum ratings

Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 5 NXP Semiconductors

1. VDD_CORE must not exceed VDD on power up or power down
2. VDDIO_E is independent of the VDD domain and can operate at a voltage independent of VDD.

1.4.1 Recommended Power-On-Reset (POR) Sequencing

• V DD/VDDIO_E and VDD_CORE

Figure 2. VDD_CORE/ VDD Powering sequence

2 General

2.1 AC electrical characteristics

Figure 3. Input signal measurement reference

• have C L=15 pF loads,
• are slew rate disabled, and
• are normal drive strength 2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements Table continues on the next page...

Table 1. Voltage and current operating requirements (continued)

• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
• 2.7 V ≤ V DD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VIH_E Input high voltage
• 2.7 V ≤ V DDIO_E ≤ 3.6 V
• 1.7 V ≤ V DDIO_E ≤ 2.7 V 0.7 × VDDIO_E 0.75 × VDDIO_E V V VIL_E Input low voltage
• 2.7 V ≤ V DDIO_E ≤ 3.6 V
• 1.7 V ≤ V DDIO_E ≤ 2.7 V 0.35 × VDDIO_E 0.3 × VDDIO_E V V VHYS Input hysteresis 0.06 × VDD — V VHYS_E Input hysteresis 0.06 × VDDIO_E — V IICIO I/O pin negative DC injection current — single pin
• V IN < VSS-0.3V -5 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
• Negative current injection -25 — mA VODPU Pseudo Open drain pullup voltage level VDD VDD V 2 VRAM VDD_CORE voltage required to retain RAM 1.14 1.47 V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD or VDDIO_E. If VIN is less than -0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(-0.3-VIN)/|IICIO|. The actual resistor value should be an order of magnitude higher to tolerate transient voltages. 2. Open drain outputs must be pulled to VDD. General 8 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

2.2.2 HVD, LVD and POR operating requirements

Table 2. V DD supply HVD, LVD and POR operating requirements

• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 60 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 40 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage NOTE There is no LVD circuit for VDDIO_E and VDD_CORE domain.

Table 3. VBAT power operating requirements

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

• 2.7 V ≤ V BAT ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOH = -2.5 mA IO Groups 2 and 3
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -10 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -5 mA IO Group 4
• 2.7 V ≤ V DDIO_E ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ V DDIO_E ≤ 2.7 V, IOH = -2.5 mA VBAT – 0.5 VBAT – 0.5 VDD – 0.5 VDD – 0.5 VDDIO_E – 0.5 VDDIO_E – 0.5 V V V V V V 2, 3 Output high voltage — High drive strength IO Group 3
• 2.7 V ≤ V DD ≤ 3.6 V, IOH = -20 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -10 mA IO Group 4
• 2.7 V ≤ V DDIO_E ≤ 3.6 V, IOH = -15 mA
• 1.71 V ≤ V DDIO_E ≤ 2.7 V, IOH = -7.5 mA VDD – 0.5 VDD – 0.5 VDDIO_E – 0.5 VDDIO_E – 0.5 V V V V IOHT Output high current total for all ports — — 100 mA VOL Output low voltage — normal drive strength IO Group 1
• 2.7 V ≤ V BAT ≤ 3.6 V, IOL = -5 mA
• 1.71 V ≤ V BAT ≤ 2.7 V, IOL = -2.5 mA IO Groups 2 and 3
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = -10 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = -5 mA IO Group 4
• 2.7 V ≤ V DDIO_E ≤ 3.6 V, IOL = -5 mA
• 1.71 V ≤ V DDIO_E ≤ 2.7 V, IOL = -2.5 mA 0.5 0.5 0.5 0.5 0.5 0.5 V V V V V V 2, 4, 5 Output low voltage — High drive strength IO Group 3
• 2.7 V ≤ V DD ≤ 3.6 V, IOL = -20 mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = -10 mA IO Group 4
• 2.7 V ≤ V DDIO_E ≤ 3.6 V, IOL = -15 mA
• 1.71 V ≤ V DDIO_E ≤ 2.7 V, IOL = -7.5 mA 0.5 0.5 0.5 0.5 V V V V 2, 4 IOLT Output low current total for all ports — — 100 mA IIN Input leakage current 6, 7, 8 Table continues on the next page... General 10 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

Table 4. Voltage and current operating behaviors (continued)

• V SS ≤ VIN ≤ VDD PORTE pins
• V SS ≤ VIN ≤ VDDIO_E VBAT domain pins
• V SS ≤ VIN ≤ VBAT 0.002 0.002 0.002 0.5 0.5 0.5 µA µA µA RPU Internal pullup resistors(except RTC_WAKEUP pins) 20 — 50 kΩ 9 RPD Internal pulldown resistors (except RTC_WAKEUP pins) 20 — 50 kΩ 10 1. Typical values characterized at 25°C and VDD = 3.6V unless otherwise noted. 2. IO Group 1 includes VBAT domain pins: RTC_WAKEUP_b. IO Group 2 includes VDD domain pins: PORTA, PORTB, PORTC, and PORTD, except PTA4. IO Group 3 includes VDD domain pins: PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7. IO Group 4 includes VDDIO_E domain pins: PORTE. 3. PTA4 has lower drive strength: IOH = -5 mA for high VDD range; IOH = -2.5 mA for low VDD range. 4. Open drain outputs must be pulled to VDD. 5. PTA4 has lower drive strength: IOL = 5mA for high VDD range; IOL = 2.5mA for low VDD range. 6. VDD domain pins include ADC, CMP, and RESET_b inputs. Measured at VDD = 3.6V. 7. PORTE analog input voltages cannot exceed VDDIO_E supply when VDD ≥ VDDIO_E. PORTE analog input voltages cannot exceed VDD supply when VDD ˂ VDDIO_E. 8. VBAT domain pins include EXTAL32, XTAL32, and RTC_WAKEUP_b pins. 9. Measured at minimum supply voltage and VIN = VSS 10. Measured at minimum supply voltage and VIN = VDD

2.2.4 Power mode transition operating behaviors

• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode=FEI NOTE VLLS1 and VLLS0 are not supported. General Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 11 NXP Semiconductors

Table 5. Power mode transition operating behaviors temperature range of the chip.

• VLLS2 –> RUN — 103 µs
• VLLS3 –> RUN — 103 µs
• LLS2 –> RUN — 6.3 µs
• LLS3 –> RUN — 6.3 µs
• VLPS –> RUN — 5.4 µs
• STOP –> RUN — 5.4 µs

2.2.5 Power consumption operating behaviors

Figure 4. Power Supplies of K28F

• On top of the device’s IDD current consumption, external loads applied to Ports A,B,C and D need to be considered
• IDDIO_E current consumption is significantly dependent on external loads applied to Port E pins, and the internal current consumption in the device is negligible compared to IDD.
• The USB_VREG provides a 3.3 V output which can drive loads of upto 150 mA need to be considered. The maximum values stated in the following table represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 6 details the IDDC values observed through the VDD_CORE supply and Table 7 details the IDD values observed through the VDD supply.

Table 6. Power consumption operating behaviors (through VDD_CORE)

• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 31.0 37.9 42.7 51.9 35.1 51.6 63.6 85.7 mA IDDC_RUN Run mode current — all peripheral clocks enabled, code of while(1) loop executing from internal flash at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 41.6 48.0 52.6 61.1 47.1 65.5 78.4 100.9 mA IDDC_RUNCO Run mode current in compute operation - 120 MHz core / 24 MHz flash / bus clock disabled, code of while(1) loop executing from internal flash at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 28.5 35.5 40.3 49.5 32.4 48.4 60.1 81.6 mA Table continues on the next page... General Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 13 NXP Semiconductors

Table 6. Power consumption operating behaviors (through VDD_CORE) (continued)

• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 42.6 53.5 59.7 71.7 49.6 74.9 91.3 121.0 mA IDDC_HSRUN High-speed Run mode current — all peripheral clocks enabled, code of while(1) loop executing from internal flash at 1.4 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 54.3 65.7 71.5 82.6 63.3 91.9 109.8 139.0 mA IDDC_HSRUNCO High-speed Run mode current in compute operation – 150 MHz core/ 25 MHz flash / bus clock disabled, code of while(1) loop executing from internal flash at 1.4 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 40.5 50.7 57.1 68.7 47.2 70.9 87.2 115.7 mA IDDC_WAIT Wait mode high frequency current at 1.2 V— all peripheral clocks disabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 15.6 23.2 28.3 38.1 17.7 31.6 42.2 62.8 mA IDDC_WAIT Wait mode reduced frequency current at 1.2 V— all peripheral clocks disabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 7.0 15.0 20.3 30.5 7.9 20.4 30.3 50.4 mA IDDC_VLPR Very-low-power run mode current at 1.2 V — all peripheral clocks disabled, code of while(1) loop executing out of internal flash — 1.2 3.9 mA Table continues on the next page... General 14 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.6 3.8 6.2 7.1 9.7 15.0 IDDC_VLPR Very-low-power run mode current at 1.2 V — all peripheral clocks enabled, code of while(1) loop executing out of internal flash
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 1.7 3.1 4.3 6.7 5.5 8.5 11.0 16.2 mA IDDC_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 1 MHz flash / bus clock disabled, code of while(1) loop executing from internal flash at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 1.1 2.5 3.7 6.1 3.6 6.9 9.5 14.8 mA IDDC_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 4.4 9.8 13.0 15.7 14.2 26.5 33.4 37.9 mA IDDC_VLPW Very-low-power wait mode current at 1.2 V — all peripheral clocks disabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 0.759 2.2 3.3 5.8 2.5 5.9 8.6 14.0 mA IDDC_VLPW Very-low-power wait mode current at 1.2 V— all peripheral clocks enabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 1.2 2.7 3.8 6.3 4.0 7.2 9.8 15.1 mA IDDC_STOP Stop mode current at 1.2 V Table continues on the next page... General Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 15 NXP Semiconductors

• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 0.749 3.4 5.4 9.1 1.9 7.5 11.3 18.7 mA IDDC_VLPS Very-low-power stop mode current at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 0.452 2.2 3.4 5.8 1.2 4.9 7.4 12.4 mA IDDC_LLS3 Low leakage stop mode current at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 15.6 129.0 244.9 535.0 30.3 189.5 347.8 737.3 μA IDDC_LLS2 Low leakage stop mode current at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 4.3 33.8 62.8 135.6 8.7 57.3 104.0 205.8 μA IDDC_VLLS3 Very low-leakage stop mode 3 current at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 13.5 112.1 212.5 460.2 26.0 159.7 294.7 621.6 μA IDDC_VLLS2 Very low-leakage stop mode 2 current at 1.2 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 0.552 6.1 10.5 24.7 0.9 8.2 14.2 32.3 μA IDD_VBAT Average current with RTC and 32 kHz disabled @ 3.0 V
• @ 25°C
• @ 70°C 0.266 0.595 0.319 0.750 μA Table continues on the next page... General 16 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

• @ 85°C
• @ 105°C 0.933 2.2 1.3 2.8 IDD_VBAT Average current when CPU is not accessing RTC registers @ 1.8 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 0.454 0.724 1.1 2.0 0.546 0.897 1.4 2.6 μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. 3. MCG configured for PEE mode. 4. 150 MHz core and system clock, 50 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. 5. 25 MHz core and system clock, 25 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for FEI mode 6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode using an 8 MHz external reference clock. Code executing from flash. 7. MCG configured for BLPE mode using an 8 MHz external reference clock. 8. By default, this mode only has 32 K of SRAM enabled. 9. Includes 32 kHz oscillator current and RTC operation.

Table 7. Power consumption operating behaviors (through VDD)

• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 mA IDD_RUN Run mode current — all peripheral clocks enabled, code of while(1) loop executing from internal flash @ 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 mA Table continues on the next page... General Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 17 NXP Semiconductors

Table 7. Power consumption operating behaviors (through VDD) (continued)

• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 1.5 1.5 1.6 1.6 1.6 1.7 1.7 1.7 mA IDD_HSRUN Run mode current — all peripheral clocks disabled, code of while(1) loop executing from internal flash @ 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 mA IDD_HSRUN Run mode current — all peripheral clocks enabled, code of while(1) loop executing from internal flash @ 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 mA IDD_HSRUNCO HSRun mode current in compute operation – 150 MHz core/ 25 MHz flash / bus clock disabled, code of while(1) loop executing from internal flash at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 mA Table continues on the next page... General 18 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.0 2.0 2.0 2.0 2.1 2.1 2.1 2.1 mA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 24.9 31.2 39.6 63.9 48.0 70.1 84.5 157.5 µA IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks enabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 25.2 31.5 40.0 64.3 48.6 70.6 85.0 158.4 µA IDD_VLPRCO Very-low-power run mode current in compute operation - 4 MHz core / 0.8 MHz flash / bus clock disabled, while(1) code executing from internal flash at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 8.3 14.4 22.7 47.0 16.0 32.3 48.5 115.8 µA IDD_PSTOP2 Stop mode current with partial stop 2 clocking option - core and system disabled / 10.5 MHz bus at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 1.8 1.8 1.9 1.9 3.5 4.1 3.9 4.6 mA IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled
• @ 25°C
• @ 70°C 24.9 31.0 47.8 69.5 µA Table continues on the next page... General Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 19 NXP Semiconductors

• @ 85°C
• @ 105°C 39.2 63.7 83.6 157.0 IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks enabled
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 25.0 31.2 39.6 63.9 48.1 70.0 84.3 157.5 µA IDD_STOP Stop mode current at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 159.3 173.8 181.4 251.2 279.3 341.8 358.4 735.0 µA IDD_VLPS Very-low-power stop mode current at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 3.1 8.5 15.2 36.9 5.6 12.0 19.4 43.9 μA IDD_LLS3 Low leakage stop mode current at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.9 7.2 13.2 33.4 4.7 9.2 16.1 39.4 μA IDD_LLS2 Low leakage stop mode current at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.9 7.2 13.2 33.4 4.7 9.2 16.1 39.4 μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• @ 25°C
• @ 70°C 2.2 4.7 3.4 6.4 μA Table continues on the next page... General 20 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

• @ 85°C
• @ 105°C 8.1 18.8 10.6 23.8 IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
• @ 25°C
• @ 70°C
• @ 85°C
• @ 105°C 2.2 4.5 7.7 17.5 3.3 6.1 10.0 22.0 μA 1. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. 2. MCG configured for PEE mode. 3. 150 MHz core and system clock, 50 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for PEE mode. 4. 25 MHz core and system clock, 25 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for FEI mode. 5. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode using an 8 MHz external reference clock. Code executing from flash. 6. MCG configured for BLPE mode using an 8 MHz external reference clock. 7. By default, this mode has only 32K of SRAM enabled. Below table list the current consumption adders for different SRAM configurations from the LLS2/VLLS2 (TYP) IDD values using a 32 KB SRAM retention referenced in Table 6.

Table 8. LLS2/VLLS2 additional Typical IDDC current consumption Adders Table continues on the next page...

Table 8. LLS2/VLLS2 additional Typical IDDC current consumption Adders (continued) Table 9. Low power mode peripheral adders — typical value IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder. IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder. IEREFSTEN4MHz External 4 MHz crystal clock adder. modes with the crystal enabled. clock source power consumption. Table continues on the next page...

Table 9. Low power mode peripheral adders — typical value (continued) placing the device in STOP or VLPS mode.

2.2.6 Electromagnetic Compatibility (EMC) specifications

EMC measurements to IC-level IEC standards are available from NXP on request.

2.2.7 Designing with radiated emissions in mind

interference from radiated emissions.

1. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 10. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 11. Device clock specifications

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

2.3.2 General switching specifications

LPUART, CMT, timers, and I2C signals. Table 12. General switching specifications Table continues on the next page...

Table 12. General switching specifications (continued)

• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7 V
• 2.7 ≤ V DD ≤ 3.6 V ns ns ns ns 4, 5 Port rise and fall time (low drive strength)
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7 V
• 2.7 ≤ V DD ≤ 3.6 V
• Slew disabled
• 1.71 ≤ V DD ≤ 2.7 V
• 2.7 ≤ V DD ≤ 3.6 V ns ns ns ns 6, 7 Port rise and fall time (high drive strength)
• Slew enabled
• 1.71 ≤ V DDIO_E ≤ 2.7 V
• 2.7 ≤ V DDIO_E ≤ 3.6 V
• Slew disabled
• 1.71 ≤ V DDIO_E ≤ 2.7 V
• 2.7 ≤ V DDIO_E ≤ 3.6 V ns ns ns ns 5, 8 Port rise and fall time (low drive strength)
• Slew enabled
• 1.71 ≤ V DDIO_E ≤ 2.7 V
• 2.7 ≤ V DDIO_E ≤ 3.6 V
• Slew disabled
• 1.71 ≤ V DDIO_E ≤ 2.7 V
• 2.7 ≤ V DDIO_E ≤ 3. 6V ns ns ns ns 7, 8 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7. 5. 75 pF load. 6. Ports A, B, C, and D. 7. 25 pF load. General Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 25 NXP Semiconductors

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 13. Thermal operating requirements (for V-Temp range)

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

Table 14. Thermal operating requirements (for C-Temp range)

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

2.4.2 Thermal attributes

Table 15. Thermal attributes Table continues on the next page...

Table 15. Thermal attributes (continued)

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.

1. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

1. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

between the top of the package and the cold plate.

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 16. Debug trace operating behaviors

Figure 5. TRACE_CLKOUT specifications Figure 6. Trace data specifications

3.1.2 JTAG electricals

Table 17. JTAG limited voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.0 — ns J7 TCLK low to boundary scan output data valid — 28 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns Table continues on the next page... Peripheral operating requirements and behaviors 28 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

Table 17. JTAG limited voltage range electricals (continued) Table 18. JTAG full voltage range electricals

• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug 12.5 ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.0 — ns J7 TCLK low to boundary scan output data valid — 30.6 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.0 — ns J11 TCLK low to TDO data valid — 19.0 ns J12 TCLK low to TDO high-Z — 17.0 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns J3 J3 J4 J4 TCLK (input)

Figure 7. Test clock input timing

Figure 10. TRST timing

3.2 Clock modules

3.2.1 MCG specifications

Table 19. MCG specifications Table continues on the next page...

Table 19. MCG specifications (continued) Table continues on the next page...

• f DCO = 48 MHz
• f DCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fpll_ref PLL reference frequency range 8 — 16 MHz fvcoclk_2x VCO output frequency 180 — 360 MHz fvcoclk PLL output frequency 90 — 180 MHz fvcoclk_90 PLL quadrature output frequency 90 — 180 MHz Ipll PLL operating current
• VCO @ 176 MHz (f pll_ref = 8 MHz, VDIV multiplier = 22, PRDIV divide=1) — 1.1 — mA 8 Ipll PLL operating current
• VCO @ 360 MHz (f pll_ref = 8 MHz, VDIV multiplier = 45, PRDIV divide=1) — 2 — mA 8 Jcyc_pll PLL period jitter (RMS)
• f vco = 180 MHz
• f vco = 360 MHz 100 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
• f vco = 180 MHz
• f vco = 360 MHz 600 300 ps ps Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 Peripheral operating requirements and behaviors Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 33 NXP Semiconductors

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency

deviation (Δfdco_t) over voltage and temperature should be considered.

1. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
2. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
3. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

1. Excludes any oscillator currents that are also consuming power while PLL is in operation.
2. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

1. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL

specification assumes it is already running.

3.2.2 IRC48M specifications

Table 20. IRC48M specifications

• Regulator disable (USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 0.5 ± 1.0 ± 1.5 %firc48m Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at high voltage (VDD=1.89 V-3.6 V) over temperature
• Regulator enable (USB_CLK_RECOVER_IRC_EN[REG_EN]=1) ± 0.5 ± 1.0 %firc48m Δfirc48m_cl Closed loop total deviation of IRC48M frequency over voltage and temperature — — ± 0.1 %fhost 1 Jcyc_irc48m Period Jitter (RMS) — 35 150 ps tirc48mst Startup time — 2 3 μs 2 1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1). 2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11 Peripheral operating requirements and behaviors 34 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

3.2.3 Oscillator electrical specifications

3.2.3.1 Oscillator DC electrical specifications

Table 21. Oscillator DC electrical specifications

• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 600 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 7.5 500 650 2.5 3.25 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low- power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 35 NXP Semiconductors

Table 21. Oscillator DC electrical specifications (continued)

1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.2.3.2 Oscillator frequency specifications

Table 22. Oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.

1. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

and cannot be moved into high power/gain mode. Table 23. 32kHz oscillator DC electrical specifications

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. Table 24. 32 kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

1. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the

applied clock must be within the range of VSS to VBAT.

3.3 Memories and memory interfaces

3.3.1 QuadSPI AC specifications

• All data is based on a negative edge data launch from the device and a positive edge data capture, as shown in the timing diagrams in this section.
• Measurements are with a load of 15 pf (1.8 V) and 35 pf (3 V) on output pins. Input slew: 1 ns
• Timings assume a setting of 0x0000_000x for QuadSPI _SMPR register (see the reference manual for details). The following table lists the QuadSPI delay chain read/write settings. Refer the device reference manual for register and bit descriptions.

Table 25. QuadSPI delay chain read/write settings Figure 11. QuadSPI input timing (SDR mode) diagram

• The below timing values are with default settings for sampling registers like QuadSPI_SMPR. Peripheral operating requirements and behaviors 38 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

• A negative time indicates the actual capture edge inside the device is earlier than clock appearing at pad.
• The below timing are for a load of 15 pf (1.8 V) and 35 pf (3 V) or output pads
• All board delays need to be added appropriately
• Input hold time being negative does not have any implication or max achievable frequency

Table 26. QuadSPI input timing (SDR mode) specifications Figure 12. QuadSPI output timing (SDR mode) diagram Table 27. QuadSPI output timing (SDR mode) specifications

Figure 13. QuadSPI input timing (DDR mode) diagram

• Numbers are for a load of 15 pf (1.8 V) and 35 pf (3 V)
• The numbers are for setting of hold condition in register QuadSPI_SMPR[DDRSNP]

Table 28. QuadSPI input timing (DDR mode) specifications

Figure 14. QuadSPI output timing (DDR mode) diagram Table 29. QuadSPI output timing (DDR mode) specifications

Table 31. QuadSPI output timing (Hyperflash mode) specifications (continued) Maximum clock frequency = 75 MHz.

3.3.2 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

3.3.2.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 32. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

3.3.2.2 Flash timing specifications — commands

Table 33. Flash command timing specifications

• 512 KB program flash 1.8 ms trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs Erase Flash Block execution time 2 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 43 NXP Semiconductors

Table 33. Flash command timing specifications (continued)

• control code 0x01
• control code 0x02
• control code 0x04
• control code 0x08
• control code 0x10 200 150 150 150 μs μs μs μs μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3.3.2.3 Flash high voltage current behaviors

Table 34. Flash high voltage current behaviors

3.3.2.4 Reliability specifications

Table 35. NVM reliability specifications

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.

3.3.3 Flexbus switching specifications

relationships can be derived from these values. Table 36. Flexbus limited voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 37. Flexbus full voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
2. Specification is valid for all FB_AD[31:0] and FB_TA.

Figure 17. FlexBus read timing diagram

Figure 18. FlexBus write timing diagram

3.3.4 SDRAM controller specifications

Following figure shows SDRAM read cycle.

Figure 19. SDRAM read timing diagram Table 38. SDRAM Timing (Full voltage range)

1. All timing specifications are based on taking into account, a 25 pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz

1. D7 and D8 are for write cycles only.

Table 39. SDRAM Timing (Limited voltage range)

1. All timing specifications are based on taking into account, a 25 pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz
3. D7 and D8 are for write cycles only.

Following figure shows an SDRAM write cycle.

1 DACR[CASL] = 2

Figure 20. SDRAM write timing diagram

3.4 Analog

3.4.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0.

Table 40. 16-bit ADC operating conditions

1.13 VDDA VDDA V

• All other modes VREFL VREFL 31/32 × VREFH VREFH V CADIN Input capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 818.330 kS/s Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 461.467 kS/s 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Peripheral operating requirements and behaviors Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 51 NXP Semiconductors

Figure 21. ADC input impedance equivalency diagram Table 41. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes
• <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes
• <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes — ±1.0 –2.7 to +1.9 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors 52 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

Table 41. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• <12-bit modes — ±0.5 –0.7 to +0.5 EFS Full-scale error • 12-bit modes
• <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
• ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
• Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
• Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. Peripheral operating requirements and behaviors Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 53 NXP Semiconductors

3.4.2 CMP and 6-bit DAC electrical specifications

Table 42. Comparator and 6-bit DAC electrical specifications

• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 55 NXP Semiconductors

Figure 24. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

Figure 25. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 43. 12-bit DAC operating requirements

1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

Table 44. 12-bit DAC operating behaviors

• High power (SP HP)
• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
• High power (SP HP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV Peripheral operating requirements and behaviors 58 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

1. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC

Figure 26. Typical INL error vs. digital code

Figure 27. Offset at half scale vs. temperature

3.4.4 Voltage reference electrical specifications

Table 45. VREF full-range operating requirements

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range

Table 46. VREF full-range operating behaviors

• current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms — Vvdrift Voltage reference voltage drift (Vmax -Vmin) due to variation of VDDA between 1.9V-1.71V — 0.5 2 mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load.

3.5 Timers

See General switching specifications.

3.6 Communication interfaces

3.6.1 USB Voltage Regulator electrical specifications

Table 47. USB VREG electrical specifications Table continues on the next page...

• VREG_IN*= 5.0 V and temperature=25 °C — 680 920 nA ILOADrun Maximum load current — Run mode — — 150 mA 3 ILOADstby Maximum load current — Standby mode — — 1 mA VDROPOUT Regulator drop-out voltage — Run mode at maximum load current with inrush current limit disabled 300 — — mV VREG_OUT Regulator programmable output target voltage — Selected input supply > programmed output target voltage + VDROPOUT
• Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 350 — mA 5 IINRUSH Inrush current limit 40 — 100 mA 6, 7, 8, 1. Typical values assume the selected input supply is 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operation range is 2.7 V to 5.5 V; tolerance voltage is up to 6 V. 3. 150mA is inclusive of the run mode current of the on-chip USB modules. Available load outside of the chip depends on USB operation and device power dissipation limits. 4. The target voltage for the regulator is programmable, accounting for the range of the max and min values. 5. Current limit disabled. 6. Current limit should be disabled after the powers have stabilized to allow full functionality of the regulator. 7. Limited Characterization 8. IINRUSH with VREGINx=4.0 V to 5.5 V 9. Total current load on startup should be less than IINRUSH min over full input voltage range of the regulator. Peripheral operating requirements and behaviors 62 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

3.6.2 USB Full Speed Transceiver and High Speed PHY

Specification with the amendments below.

• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
• Revision 2.0 version 1.1a July 27, 2012
• Battery Charging Specification (available from USB-IF)
• Revision 1.2 (including errata and ECNs through March 15, 2012), March 15, 2012 USB1_VBUS pin is a detector function which is 5v tolerant and complies with the above specifications without needing any external voltage division components.

3.6.3 USB DCD electrical specifications

Table 48. USB DCD electrical specifications Table continues on the next page...

3.6.4 DSPI switching specifications (limited voltage range)

formats used for communicating with slower peripheral devices. Table 49. Master mode DSPI timing (limited voltage range)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 28. DSPI classic SPI timing — master mode Table 50. Slave mode DSPI timing (limited voltage range)

1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

when bus clock is 60MHz, SPI clock should not be greater than 10MHz.

Figure 29. DSPI classic SPI timing — slave mode Table 51. Master mode DSPI3 timing (limited voltage range)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Table 52. Slave mode DSPI3 timing (limited voltage range) Table continues on the next page...

Table 52. Slave mode DSPI3 timing (limited voltage range) (continued)

1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

when bus clock is 60MHz, SPI clock should not be greater than 10MHz.

3.6.5 DSPI switching specifications (full voltage range)

formats used for communicating with slower peripheral devices. Table 53. Master mode DSPI timing (full voltage range)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Table 55. Master mode DSPI3 timing (full voltage range)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Table 56. Slave mode DSPI3 timing (full voltage range)

1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with

example,when bus clock is 60MHz, SPI clock should not be greater than 10MHz.

3.6.6 Inter-Integrated Circuit Interface (I2C) timing

Table 57. I 2C timing Table continues on the next page...

Table 57. I 2C timing (continued) Hold time (repeated) START condition.

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

1. Cb = total capacitance of the one bus line in pF.

Table 58. I 2C 1 Mbps timing period, the first clock pulse is generated. Table continues on the next page...

Table 58. I 2C 1 Mbps timing (continued)

1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins

across the full voltage range.

1. Cb = total capacitance of the one bus line in pF.

Figure 32. Timing definition for devices on the I2C bus

3.6.7 LPUART switching specifications

See General switching specifications.

3.6.8 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 59. SDHC full voltage range switching specifications Table continues on the next page...

Table 60. SDHC limited voltage range switching specifications

Figure 33. SDHC timing

3.6.9 I2S switching specifications

the frame sync (I2S_FS) shown in the figures below. Table 61. I2S master mode timing (limited voltage range)

Figure 34. I2S timing — master mode Table 62. I2S slave mode timing (limited voltage range)

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 35. I2S timing — slave modes

3.6.9.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 63. I2S/SAI master mode timing

Figure 36. I2S/SAI timing — master modes Table 64. I2S/SAI slave mode timing

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 37. I2S/SAI timing — slave modes

3.6.9.2 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 65. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Figure 38. I2S/SAI timing — master modes Table 66. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Figure 39. I2S/SAI timing — slave modes

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

5 Pinout

5.1 K28F Signal Multiplexing and Pin Assignments

1. Click the paperclip symbol on the left side of the PDF window.
2. Double-click on the Excel file to open it.

5.2 Recommended connection for unused analog and digital

Table 67. Recommended connection for unused analog interfaces Table continues on the next page...

Table 67. Recommended connection for unused analog interfaces (continued)

5.3 K28F Pinouts

1. Click the paperclip symbol on the left side of the PDF window.
2. Double-click on the Excel file to open it.
3. Select the respective package tab.

used on which pin, see the previous section.

6 Ordering parts

6.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: MK28.

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format: Q K## A M FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification K## Kinetis family • K28 A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory FFF Program flash memory size • 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB Table continues on the next page... Part identification 82 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

R Silicon revision • Z = Initial

• (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MI = 169 MAPBGA (9 mm x 9 mm)
• AU = 210 WLCSP (6.9 mm x 6.9 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 18 = 180 MHz N Packaging type • R = Tape and reel
• (Blank) = Trays

7.4 Example

This is an example part number: MK28FN2M0AVMI15

8 Terminology and guidelines

8.1 Definitions

Key terms are defined in the following table: Term Definition Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: Table continues on the next page... Terminology and guidelines Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 83 NXP Semiconductors

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

8.2 Examples

Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE Terminology and guidelines 84 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

8.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V

8.4 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

8.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. Terminology and guidelines Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 85 NXP Semiconductors

9 Revision History

The following table provides a revision history for this document. Table 68. Revision History

Revision History

86 Kinetis K28F MCU Sub-Family, Rev. 0, 08/2017 NXP Semiconductors

How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM powered logo, Thumb, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2016–2017 NXP B.V. Document Number K28P210M150SF5V2 Revision 0, 08/2017