MK2703 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Packaged in 8-pin SOIC
  • Pb (lead) free package
  • Uses an inexpensive, fundamental mode crystal or clock
  • Supports MPEG sampling rates of 32 kHz, 44.1 kHz, 48 kHz, and 96 kHz
  • Patented zero ppm synthesis error in all clocks
  • All frequencies are frequency locked
  • Advanced, low power, sub-micron CMOS process
  • Operating voltage of 3.3 V or 5 V
  • Industrial temperature version available
  • The MK2703B is recommended for new designs Block Diagram Audio Clock PLL Clock Synthesis and Control Circuitry

27 MHz

S1:0 27M GND Capacitors are required for crystal tuning

PLL AUDIO CLOCK SYNTHESIZER CLOCK SYNTHESIZER IDT™ PLL AUDIO CLOCK SYNTHESIZER 2 MK2703 REV K 051310 Pin Assignment 8-pin (150 mil) SOIC AUDIO CLOCK OUTPUT SELECT TABLE Key: 0 = Connect pin directly to ground 1 = Connect pin directly to VDD Pin Descriptions External Components Decoupling Capacitor As with any high-performance mixed-signal IC, the MK2703 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01µF must be connected between VDD and GND on pins 2 and 3. It must be connected close to the MK2703 to minimize lead inductance. No external power supply filtering is required for the MK2703. Series Termination Resistor A 33Ω terminating resistor can be used next to the clock outputs for trace lengths over one inch. Crystal Load Capacitors The total on-chip capacitance is approximately 16 pF . A parallel resonant, fundamental mode, AT cut 27 MHz crystal should be used. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the VDD GND 27M CLK X21 S1 S0 CLK (MHz) 0 0 8.192 0 1 11.2896 1 0 12.288 1 1 24.576 Pin Number Pin Name Pin Type Pin Description 1 X1 XI Crystal Connection. Connect to a 27 MHz fundamental crystal or clock. 2 VDD Power Connect to +3.3 V or +5 V. 3 GND Power Connect to ground. 4 27M Output 27 MHz buffered reference clock output. 5 CLK Output Audio clock output per table above. 6 S1 Input Audio clock frequency select input #1. Determines CLK output per table above. Internal pull-up resistor. 7 S0 Input Audio clock frequency select input #0. Determines CLK output per table above. Internal pull-up resistor.

8 X2 XO Crystal connection to a 27 MHz crystal, or leave unconnected for clock

output.

PLL AUDIO CLOCK SYNTHESIZER CLOCK SYNTHESIZER IDT™ PLL AUDIO CLOCK SYNTHESIZER 3 MK2703 REV K 051310 stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (C L -16 pF)*2. In this equation, CL= crystal load capacitance in pF . Example: For a crystal with an 18 pF load capacitance, each crystal capacitor would be 4 pF [(18-16) x 2] = 4. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2703. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Recommended Operation Conditions VDD=3.3 V ±5% , Ambient temperature -40 to +85° C, unless stated otherwise Item Rating Supply Voltage, VDD -0.5 V to 7 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature, MK2703S (commercial) 0 to +70 ° C Ambient Operating Temperature, MK2703SI (industrial) -40 to +85 ° C Storage Temperature -65 to +150 ° C Soldering Temperature 260 ° C Parameter Min. Typ. Max. Units Ambient Operating Temperature -40 +85 ° C Power Supply Voltage (measured in respect to GND) +3.13 +5.50 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.13 5.50 V Input High Voltage V IH X1 pin only Note 1 (VDD/2)+1 VDD/2 V Input Low Voltage V IL X1 pin only Note 1 VDD/2 (VDD/2)-1 V Input High Voltage V IH S0, S1 pins 2.0 V Input Low Voltage V IL S0, S1 pins 0.8 V Output High Voltage V OH IOH = -12 mA 2.4 V

PLL AUDIO CLOCK SYNTHESIZER CLOCK SYNTHESIZER IDT™ PLL AUDIO CLOCK SYNTHESIZER 4 MK2703 REV K 051310 Note 1: CMOS level input. Nominal trigger point is VDD/2 for 3.3 V or 5 V operation. VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C, unless stated otherwise Note 1: Measured with 15 pF load. Thermal Characteristics Output Low Voltage V OL IOL = 12 mA 0.4 V Output High Voltage, CMOS level V OH IOH = -4 mA VDD-0.4 V Operating Supply Current IDD No load VDD = 3.3 V 25 mA Short Circuit Current CLK output + 50 mA Input Capacitance C IN S0, S1 pins 5 pF Nominal Output Impedance 20 Ω Frequency Synthesis Error All Clocks 0 ppm Internal Pull-up Resistor R PUP S1, S0 pins 500 k Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Crystal or Clock Frequency F IN 27 MHz Output Clock Rise Time t OR 0.8 to 2.0 V, Note 1 1.5 ns Output Clock Fall Time t OF 2.0 to 8.0 V, Note 1 1.5 ns Clock Stabilization Time after Power-up 10 ms Changing Frequency Setting 10 ms Output Clock Duty Cycle at VDD/2, Note 1 40 60 % Maximum Absolute Jitter, short term tja Deviation from mean ±190 ps Parameter Symbol Conditions Min. Typ. Max. Units Thermal Resistance Junction to Ambient θJA Still air 150 ° C/W θJA 1 m/s air flow 140 ° C/W θJA 3 m/s air flow 120 ° C/W Thermal Resistance Junction to Case θJC 40 ° C/W Parameter Symbol Conditions Min. Typ. Max. Units

PLL AUDIO CLOCK SYNTHESIZER CLOCK SYNTHESIZER IDT™ PLL AUDIO CLOCK SYNTHESIZER 5 MK2703 REV K 051310 Marking Diagram - MK2703SLF M arking Diagram - MK2703SILF Notes: 2. YYWW is the last two digits of the year and the week number that the part was assembled. 3. Bottom mark denotes country of origin. µCLOCK MK2703SL YYWW Bottom Marking: Line 2 & 3: Origin MK2703IL YYWW$$ Bottom Marking: Origin

PLL AUDIO CLOCK SYNTHESIZER CLOCK SYNTHESIZER IDT™ PLL AUDIO CLOCK SYNTHESIZER 6 MK2703 REV K 051310 Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Part / Order Number Marking Shipping Packaging Package Temperature MK2703SLF see page 5 Tubes 8-pin SOIC 0 to +70 ° C MK2703SLFTR Tape and Reel 8-pin SOIC 0 to +70 ° C MK2703SILF see page 5 Tubes 8-pin SOIC -40 to +85 ° C MK2703SILFTR Tape and Reel 8-pin SOIC -40 to +85 ° C INDEX AREA 1 2 D E SEATING PLANE A e - C - B .10 (.004) C C L H h x 45 Millimeters Inches Symbol Min Max Min Max A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0 . 3 30 . 5 1. 0 1 3. 0 2 0 C 0.19 0.25 .0075 .0098 D 4.80 5.00 .1890 .1968 E 3.80 4.00 .1497 .1574 e 1.27 BASIC 0.050 BASIC H 5.80 6.20 .2284 .2440 h 0 . 2 50 . 5 0. 0 1 0. 0 2 0 L 0 . 4 01 . 2 7. 0 1 6. 0 5 0 α 0° 8° 0° 8°

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