DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 69
Technical content
Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP
120 MHz ARM® Cortex®-M4-Based Microcontroller with FPU
The Kinetis K22 WLCSP product family members are optimized for space-constrained, cost-sensitive applications requiring low power, USB connectivity, and processing efficiency with a floating point unit. These devices share the comprehensive enablement and scalability of the Kinetis family. This product offers:
- Run power consumption down to 153 μA/MHz and static power consumption down to 2.6 μA with full state retention and 6 μs wakeup. Lowest static mode down to 120 nA
- USB LS/FS OTG 2.0 w/ embedded 3.3 V, 120 mA LDO voltage regulator. USB FS device crystal-less functionality. Performance
- 120 MHz ARM® Cortex®-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces
- Up to 256 KB of embedded flash and 48 KB of RAM
- Serial programming interface (EzPort)
- Preprogrammed Kinetis flashloader for one-time, in- system factory programming System peripherals
- Flexible low-power modes, multiple wake up sources
- 16-channel DMA controller
- Independent external and software watchdog monitor Clocks
- Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or 3-32 MHz
- Three internal oscillators: 32kHz, 4MHz, and 48MHz
- Multipurpose clock generator with PLL and FLL Security and integrity modules
- Hardware CRC module
- 128-bit unique identification (ID) number per chip
- Hardware random-number generator
- Flash access control to protect proprietary software Human-machine interface
- Up to 40 general-purpose I/O (GPIO) Analog modules
- Two 16-bit SAR ADCs (1.2 MS/s in 12-bit mode)
- One 12-bit DAC
- Two analog comparators (CMP) with 6- bit DAC
- Accurate internal voltage reference Communication interfaces
- USB LS/FS OTG 2.0 with on-chip transceiver and USB LDO voltage regulator
- USB full-speed device crystal-less operation
- Two SPI modules
- Three UART modules and one low-power UART
- Two I2C: Support for up to 1 Mbps operation
- I2S module Timers
- One 8-ch general-purpose PWM timer
- Two 2-ch general-purpose timers with quadrature decoder functionality
- Periodic interrupt timers
- 16-bit low-power timer
- Real-time clock with independent power domain
- Programmable delay block Operating Characteristics
- Voltage range (including flash writes): 1.71 to 3.6 V
- Temperature range (ambient): -40 to 85°C MK22FN256CAH12R MK22FN128CAH12R
64 WLCSP (AH)
3.36 x 3.33 x 0.56 Pitch 0.4 mm NXP Semiconductors K22P64M120SF8 Data Sheet: Technical Data Rev. 7, 08/2016 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
Ordering Information
Part Number Memory Number of GPIOs Flash (KB) SRAM (KB) MK22FN256CAH12R 256 48 40 MK22FN128CAH12R 128 48 40 Device Revision Number Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN] 0N51M 0001 0001 Related Resources Type Description Document Selector Guide The NXP Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector KINETISKMCUSELGD Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K22P121M120SF8RM Data Sheet The Data Sheet is this document. It includes electrical characteristics and signal connections. K22P64M120SF8 Chip Errata The chip mask set Errata provides additional or corrective information for a particular device mask set. KINETIS_K_xN51M 1 Package drawing Package dimensions are provided by part number:
- MK22FN256CAH12R
- MK22FN128CAH12R Package drawing:
- 98ASA00650D
- 98ASA00650D 1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision of the device you are using. Figure 1 shows the functional modules in the chip. 2 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
40 GPIOs
Figure 1. Functional block diagram
3.8.3 DSPI switching specifications (limited voltage
3.8.4 DSPI switching specifications (full voltage
5.2 Recommended connection for unused analog and
7.4 Relationship between ratings and operating
4 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 1 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 5 NXP Semiconductors
- Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V
- 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICIO Analog and I/O pin DC injection current — single pin
- V IN < VSS-0.3V (Negative current injection) -3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
- Negative current injection -25 — mA VODPU Open drain pullup voltage level VDD VDD V 2 VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VIO_MIN-VIN)/|IICIO|. 2. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. V DD supply LVD and POR operating requirements
- Level 1 falling (LVWV=00) 2.62 2.70 2.78 V Table continues on the next page... General Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 7 NXP Semiconductors
Table 2. V DD supply LVD and POR operating requirements (continued)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 2.72 2.82 2.92 2.80 2.90 3.00 2.88 2.98 3.08 V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
- Level 1 falling (LVWV=00)
- Level 2 falling (LVWV=01)
- Level 3 falling (LVWV=10)
- Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors Table continues on the next page...
Table 4. Voltage and current operating behaviors (continued)
- PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
- Measured at VDD supply voltage = VDD min and Vinput = VSS
- Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
- CPU and system clocks = 80 MHz
- Bus clock = 40 MHz
- Flash clock = 20 MHz
- MCG mode: FEI
Table 5. Power mode transition operating behaviors Table continues on the next page...
Table 5. Power mode transition operating behaviors (continued) temperature range of the chip.
- VLLS0 → RUN 140 μs
- VLLS1 → RUN 140 μs
- VLLS2 → RUN μs
- VLLS3 → RUN μs
- LLS2 → RUN μs
- LLS3 → RUN μs
- VLPS → RUN 5.7 μs
- STOP → RUN 5.7 μs 1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
loop from flash, unless otherwise noted. results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). Table 6. Power consumption operating behaviors Table continues on the next page...
Table 6. Power consumption operating behaviors (continued)
- @ 25°C — 20.5 21.19 mA
- @ 70°C — 20.5 21.19 mA
- @ 85°C — 20.5 21.19 mA IDD_RUN Run mode current — Compute operation, code executing from flash @ 1.8V — 14.0 14.69 mA 9 @ 3.0V
- @ 25°C — 14.0 14.69 mA
- @ 70°C — 14.0 14.69 mA
- @ 85°C — 14.0 14.69 mA IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 8.1 8.79 mA 7 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 4.4 5.09 mA 10 Table continues on the next page... General Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 11 NXP Semiconductors
Table continues on the next page...
- @ -40°C to 25°C — 0.59 0.70 µA 15 @ 3.0V
- @ -40°C to 25°C — 0.71 0.84 µA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. Cache on and prefetch on, low compiler optimization. 4. Coremark benchmark compiled using IAR 7.2 with optimization level low. 5. 120MHz core and system clock, 60MHz bus clock, and 24MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 6. 80 MHz core and system clock, 40 MHz bus clock, and 26.67 MHz flash clock. MCG configured for PEE mode. Compute operation. 7. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All peripheral clocks disabled. 8. 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. General Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 13 NXP Semiconductors
- 80MHz core and system clock, 40MHz bus clock, and 26.67MHz flash clock. MCG configured for FEI mode. Compute
- 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.
- 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute operation. Code
- 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
- 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
- 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
- Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders—typical value VLPS mode with 4 MHz IRC enabled. mode with the 32 kHz IRC enabled. IEREFSTEN4MHz External 4 MHz crystal clock adder. mode with the crystal enabled. single external input for compare. Includes 6-bit DAC power consumption. the RTC ALARM set for 1 minute. Table continues on the next page...
Table 7. Low power mode peripheral adders—typical value (continued) for RX data at 115200 baud rate.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
- MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at frequencies between 50 MHz and 100MHz. MCG in PEE mode at frequencies greater than 100 MHz.
- USB regulator disabled
- No GPIOs toggled
- Code execution from flash with cache enabled
- For the ALLOFF curve, all peripheral clocks are disabled except FTFA General Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 15 NXP Semiconductors
Figure 3. Run mode supply current vs. core frequency
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors for 64 LQFP package
- VREGIN (USB) = 5.0 V
- VDD = 3.3 V Temp = 25°C FSYS = 120 MHz FBUS = 60 MHz External crystal = 8 MHz 150 kHz–50 MHz 14 dBuV 1, 2, 3
50 MHz–150 MHz 23
150 MHz–500 MHz 23
500 MHz–1000 MHz 9
- Measurements were made per IEC 61967-2 while the device was running typical application code.
- Measurements were performed on the 64LQFP device, MK22FN512VLH12 .
- The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
- IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
2.2.7 Designing with radiated emissions in mind
- Go to nxp.com
- Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications Table continues on the next page...
Table 10. Device clock specifications (continued)
- The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
2.3.2 General switching specifications
Table 11. General switching specifications
- Slew disabled
- 1.71 ≤ V DD ≤ 2.7V
- Slew enabled
- 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater of synchronous and asynchronous timing must be met. 3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be recognized. General Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 19 NXP Semiconductors
- These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
- Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Table continues on the next page...
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.
- Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
- Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
- Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
- Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 13. SWD full voltage range electricals
- Serial wire debug MHz S2 SWD_CLK cycle period 1/S1 — ns S3 SWD_CLK clock pulse width
- Serial wire debug ns S4 SWD_CLK rise and fall times — 3 ns S9 SWD_DIO input data setup time to SWD_CLK rise 8 — ns S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 — ns Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 21 NXP Semiconductors
Table 13. SWD full voltage range electricals (continued) Figure 5. Serial wire clock input timing Figure 6. Serial wire data timing
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals Table continues on the next page...
Table 14. JTAG limited voltage range electricals (continued)
- Boundary Scan
- JTAG and CJTAG J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- Boundary Scan
- JTAG and CJTAG ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 1 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 19 ns J12 TCLK low to TDO high-Z — 19 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns
Table 15. JTAG full voltage range electricals
- Boundary Scan
- JTAG and CJTAG MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
- Boundary Scan
- JTAG and CJTAG ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 1.4 — ns J7 TCLK low to boundary scan output data valid — 27 ns J8 TCLK low to boundary scan output high-Z — 27 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 23 NXP Semiconductors
Figure 9. Test Access Port timing Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 16. MCG specifications Table continues on the next page...
Table 16. MCG specifications (continued)
- f VCO = 48 MHz
- f VCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fvco VCO operating frequency 48.0 — 120 MHz Ipll PLL operating current
- PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
- PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
- f vco = 48 MHz
- f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
- f vco = 48 MHz
- f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 27 NXP Semiconductors
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
- The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
- Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
- IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
- USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or
- MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or
- SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high-gain mode (HGO=1)
- 32 kHz
- 4 MHz
- 8 MHz (RANGE=01)
- 16 MHz
- 24 MHz
- 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low- power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Vpp5 Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 29 NXP Semiconductors
Table 18. Oscillator DC electrical specifications (continued)
- VDD=3.3 V, Temperature =25 °C
- See crystal or resonator manufacturer's recommendation
- Cx and Cy can be provided by using either integrated capacitors or external components.
- When low-power mode is selected, RF is integrated and must not be attached externally.
- The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
3.3.3.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
- Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
- When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
- Proper PC board layout procedures must be followed to achieve specifications.
- Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
Table 20. 32kHz oscillator DC electrical specifications
- When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices. Table 21. 32 kHz oscillator frequency specifications
- Proper PC board layout procedures must be followed to achieve specifications.
- This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
- The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 22. NVM program/erase timing specifications
- Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 23. Flash command timing specifications
- Assumes 25 MHz flash clock frequency.
- Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
3.4.1.4 Reliability specifications
Table 25. NVM reliability specifications
- Typical data retention values are based on measured response accelerated at high temperature and derated to a
- Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.4.2 EzPort switching specifications
Table 26. EzPort switching specifications
Figure 11. EzPort Timing Diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
differential pins ADCx_DPx, ADCx_DMx. Table 27. 16-bit ADC operating conditions Table continues on the next page...
Table 27. 16-bit ADC operating conditions (continued)
1.13 VDDA VDDA V
- All other modes VREFL VREFL 31/32 * VREFH VREFH V CADIN Input capacitance
- 16-bit mode
- 8-bit / 10-bit / 12-bit modes pF RADIN Input series resistance — 2 5 kΩ RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 24.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 1200 Ksps Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 461 Ksps 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS time constant should be kept to < 1 ns. 4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Peripheral operating requirements and behaviors Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 35 NXP Semiconductors
Figure 12. ADC input impedance equivalency diagram Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)
- ADLPC = 1, ADHSC = 0
- ADLPC = 1, ADHSC = 1
- ADLPC = 0, ADHSC = 0
- ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
- 12-bit modes
- <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
- 12-bit modes
- <12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non-linearity • 12-bit modes — ±1.0 –2.7 to +1.9 LSB4 5 Table continues on the next page... Peripheral operating requirements and behaviors 36 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)
- <12-bit modes — ±0.5 –0.7 to +0.5 EFS Full-scale error • 12-bit modes
- <12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error • 16-bit modes
- ≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
- Avg = 32
- Avg = 4 16-bit single-ended mode
- Avg = 32
- Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
- Avg = 32 16-bit single-ended mode
- Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
- Avg = 32 16-bit single-ended mode
- Avg = 32 dB dB EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. Peripheral operating requirements and behaviors Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 37 NXP Semiconductors
3.6.2 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
- CR0[HYSTCTR] = 00
- CR0[HYSTCTR] = 01
- CR0[HYSTCTR] = 10
- CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Peripheral operating requirements and behaviors Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 39 NXP Semiconductors
Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 30. 12-bit DAC operating requirements
- The DAC reference can be selected to be VDDA or VREFH.
- A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Table 31. 12-bit DAC operating behaviors
- High power (SP HP)
- Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs BW 3dB bandwidth
- High power (SP HP)
- Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV 6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to 0x800, temperature range is across the full range of the device Peripheral operating requirements and behaviors 42 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
Figure 17. Typical INL error vs. digital code
Figure 18. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
- CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
- The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
Table 33. VREF full-range operating behaviors
- current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs Tchop_osc_st up Internal bandgap start-up delay with chop oscillator enabled — — 35 ms Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements Table 35. VREF limited-range operating behaviors
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
3.8.1 USB electrical specifications
clock/crystal for both Device and Host modes. rate specifications for certification.
3.8.2 USB VREG electrical specifications
Table 36. USB VREG electrical specifications
- VREGIN = 5.0 V and temperature=25 °C
- Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V
- Run mode
- Standby mode 2.1 3.3 2.8 3.6 3.6 V V Table continues on the next page... Peripheral operating requirements and behaviors 46 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
- Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
- Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
3.8.3 DSPI switching specifications (limited voltage range)
with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. transfer formats used for communicating with slower peripheral devices. Table 37. Master mode DSPI timing (limited voltage range)
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
3.8.4 DSPI switching specifications (full voltage range)
with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes. transfer formats used for communicating with slower peripheral devices. Table 39. Master mode DSPI timing (full voltage range)
- The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
- The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
- The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Figure 21. DSPI classic SPI timing — master mode
Table 40. Slave mode DSPI timing (full voltage range) Figure 22. DSPI classic SPI timing — slave mode
3.8.5 Inter-Integrated Circuit Interface (I2C) timing
Table 41. I 2C timing Hold time (repeated) START condition. Table continues on the next page...
Table 41. I 2C timing (continued)
- The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
- The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
- The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
- Input signal Slew = 10 ns and Output Load = 50 pF
- Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
- A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
- Cb = total capacitance of the one bus line in pF.
Table 42. I 2C 1 Mbps timing period, the first clock pulse is generated.
- The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across
- Cb = total capacitance of the one bus line in pF.
Figure 23. Timing definition for devices on the I2C bus
3.8.6 UART switching specifications
See General switching specifications.
3.8.7 I2S/SAI switching specifications
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
3.8.7.1 Normal Run, Wait and Stop mode performance over a limited
device in Normal Run, Wait and Stop modes. Table 43. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage Table continues on the next page...
Figure 24. I2S/SAI timing — master modes Table 44. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage Table continues on the next page...
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 25. I2S/SAI timing — slave modes
3.8.7.2 Normal Run, Wait and Stop mode performance over the full
device in Normal Run, Wait and Stop modes. Table 45. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage Table continues on the next page...
Figure 26. I2S/SAI timing — master modes Table 46. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage Table continues on the next page...
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 27. I2S/SAI timing — slave modes
3.8.7.3 VLPR, VLPW, and VLPS mode performance over the full
device in VLPR, VLPW, and VLPS modes. Table 47. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Table continues on the next page...
Figure 28. I2S/SAI timing — master modes Table 48. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Table continues on the next page...
- Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Figure 29. I2S/SAI timing — slave modes
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
5 Pinout
5.1 K22F Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. WLC SP Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort A8 PTE0/ CLKOUT32K ADC1_SE4aADC1_SE4aPTE0/ CLKOUT32K SPI1_PCS1UART1_TX I2C1_SDARTC_ CLKOUT B8 PTE1/ LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RX I2C1_SCLSPI1_SIN D5 VDD VDD VDD D6 VSS VSS VSS C8 USB0_DPUSB0_DPUSB0_DP D8 USB0_DMUSB0_DMUSB0_DM C7 VOUT33 VOUT33 VOUT33 D7 VREGIN VREGIN VREGIN E8 ADC0_DP1ADC0_DP1ADC0_DP1 F8 ADC0_DM1ADC0_DM1ADC0_DM1 E7 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 F7 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 G8 VDDA VDDA VDDA F6 VREFH VREFH VREFH G7 VREFL VREFL VREFL H8 VSSA VSSA VSSA G6 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 G5 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 H7 XTAL32 XTAL32 XTAL32 H6 EXTAL32 EXTAL32 EXTAL32 H5 VBAT VBAT VBAT Pinout Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 59 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort F5 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_ CTS_b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK E6 PTA1 JTAG_TDI/ EZP_DI PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI E5 PTA2 JTAG_TDO/ TRACE_ SWO/ EZP_DO PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO E4 PTA3 JTAG_TMS/ SWD_DIO PTA3 UART0_ RTS_b FTM0_CH0 JTAG_TMS/ SWD_DIO H4 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b G4 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2 I2S0_TX_ BCLK JTAG_TRST_ b F4 PTA12 DISABLED PTA12 FTM1_CH0 I2S0_TXD0FTM1_QD_ PHA H3 PTA13/ LLWU_P4 DISABLED PTA13/ LLWU_P4 FTM1_CH1 I2S0_TX_FSFTM1_QD_ PHB G3 VDD VDD VDD H2 VSS VSS VSS H1 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 G1 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ ALT1 G2 RESET_b RESET_b RESET_b F3 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8 ADC0_SE8/ ADC1_SE8 PTB0/ LLWU_P5 I2C0_SCLFTM1_CH0 FTM1_QD_ PHA F2 PTB1 ADC0_SE9/ ADC1_SE9 ADC0_SE9/ ADC1_SE9 PTB1 I2C0_SDAFTM1_CH1 FTM1_QD_ PHB E3 PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCLUART0_ RTS_b FTM0_FLT3 E1 PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDAUART0_ CTS_b FTM0_FLT0 E2 PTB16 DISABLED PTB16 SPI1_SOUTUART0_RXFTM_CLKIN0 EWM_IN D1 PTB17 DISABLED PTB17 SPI1_SIN UART0_TXFTM_CLKIN1 EWM_OUT_b D2 PTB18 DISABLED PTB18 FTM2_CH0I2S0_TX_ BCLK FTM2_QD_ PHA D3 PTB19 DISABLED PTB19 FTM2_CH1I2S0_TX_FS FTM2_QD_ PHB C1 PTC0 ADC0_SE14ADC0_SE14PTC0 SPI0_PCS4PDB0_ EXTRG USB_SOF_ OUT C2 PTC1/ LLWU_P6 ADC0_SE15ADC0_SE15PTC1/ LLWU_P6 SPI0_PCS3UART1_ RTS_b FTM0_CH0 I2S0_TXD0LPUART0_ RTS_b C3 PTC2 ADC0_SE4b/ CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2UART1_ CTS_b FTM0_CH1 I2S0_TX_FSLPUART0_ CTS_b Pinout 60 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort B1 PTC3/ LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK LPUART0_ RX F1 VSS VSS VSS D4 VDD VDD VDD A1 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3 CMP1_OUTLPUART0_TX B2 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0 CMP0_OUTFTM0_CH2 B3 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_ EXTRG I2S0_RX_ BCLK I2S0_MCLK A2 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FS C4 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLK A3 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_ BCLK FTM2_FLT0 B4 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCL I2S0_RX_FS A4 PTC11/ LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDA D6 VSS VSS VSS D5 VDD VDD VDD A5 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_ RTS_b LPUART0_ RTS_b B5 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_ CTS_b LPUART0_ CTS_b C5 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RX LPUART0_ RX I2C0_SCL A6 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX LPUART0_TXI2C0_SDA B6 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_ RTS_b FTM0_CH4 EWM_IN SPI1_PCS0 C6 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_ CTS_b FTM0_CH5 EWM_OUT_bSPI1_SCK A7 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6 FTM0_FLT0SPI1_SOUT B7 PTD7 DISABLED PTD7 UART0_TXFTM0_CH7 FTM0_FLT1SPI1_SIN
5.2 Recommended connection for unused analog and digital
The following table shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application. Pinout Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 61 NXP Semiconductors
Table 49. Recommended connection for unused analog interfaces
5.3 K22F Pinouts
signals can be used on which pin, see the previous section. Figure 30. K22F 64 WLCSP pinout diagram (transparent top view)
6 Part identification
6.1 Description
values of these fields to determine the specific part you have received.
6.2 Format
Part numbers for this device have the following format: Q K## A M FFF R T PP CC N
6.3 Fields
This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow, full reel
- P = Prequalification
- K = Fully qualified, general market flow, 100 piece reel K## Kinetis family • K22 A Key attribute • D = Cortex-M4 w/ DSP
- F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
- X = Program flash and FlexMemory FFF Program flash memory size • 128 = 128 KB
- 256 = 256 KB
- 512 = 512 KB R Silicon revision • Z = Initial
- (Blank) = Main
- A = Revision after main T Temperature range (°C) • V = –40 to 105
- C = –40 to 85 CC Maximum CPU frequency (MHz) • 5 = 50 MHz
- 7 = 72 MHz
- 10 = 100 MHz
- 12 = 120 MHz
- 15 = 150 MHz N Packaging type • R = Tape and reel
6.4 Example
This is an example part number: MK22FN256CAH12R Part identification 64 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
Table 50. 64-pin WLCSP part marking
7 Terminology and guidelines
7.1 Definitions
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered. NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions Typical value A specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 65 NXP Semiconductors
7.2 Examples
Operating rating: Operating requirement: Operating behavior that includes a typical value: EXAMPLE EXAMPLEEXAMPLE EXAMPLE
7.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD Supply voltage 3.3 V Terminology and guidelines 66 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
7.4 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
7.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
8 Revision History
The following table provides a revision history for this document. Table 51. Revision History
- Added Device Revision Number Table
- Editorial Updates
- Updated Chip Errata naming convention in Related Resource table Table continues on the next page...
Revision History
Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 67 NXP Semiconductors
Table 51. Revision History (continued)
- In "Thermal operating requirements" table, in footnote, corrected "T J = TA + ΘJA" to "TJ = TA + RΘJA"
- Updated "IRC48M specifications" table
- Updated "NVM program/erase timing specifications" table; updated values for thversall (Erase All high-voltage time)
- In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding maximum frequency of operation
- Added new section, "Recommended connections for unused analog and digital pins" 5 4/2015 • On page 1:
- In first bullet of introduction, updated power consumption data to align with the data in the "Power consumption operating behaviors" table
- In second bullet of introduction, added "USB FS device crystal-less functionality"
- Under "Security and integrity modules" added "Hardware random-number generator"
- Under "Communication interfaces," updated I 2C bullet to indicate support for up to 1 Mbps operation
- Under "Operating characteristics," specified that voltage range includes flash writes
- In figure, "Functional block diagram," added "Random-number generator."
- In "Voltage and current operating requirements" table:
- Removed content related to positive injection
- Updated footnote 1 to say that all analog and I/O pins are internally clamped to VSS only (not VSS and VDD)through ESD protection diodes.
- In"Power consumption operating behaviors" table:
- Added additional temperature data in power consumption table
- Added Max IDD values based on characterization results equivalent to mean + 3 sigma
- Updated "EMC radiated emissions operating behaviors" table
- In "Thermal operating requirements" table, added the following footnote for ambient temperature: "Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + ΘJA x chip power dissipation"
- Updated "IRC48M Specifications":
- Updated maximum values for Δfirc48m_ol_lv and Δfirc48m_ol_hv (full temperature)
- Added specifications for Δfirc48m_ol_hv (-40°C to 85°C)
- Updated notes in "USB electrical specifications" section
- In "I 2C timing" table,
- Added the following footnote on maximum Fast mode value for SCL Clock Frequency: "The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V."
- Updated minimum Fast mode value for LOW period of the SCL clock to 1.25 µ
- Added "I 2C 1 Mbps timing" table
- Removed Section 6, "Ordering parts."
- Added "64-pin WLCSP part marking" section 4 12/2014 Initial public release
68 Kinetis K22F 128 KB/256 KB Flash 64-pin WLCSP, Rev. 7, 08/2016 NXP Semiconductors
How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address:nxp.com/SalesTermsandConditions. NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V. All other product or service names are the property of their respective owners. ARM, the ARM Powered logo, and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. © 2014–2016 NXP B.V. Document Number K22P64M120SF8 Revision 7, 08/2016