MK21FN1M0VMC12

NXP Semiconductors

Kinetis K21F Sub-Family Rev 4, 11/2014

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Technical content

Kinetis K21F Sub-Family Data Sheet

120 MHz ARM® Cortex®-M4-based Microcontroller with FPU

The K21 product family members are optimized for cost-sensitive applications requiring low-power, USB connectivity, processing efficiency with floating point unit and the need for extensive tamper protection, such as Electronic Point of Sales. It shares the comprehensive enablement and scalability of the Kinetis family. This product offers:

Up to 1 MB of flash memory with up to 128 KB of SRAM
DryIce Tamper Detection with active/passive pin, temperature, clock, supply voltage monitoring
Run power consumption down to 279 μA/MHz. Static power consumption down to 5.1 μA with full state retention and 5 μs wakeup. Lowest Static mode down to 268 nA
USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO voltage regulator Performance
Up to 120 MHz ARM Cortex-M4-based core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz Memories and memory interfaces
Up to 1 MB program flash memory and 128 KB RAM
Up to 128 KB FlexNVM and 4 KB FlexRAM on FlexMemory devices
FlexBus external bus interface System peripherals
Multiple low-power modes; low leakage wakeup unit
Memory protection unit with multi-master protection
16-channel DMA controller
External watchdog monitor and software watchdog Security and integrity modules
Hardware CRC module
Tamper detect and secure storage
Hardware random-number generator
Hardware encryption
128-bit unique identification (ID) number per chip Analog modules
Two 16-bit SAR ADCs
Two 12-bit DACs Communication interfaces
USB full-/low-speed On-the-Go controller
USB Device Charger detect
Controller Area Network (CAN) module
Three SPI modules
Three I2C modules
Six UART modules
Secure Digital host controller (SDHC)
I2S module Timers
Two 8-channel Flex-Timers (PWM/Motor Control)
Two 2-channel Flex-Timers (PWM/Quad Decoder)
Periodic interrupt timers and 16-bit low-power timer
Carrier modulator transmitter
Real-time clock
Programmable delay block Clocks
3 to 32 MHz and 32 kHz crystal oscillator
PLL, FLL, and multiple internal oscillators Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): –40 to 105°C MK21FX512VMC12 MK21FN1M0VMC12

121 MAPBGA

8 x 8 x 1.4 mm Pitch 0.65 mm Freescale Semiconductor, Inc. K21P121M120SF5 Data Sheet: Technical Data Rev 4, 11/2014 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2013–2015 Freescale Semiconductor, Inc. All rights reserved.

Three analog comparators (CMP)
Voltage reference Ordering Information 1 Part Number Memory Maximum number of I\\O's Flash (KB) SRAM (KB) MK21FX512VMC12 512 KB 128 81 MK21FN1M0VMC12 1 MB 128 81 1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number search. Related Resources Type Description Resource Selector Guide The Freescale Solution Advisor is a web-based tool that features interactive application wizards and a dynamic product selector. Solution Advisor Product Brief The Product Brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. K20PB1 Reference Manual The Reference Manual contains a comprehensive description of the structure and function (operation) of a device. K21P121M50SF5RM1 Data Sheet The Data Sheet includes electrical characteristics and signal connections. K21P121M50SF51 Package drawing Package dimensions are provided in package drawings. • MAPBGA 121-pin: 98ASA00344D1 1. To find the associated resource, go to http://www.freescale.com and perform a search using this term. 2 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 1. K20 block diagram Freescale Semiconductor, Inc.

3.8.5 DSPI switching specifications (limited voltage

3.8.6 DSPI switching specifications (full voltage

4 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 5 Freescale Semiconductor, Inc.

Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Figure 2. Input signal measurement reference

have C L=30pF loads,
are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
have their passive filter disabled (PORTx_PCRn[PFE]=0) General 6 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

2.7 V ≤ V DD ≤ 3.6 V
1.71 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage
2.7 V ≤ V DD ≤ 3.6 V
1.71 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICDIO Digital pin (except Tamper pins) negative DC injection current — single pin
V IN < VSS-0.3V -5 — mA IICAIO Analog2, EXTAL, and XTAL pin DC injection current — single pin
V IN < VSS-0.3V (Negative current injection)
V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins
Negative current injection
Positive current injection -25 +25 mA VODPU Open drain pullup voltage level VDD VDD V 4 VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. General Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 7 Freescale Semiconductor, Inc.

Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements

Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — 80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range
Level 1 falling (LVWV=00)
Level 2 falling (LVWV=01)
Level 3 falling (LVWV=10)
Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — 60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements 8 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

2.7 V ≤ V DD ≤ 3.6 V, IOH = -8mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOH = -2mA
1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — — 100 mA VOH_Tamper Output high voltage — high drive strength
2.7 V ≤ V BAT ≤ 3.6 V, IOH = -10mA
1.71 V ≤ V BAT ≤ 2.7 V, IOH = -3mA VBAT – 0.5 VBAT – 0.5 V V Output high voltage — low drive strength
2.7 V ≤ V BAT ≤ 3.6 V, IOH = -2mA
1.71 V ≤ V BAT ≤ 2.7 V, IOH = -0.6mA VBAT – 0.5 VBAT – 0.5 V V IOH_Tamper Output high current total for Tamper pins — — 100 mA VOL Output low voltage — high drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOL = 9mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
2.7 V ≤ V DD ≤ 3.6 V, IOL = 2mA
1.71 V ≤ V DD ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOLT Output low current total for all ports — — 100 mA VOL_Tamper Output low voltage — high drive strength
2.7 V ≤ V BAT ≤ 3.6 V, IOL = 10mA
1.71 V ≤ V BAT ≤ 2.7 V, IOL = 3mA 0.5 0.5 V V Output low voltage — low drive strength
2.7 V ≤ V BAT ≤ 3.6 V, IOL = 2mA
1.71 V ≤ V BAT ≤ 2.7 V, IOL = 0.6mA 0.5 0.5 V V IOL_Tamper Output low current total for Tamper pins — — 100 mA IIND Input leakage current, digital pins
V SS ≤ VIN ≤ VIL
All digital pins 0.002 0.5 μA 2, 3 Table continues on the next page... General Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 9 Freescale Semiconductor, Inc.

Table 4. Voltage and current operating behaviors (continued)

V IN = VDD
All digital pins except PTD7
PTD7 0.002 0.004 0.5 μA μA IIND Input leakage current, digital pins
V IL < VIN < VDD
V DD = 3.6 V
V DD = 3.0 V
V DD = 2.5 V
V DD = 1.7 V μA μA μA μA IIND Input leakage current, digital pins
V DD < VIN < 5.5 V μA IIN_Tamper Input leakage current (per Tamper pin) for full temperature range — — 1 μA IIN_Tamper Input leakage current (per Tamper pin) at 25°C — — 0.025 μA IOZ Hi-Z (off-state) leakage current (per pin) — — 0.25 μA IOZ_Tamper Hi-Z (off-state) leakage current (per Tamper pin) — — 0.25 μA RPU Internal pullup resistors (except Tamper pins) 20 35 50 kΩ 4 RPD Internal pulldown resistors (except Tamper pins) 20 35 50 kΩ 5 1. Open drain outputs must be pulled to VDD. 2. Measured at VDD=3.6V 3. Internal pull-up/pull-down resistors disabled. 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 5. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

CPU and system clocks = 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz General 10 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 5. Power mode transition operating behaviors

VLLS0 → RUN — 183 μs
VLLS1 → RUN — 183 μs
VLLS2 → RUN — 105 μs
VLLS3 → RUN — 105 μs
LLS → RUN — 5.0 μs
VLPS → RUN — 4.4 μs
STOP → RUN — 4.4 μs

2.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

@ 1.8V
@ 3.0V 33.57 33.51 36.2 36.1 mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash
@ 1.8V
@ 3.0V
@ 25°C
@ 125°C 46.36 46.31 57.4 50.1 49.9 mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 18.2 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 7.2 — mA 5 Table continues on the next page... General Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 11 Freescale Semiconductor, Inc.

Table 6. Power consumption operating behaviors (continued)

@ –40 to 25°C
@ 70°C
@ 105°C 0.528 1.6 5.2 2.25 mA mA mA IDD_VLPS Very-low-power stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 498 1300 700 2400 3600 μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 5.1 124 300 μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 3.1 14.5 63.5 7.5 195 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 2.0 6.9 112 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 1.25 6.5 2.1 18.5 108 μA μA μA IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with POR detect circuit enabled
@ –40 to 25°C
@ 70°C
@ 105°C 0.745 6.03 1.65 108 μA μA μA Table continues on the next page... General 12 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

@ –40 to 25°C
@ 70°C
@ 105°C 0.268 3.7 22.9 1.25 μA μA μA IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V
@ –40 to 25°C
@ 70°C
@ 105°C 0.19 0.49 2.2 0.22 0.64 3.2 μA μA μA IDD_VBAT Average current when CPU is not accessing RTC registers
@ 1.8V
@ –40 to 25°C
@ 70°C
@ 105°C
@ 3.0V
@ –40 to 25°C
@ 70°C
@ 105°C 0.68 1.2 3.6 0.81 1.45 4.3 0.8 1.56 5.3 0.96 1.89 6.33 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 120 MHz core and system clock, 60 MHz bus 40 Mhz and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks disabled. 3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Includes 32kHz oscillator current and RTC operation.

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

MCG in PEE mode at greater than 100 MHz frequencies General Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 13 Freescale Semiconductor, Inc.

No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Figure 3. Run mode supply current vs. core frequency 14 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors

Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,

Freescale Semiconductor, Inc.

whole number, from among the measured orientations in each frequency range.

Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

2.2.7 Designing with radiated emissions in mind

Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 8. Capacitance attributes

2.3 Switching specifications

2.3.1 Device clock specifications

Table 9. Device clock specifications Table continues on the next page... 16 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 9. Device clock specifications (continued)

The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

2.3.2 General switching specifications

GPIO signaling
Other peripheral module signaling not explicitly stated elsewhere

Table 10. General switching specifications

Slew disabled
1.71 ≤ V DD ≤ 2.7V
Slew enabled
1.71 ≤ V DD ≤ 2.7V ns ns ns ns Table continues on the next page... General Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 17 Freescale Semiconductor, Inc.

Table 10. General switching specifications (continued)

Slew disabled
1.71 ≤ V DD ≤ 2.7V
Slew enabled
1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

2.4.2 Thermal attributes

Table continues on the next page... 18 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Board type Symbol Description 121 MAPBGA Unit Notes (natural convection) Single-layer (1s) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 52 °C/W 1 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./min. air speed) 31 °C/W 1 — RθJB Thermal resistance, junction to board 17 °C/W 2 — RθJC Thermal resistance, junction to case 13 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 3 °C/W 4 Notes 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 19 Freescale Semiconductor, Inc.

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 12. Debug trace operating behaviors Figure 5. TRACE_CLKOUT specifications Figure 6. Trace data specifications 20 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

3.1.2 JTAG electricals

Table 13. JTAG limited voltage range electricals

Boundary Scan
JTAG and CJTAG
Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 2.6 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns

Table 14. JTAG full voltage range electricals

Boundary Scan
JTAG and CJTAG
Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width
Boundary Scan
JTAG and CJTAG
Serial Wire Debug 12.5 ns ns ns Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 21 Freescale Semiconductor, Inc.

Figure 9. Test Access Port timing Figure 10. TRST timing

3.2 System modules

There are no specifications necessary for the device's system modules.

3.3 Clock modules

Freescale Semiconductor, Inc.

3.3.1 MCG specifications

Table 15. MCG specifications Table continues on the next page... 24 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 15. MCG specifications (continued)

f DCO = 48 MHz
f DCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 7 PLL fvco VCO operating frequency 48.0 — 120 MHz Ipll PLL operating current
PLL @ 96 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

PLL @ 48 MHz (f osc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 24)

f vco = 48 MHz
f vco = 120 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS)
f vco = 48 MHz
f vco = 120 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 10 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Excludes any oscillator currents that are also consuming power while PLL is in operation. 9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 25 Freescale Semiconductor, Inc.

3.3.2 Oscillator electrical specifications

3.3.2.1 Oscillator DC electrical specifications

Table 16. Oscillator DC electrical specifications

32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 600 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1)
32 kHz
4 MHz
8 MHz (RANGE=01)
16 MHz
24 MHz
32 MHz 7.5 500 650 2.5 3.25 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) Table continues on the next page... Peripheral operating requirements and behaviors 26 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 16. Oscillator DC electrical specifications (continued)

VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using either the integrated capacitors or by using external components.
When low power mode is selected, RF is integrated and must not be attached externally.
The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

3.3.2.2 Oscillator frequency specifications

Table 17. Oscillator frequency specifications

Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

Freescale Semiconductor, Inc.

When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

Proper PC board layout procedures must be followed to achieve specifications.
Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

and cannot be moved into high power/gain mode. Table 18. 32kHz oscillator DC electrical specifications

When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. Table 19. 32 kHz oscillator frequency specifications

Proper PC board layout procedures must be followed to achieve specifications.
This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied

clock must be within the range of VSS to VBAT.

3.4 Memories and memory interfaces

28 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

3.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

3.4.1.1 Flash timing specifications — program and erase

are active and do not include command overhead. Table 20. NVM program/erase timing specifications

Maximum time based on expectations at cycling end-of-life.

3.4.1.2 Flash timing specifications — commands

Table 21. Flash command timing specifications

128 KB data flash
512 KB program flash 0.5 1.8 ms ms trd1sec4k Read 1s Section execution time (4 KB flash) — — 100 μs 1 tpgmchk Program Check execution time — — 95 μs 1 trdrsrc Read Resource execution time — — 40 μs 1 tpgm8 Program Phrase execution time — 90 150 μs tersblk128k tersblk512k Erase Flash Block execution time
128 KB data flash
512 KB program flash 110 435 925 3700 ms ms tersscr Erase Flash Sector execution time — 15 115 ms 2 tpgmsec1k Program Section execution time (1KB flash) — 5 — ms trd1allx Read 1s All Blocks execution time
FlexNVM devices 2.2 ms trdonce Read Once execution time — — 30 μs 1 tpgmonce Program Once execution time — 90 — μs tersall Erase All Blocks execution time — 870 7400 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 29 Freescale Semiconductor, Inc.

Table 21. Flash command timing specifications (continued)

control code 0x01
control code 0x02
control code 0x04
control code 0x08 200 150 150 μs μs μs μs tpgmpart32k tpgmpart128k Program Partition for EEPROM execution time
32 KB EEPROM backup
128 KB EEPROM backup ms ms tsetramff tsetram32k tsetram64k tsetram128k Set FlexRAM Function execution time:
Control Code 0xFF
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup 0.8 1.3 2.4 1.2 1.9 3.1 μs ms ms ms teewr8bers Byte-write to erased FlexRAM location execution time — 175 275 μs 3 teewr8b32k teewr8b64k teewr8b128k Byte-write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup 385 475 650 1700 2000 2350 μs μs μs teewr16bers 16-bit write to erased FlexRAM location execution time — 175 275 μs teewr16b32k teewr16b64k teewr16b128k 16-bit write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup 385 475 650 1700 2000 2350 μs μs μs teewr32bers 32-bit write to erased FlexRAM location execution time — 360 550 μs teewr32b32k teewr32b64k teewr32b128k 32-bit write to FlexRAM execution time:
32 KB EEPROM backup
64 KB EEPROM backup
128 KB EEPROM backup 630 810 1200 2000 2250 2650 μs μs μs 1. Assumes 25MHz or greater flash clock frequency. 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. Peripheral operating requirements and behaviors 30 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

3.4.1.3 Flash high voltage current behaviors

Table 22. Flash high voltage current behaviors

3.4.1.4 Reliability specifications

Table 23. NVM reliability specifications

EEPROM backup to FlexRAM ratio = 16
EEPROM backup to FlexRAM ratio = 128
EEPROM backup to FlexRAM ratio = 512
EEPROM backup to FlexRAM ratio = 2,048
EEPROM backup to FlexRAM ratio = 4,096 70 K 630 K 2.5 M 10 M 20 M 175 K 1.6 M 6.4 M 25 M 50 M writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 31 Freescale Semiconductor, Inc.

3.4.1.5 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the FTFE to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = × Write_efficiency × nEEPROM – 2 × EEESPLIT × EEESIZEEEESPLIT × EEESIZEnvmcycee where

Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)
EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command
EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command
Write_efficiency —
0.25 for 8-bit writes to FlexRAM
0.50 for 16-bit or 32-bit writes to FlexRAM
n nvmcycee — EEPROM-backup cycling endurance Peripheral operating requirements and behaviors 32 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 11. EEPROM backup writes to FlexRAM

3.4.2 EzPort switching specifications

Table 24. EzPort switching specifications Freescale Semiconductor, Inc.

Figure 12. EzPort Timing Diagram

3.4.3 Flexbus switching specifications

be derived from these values. Table 25. Flexbus limited voltage range switching specifications

Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,

34 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Specification is valid for all FB_AD[31:0] and FB_TA.

Table 26. Flexbus full voltage range switching specifications

Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
Specification is valid for all FB_AD[31:0] and FB_TA.

Freescale Semiconductor, Inc.

Figure 13. FlexBus read timing diagram 36 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 14. FlexBus write timing diagram

3.5 Security and integrity modules

3.5.1 DryIce Tamper Electrical Specifications

NDA, please contact your local Freescale sales representative. Freescale Semiconductor, Inc.

3.6 Analog

3.6.1 ADC electrical specifications

differential pins ADCx_DP0, ADCx_DM0. Table 27. 16-bit ADC operating conditions

1.13 VDDA VDDA V

All other modes VREFL VREFL 31/32 * VREFH VREFH V — CADIN Input capacitance
16-bit mode
8-bit / 10-bit / 12-bit modes pF — RADIN Input series resistance — 2 5 kΩ — RAS Analog source resistance (external) 13-bit / 12-bit modes fADCK < 4 MHz kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 18.0 MHz 4 fADCK ADC conversion clock frequency 16-bit mode 2.0 — 12.0 MHz 4 Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging 20.000 818.330 Ksps Table continues on the next page... Peripheral operating requirements and behaviors 38 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 27. 16-bit ADC operating conditions (continued)

Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

RAS/CAS time constant should be kept to < 1 ns.

To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

Figure 15. ADC input impedance equivalency diagram Freescale Semiconductor, Inc.

Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA)

ADLPC = 1, ADHSC = 0
ADLPC = 1, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
12-bit modes
<12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
12-bit modes
<12-bit modes ±0.7 ±0.2 –1.1 to +1.9 –0.3 to 0.5 LSB4 5 INL Integral non- linearity
12-bit modes
<12-bit modes ±1.0 ±0.5 –2.7 to +1.9 –0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes
<12-bit modes –1.4 –5.4 –1.8 LSB4 VADIN = VDDA5 EQ Quantization error
16-bit modes
≤13-bit modes –1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode
Avg = 32
Avg = 4 16-bit single-ended mode
Avg = 32
Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode
Avg = 32 16-bit single-ended mode
Avg = 32 -94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode
Avg = 32 16-bit single-ended mode dB dB Table continues on the next page... Peripheral operating requirements and behaviors 40 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

Avg = 32 EIL Input leakage error IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) Temp sensor slope Across the full temperature range of the device 1.55 1.62 1.69 mV/°C 8 VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8 1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA 2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1 MHz ADC conversion clock speed. 4. 1 LSB = (VREFH - VREFL)/2N 5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) 6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. 7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. 8. ADC conversion clock < 3 MHz Typical ADC 16-bit Differential ENOB vs ADC Clock 100Hz, 90% FS Sine Input ENOB ADC Clock Frequency (MHz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 12 11 Hardware Averaging Disabled Averaging of 4 samples Averaging of 8 samples Averaging of 32 samples

Figure 16. Typical ENOB vs. ADC_CLK for 16-bit differential mode Freescale Semiconductor, Inc.

Figure 17. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

3.6.2 CMP and 6-bit DAC electrical specifications

Table 29. Comparator and 6-bit DAC electrical specifications

CR0[HYSTCTR] = 00
CR0[HYSTCTR] = 01
CR0[HYSTCTR] = 10
CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB Peripheral operating requirements and behaviors 42 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level. Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Freescale Semiconductor, Inc.

Figure 19. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1) Table 30. 12-bit DAC operating requirements

The DAC reference can be selected to be VDDA or VREFH.
A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.

44 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 31. 12-bit DAC operating behaviors

High power (SP HP)
Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth
High power (SP HP)
Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0 + 100 mV to VDACR −100 mV 3. The DNL is measured for 0 + 100 mV to VDACR −100 mV 4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V 5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 45 Freescale Semiconductor, Inc.

VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

Figure 20. Typical INL error vs. digital code 46 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 21. Offset at half scale vs. temperature

3.6.4 Voltage reference electrical specifications

Table 32. VREF full-range operating requirements

CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature

Freescale Semiconductor, Inc.

Table 33. VREF full-range operating behaviors

current = ± 1.0 mA 200 µV 1, 2 Tstup Buffer startup time — — 100 µs — Vvdrift Voltage drift (Vmax -Vmin across the full voltage range) — 2 — mV 1 1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. 2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 34. VREF limited-range operating requirements Table 35. VREF limited-range operating behaviors

3.7 Timers

See General switching specifications.

3.8 Communication interfaces

48 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

3.8.1 USB electrical specifications

date standards, visit usb.org. specifications for certification.

3.8.2 USB DCD electrical specifications

Table 36. USB0 DCD electrical specifications

3.8.3 USB VREG electrical specifications

Table 37. USB VREG electrical specifications

VREGIN = 5.0 V and temperature=25 °C
Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V Table continues on the next page... Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 49 Freescale Semiconductor, Inc.

Run mode
Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ ILIM Short circuit current — 290 — mA 1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. 2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.

3.8.4 CAN switching specifications

See General switching specifications.

3.8.5 DSPI switching specifications (limited voltage range)

formats used for communicating with slower peripheral devices. Table 38. Master mode DSPI timing (limited voltage range) Table continues on the next page... 50 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 38. Master mode DSPI timing (limited voltage range) (continued)

The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 22. DSPI classic SPI timing — master mode Table 39. Slave mode DSPI timing (limited voltage range) Freescale Semiconductor, Inc.

Figure 23. DSPI classic SPI timing — slave mode

3.8.6 DSPI switching specifications (full voltage range)

formats used for communicating with slower peripheral devices. Table 40. Master mode DSPI timing (full voltage range)

The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

52 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

3.8.7 I2C switching specifications

See General switching specifications.

3.8.8 UART switching specifications

See General switching specifications.

3.8.9 SDHC specifications

following timing specifications assume a load of 50 pF. Table 42. SDHC switching specifications 54 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 26. SDHC timing

3.8.10 I2S switching specifications

the frame sync (I2S_FS) shown in the figures below. Table 43. I 2S master mode timing Freescale Semiconductor, Inc.

Figure 27. I2S timing — master mode Table 44. I 2S slave mode timing

Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

56 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 28. I2S timing — slave modes

3.8.10.1 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 45. I2S/SAI master mode timing Freescale Semiconductor, Inc.

Figure 29. I2S/SAI timing — master modes Table 46. I2S/SAI slave mode timing

Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

58 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 30. I2S/SAI timing — slave modes

3.8.10.2 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 47. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes Freescale Semiconductor, Inc.

Figure 31. I2S/SAI timing — master modes Table 48. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full

Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

60 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Figure 32. I2S/SAI timing — slave modes

3.8.10.3 Ordering parts

3.8.10.3.1 Determining valid orderable parts

3.8.10.4 Part identification

3.8.10.4.1 Description

values of these fields to determine the specific part you have received.

3.8.10.4.2 Format

3.8.10.4.3 Fields

Freescale Semiconductor, Inc.

Q Qualification status • M = Fully qualified, general market flow

P = Prequalification K## Kinetis family • K21 A Key attribute • D = Cortex-M4 w/ DSP
F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only
X = Program flash and FlexMemory FFF Program flash memory size • 32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB R Silicon revision • Z = Initial
(Blank) = Main
A = Revision after main T Temperature range (°C) • V = –40 to 105
C = –40 to 85
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz N Packaging type • R = Tape and reel
(Blank) = Trays

3.8.10.4.4 Example

This is an example part number: MK21FN1M0VMC10 Peripheral operating requirements and behaviors 62 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

3.8.10.4.5 Small package marking

In an effort to save space, small package devices use special marking on the chip. These markings have the following format: Q ## C F T PP This table lists the possible values for each field in the part number for small packages (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow

P = Prequalification ## Kinetis family • 2# = K21/K22 C Speed • H = 120 MHz F Flash memory configuration • K = 512 KB + Flex
1 = 1 MB T Temperature range (°C) • V = –40 to 105
MC = 121 MAPBGA
LQ = 144 LQFP
MD = 144 MAPBGA
DC = 121 XFBGA This tables lists some examples of small package marking along with the original part numbers: Original part number Alternate part number MK21FX512VMC12 M21HKVMC

3.8.10.5 Terminology and guidelines

3.8.10.5.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. This is an example of an operating requirement: Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 63 Freescale Semiconductor, Inc.

Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

3.8.10.5.2 Definition: Operating behavior

Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA

3.8.10.5.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF

3.8.10.5.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

Operating ratings apply during operation of the chip.
Handling ratings apply when the chip is not powered. Peripheral operating requirements and behaviors 64 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

3.8.10.5.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings.

3.8.10.5.6 Relationship between ratings and operating requirements

No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

3.8.10.5.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

Never exceed any of the chip’s ratings. Peripheral operating requirements and behaviors Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 65 Freescale Semiconductor, Inc.

During normal operation, don’t exceed any of the chip’s operating requirements.
If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8.10.5.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

Lies within the range of values specified by the operating behavior
Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA This is an example of a chart that shows typical values for various voltage and temperature conditions: Peripheral operating requirements and behaviors 66 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

3.8.10.5.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V

4 Dimensions

4.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 121-pin MAPBGA 98ASA00344D 169-pin MAPBGA 98ASA00628D Dimensions Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 67 Freescale Semiconductor, Inc.

5 Pinout

5.1 K21 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. NOTE

The analog input signals ADC0_DP2 and ADC0_DM2 on PTE2 and PTE3 are available only for K21 and K22 devices and are not present on K10 and K20 devices.
The TRACE signals on PTE0, PTE1, PTE2, PTE3, and PTE4 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices.
If the VBAT pin is not used, the VBAT pin should be left floating. Do not connect VBAT pin to VSS.
The FTM_CLKIN signals on PTB16 and PTB17 are available only for K11, K12, K21, and K22 devices and is not present on K10 and K20 devices. For K22D devices this signal is on ALT7, and for K22F devices, this signal is on ALT4.
The FTM0_CH2 signal on PTC5/LLWU_P9 is available only for K11, K12, K21, and K22 devices and is not present on K10 and K20 devices.
The I2C0_SCL signal on PTD2/LLWU_P13 and I2C0_SDA signal on PTD3 are available only for K11, K12, K21, and K22 devices and are not present on K10 and K20 devices. 121 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort E4 PTE0 ADC1_SE4aADC1_SE4aPTE0 SPI1_PCS1UART1_TXSDHC0_D1TRACE_ CLKOUT I2C1_SDARTC_ CLKOUT E3 PTE1/ LLWU_P0 ADC1_SE5aADC1_SE5aPTE1/ LLWU_P0 SPI1_SOUTUART1_RXSDHC0_D0TRACE_D3I2C1_SCL SPI1_SIN E2 PTE2/ LLWU_P1 ADC0_DP2/ ADC1_SE6a ADC0_DP2/ ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCKUART1_CTS_ b SDHC0_ DCLK TRACE_D2 Pinout 68 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort F4 PTE3 ADC0_DM2/ ADC1_SE7a ADC0_DM2/ ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_ b SDHC0_CMDTRACE_D1 SPI1_SOUT E7 VDD VDD VDD F7 VSS VSS VSS H7 PTE4/ LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0UART3_TXSDHC0_D3TRACE_D0 G4 PTE5 DISABLED PTE5 SPI1_PCS2UART3_RXSDHC0_D2 FTM3_CH0 F3 PTE6 DISABLED PTE6 SPI1_PCS3UART3_CTS_ b I2S0_MCLK FTM3_CH1USB_SOF_ OUT E6 VDD VDD VDD G7 VSS VSS VSS K3 PTE16 ADC0_SE4aADC0_SE4aPTE16 SPI0_PCS0UART2_TXFTM_CLKIN0 FTM0_FLT3 H4 PTE17 ADC0_SE5aADC0_SE5aPTE17 SPI0_SCKUART2_RXFTM_CLKIN1 LPTMR0_ ALT3 A11 PTE18 ADC0_SE6aADC0_SE6aPTE18 SPI0_SOUTUART2_CTS_ b I2C0_SDA L6 VSS VSS VSS F1 USB0_DP USB0_DP USB0_DP F2 USB0_DMUSB0_DMUSB0_DM G1 VOUT33 VOUT33 VOUT33 G2 VREGIN VREGIN VREGIN H1 ADC0_DP1ADC0_DP1ADC0_DP1 H2 ADC0_DM1ADC0_DM1ADC0_DM1 J1 ADC1_DP1ADC1_DP1ADC1_DP1 J2 ADC1_DM1ADC1_DM1ADC1_DM1 K1 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 ADC0_DP0/ ADC1_DP3 K2 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 ADC0_DM0/ ADC1_DM3 L1 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 ADC1_DP0/ ADC0_DP3 L2 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 ADC1_DM0/ ADC0_DM3 F5 VDDA VDDA VDDA G5 VREFH VREFH VREFH G6 VREFL VREFL VREFL F6 VSSA VSSA VSSA J3 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 H3 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 Pinout Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 69 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort L3 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 K5 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 K4 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 L7 TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B TAMPER0/ RTC_ WAKEUP_B H5 TAMPER1TAMPER1TAMPER1 J5 TAMPER2TAMPER2TAMPER2 H6 TAMPER3TAMPER3TAMPER3 J9 TAMPER4TAMPER4TAMPER4 J4 TAMPER5TAMPER5TAMPER5 L4 XTAL32 XTAL32 XTAL32 L5 EXTAL32 EXTAL32 EXTAL32 K6 VBAT VBAT VBAT J6 PTA0 JTAG_TCLK/ SWD_CLK/ EZP_CLK PTA0 UART0_CTS_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK H8 PTA1 JTAG_TDI/ EZP_DI PTA1 UART0_RXFTM0_CH6 JTAG_TDIEZP_DI J7 PTA2 JTAG_TDO/ TRACE_ SWO/ EZP_DO PTA2 UART0_TXFTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO H9 PTA3 JTAG_TMS/ SWD_DIO PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO J8 PTA4/ LLWU_P3 NMI_b/ EZP_CS_b PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b K7 PTA5 DISABLED PTA5 USB_CLKINFTM0_CH2 CMP2_OUTI2S0_TX_ BCLK JTAG_TRST_ b E5 VDD VDD VDD G3 VSS VSS VSS K8 PTA12 CMP2_IN0CMP2_IN0PTA12 CAN0_TX FTM1_CH0 I2C2_SCL I2S0_TXD0FTM1_QD_ PHA L8 PTA13/ LLWU_P4 CMP2_IN1CMP2_IN1PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 I2C2_SDAI2S0_TX_FSFTM1_QD_ PHB K9 PTA14 DISABLED PTA14 SPI0_PCS0UART0_TX I2C2_SCL I2S0_RX_ BCLK I2S0_TXD1 Pinout 70 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort L9 PTA15 DISABLED PTA15 SPI0_SCKUART0_RX I2S0_RXD0 J10 PTA16 DISABLED PTA16 SPI0_SOUTUART0_CTS_ b I2S0_RX_FSI2S0_RXD1 H10 PTA17 ADC1_SE17ADC1_SE17PTA17 SPI0_SIN UART0_RTS_ b I2S0_MCLK L10 VDD VDD VDD K10 VSS VSS VSS L11 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2FTM_CLKIN0 K11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0FTM_CLKIN1 LPTMR0_ ALT1 J11 RESET_b RESET_b RESET_b H11 PTA29 DISABLED PTA29 FB_A24 G11 PTB0/ LLWU_P5 ADC0_SE8/ ADC1_SE8 ADC0_SE8/ ADC1_SE8 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA G10 PTB1 ADC0_SE9/ ADC1_SE9 ADC0_SE9/ ADC1_SE9 PTB1 I2C0_SDAFTM1_CH1 FTM1_QD_ PHB G9 PTB2 ADC0_SE12ADC0_SE12PTB2 I2C0_SCL UART0_RTS_ b FTM0_FLT3 G8 PTB3 ADC0_SE13ADC0_SE13PTB3 I2C0_SDAUART0_CTS_ b FTM0_FLT0 F11 PTB6 ADC1_SE12ADC1_SE12PTB6 FB_AD23 E11 PTB7 ADC1_SE13ADC1_SE13PTB7 FB_AD22 D11 PTB8 DISABLED PTB8 UART3_RTS_ b FB_AD21 E10 PTB9 DISABLED PTB9 SPI1_PCS1UART3_CTS_ b FB_AD20 D10 PTB10 ADC1_SE14ADC1_SE14PTB10 SPI1_PCS0UART3_RX FB_AD19 FTM0_FLT1 C10 PTB11 ADC1_SE15ADC1_SE15PTB11 SPI1_SCKUART3_TX FB_AD18 FTM0_FLT2 B11 PTB12 DISABLED PTB12 UART3_RTS_ b FTM1_CH0FTM0_CH4 FTM1_QD_ PHA C11 PTB13 DISABLED PTB13 UART3_CTS_ b FTM1_CH1FTM0_CH5 FTM1_QD_ PHB B10 PTB16 DISABLED PTB16 SPI1_SOUTUART0_RXFTM_CLKIN0FB_AD17 EWM_IN E9 PTB17 DISABLED PTB17 SPI1_SIN UART0_TXFTM_CLKIN1FB_AD16 EWM_OUT_b D9 PTB18 DISABLED PTB18 CAN0_TX FTM2_CH0I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA C9 PTB19 DISABLED PTB19 CAN0_RX FTM2_CH1I2S0_TX_FSFB_OE_b FTM2_QD_ PHB F10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT F9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT F8 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT E8 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28 Pinout Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 71 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort B9 PTC0 ADC0_SE14ADC0_SE14PTC0 SPI0_PCS4PDB0_ EXTRG FB_AD14 I2S0_TXD1 D8 PTC1/ LLWU_P6 ADC0_SE15ADC0_SE15PTC1/ LLWU_P6 SPI0_PCS3UART1_RTS_ b FTM0_CH0FB_AD13 I2S0_TXD0 C8 PTC2 ADC0_SE4b/ CMP1_IN0 ADC0_SE4b/ CMP1_IN0 PTC2 SPI0_PCS2UART1_CTS_ b FTM0_CH1FB_AD12 I2S0_TX_FS B8 PTC3/ LLWU_P7 CMP1_IN1CMP1_IN1PTC3/ LLWU_P7 SPI0_PCS1UART1_RXFTM0_CH2CLKOUT I2S0_TX_ BCLK A8 PTC4/ LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0UART1_TXFTM0_CH3FB_AD11 CMP1_OUT D7 PTC5/ LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCKLPTMR0_ ALT2 I2S0_RXD0FB_AD10 CMP0_OUTFTM0_CH2 C7 PTC6/ LLWU_P10 CMP0_IN0CMP0_IN0PTC6/ LLWU_P10 SPI0_SOUTPDB0_ EXTRG I2S0_RX_ BCLK FB_AD9 I2S0_MCLK B7 PTC7 CMP0_IN1CMP0_IN1PTC7 SPI0_SIN USB_SOF_ OUT I2S0_RX_FSFB_AD8 A7 PTC8 ADC1_SE4b/ CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 FTM3_CH4I2S0_MCLKFB_AD7 D6 PTC9 ADC1_SE5b/ CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 FTM3_CH5I2S0_RX_ BCLK FB_AD6 FTM2_FLT0 C6 PTC10 ADC1_SE6bADC1_SE6bPTC10 I2C1_SCL FTM3_CH6I2S0_RX_FSFB_AD5 C5 PTC11/ LLWU_P11 ADC1_SE7bADC1_SE7bPTC11/ LLWU_P11 I2C1_SDAFTM3_CH7I2S0_RXD1FB_RW_b B6 PTC12 DISABLED PTC12 UART4_RTS_ b FB_AD27 FTM3_FLT0 A6 PTC13 DISABLED PTC13 UART4_CTS_ b FB_AD26 A5 PTC14 DISABLED PTC14 UART4_RX FB_AD25 B5 PTC15 DISABLED PTC15 UART4_TX FB_AD24 D5 PTC16 DISABLED PTC16 UART3_RX FB_CS5_b/ FB_TSIZ1/ FB_BE23_ 16_BLS15_8_ b C4 PTC17 DISABLED PTC17 UART3_TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_ 24_BLS7_0_b B4 PTC18 DISABLED PTC18 UART3_RTS_ b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_ BLS23_16_b A4 PTC19 DISABLED PTC19 UART3_CTS_ b FB_CS3_b/ FB_BE7_0_ BLS31_24_b FB_TA_b Pinout 72 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort D4 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0UART2_RTS_ b FTM3_CH0FB_ALE/ FB_CS1_b/ FB_TS_b D3 PTD1 ADC0_SE5bADC0_SE5bPTD1 SPI0_SCKUART2_CTS_ b FTM3_CH1FB_CS0_b C3 PTD2/ LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUTUART2_RXFTM3_CH2FB_AD4 I2C0_SCL B3 PTD3 DISABLED PTD3 SPI0_SIN UART2_TXFTM3_CH3FB_AD3 I2C0_SDA A3 PTD4/ LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1UART0_RTS_ b FTM0_CH4FB_AD2 EWM_IN A2 PTD5 ADC0_SE6bADC0_SE6bPTD5 SPI0_PCS2UART0_CTS_ b FTM0_CH5FB_AD1 EWM_OUT_b B2 PTD6/ LLWU_P15 ADC0_SE7bADC0_SE7bPTD6/ LLWU_P15 SPI0_PCS3UART0_RXFTM0_CH6FB_AD0 FTM0_FLT0 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TXFTM0_CH7 FTM0_FLT1 A10 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16 A9 PTD9 DISABLED PTD9 I2C0_SDAUART5_TX FB_A17 B1 PTD10 DISABLED PTD10 UART5_RTS_ b FB_A18 C2 PTD11 DISABLED PTD11 SPI2_PCS0UART5_CTS_ b SDHC0_ CLKIN FB_A19 C1 PTD12 DISABLED PTD12 SPI2_SCKFTM3_FLT0SDHC0_D4 FB_A20 D2 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21 D1 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22 E1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23

5.2 K21 Pinouts

The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 73 Freescale Semiconductor, Inc.

F USB0_DP G VOUT33 H ADC0_DP1 J ADC1_DP1 K ADC0_DP0/ ADC1_DP3 L ADC1_DP0/ ADC0_DP3 PTD5 PTD6/ LLWU_P15 PTD11 PTD13 PTE2/ LLWU_P1 USB0_DM VREGIN ADC0_DM1 ADC1_DM1 ADC0_DM0/ ADC1_DM3 ADC1_DM0/ ADC0_DM3 PTD4/ LLWU_P14 PTD3 PTD2/ LLWU_P13 PTD1 PTE1/ LLWU_P0 PTE6 VSS ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 PTE16 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 PTC19 PTC18 PTC17 PTD0/ LLWU_P12 PTE0 PTE3 PTE5 PTE17 TAMPER5 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 XTAL32 PTC14 PTC15 PTC11/ LLWU_P11 PTC16 VDD VDDA VREFH TAMPER1 TAMPER2 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 EXTAL32 PTC13 PTC12 PTC10 PTC9 VDD VSSA VREFL TAMPER3 PTA0 VBAT VSS PTC8 PTC7 PTC6/ LLWU_P10 PTC5/ LLWU_P9 VDD VSS VSS PTE4/ LLWU_P2 PTA2 PTA5 TAMPER0/ RTC_ WAKEUP_B PTC4/ LLWU_P8 PTC3/ LLWU_P7 PTC2 PTC1/ LLWU_P6 PTB23 PTB22 PTB3 PTA1 PTA4/ LLWU_P3 PTA12 PTA13/ LLWU_P4 PTD9 PTC0 PTB19 PTB18 PTB17 PTB21 PTB2 PTA3 TAMPER4 PTA14 PTA15 PTD8 PTB16 PTB11 PTB10 PTB9 PTB20 PTB1 PTA17 PTA16 VSS VDD APTE18 BPTB12 CPTB13 DPTB8 EPTB7 FPTB6 GPTB0/ LLWU_P5 HPTA29 JRESET_b KPTA19 LPTA18 Figure 33. K21 121 MAPBGA Pinout Diagram

6 Revision History

The following table provides a revision history for this document. Table 49. Revision History

Updated section "Voltage and current operating behaviors" Table continues on the next page...

Revision History

74 Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. Freescale Semiconductor, Inc.

Table 49. Revision History (continued)

Added DryIce Tamper Electrical Specifications
Added the following figures:
Run mode supply current vs. core frequency
VLPR mode supply current vs. core frequency
Updated section "Device clock specifications"
Updated section "Power consumption operating behaviors"
Updated section "Power mode transition operating behaviors"
Updated section "JTAG limited voltage range electricals"
Updated section "MCG specifications"
Updated section "Oscillator DC electrical specifications"
Updated section "16-bit ADC operating conditions"
Updated the pinouts
Added section "Alternate part numbers for small packages" 3 08/2013 • Updated section "Power consumption operating behaviors"
Updated the "Run mode supply current vs. core frequency" figure in section "Diagram: Typical IDD_RUN operating behavior 4 11/2014 • Updated the table "Voltage and current operating behavior"
Format changes

Kinetis K21F Sub-Family Data Sheet, Rev4, 11/2014. 75 Freescale Semiconductor, Inc.

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Product Information

MK21FN1M0VMC12 specifications and overview.

Summary

Kinetis K21F Sub-Family Rev 4, 11/2014

Description

Kinetis K21F Sub-Family Rev 4, 11/2014

Source title MK21FN1M0VMC12 Datasheet(PDF) - NXP Semiconductors

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