MK20DN512VLQ10

K20P144M100SF2V2 NXP | Alldatasheet

Document overview

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• PDF pages: 82

Technical content

Features

• Operating Characteristics Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.6 V – Temperature range (ambient): -40 to 105°C
• Performance – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
• Memories and memory interfaces – Up to 512 KB program flash memory on non- FlexMemory devices – Up to 256 KB program flash memory on FlexMemory devices – Up to 256 KB FlexNVM on FlexMemory devices – 4 KB FlexRAM on FlexMemory devices – Up to 128 KB RAM – Serial programming interface (EzPort) – FlexBus external bus interface
• Clocks – 3 to 32 MHz crystal oscillator – 32 kHz crystal oscillator – Multi-purpose clock generator
• System peripherals – Multiple low-power modes to provide power optimization based on application requirements – Memory protection unit with multi-master protection – 16-channel DMA controller, supporting up to 63 request sources – External watchdog monitor – Software watchdog – Low-leakage wakeup unit
• Security and integrity modules Hardware CRC module to support fast cyclic redundancy checks – 128-bit unique identification (ID) number per chip
• Human-machine interface – Low-power hardware touch sensor interface (TSI) – General-purpose input/output
• Analog modules – Two 16-bit SAR ADCs – Programmable gain amplifier (PGA) (up to x64) integrated into each ADC – Two 12-bit DACs – Two transimpedance amplifiers – Three analog comparators (CMP) containing a 6-bit DAC and programmable reference input – Voltage reference
• Timers – Programmable delay block – Eight-channel motor control/general purpose/PWM timer – Two 2-channel quadrature decoder/general purpose timers – Periodic interrupt timers – 16-bit low-power timer – Carrier modulator transmitter – Real-time clock Freescale Semiconductor Document Number: K20P144M100SF2V2 Data Sheet: Technical Data Rev. 3, 6/2013 Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2012–2013 Freescale Semiconductor, Inc.

• Communication interfaces USB full-/low-speed On-the-Go controller with on-chip transceiver – Two Controller Area Network (CAN) modules – Three SPI modules – Two I2C modules – Six UART modules – Secure Digital host controller (SDHC) – I2S module K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 2 Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating

6.8.5 DSPI switching specifications (limited voltage

6.8.6 DSPI switching specifications (full voltage

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 3

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 4 Freescale Semiconductor, Inc.

1 Ordering parts

1.1 Determining valid orderable parts

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: PK20 and MK20 .

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format: Q K## A M FFF R T PP CC N

2.3 Fields

This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values Q Qualification status • M = Fully qualified, general market flow P = Prequalification K## Kinetis family • K20 A Key attribute • D = Cortex-M4 w/ DSP F = Cortex-M4 w/ DSP and FPU M Flash memory type • N = Program flash only X = Program flash and FlexMemory Table continues on the next page... Ordering parts K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 5

FFF Program flash memory size • 32 = 32 KB 64 = 64 KB

• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB R Silicon revision • Z = Initial (Blank) = Main
• A = Revision after main T Temperature range (°C) • V = –40 to 105 C = –40 to 85 FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm) CC Maximum CPU frequency (MHz) • 5 = 50 MHz 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz N Packaging type • R = Tape and reel (Blank) = Trays

2.4 Example

This is an example part number: MK20DN512ZVMD10

3 Terminology and guidelines

3.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. Terminology and guidelines K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 6 Freescale Semiconductor, Inc.

3.1.1 Example

This is an example of an operating requirement: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.

3.2.1 Example

This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example

This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF Terminology and guidelines K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 7

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure:

• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.

3.4.1 Example

This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V

3.5 Result of exceeding a rating

Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 8 Freescale Semiconductor, Inc.

3.6 Relationship between ratings and operating requirements

• No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements: Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that: Lies within the range of values specified by the operating behavior

• Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 9

3.8.1 Example 1

This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA

3.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 10 Freescale Semiconductor, Inc.

4 Ratings

4.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes MSL Moisture sensitivity level — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1 VCDM Electrostatic discharge voltage, charged-device model -500 +500 V 2 ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

4.4 Voltage and current operating ratings

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 11

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General

5.1 AC electrical characteristics

Figure 1. Input signal measurement reference

• have C L=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1) 2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0) General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 12 Freescale Semiconductor, Inc.

5.2 Nonswitching electrical specifications

5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

• 1.7 V ≤ V DD ≤ 2.7 V 0.7 × VDD 0.75 × VDD V V VIL Input low voltage 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ V DD ≤ 2.7 V 0.35 × VDD 0.3 × VDD V V VHYS Input hysteresis 0.06 × VDD — V IICDIO Digital pin negative DC injection current — single pin VIN < VSS-0.3V -5 — mA IICAIO Analog2, EXTAL, and XTAL pin DC injection current — single pin VIN < VSS-0.3V (Negative current injection)
• V IN > VDD+0.3V (Positive current injection) mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins Negative current injection
• Positive current injection -25 +25 mA VODPU Open drain pullup voltage level VDD VDD V 4 VRAM VDD voltage required to retain RAM 1.2 — V VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V 1. All 5 V tolerant digital I/O pins are internally clamped to V SS through an ESD protection diode. There is no diode connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|. 2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and XTAL are analog pins. 3. All analog pins are internally clamped to V SS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. Open drain outputs must be pulled to VDD. General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 13

5.2.2 LVD and POR operating requirements

Table 2. V DD supply LVD and POR operating requirements

• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 V V V V VHYSH Low-voltage inhibit reset/recover hysteresis — high range — ±80 — mV VLVDL Falling low-voltage detect threshold — low range (LVDV=00) 1.54 1.60 1.66 V VLVW1L VLVW2L VLVW3L VLVW4L Low-voltage warning thresholds — low range Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 V V V V VHYSL Low-voltage inhibit reset/recover hysteresis — low range — ±60 — mV VBG Bandgap voltage reference 0.97 1.00 1.03 V tLPO Internal low power oscillator period — factory trimmed 900 1000 1100 μs 1. Rising thresholds are falling threshold + hysteresis voltage

Table 3. VBAT power operating requirements K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 14 Freescale Semiconductor, Inc.

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -3mA VDD – 0.5 VDD – 0.5 V V Output high voltage — low drive strength 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 VDD – 0.5 V V IOHT Output high current total for all ports — — 100 mA VOL Output low voltage — high drive strength 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 5mA 0.5 0.5 V V Output low voltage — low drive strength 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ V DD ≤ 2.7 V, IOL = 1mA 0.5 0.5 V V IOLT Output low current total for all ports — — 100 mA IINA Input leakage current, analog pins and digital pins configured as analog inputs VSS ≤ VIN ≤ VDD
• All pins except EXTAL32, XTAL32, EXTAL, XTAL
• EXTAL (PTA18) and XTAL (PTA19)
• EXTAL32, XTAL32 0.002 0.004 0.075 0.5 1.5 μA μA μA 3, 4 IIND Input leakage current, digital pins VSS ≤ VIN ≤ VIL
• All digital pins
• V IN = VDD
• All digital pins except PTD7
• PTD7 0.002 0.002 0.004 0.5 0.5 μA μA μA 4, 5 IIND Input leakage current, digital pins VIL < VIN < VDD
• V DD = 3.6 V
• V DD = 3.0 V
• V DD = 2.5 V
• V DD = 1.7 V μA μA μA μA 4, 5, 6 Table continues on the next page... General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 15

Table 4. Voltage and current operating behaviors (continued)

• V DD = 3.0 V
• V DD = 2.5 V
• V DD = 1.7 V kΩ kΩ kΩ kΩ 4, 7 RPU Internal pullup resistors 20 35 50 kΩ 8 RPD Internal pulldown resistors 20 35 50 kΩ 9 1. Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted. 2. Open drain outputs must be pulled to V DD. 3. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 4. Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. 5. Internal pull-up/pull-down resistors disabled. 6. Characterized, not tested in production. 7. Examples calculated using V IL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. 8. Measured at V DD supply voltage = VDD min and Vinput = VSS 9. Measured at V DD supply voltage = VDD min and Vinput = VDD Digital input Source Z IND I IND

5.2.4 Power mode transition operating behaviors

• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode: FEI General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 16 Freescale Semiconductor, Inc.

Table 5. Power mode transition operating behaviors across the operating temperature range of the chip.

• V DD slew rate < 5.7 kV/s 300

1.7 V / (VDD

• VLLS1 → RUN — 130 μs
• VLLS2 → RUN — 92 μs
• VLLS3 → RUN — 92 μs
• LLS → RUN — 5.9 μs
• VLPS → RUN — 5.0 μs
• STOP → RUN — 5.0 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1)

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

• @ 3.0V mA mA IDD_RUN Run mode current — all peripheral clocks enabled, code executing from flash @ 1.8V
• @ 3.0V
• @ 25°C
• @ 125°C mA mA mA 3, 4 IDD_WAIT Wait mode high frequency current at 3.0 V — all peripheral clocks disabled — 20 — mA 2 IDD_WAIT Wait mode reduced frequency current at 3.0 V — all peripheral clocks disabled — 9 — mA 5 IDD_VLPR Very-low-power run mode current at 3.0 V — all peripheral clocks disabled — 1.12 — mA 6 Table continues on the next page... General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 17

Table 6. Power consumption operating behaviors (continued)

• @ 70°C
• @ 105°C 0.74 2.45 6.61 1.41 11.5 mA mA mA IDD_VLPS Very-low-power stop mode current at 3.0 V @ –40 to 25°C
• @ 70°C
• @ 105°C 425 1280 435 2000 4000 μA μA μA IDD_LLS Low leakage stop mode current at 3.0 V @ –40 to 25°C
• @ 70°C
• @ 105°C 4.58 30.6 137 19.9 105 500 μA μA μA IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V @ –40 to 25°C
• @ 70°C
• @ 105°C 3.0 18.6 84.9 230 μA μA μA IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V @ –40 to 25°C
• @ 70°C
• @ 105°C 2.2 9.3 41.4 5.4 128 μA μA μA IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V @ –40 to 25°C
• @ 70°C
• @ 105°C 2.1 7.6 33.5 95.5 μA μA μA IDD_VBAT Average current with RTC and 32kHz disabled at 3.0 V @ –40 to 25°C
• @ 70°C
• @ 105°C 0.19 0.49 2.2 0.22 0.64 3.2 μA μA μA Table continues on the next page... General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 18 Freescale Semiconductor, Inc.

• @ –40 to 25°C
• @ 70°C
• @ 105°C
• @ 3.0V
• @ –40 to 25°C
• @ 70°C
• @ 105°C 0.57 0.90 2.4 0.67 1.0 2.7 0.67 1.2 3.5 0.94 1.4 3.9 μA μA μA μA μA μA 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See each module's specification for its supply current. 2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral clocks disabled. 3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral clocks enabled. 4. Max values are measured with CPU executing DSP instructions. 5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. 6. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. Code executing from flash. 7. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled but peripherals are not in active operation. Code executing from flash. 8. 4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled. 9. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. For devices with 32 KB of RAM, power consumption is reduced by 3 μA. 10. Includes 32kHz oscillator current and RTC operation.

5.2.5.1 Diagram: Typical IDD_RUN operating behavior

• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 19

Figure 2. Run mode supply current vs. core frequency

5.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors for 144LQFP and

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

measured orientations in each frequency range. K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 20 Freescale Semiconductor, Inc.

1. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

5.2.7 Designing with radiated emissions in mind

1. Perform a keyword search for “EMC design.”

5.2.8 Capacitance attributes

Table 8. Capacitance attributes

5.3 Switching specifications

5.3.1 Device clock specifications

Table 9. Device clock specifications Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Table 9. Device clock specifications (continued)

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

5.3.2 General switching specifications

Table 10. General switching specifications

• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns Table continues on the next page... General K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 22 Freescale Semiconductor, Inc.

Table 10. General switching specifications (continued)

• 1.71 ≤ V DD ≤ 2.7V
• Slew enabled
• 1.71 ≤ V DD ≤ 2.7V ns ns ns ns 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater synchronous and asynchronous timing must be met. 3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and VLLSx modes. 4. 75 pF load 5. 15 pF load

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

5.4.2 Thermal attributes

Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Board type Symbol Description 144 LQFP 144 MAPBGA Unit Notes Four-layer (2s2p) RθJA Thermal resistance, junction to ambient (natural convection) 36 29 °C/W 1 Single-layer (1s) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 36 38 °C/W 1 Four-layer (2s2p) RθJMA Thermal resistance, junction to ambient (200 ft./ min. air speed) 30 25 °C/W 1 — RθJB Thermal resistance, junction to board 24 16 °C/W 2 — RθJC Thermal resistance, junction to case 9 9 °C/W 3 — ΨJT Thermal characterization parameter, junction to package top outside center (natural convection) 2 2 °C/W 4 1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air). 2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. 3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors

6.1 Core modules

Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 24 Freescale Semiconductor, Inc.

6.1.1 Debug trace timing specifications

Table 12. Debug trace operating behaviors Figure 3. TRACE_CLKOUT specifications Figure 4. Trace data specifications

6.1.2 JTAG electricals

Table 13. JTAG limited voltage range electricals

• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns Table continues on the next page... Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 25

Table 13. JTAG limited voltage range electricals (continued)

• JTAG and CJTAG
• Serial Wire Debug ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1 — ns J11 TCLK low to TDO data valid — 17 ns J12 TCLK low to TDO high-Z — 17 ns J13 TRST assert time 100 — ns J14 TRST setup time (negation) to TCLK high 8 — ns

Table 14. JTAG full voltage range electricals

• JTAG and CJTAG
• Serial Wire Debug MHz J2 TCLK cycle period 1/J1 — ns J3 TCLK clock pulse width Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug 12.5 ns ns ns J4 TCLK rise and fall times — 3 ns J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns J11 TCLK low to TDO data valid — 22.1 ns J12 TCLK low to TDO high-Z — 22.1 ns Table continues on the next page... Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 26 Freescale Semiconductor, Inc.

Figure 7. Test Access Port timing Figure 8. TRST timing

6.2 System modules

There are no specifications necessary for the device's system modules.

6.3 Clock modules

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 28 Freescale Semiconductor, Inc.

6.3.1 MCG specifications

Table 15. MCG specifications Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Table 15. MCG specifications (continued)

• f DCO = 98 MHz 180 150 ps tfll_acquire FLL target frequency acquisition time — — 1 ms 6 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

2 MHz, VDIV multiplier = 24)

• f vco = 100 MHz 120 ps ps Jacc_pll PLL accumulated jitter over 1µs (RMS) fvco = 48 MHz
• f vco = 100 MHz 1350 600 ps ps Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 9 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. 3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation (Δfdco_t) over voltage and temperature should be considered. 4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. 5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. Excludes any oscillator currents that are also consuming power while PLL is in operation. 8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

6.3.2 Oscillator electrical specifications

This section provides the electrical characteristics of the module. K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 30 Freescale Semiconductor, Inc.

6.3.2.1 Oscillator DC electrical specifications

Table 16. Oscillator DC electrical specifications

• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 500 200 300 950 1.2 1.5 nA μA μA μA mA mA IDDOSC Supply current — high gain mode (HGO=1) 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz 400 500 2.5 μA μA μA mA mA mA Cx EXTAL load capacitance — — — 2, 3 Cy XTAL load capacitance — — — 2, 3 RF Feedback resistor — low-frequency, low-power mode (HGO=0) — — — MΩ 2, 4 Feedback resistor — low-frequency, high-gain mode (HGO=1) — 10 — MΩ Feedback resistor — high-frequency, low-power mode (HGO=0) — — — MΩ Feedback resistor — high-frequency, high-gain mode (HGO=1) — 1 — MΩ RS Series resistor — low-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — low-frequency, high-gain mode (HGO=1) — 200 — kΩ Series resistor — high-frequency, low-power mode (HGO=0) — — — kΩ Series resistor — high-frequency, high-gain mode (HGO=1) kΩ Table continues on the next page... Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 31

Table 16. Oscillator DC electrical specifications (continued)

1. V DD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. C x,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, R F is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

6.3.2.2 Oscillator frequency specifications

Table 17. Oscillator frequency specifications

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it

remains within the limits of the DCO input clock frequency.

1. Proper PC board layout procedures must be followed to achieve specifications.

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 32 Freescale Semiconductor, Inc.

1. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

cannot be moved into high power/gain mode. This section describes the module electrical characteristics. Table 18. 32kHz oscillator DC electrical specifications

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices. Table 19. 32 kHz oscillator frequency specifications

1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

1. The parameter specified is a peak-to-peak value and V IH and VIL specifications do not apply. The voltage of the applied

clock must be within the range of VSS to VBAT.

6.4 Memories and memory interfaces

K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

6.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

6.4.1.1 Flash timing specifications — program and erase

active and do not include command overhead. Table 20. NVM program/erase timing specifications

1. Maximum time based on expectations at cycling end-of-life.

6.4.1.2 Flash timing specifications — commands

Table 21. Flash command timing specifications

256 KB program/data flash

• 1 KB flash
• 2 KB flash 2.4 4.7 9.3 ms ms ms trd1all Read 1s All Blocks execution time — — 1.8 ms trdonce Read Once execution time — — 25 μs 1 tpgmonce Program Once execution time — 65 — μs tersall Erase All Blocks execution time — 250 2000 ms 2 tvfykey Verify Backdoor Access Key execution time — — 30 μs 1 Table continues on the next page... Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 34 Freescale Semiconductor, Inc.

Table 21. Flash command timing specifications (continued)

• control code 0x02
• control code 0x04
• control code 0x08 200 150 150 μs μs μs μs tpgmpart64k tpgmpart256k Program Partition for EEPROM execution time

64 KB FlexNVM

• 256 KB FlexNVM 138 145 ms ms tsetramff tsetram32k tsetram64k tsetram256k Set FlexRAM Function execution time: Control Code 0xFF
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 256 KB EEPROM backup 0.8 1.3 4.5 1.2 1.9 5.5 μs ms ms ms Byte-write to FlexRAM for EEPROM operation teewr8bers Byte-write to erased FlexRAM location execution time — 175 260 μs 3 teewr8b32k teewr8b64k teewr8b128k teewr8b256k Byte-write to FlexRAM execution time:

32 KB EEPROM backup

• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 385 475 650 1000 1800 2000 2400 3200 μs μs μs μs Word-write to FlexRAM for EEPROM operation teewr16bers Word-write to erased FlexRAM location execution time — 175 260 μs teewr16b32k teewr16b64k teewr16b128k teewr16b256k Word-write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 385 475 650 1000 1800 2000 2400 3200 μs μs μs μs Longword-write to FlexRAM for EEPROM operation teewr32bers Longword-write to erased FlexRAM location execution time — 360 540 μs teewr32b32k teewr32b64k teewr32b128k teewr32b256k Longword-write to FlexRAM execution time:
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup 630 810 1200 1900 2050 2250 2675 3500 μs μs μs μs Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 35

1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

6.4.1.3 Flash high voltage current behaviors

Table 22. Flash high voltage current behaviors

6.4.1.4 Reliability specifications

Table 23. NVM reliability specifications

• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 4096
• EEPROM backup to FlexRAM ratio = 32,768 35 K 315 K 1.27 M 10 M 80 M 175 K 1.6 M 6.4 M 50 M 400 M writes writes writes writes writes 1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619. 2. Cycling endurance represents number of program/erase cycles at -40°C ≤ T j ≤ 125°C. 3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and typical values assume all byte-writes to FlexRAM. Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 36 Freescale Semiconductor, Inc.

6.4.1.5 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space. While different partitions of the FlexNVM are available, the intention is that a single choice for the FlexNVM partition code and EEPROM data set size is used throughout the entire lifetime of a given application. The EEPROM endurance equation and graph shown below assume that only one configuration is ever used. Writes_subsystem = × Write_efficiency × nEEPROM – 2 × EEESPLIT × EEESIZE EEESPLIT × EEESIZE nvmcycd where Writes_subsystem — minimum number of writes to each FlexRAM location for subsystem (each subsystem can have different endurance)

• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; entered with the Program Partition command
• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program Partition command
• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command
• Write_efficiency —
• 0.25 for 8-bit writes to FlexRAM
• 0.50 for 16-bit or 32-bit writes to FlexRAM
• n nvmcycd — data flash cycling endurance (the following graph assumes 10,000 cycles) Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 37

Figure 9. EEPROM backup writes to FlexRAM

6.4.2 EzPort switching specifications

Table 24. EzPort switching specifications K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 38 Freescale Semiconductor, Inc.

Figure 10. EzPort Timing Diagram

6.4.3 Flexbus switching specifications

the same as the internal system bus frequency or an integer divider of that frequency. Table 25. Flexbus limited voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,

K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

1. Specification is valid for all FB_AD[31:0] and FB_TA.

Table 26. Flexbus full voltage range switching specifications

1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 40 Freescale Semiconductor, Inc.

Figure 11. FlexBus read timing diagram K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Figure 12. FlexBus write timing diagram

6.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

6.6 Analog

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 42 Freescale Semiconductor, Inc.

6.6.1 ADC electrical specifications

Table 27. 16-bit ADC operating conditions

1.13 VDDA VDDA V

Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Table 27. 16-bit ADC operating conditions (continued)

1. Typical values assume V DDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

1. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

time constant should be kept to < 1 ns.

1. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
2. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.RAS

Figure 13. ADC input impedance equivalency diagram Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 44 Freescale Semiconductor, Inc.

Table 28. 16-bit ADC characteristics (V REFH = VDDA, VREFL = VSSA) (continued)

• ADLPC = 1, ADHSC = 0 ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 MHz MHz MHz MHz tADACK = 1/ fADACK Sample Time See Reference Manual chapter for sample times TUE Total unadjusted error
• 12-bit modes <12-bit modes ±1.4 ±6.8 ±2.1 LSB4 5 DNL Differential non- linearity
• 12-bit modes <12-bit modes ±0.7 ±0.2 -1.1 to +1.9 -0.3 to 0.5 LSB4 5 INL Integral non- linearity
• 12-bit modes <12-bit modes ±1.0 ±0.5 -2.7 to +1.9 -0.7 to +0.5 LSB4 5 EFS Full-scale error • 12-bit modes <12-bit modes -1.4 -5.4 -1.8 LSB4 VADIN = VDDA EQ Quantization error
• 16-bit modes ≤13-bit modes -1 to 0 ±0.5 LSB4 ENOB Effective number of bits 16-bit differential mode Avg = 32
• Avg = 4 16-bit single-ended mode
• Avg = 32
• Avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits SINAD Signal-to-noise plus distortion See ENOB 6.02 × ENOB + 1.76 dB THD Total harmonic distortion 16-bit differential mode Avg = 32 16-bit single-ended mode
• Avg = 32 –94 -85 dB dB SFDR Spurious free dynamic range 16-bit differential mode Avg = 32 16-bit single-ended mode
• Avg = 32 dB dB Table continues on the next page... Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 45

1. All accuracy numbers assume the ADC is calibrated with V REFH = VDDA
2. Typical values assume V DDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

MHz ADC conversion clock speed.

1. 1 LSB = (V REFH - VREFL)/2N
2. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
3. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
4. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

Figure 14. Typical ENOB vs. ADC_CLK for 16-bit differential mode K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 46 Freescale Semiconductor, Inc.

Figure 15. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode Table 29. 16-bit ADC with PGA operating conditions Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Table 29. 16-bit ADC with PGA operating conditions (continued)

1. Typical values assume V DDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

1. ADC must be configured to use the internal voltage reference (VREF_OUT)
2. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other

than the output of the VREF module, the VREF module must be disabled.

1. For single ended configurations the input impedance of the driven input is R PGAD/2
2. The analog source resistance (R AS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop

in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.

1. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
2. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
3. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1

Table 30. 16-bit ADC with PGA characteristics Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 48 Freescale Semiconductor, Inc.

Table 30. 16-bit ADC with PGA characteristics (continued)

• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 RAS < 100Ω BW Input signal bandwidth
• 16-bit modes < 16-bit modes kHz kHz PSRR Power supply rejection ratio Gain=1 — -84 — dB VDDA= 3V ±100mV, fVDDA= 50Hz, 60Hz CMRR Common mode rejection ratio
• Gain=1 Gain=64 -84 -85 dB dB VCM= 500mVpp, fVCM= 50Hz, 100Hz VOFS Input offset voltage — 0.2 — mV Output offset = VOFS*(Gain+1) TGSW Gain switching settling time — — 10 µs 5 dG/dT Gain drift over full temperature range
• Gain=1 Gain=64 ppm/°C ppm/°C dG/dVDDA Gain drift over supply voltage
• Gain=1 Gain=64 0.07 0.14 0.21 0.31 %/V %/V VDDA from 1.71 to 3.6V EIL Input leakage error All modes IIn × RAS mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VPP,DIFF Maximum differential input signal swing where VX = VREFPGA × 0.583 V 6 SNR Signal-to-noise ratio
• Gain=1 Gain=64 dB dB 16-bit differential mode, Average=32 THD Total harmonic distortion
• Gain=1 Gain=64 100 dB dB 16-bit differential mode, Average=32, fin=100Hz Table continues on the next page... Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 49

• Gain=1 Gain=64 105 dB dB 16-bit differential mode, Average=32, fin=100Hz ENOB Effective number of bits
• Gain=1, Average=4 Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32 11.6 8.0 7.2 6.3 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 13.6 9.6 9.6 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,fin=100Hz SINAD Signal-to-noise plus distortion ratio See ENOB 6.02 × ENOB + 1.76 dB 1. Typical values assume V DDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. 2. This current is a PGA module adder, in addition to ADC conversion currents. 3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong function of input common mode voltage (VCM) and the PGA gain. 4. Gain = 2 PGAG 5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. 6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the PGA reference voltage and gain setting.

6.6.2 CMP and 6-bit DAC electrical specifications

Table 31. Comparator and 6-bit DAC electrical specifications Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 50 Freescale Semiconductor, Inc.

Table 31. Comparator and 6-bit DAC electrical specifications (continued)

• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to V DD-0.6 V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = V reference/64 Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 51

Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 52 Freescale Semiconductor, Inc.

Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) Table 32. 12-bit DAC operating requirements

1. The DAC reference can be selected to be V DDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC

K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Table 33. 12-bit DAC operating behaviors

• Low power (SP LP) 1.2 0.05 1.7 0.12 V/μs CT Channel to channel cross talk — — -80 dB BW 3dB bandwidth High power (SPHP)
• Low power (SP LP) 550 kHz 1. Settling within ±1 LSB 2. The INL is measured for 0+100mV to V DACR−100 mV 3. The DNL is measured for 0+100 mV to V DACR−100 mV 4. The DNL is measured for 0+100mV to V DACR−100 mV with VDDA > 2.4V 5. Calculated by a best fit curve from V SS+100 mV to VDACR−100 mV 6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set to 0x800, Temp range from -40C to 105C Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 54 Freescale Semiconductor, Inc.

Figure 18. Typical INL error vs. digital code K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Figure 19. Offset at half scale vs. temperature

6.6.4 Voltage reference electrical specifications

Table 34. VREF full-range operating requirements

1. C L must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
2. The load capacitance should not exceed +/-25% of the nominal specified C L value over the operating temperature range of

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 56 Freescale Semiconductor, Inc.

Table 35. VREF full-range operating behaviors

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

Table 36. VREF limited-range operating requirements Table 37. VREF limited-range operating behaviors

6.7 Timers

See General switching specifications.

6.8 Communication interfaces

K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

6.8.1 USB electrical specifications

6.8.2 USB DCD electrical specifications

Table 38. USB DCD electrical specifications

6.8.3 USB VREG electrical specifications

Table 39. USB VREG electrical specifications

• Across operating voltage and temperature 650 nA μA ILOADrun Maximum load current — Run mode — — 120 mA ILOADstby Maximum load current — Standby mode — — 1 mA VReg33out Regulator output voltage — Input supply (VREGIN) > 3.6 V Run mode
• Standby mode 2.1 3.3 2.8 3.6 3.6 V V VReg33out Regulator output voltage — Input supply (VREGIN) < 3.6 V, pass-through mode 2.1 — 3.6 V 2 COUT External output capacitor 1.76 2.2 8.16 μF ESR External output capacitor equivalent series resistance 1 — 100 mΩ Table continues on the next page... Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 58 Freescale Semiconductor, Inc.

1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I Load.

6.8.4 CAN switching specifications

See General switching specifications.

6.8.5 DSPI switching specifications (limited voltage range)

used for communicating with slower peripheral devices. Table 40. Master mode DSPI timing (limited voltage range)

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

6.8.6 DSPI switching specifications (full voltage range)

used for communicating with slower peripheral devices. Table 42. Master mode DSPI timing (full voltage range)

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Figure 22. DSPI classic SPI timing — master mode Table 43. Slave mode DSPI timing (full voltage range) Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Table 43. Slave mode DSPI timing (full voltage range) (continued) Figure 23. DSPI classic SPI timing — slave mode

6.8.7 Inter-Integrated Circuit Interface (I 2C) timing

Table 44. I 2C timing Hold time (repeated) START condition. Table continues on the next page... K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 62 Freescale Semiconductor, Inc.

Table 44. I 2C timing (continued)

1. The master mode I 2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I 2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must

= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

1. C b = total capacitance of the one bus line in pF.

Figure 24. Timing definition for fast and standard mode devices on the I2C bus

6.8.8 UART switching specifications

See General switching specifications. K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

6.8.9 SDHC specifications

appropriately to arrive at timing specs/constraints for the physical interface. Table 45. SDHC switching specifications Figure 25. SDHC timing K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 64 Freescale Semiconductor, Inc.

6.8.10 I2S/SAI switching specifications

frame sync (FS) signal shown in the following figures.

6.8.10.1 Normal Run, Wait and Stop mode performance over a limited

device in Normal Run, Wait and Stop modes. Table 46. I2S/SAI master mode timing in Normal Run, Wait and Stop modes K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Figure 26. I2S/SAI timing — master modes Table 47. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes

• All other modes ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 66 Freescale Semiconductor, Inc.

Figure 27. I2S/SAI timing — slave modes

6.8.10.2 Normal Run, Wait and Stop mode performance over the full

device in Normal Run, Wait and Stop modes. Table 48. I2S/SAI master mode timing in Normal Run, Wait and Stop modes K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Figure 28. I2S/SAI timing — master modes Table 49. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes

• All other modes 20.6 ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 5.8 — ns S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns S19 I2S_TX_FS input assertion to I2S_TXD output valid1 — 25 ns 1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 68 Freescale Semiconductor, Inc.

Figure 29. I2S/SAI timing — slave modes

6.8.10.3 VLPR, VLPW, and VLPS mode performance over the full

device in VLPR, VLPW, and VLPS modes. Table 50. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

Figure 30. I2S/SAI timing — master modes Table 51. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 70 Freescale Semiconductor, Inc.

Figure 31. I2S/SAI timing — slave modes

6.9 Human-machine interfaces (HMI)

6.9.1 TSI electrical specifications

Table 52. TSI electrical specifications

• 2 μA setting (REFCHRG = 0)
• 32 μA setting (REFCHRG = 15) μA 2, 6 IELE Electrode oscillator current source base current
• 2 μA setting (EXTCHRG = 0)
• 32 μA setting (EXTCHRG = 15) μA 2, 7 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.3333 38400 fF/count 10 MaxSens Maximum sensitivity 0.008 1.46 — fF/count 11 Res Resolution — — 16 bits TCon20 Response time @ 20 pF 8 15 25 μs 12 ITSI_RUN Current added in run mode — 55 — μA ITSI_LP Low power mode current adder — 1.3 2.5 μA 13 Peripheral operating requirements and behaviors K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 71

1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. 2. Fixed external capacitance of 20 pF. 3. REFCHRG = 2, EXTCHRG=0. 4. REFCHRG = 0, EXTCHRG = 10. 5. V DD = 3.0 V. 6. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. 7. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. 8. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. 9. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. 10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. 11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity depends on the configuration used. The documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN) The typical value is calculated with the following configuration: Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF The minimum value is calculated with the following configuration: Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 electrode, EXTCHRG = 7. 13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of 20 pF. Data is captured with an average of 7 periods window.

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings. To find a package drawing, go to freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 144-pin LQFP 98ASS23177W 144-pin MAPBGA 98ASA00222D

8 Pinout

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 72 Freescale Semiconductor, Inc.

8.1 K20 signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. 144 LQFP 144 MAP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort — L5 RTC_ WAKEUP_B RTC_ WAKEUP_B RTC_ WAKEUP_B — M5 NC NC NC — A10 NC NC NC — B10 NC NC NC — C10 NC NC NC

1 D3 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA RTC_CLKOUT

2 D2 PTE1/

LLWU_P0 ADC1_SE5a ADC1_SE5a PTE1/ LLWU_P0 SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL SPI1_SIN

3 D1 PTE2/

LLWU_P1 ADC1_SE6a ADC1_SE6a PTE2/ LLWU_P1 SPI1_SCK UART1_CTS_ b SDHC0_DCLK

4 E4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_

b SDHC0_CMD SPI1_SOUT

5 E5 VDD VDD VDD

6 F6 VSS VSS VSS

7 E3 PTE4/

LLWU_P2 DISABLED PTE4/ LLWU_P2 SPI1_PCS0 UART3_TX SDHC0_D3

8 E2 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2

9 E1 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_

b I2S0_MCLK USB_SOF_ OUT

10 F4 PTE7 DISABLED PTE7 UART3_RTS_

b I2S0_RXD0

11 F3 PTE8 DISABLED PTE8 I2S0_RXD1 UART5_TX I2S0_RX_FS

12 F2 PTE9 DISABLED PTE9 I2S0_TXD1 UART5_RX I2S0_RX_

13 F1 PTE10 DISABLED PTE10 UART5_CTS_

b I2S0_TXD0

14 G4 PTE11 DISABLED PTE11 UART5_RTS_

b I2S0_TX_FS

15 G3 PTE12 DISABLED PTE12 I2S0_TX_

16 E6 VDD VDD VDD

17 F7 VSS VSS VSS

18 H3 VSS VSS VSS

19 H1 USB0_DP USB0_DP USB0_DP

20 H2 USB0_DM USB0_DM USB0_DM

21 G1 VOUT33 VOUT33 VOUT33

22 G2 VREGIN VREGIN VREGIN

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 73

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

23 J1 ADC0_DP1 ADC0_DP1 ADC0_DP1

24 J2 ADC0_DM1 ADC0_DM1 ADC0_DM1

25 K1 ADC1_DP1 ADC1_DP1 ADC1_DP1

26 K2 ADC1_DM1 ADC1_DM1 ADC1_DM1

27 L1 PGA0_DP/

ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3

28 L2 PGA0_DM/

ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3

29 M1 PGA1_DP/

ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3

30 M2 PGA1_DM/

ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3

31 H5 VDDA VDDA VDDA

32 G5 VREFH VREFH VREFH

33 G6 VREFL VREFL VREFL

34 H6 VSSA VSSA VSSA

35 K3 ADC1_SE16/

CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22 ADC1_SE16/ CMP2_IN2/ ADC0_SE22

36 J3 ADC0_SE16/

CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21 ADC0_SE16/ CMP1_IN2/ ADC0_SE21

37 M3 VREF_OUT/

CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18 VREF_OUT/ CMP1_IN5/ CMP0_IN5/ ADC1_SE18

38 L3 DAC0_OUT/

CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23 DAC0_OUT/ CMP1_IN3/ ADC0_SE23

39 L4 DAC1_OUT/

CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23 DAC1_OUT/ CMP0_IN4/ CMP2_IN3/ ADC1_SE23

40 M7 XTAL32 XTAL32 XTAL32

41 M6 EXTAL32 EXTAL32 EXTAL32

42 L6 VBAT VBAT VBAT

— VDD VDD VDD 44 — VSS VSS VSS

45 M4 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b

46 K5 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN

47 K4 PTE26 DISABLED PTE26 UART4_CTS_

b RTC_CLKOUT USB_CLKIN Pinout K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 74 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

48 J4 PTE27 DISABLED PTE27 UART4_RTS_

b

49 H4 PTE28 DISABLED PTE28

50 J5 PTA0 JTAG_TCLK/

SWD_CLK/ EZP_CLK TSI0_CH1 PTA0 UART0_CTS_ UART0_COL_ b FTM0_CH5 JTAG_TCLK/ SWD_CLK EZP_CLK

51 J6 PTA1 JTAG_TDI/

EZP_DI TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI

52 K6 PTA2 JTAG_TDO/

TRACE_SWO/ EZP_DO TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/ TRACE_SWO EZP_DO

53 K7 PTA3 JTAG_TMS/

SWD_DIO TSI0_CH4 PTA3 UART0_RTS_ b FTM0_CH0 JTAG_TMS/ SWD_DIO

54 L7 PTA4/

LLWU_P3 NMI_b/ EZP_CS_b TSI0_CH5 PTA4/ LLWU_P3 FTM0_CH1 NMI_b EZP_CS_b

55 M8 PTA5 DISABLED PTA5 USB_CLKIN FTM0_CH2 CMP2_OUT I2S0_TX_

JTAG_TRST_ b

56 E7 VDD VDD VDD

57 G7 VSS VSS VSS

58 J7 PTA6 DISABLED PTA6 FTM0_CH3 TRACE_

59 J8 PTA7 ADC0_SE10 ADC0_SE10 PTA7 FTM0_CH4 TRACE_D3

60 K8 PTA8 ADC0_SE11 ADC0_SE11 PTA8 FTM1_CH0 FTM1_QD_

TRACE_D2

61 L8 PTA9 DISABLED PTA9 FTM1_CH1 FTM1_QD_

TRACE_D1

62 M9 PTA10 DISABLED PTA10 FTM2_CH0 FTM2_QD_

TRACE_D0

63 L9 PTA11 DISABLED PTA11 FTM2_CH1 FTM2_QD_

64 K9 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD0 FTM1_QD_

65 J9 PTA13/

LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_ PHB

66 L10 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_RX_

I2S0_TXD1

67 L11 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0

68 K10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_

UART0_COL_ b I2S0_RX_FS I2S0_RXD1

69 K11 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_

b I2S0_MCLK

70 E8 VDD VDD VDD

71 G8 VSS VSS VSS

72 M12 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 75

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

73 M11 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_

74 L12 RESET_b RESET_b RESET_b

75 K12 PTA24 DISABLED PTA24 FB_A29

76 J12 PTA25 DISABLED PTA25 FB_A28

77 J11 PTA26 DISABLED PTA26 FB_A27

78 J10 PTA27 DISABLED PTA27 FB_A26

79 H12 PTA28 DISABLED PTA28 FB_A25

80 H11 PTA29 DISABLED PTA29 FB_A24

81 H10 PTB0/

LLWU_P5 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 ADC0_SE8/ ADC1_SE8/ TSI0_CH0 PTB0/ LLWU_P5 I2C0_SCL FTM1_CH0 FTM1_QD_ PHA

82 H9 PTB1 ADC0_SE9/

ADC1_SE9/ TSI0_CH6 ADC0_SE9/ ADC1_SE9/ TSI0_CH6 PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_ PHB

83 G12 PTB2 ADC0_SE12/

TSI0_CH7 ADC0_SE12/ TSI0_CH7 PTB2 I2C0_SCL UART0_RTS_ b FTM0_FLT3

84 G11 PTB3 ADC0_SE13/

TSI0_CH8 ADC0_SE13/ TSI0_CH8 PTB3 I2C0_SDA UART0_CTS_ UART0_COL_ b FTM0_FLT0

85 G10 PTB4 ADC1_SE10 ADC1_SE10 PTB4 FTM1_FLT0

86 G9 PTB5 ADC1_SE11 ADC1_SE11 PTB5 FTM2_FLT0

87 F12 PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23

88 F11 PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22

89 F10 PTB8 DISABLED PTB8 UART3_RTS_

b FB_AD21

90 F9 PTB9 DISABLED PTB9 SPI1_PCS1 UART3_CTS_

b FB_AD20

91 E12 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1

92 E11 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2

93 H7 VSS VSS VSS

94 F5 VDD VDD VDD

95 E10 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN

96 E9 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b

97 D12 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_

FB_AD15 FTM2_QD_ PHA

98 D11 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_FS FB_OE_b FTM2_QD_

99 D10 PTB20 DISABLED PTB20 SPI2_PCS0 FB_AD31 CMP0_OUT

100 D9 PTB21 DISABLED PTB21 SPI2_SCK FB_AD30 CMP1_OUT

101 C12 PTB22 DISABLED PTB22 SPI2_SOUT FB_AD29 CMP2_OUT

102 C11 PTB23 DISABLED PTB23 SPI2_SIN SPI0_PCS5 FB_AD28

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 76 Freescale Semiconductor, Inc.

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

103 B12 PTC0 ADC0_SE14/

TSI0_CH13 ADC0_SE14/ TSI0_CH13 PTC0 SPI0_PCS4 PDB0_EXTRG FB_AD14 I2S0_TXD1

104 B11 PTC1/

LLWU_P6 ADC0_SE15/ TSI0_CH14 ADC0_SE15/ TSI0_CH14 PTC1/ LLWU_P6 SPI0_PCS3 UART1_RTS_ b FTM0_CH0 FB_AD13 I2S0_TXD0

105 A12 PTC2 ADC0_SE4b/

CMP1_IN0/ TSI0_CH15 ADC0_SE4b/ CMP1_IN0/ TSI0_CH15 PTC2 SPI0_PCS2 UART1_CTS_ b FTM0_CH1 FB_AD12 I2S0_TX_FS

106 A11 PTC3/

LLWU_P7 CMP1_IN1 CMP1_IN1 PTC3/ LLWU_P7 SPI0_PCS1 UART1_RX FTM0_CH2 CLKOUT I2S0_TX_ BCLK

107 H8 VSS VSS VSS

— VDD VDD VDD

109 A9 PTC4/

LLWU_P8 DISABLED PTC4/ LLWU_P8 SPI0_PCS0 UART1_TX FTM0_CH3 FB_AD11 CMP1_OUT

110 D8 PTC5/

LLWU_P9 DISABLED PTC5/ LLWU_P9 SPI0_SCK LPTMR0_ ALT2 I2S0_RXD0 FB_AD10 CMP0_OUT

111 C8 PTC6/

LLWU_P10 CMP0_IN0 CMP0_IN0 PTC6/ LLWU_P10 SPI0_SOUT PDB0_EXTRG I2S0_RX_ BCLK FB_AD9 I2S0_MCLK

112 B8 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_

I2S0_RX_FS FB_AD8

113 A8 PTC8 ADC1_SE4b/

CMP0_IN2 ADC1_SE4b/ CMP0_IN2 PTC8 I2S0_MCLK FB_AD7

114 D7 PTC9 ADC1_SE5b/

CMP0_IN3 ADC1_SE5b/ CMP0_IN3 PTC9 I2S0_RX_ BCLK FB_AD6 FTM2_FLT0

115 C7 PTC10 ADC1_SE6b ADC1_SE6b PTC10 I2C1_SCL I2S0_RX_FS FB_AD5

116 B7 PTC11/

LLWU_P11 ADC1_SE7b ADC1_SE7b PTC11/ LLWU_P11 I2C1_SDA I2S0_RXD1 FB_RW_b

117 A7 PTC12 DISABLED PTC12 UART4_RTS_

b FB_AD27

118 D6 PTC13 DISABLED PTC13 UART4_CTS_

b FB_AD26

119 C6 PTC14 DISABLED PTC14 UART4_RX FB_AD25

120 B6 PTC15 DISABLED PTC15 UART4_TX FB_AD24

— VSS VSS VSS 122 — VDD VDD VDD

123 A6 PTC16 DISABLED PTC16 CAN1_RX UART3_RX FB_CS5_b/

FB_TSIZ1/ FB_BE23_16_ b

124 D5 PTC17 DISABLED PTC17 CAN1_TX UART3_TX FB_CS4_b/

FB_TSIZ0/ FB_BE31_24_ b

125 C5 PTC18 DISABLED PTC18 UART3_RTS_

b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_b

126 B5 PTC19 DISABLED PTC19 UART3_CTS_

b FB_CS3_b/ FB_BE7_0_b FB_TA_b Pinout K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 77

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort

127 A5 PTD0/

LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ b FB_ALE/ FB_CS1_b/ FB_TS_b

128 D4 PTD1 ADC0_SE5b ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_

b FB_CS0_b

129 C4 PTD2/

LLWU_P13 DISABLED PTD2/ LLWU_P13 SPI0_SOUT UART2_RX FB_AD4

130 B4 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX FB_AD3

131 A4 PTD4/

LLWU_P14 DISABLED PTD4/ LLWU_P14 SPI0_PCS1 UART0_RTS_ b FTM0_CH4 FB_AD2 EWM_IN

132 A3 PTD5 ADC0_SE6b ADC0_SE6b PTD5 SPI0_PCS2 UART0_CTS_

UART0_COL_ b FTM0_CH5 FB_AD1 EWM_OUT_b

133 A2 PTD6/

LLWU_P15 ADC0_SE7b ADC0_SE7b PTD6/ LLWU_P15 SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0

134 M10 VSS VSS VSS

135 F8 VDD VDD VDD

136 A1 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1

137 C9 PTD8 DISABLED PTD8 I2C0_SCL UART5_RX FB_A16

138 B9 PTD9 DISABLED PTD9 I2C0_SDA UART5_TX FB_A17

139 B3 PTD10 DISABLED PTD10 UART5_RTS_

b FB_A18

140 B2 PTD11 DISABLED PTD11 SPI2_PCS0 UART5_CTS_

b SDHC0_ CLKIN FB_A19

141 B1 PTD12 DISABLED PTD12 SPI2_SCK SDHC0_D4 FB_A20

142 C3 PTD13 DISABLED PTD13 SPI2_SOUT SDHC0_D5 FB_A21

143 C2 PTD14 DISABLED PTD14 SPI2_SIN SDHC0_D6 FB_A22

144 C1 PTD15 DISABLED PTD15 SPI2_PCS1 SDHC0_D7 FB_A23

8.2 K20 pinouts

The figure below shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. Pinout K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 78 Freescale Semiconductor, Inc.

108 VDD

116 PTC11/LLWU_P11

124 PTC17

132 PTD5

140 PTD11

Figure 32. K20 144 LQFP Pinout Diagram K20 Sub-Family Data Sheet, Rev. 3, 6/2013.

A B C D E F G H J A B C D E F G H J KK LL MM PTA18 PTC8 PTC4/ NC PTC3/ PTC2 PTA1 PTA6PTA0PTE27 ADC0_SE16/ ADC1_SE16/ PTE26 PTE25 PTA2 PTA3 PTA8 PTA7 VSSVSSVSSAVDDAPTE28VSSUSB0_DM ADC0_DM1 ADC1_DM1 PGA0_DM/ DAC0_OUT/ DAC1_OUT/ RTC VBAT PTA4/ PTA9 PTA11 PTA12 PTA13/ PTB1 PTA27 PTB0/ PTB4PTB5VSSVSSVREFLVREFHPTE11PTE12VREGINVOUT33 USB0_DP ADC0_DP1 ADC1_DP1 PGA0_DP/ PGA1_DP/ PGA1_DM/ VREF_OUT/ PTE24 NC EXTAL32 XTAL32 PTA5 PTA10 VSS PTA16 PTA14 PTB3 PTA29 PTA26 PTA17 PTA15 PTA19 RESET_b PTA24 PTA25 PTA28 PTB2 PTB6PTB7PTB8PTB9VDD VDD PTB17 PTB16 PTB10PTB11 PTB19 PTB18 PTB22PTB23NC PTB20PTB21PTC5/ PTD8PTC6/ PTC7 PTD9 NC PTC1/ PTC0 VSS VSS VDDVDD PTC13 PTC9 PTC11/ PTC10 PTC19 PTC15 PTC14PTC18PTD2/ PTD3PTD10 PTD13 PTE0 PTD1 PTC17 VDD VDDPTE7 PTE3PTE4/ PTE8PTE9PTE10 PTE6 PTE5 PTE1/PTE2/ PTD15 PTD14 PTD11PTD12 PTC12PTC16PTD0/PTD4/PTD5PTD6/PTD7 LLWU_P15 LLWU_P14 LLWU_P12 LLWU_P8 LLWU_P7 LLWU_P11 LLWU_P6 LLWU_P13 LLWU_P10 LLWU_P1 LLWU_P0 LLWU_P9 LLWU_P2 LLWU_P5 CMP1_IN2/ ADC0_SE21 LLWU_P4 ADC0_DP0/ ADC1_DP3 ADC0_DM0/ ADC1_DM3 CMP1_IN3/ ADC0_SE23 CMP0_IN4/ CMP2_IN3/ ADC1_SE23 _WAKEUP_B CMP2_IN2/ ADC0_SE22 LLWU_P3 ADC1_DP0/ ADC0_DP3 ADC1_DM0/ ADC0_DM3 CMP1_IN5/ CMP0_IN5/ ADC1_SE18 Figure 33. K20 144 MAPBGA Pinout Diagram

9 Revision history

The following table provides a revision history for this document. Table 53. Revision history Table continues on the next page...

Revision history

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. 80 Freescale Semiconductor, Inc.

Table 53. Revision history (continued) 2 12/2012 Replaced TBDs throughout. 3 6/2013 • In ESD handling ratings, added a note for ILAT. Updated "Voltage and current operating requirements" Table 1.

• Updated I OL data for VOL row in "Voltage and current operating behaviors" Table 4.
• Updated wakeup times and t POR value in "Power mode transition operating behaviors" Table 5.
• In "EMC radiated emissions operating behaviors . . ." Table 7, added a column for 144MAPBGA.
• In "16-bit ADC operating conditions" Table 27, updated the max spec of VADIN.
• In "16-bit ADC electrical characteristics" Table 28, updated the temp sensor slope and voltage specs.
• Updated Inter-Integrated Circuit Interface (I 2C) timing.
• In SDHC specifications, added operating voltage row.

K20 Sub-Family Data Sheet, Rev. 3, 6/2013. Freescale Semiconductor, Inc. 81

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